Pinned Loading

1. RISCV-single-core RISCV-single-core Public

   32-bit RISC-V processor with 5-stage pipeline, full RV32I support, and comprehensive hazard handling

   Verilog 1

2. core-v-verif core-v-verif Public

   Forked from openhwfoundation/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly 1

3. rv32im-npu-soc rv32im-npu-soc Public

   SystemVerilog 2

4. 3-1-arbiter-router 3-1-arbiter-router Public

   Verilog

5. llama.cpp llama.cpp Public

   Forked from ggml-org/llama.cpp

   LLM inference in C/C++

   C++