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[RISC-V] Vectorize float32 minimum reductions with RVV - #12
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Co-authored-by: Yang Wang <yangwang@iscas.ac.cn> Co-authored-by: Yuansheng <yuansheng@isrc.iscas.ac.cn>
This reverts commit ae89f72.
Co-authored-by: Yang Wang <yangwang@iscas.ac.cn> Co-authored-by: Yuansheng <yuansheng@isrc.iscas.ac.cn>
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[RISC-V] Vectorize float32 minimum reductions with RVV
Motivation
Single-axis minimum reductions over long rows are a common tensor operation. The current sequential CPU reduction processes those rows one element at a time, which limits throughput on RVV hardware. A specialized vector reduction improves this case while preserving the general reduction machinery for more complex shapes and operators.
Implementation
Testing
The patch was tested against commit
b84609d3fc73d20929c114eab95faaa56e6c5edeon a RISC-V host with eight SpacemiT A100 cores (CPUs 0-7), GCC 14.3.0, and Linux 6.18.3.Apply and build:
The full build completed successfully. Functional operator tests were not run as part of this performance-validation pass; the results below are performance measurements, not a numerical-correctness claim.
The benchmark used MXNet's
benchmark.opperf.utils.benchmark_utils.run_performance_testwith the native profiler, float32 CPU tensors, 50 warm-up iterations, and 300 measured iterations. Each result below is from an independent invocation withOMP_NUM_THREADS=8,OMP_DYNAMIC=FALSE, andtaskset -c 0-7.Performance
Lower is better.
git apply patch-opt.diffThe median latency is reduced by 48.85%, corresponding to a 1.96x speedup. The patched run-to-run range was 0.57% of its median.