Risc-V Business

• Tiny ML Risc V backend AI Accelerator. Adapting CFU Playground to support the open source GF180 PDK and joint FPGA and ASIC workflows. With a sample design incorporating paddle-paddle OCR as a custom functional unit (CFU) accelerator. With the vision pipelines being handled via base64 decoding and encoding from a UART input stream.

Description

The project being demonstrated is a continuation of the design philosophy as shown in the open source repository CFU Playground by Google. This project will the backbone for our implementation providing a Risc V backend and SoC, with ability to define a Custom Functional Unit (CFU) which are project will be contained in. This structure has been used in https://arxiv.org/abs/2511.21232 to be able to create unique structures for FPGA platforms. Our group will utilize this project structure to:

1. Adapt the system for tape out and support of GF180.

2. Implement support for Paddle Paddle OCR a low resource OCR implementation, with BASE64 encoded images being processed via UART, eliminating the need for a complex IO pipeline to support camera input.

Setup Instructions

1. Clone the repository
2. git submodule update --init --recursive
3. Sym link project in correct location: ln -s wam-CFU/ src/CFU-Playground/proj/wam-CFU/
4. chmod +x setup.sh
5. run ./setup.sh
6. chmod +x start-env.sh

Starting The Environment

1. run ./start-env.sh
2. cd ../../
3. cd wam-CFU
4. make clean
5. make prog TARGET=tul_pynq_z2 USE_SYMBIFLOW=1

Vivado Notes

Note: Vivado must be installed with Zynq SOC Support. Only core usage is for schematic creation and block diagraming as symbiflow is used for core synthesis and bitstream generation. Vivado should not be used for synthesis or bitstream generation to comply with open source tools only requirements.

1. make prog TARGET=tul_pynq_z2 USE_SYMBIFLOW=1
2. cd src/CFU-Playground/soc/build/tul_pynq_z2.wam-CFU/gateware
3. vivado tul_pynq_z2.xpr