[bri-prism]

What

• PTQ1_0 MUL_MAT_ID mat-vec with one column and K <= 4096 (at most 32 blocks per row): each of the 4 warps in the
  CTA now owns one row, and its lanes stride that row's 128-weight blocks on the planar layout.

Why

• The generic loop spreads the blocks of a row over all 128 threads of the CTA. With 32 blocks or fewer per row, only
  the first warp loads anything, so MoE expert mat-vecs at these shapes ran at about 0.5 TB/s on H200.

How

• Same per-row accumulation order, same warp_reduce_sum and the same epilogue (bias, gate, GLU), so outputs are
  bit-identical to the current path.
• Other types, other K, the non-ids path, HIP and MUSA are unchanged.

Testing

• test-backend-ops MUL_MAT_ID, MUL_MAT_VEC_FUSION and MUL_MAT pass (CUDA vs CPU).
• Greedy output is byte-identical before and after on several PTQ1_0 models, MoE and dense.
• H200: a fused gate/up expert mat-vec at K = 4096 goes from 63 to 32 us. End-to-end MoE decode improves by 2-15%,
  depending on how much of the token time the expert mat-vecs take. No change on dense PTQ1_0 models.
• Tested on H200 only.