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Pull requests: OpenXiangShan/GEM5
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feat(smt): add safe per-IQ watermark policy
#1175
opened Sep 18, 2026 by
TFS-star
Contributor
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misc: Add RTL alignment and PerfCCT analysis skills
#1173
opened Sep 17, 2026 by
jensen-yan
Collaborator
•
Draft
cpu-o3, mem-cache: Align SBuffer store miss handling with KMHV3 RTL
#1171
opened Sep 17, 2026 by
XDu5
Contributor
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cpu-o3: Align FTQ-driven I-cache prefetch
#1170
opened Sep 17, 2026 by
CaoJiaming776
Member
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mem-cache: Add CQF admission control to BOP
do not merge
#1168
opened Sep 16, 2026 by
XXtaoo
Collaborator
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cpu-o3: Align FP16 and FP32 divide latency with RTL
#1167
opened Sep 16, 2026 by
XXtaoo
Collaborator
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cpu-o3: RVV decode bandwidth align with RTL
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
#1166
opened Sep 16, 2026 by
XDu5
Contributor
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9 tasks done
cpu-o3,mem-cache: Add hit-under-block and per-thread fetch gate
#1164
opened Sep 15, 2026 by
YihengChen1
Contributor
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cpu-o3: Fix Topdown stats and expose late load cancels
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
#1163
opened Sep 15, 2026 by
jensen-yan
Collaborator
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cpu-o3: Replay conflicting SMT load-reserved operations
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
#1160
opened Sep 15, 2026 by
jensen-yan
Collaborator
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mem: Add CHIron CCHI fabric with pluggable L2/home endpoints
align-kmhv3
do not merge
#1142
opened Sep 11, 2026 by
Kumonda221-CrO3
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cpu-o3: Disable IBuffer bypass for pflush vset
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
#1135
opened Sep 9, 2026 by
jueshiwenli
Collaborator
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cpu-o3: Remove serialization barriers for vsetvli and vsetivli
#1128
opened Sep 8, 2026 by
Ziyue-Zhang
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cpu: Clarify difftest lifecycle and handle initial events
#1108
opened Sep 2, 2026 by
jensen-yan
Collaborator
•
2/2
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cpu: Synchronize initial DUT state to difftest reference
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
regression
Run the full gem5 regression suite before merge
#1106
opened Sep 2, 2026 by
jensen-yan
Collaborator
•
1/2
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tests,util: Add post-run performance anomaly monitor
#1100
opened Aug 31, 2026 by
jensen-yan
Collaborator
•
Draft
cpu-o3: Guarantee SMT LSQ bank-conflict progress
do not merge
#1084
opened Aug 27, 2026 by
jensen-yan
Collaborator
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PairTAGE PPA-Aware Model Implementation
perf
#1080
opened Aug 26, 2026 by
Yakkhini
Collaborator
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cpu: Fix dispatch FetchFrag recount and split leftover fetch cuts
Ready to Merge
This PR has completed all required changes and is ready to merge once it passes review.
#1066
opened Aug 25, 2026 by
aphlta
Contributor
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3 of 4 tasks
feat(smt): add per-IQ Watermark partitioning policy for SMT
#1025
opened Aug 6, 2026 by
TFS-star
Contributor
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arch-riscv: Add configurable RVV VLEN (128/256/512)
rvv
#1023
opened Aug 4, 2026 by
aphlta
Contributor
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9 of 10 tasks
arch-riscv: Add H-mode L1 TLB compression
#1006
opened Jul 30, 2026 by
Gekyume777
Collaborator
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mem: Preserve shared DTLB defaults while enabling RTL alignment
#1005
opened Jul 30, 2026 by
Ergou-ren
Collaborator
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