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[None][feat] Add the PrimTS native sparse MLA FMHA for DeepSeek-V4 generation and enable it by default on SM100 - #20209

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yunruis:user/yunruis/dsv4-prims-ts-sparse-mla
Oct 26, 2026
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yunruis merged 19 commits into
NVIDIA:mainfrom
yunruis:user/yunruis/dsv4-prims-ts-sparse-mla

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@yunruis yunruis commented Oct 13, 2026 •

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Description

Impact

  • New FMHA library prims_ts_sparse_mla (PrimsTSSparseMlaFmha, tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py): DeepSeek-V4 generation-phase sparse MLA on the vendored PrimTS CuTe DSL kernel (BatchSparseMLADecodePagedTSWrapper, feat(prims-ts): add native two-source sparse MLA flashinfer-ai/flashinfer#5434).
  • Default path change, SM100 only. DeepSeek-V4 Flash / Pro generation attention on B200 / GB200 now runs on PrimTS instead of TRTLLM-Gen (DEFAULT_FMHA_LIBS order: prims_ts_sparse_mla > flashinfer_trtllm_gen > fallback). Selection is logged at info level: FMHA layer N: PrimsTSSparseMlaFmha serves causal requests (...).
  • Unchanged: context phase (TRTLLM-Gen), SM103 / Rubin / all other archs, all other models, fp8_ds_mla footer-scale cache and NVFP4 compressed pools (fallback).
  • Opt-out: TLLM_FMHA_LIBS=-prims_ts_sparse_mla.
  • Vendored tree re-pin: flashinfer-prims-ts → yunruis/flashinfer trtllm-prims-ts-dev-20261023 @ aa709061 (canonical trtllm-prims-ts-dev-20261012 @ 0e0761ef + upstream main commits touching flashinfer/attention/prims_ts, byte-identical to main @ 3bf6d3202). Also updates the existing prims_ts_block_sparse / prims_ts libraries and brings in the persistent CuTe DSL compile cache (flashinfer [FEAT] Add option to link statically with cublas&curand #6529).
  • Metadata: DeepSeek-V4 attention metadata keeps absolute token positions for every KV cache mode (one int32 [max_num_tokens] buffer; previously fp8_ds_mla only).

Interface / knobs

Knob Default Effect
TLLM_FMHA_LIBS=-prims_ts_sparse_mla library on Restore TRTLLM-Gen for DSv4 generation
TRTLLM_FLASHINFER_WORKSPACE_PER_PROCESS 1 Per-rank FlashInfer workspace under the default launcher; 0 shares one compile cache per host
TLLM_PRIMTS_WARM_WORKERS 4 (capped so a host starts ≤16 workers) Precompile worker subprocesses per rank; 0 = compile in-process
TLLM_PRIMTS_WARM_TIMEOUT — Bound on the precompile wait; on expiry falls back to in-process compile
FLASHINFER_WORKSPACE_BASE ~/.cache/flashinfer Location of the persistent compile cache (.../0.6.18/<arch>/cached_ops/prims_ts_*_cute_dsl/)

Notes: the first compile needs the cache directory writable; FLASHINFER_DISABLE_JIT=1 now refuses a cold compile of these kernels.

How the backend works

  • Consumes the dual-pool storage-row indices from DeepseekV4TrtllmAttention.sparse_attn_predict directly ([T, K] int32 rows + per-row lengths; SWA pool primary, compressed pool extra; -1 holes handled in-kernel). No page-table conversion, no packing kernel.
  • BF16 and per-tensor FP8 KV caches, attention sinks. Scales are host scalars (softmax_scale = attn_scale * q_descale * kv_descale, output_scale = kv_descale), read once at eager warm-up, never under graph capture.
  • Fused DSv4 epilogue written in place in TRT-LLM's group-major [G, T, (H/G)*512] / [G, (H/G)*4, pad4(T)] block-128 E4M3 + FP32-scale layout.
  • Plans live in TrtllmAttentionMetadata.fmha_plan_caches["prims_ts_sparse_mla"]: one plan per static profile shared by all layers of a metadata object, one shared workspace. First eager forward per profile warms all kernel variants once per process; index contract validated once per process; nothing planned or validated under capture.
  • Per-source live lengths (sparse_mla_swa_lens, sparse_mla_extra_lens[ratio]) derived once per step in the DSv4 metadata; no per-layer helper kernels.
  • Eager host path: run() memoizes the static launch state per (pool, extra pool, sinks, scales) tuple and later validate=False calls take _run_prepared. B100 TP4 eager c8: adapter host p50 per layer 141 → 91 µs, decode 132.3 → 128.5 ms/step; CUDA-graph steps unchanged. Ships in flashinfer-prims-ts.patch, to be upstreamed.
  • SM103 kept on the fallback on purpose: kernels not signoff-qualified there and L0 #64329 hit an illegal memory access on GB300 that does not reproduce on B200.

Vendor patch

  • Regenerated for the new tree (7 files, 33 hunks): flashinfer_api for flashinfer_experimental_api, trace= arguments dropped (flashinfer-python 0.6.18), absolute flashinfer.jit / utils / cute_dsl imports, relative kernel imports in the sparse plan resolver (guarded by test_prims_ts_vendored_imports.py).
  • One functional fix, dropped at the next re-pin: _launch_mla_decode passes output_quant_args positionally and unconditionally (fix(prims-ts): pass output quantization argument positionally to MLA kernels flashinfer-ai/flashinfer#6843). Without it every kernel reloaded from the persistent cache fails with TypeError: Expects 15 parameters. Covered by test_reloaded_kernel_accepts_the_same_launch.
  • Numerics: fused output differs from trtllm.fused_inv_rope_fp8_quant_vllm_port only on near-zero RoPE channels (D[448:512]), within one quantization step.

Performance vs. TRTLLM-Gen fallback

Exclusive 4x B200 (umbriel-b200-145), DeepSeek-V4-Flash TP4/EP4 attention-DP, bench_dsv4_flash_decode.py, 256 output tokens, ms per decode step (lower is better). "short" ≈ 256-token prompts, "long" ≈ 3000-token prompts (top-k saturated).

mode prompt concurrency TRTLLM-Gen PrimTS (this PR) ratio
CUDA graph short 8 / 32 / 128 10.31 / 13.83 / 15.70 10.59 / 13.86 / 15.83 1.03 / 1.00 / 1.01
CUDA graph long 8 / 32 / 128 10.84 / 18.15 / 29.29 10.96 / 18.05 / 28.79 1.01 / 0.99 / 0.98
eager short 8 / 128 10.91 / 19.13 10.92 / 19.03 1.00 / 0.99
eager long 8 / 32 / 128 12.41 / 19.71 / 29.42 12.67 / 19.21 / 30.18 1.02 / 0.97 / 1.03

All points within ±3 %. Steady-state attention kernel time is identical with and without the valid-prefix plan hint (torch.profiler). Raw numbers: dsv4-trtllm-logs/e2e/exclB200_*.json, A-agent_flow/DSV4-trtllm/trace/perf_history.csv.

Startup time (default launcher, per-rank workspaces, LLM() ready time, exclusive nodes)

Node / model Cache state TRTLLM-Gen (opt-out) PrimTS
4x B100, DSv4-Flash TP4/EP4 fresh root 652 s 786 s (PrimTS kernels cold, rest warm)
4x B100, DSv4-Flash TP4/EP4 warm 257 s 268 s
8x B200, DSv4-Flash TP8/EP8 fresh root 1071 s 1640 s (872 s with only PrimTS kernels cold)
8x B200, DSv4-Flash TP8/EP8 warm 327 s 294 s
  • PrimTS adds ≈530 s (TP4) to ≈570 s (TP8) to the first start on a host; warm starts are equal or faster.
  • The first-start cost is three back-to-back per-profile precompile fan-outs (3 + 6 + 3 variants, ≈105 s worker start-up + ≈20 s per kernel each); the worker count is capped by the variant count, so TLLM_PRIMTS_WARM_WORKERS=4 / 8 measure the same (872 / 860 s) and 0 (in-process) is 1040 s.
  • Follow-up (not in this PR): one fan-out over the union of profiles, lazy dynamic-scale kernel compile.

CI history

L0 build Commit Result Notes
#64329 first revision 3 failure groups softmax scale off by sqrt(512/192) in the unit-test scenario (fixed, _softmax_scale); GB300 perf-sanity illegal address (SM103 now unavailable); GB200 2-node DSR1/Kimi failures shared with other PRs
#64663 second revision DSv4 / PrimTS all pass remaining failures shared with other PRs; TestDeepSeekV4ProDSpark::test_gsm8k_dep8_megamoe_deepgemm OOM in KV-cache estimation (passes on all neighbouring builds)
#65568 ebba1f1 79,807 passed / 5 failed failures in flux, sampler, B300 attention aggregate, all "terminated unexpectedly" in untouched code and failing on other PRs
#65915 99958d2 84,482 passed / 10 failed one group: test_forward_error_survival.py on CPU stages, main-side (kv_cache_retention_config, fix #20883)
#66018 8e22202 79,319 passed / 50 failed KVCM2 poison latch (#20816), CSA2 illegal address (unrelated aggregate), test_mpi_session flake (nvbug 6913451); re-trigger refused because of a merge conflict → rebased
#66101 c67aa5f 89,314 passed / 1 failed B300 attention aggregate hit the 3600 s wrapper limit (main's budget: 58-59 min on post-merge builds, nvbug 6964732, fix #20822); re-triggered
#66179 c67aa5f rerun B300 aggregate passed (27.4 min); 3 x86 multi-GPU failures test_disaggregated_deepseek_v3_lite_fp8_nixl (auth flake, also on #18843 / post-merge), test_llm_partial_update_weights_qwen35_mxfp8 (overlap flake, 7/167 on main), TestDeepSeekV4FlashDSpark::test_gsm8k_1p1d_dep4 gen worker not ready in 3600 s (same signature on gRPC-only PR #20437 the same day)
#66272 c67aa5f rerun SUCCESS all three stages passed; test_gsm8k_1p1d_dep4 17.9 min (main 11.1-11.9 min, the delta is the gen worker's cold PrimTS compile)

Every DeepSeek-V4 / PrimTS test passed on every build from #64663 on (test_prims_ts_sparse_mla_fmha.py 62/62 on DGX_B200, test_deepseek_v4_sparse_mla.py, test_fmha_registry.py, test_prims_ts_vendored_imports.py).

schema_version: 1
vendors:
  flashinfer-prims-ts:
    upstream_prs:
      - https://github.com/flashinfer-ai/flashinfer/pull/5434
      - https://github.com/flashinfer-ai/flashinfer/pull/6529
      - https://github.com/flashinfer-ai/flashinfer/pull/5351
      - https://github.com/flashinfer-ai/flashinfer/pull/6089

Test Coverage

Verified on B200 in the TRT-LLM devel container (CuTe DSL 4.8.0, CUDA 13.4, torch 2.14 nv26.08).

  • New tests/unittest/_torch/attention/sparse/deepseek_v4/test_prims_ts_sparse_mla_fmha.py (added to l0_b200.yml, TIMEOUT 90, excluded from the attention aggregate): registry order and opt-out; softmax-scale derivation; kernel-level fused-output parity vs fused_inv_rope_fp8_quant_vllm_port (bf16 / fp8); test_forward_sparse_mla_unified on the default library set with PrimTS asserted to serve generation, parametrized over {prims_ts, fallback}; test_forward_sparse_mla_unified_fused_epilogue; speculative-decoding rows (next_n 2 / 6, ragged) on PrimTS; warm-set coverage of requests * (1 + draft) rows; per-host precompile worker cap; plan sharing; pool-view lifetime; reloaded-kernel launch; CUDA graph capture / replay with swapped indices; shared-workspace growth. 62 passed on DGX_B200 in CI.
  • tests/unittest/_torch/attention/sparse/deepseek_v4/ + test_fmha_registry.py: 578 passed / 28 skipped cold (34 min) and again from the compile cache (2.5 min).
  • Existing test_prims_ts_fmha.py, test_prims_ts_attention_backend.py, sparse/test_prims_ts_block_sparse.py against the new vendored tree: 328 passed cold and 328 passed from the cache (the cache run caught the output_quant_args reload bug).

End to end GSM8K (1319 samples):

Model / config FMHA library set GSM8K reference
DSv4-Flash, TestDeepSeekV4Flash::test_auto_dtype (4x B200, TP4/EP4 ADP, auto KV) default (PrimTS serves generation) 95.26 95.11
same TLLM_FMHA_LIBS=-prims_ts_sparse_mla 94.84 95.11
DSv4-Pro, TestDeepSeekV4Pro::test_gsm8k_full_accuracy (8x B200, TP8/EP8 ADP, FP8 KV, MTP 1, padded graphs) default (PrimTS serves generation) 96.13 96.0
same TLLM_FMHA_LIBS=-prims_ts_sparse_mla 96.25 96.0

The Pro run logs PrimsTSSparseMlaFmha serves causal requests (generation_seq_len_q<=2, output_dtype=torch.float8_e4m3fn) for all 62 layers on every rank, so the fused E4M3 epilogue and MTP two-token generation are exercised end to end.

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

  • Test cases are provided for new code paths (see test instructions)

  • If PR introduces API changes, an appropriate PR label is added - either api-compatible or api-breaking. For api-breaking, include BREAKING in the PR title.

  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

  • Update tava architecture diagram if there is a significant design change in PR.

  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

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@yuxianq

yuxianq commented Oct 13, 2026 •

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Vendor promotion metadata and source attribution are valid. This is not a code-review approval. Promotion still requires the source PR to merge.

No exact match was found for the following commits; similarity matching accepted them:

  • ae3851ab5f958ba22f154059df5b38321f6369d2: upstream PR #6482, similarity 98.59% — accepted (threshold 90.00%; similar-edits).

Scores compare normalized patch lines in lock-selected files, not semantic equivalence. These changes retain retain-until-verified refresh policy.

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Vendor validation result: no source-validation objection.

Latest vendor validation and step-by-step fix.

@yuxianq

yuxianq commented Oct 13, 2026

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@yunruis — the PrimTS upstream refresh #20155 has merged. Please update this source-update PR before merging it.

The new canonical source branch is yuxianq/flashinfer:trtllm-prims-ts-dev-20261012, initially pinned at ae312f7cc1723b06fda5168105ade0f328ee47d8.

  1. Rebase your temporary FlashInfer branch onto the new canonical branch; retain only changes not already included upstream, resolving any API differences.
  2. Rebase this TRT-LLM PR onto latest main, including the refreshed compatibility patch and integration changes.
  3. Keep vendors.flashinfer-prims-ts in 3rdparty/vendor_sources.lock.yaml pointing to your temporary source branch, update its immutable commit, and regenerate the selected vendored files and digests. Do not restore the old canonical branch/pin while resolving conflicts.
  4. Add the required <!-- vendor-promotion:start --> / <!-- vendor-promotion:end --> block to the PR description, listing upstream PRs for the remaining source changes (or a justified unpaired_reason). The vendor bot provides a copyable template.
  5. Verify the vendored snapshot and rerun the relevant tests and CI.

The publishing bot now targets the new dated canonical branch. After this source-update PR merges, its lock-only promotion will target that branch. The old trtllm-prims-ts-dev branch is intentionally unchanged.

@yunruis
yunruis force-pushed the user/yunruis/dsv4-prims-ts-sparse-mla branch from 8bcce6c to 3c1c7b6 Compare October 13, 2026 09:10
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/bot run --disable-fail-fast

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PR_Github #77488 [ run ] triggered by Bot. Commit: 3c1c7b6 Link to invocation

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PR_Github #77488 [ run ] completed with state SUCCESS. Commit: 3c1c7b6
/LLM/main/L0_MergeRequest_PR pipeline #63877 completed with status: 'SUCCESS'
Pipeline passed with automatic retried tests. Check the rerun report for details.

CI Report

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yuxianq dismissed their stale review October 15, 2026 03:10

Automated vendor metadata issue resolved; code review remains required.

@yunruis
yunruis marked this pull request as ready for review October 15, 2026 03:18
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yunruis requested review from a team as code owners October 15, 2026 03:18
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/bot run --disable-fail-fast --add-multi-gpu-test

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📒 Files selected for processing: 3
  • tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py
  • tests/integration/test_lists/test-db/l0_b200.yml
  • tests/unittest/_torch/attention/sparse/deepseek_v4/test_prims_ts_sparse_mla_fmha.py
🚧 Files skipped from review as they are similar to previous changes: 2
  • tests/unittest/_torch/attention/sparse/deepseek_v4/test_prims_ts_sparse_mla_fmha.py
  • tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py

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Walkthrough

This change adds a generation-only PrimTS sparse MLA FMHA adapter for DeepSeek-V4 on supported SM100 systems. It updates FlashInfer integration, prepares token-position metadata, registers the adapter by default, logs cached selections, and adds tests.

Changes

PrimTS Sparse MLA

Layer / File(s) Summary
Vendor source compatibility
3rdparty/vendor_sources.lock.yaml, 3rdparty/vendor_patches/flashinfer-prims-ts.patch
Updates the FlashInfer source pin and patch for vendored imports, API decorators, tracing behavior, resource imports, and MLA argument handling.
Adapter support and request validation
tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py
Adds hardware, toolchain, cache, tensor, layout, and request validation for the PrimTS sparse MLA backend.
Plan preparation and decode execution
tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py, tensorrt_llm/_torch/attention/backends/sparse/deepseek_v4/metadata.py
Adds cached pool views, sinks, scales, execution plans, and the forward path. Metadata allocates and copies token positions for all cache modes.
FMHA registration and validation
tensorrt_llm/_torch/attention/backends/fmha/__init__.py, tensorrt_llm/_torch/attention/backends/fmha/registry.py, tensorrt_llm/_torch/attention/backends/fmha/manager.py, tests/unittest/_torch/attention/sparse/deepseek_v4/test_prims_ts_sparse_mla_fmha.py, tests/unittest/_torch/attention/test_fmha_registry.py, tests/integration/test_lists/test-db/l0_b200.yml
Exports and registers the adapter before flashinfer_trtllm_gen. The adapter is included by default while prims_ts remains excluded. Tests cover registry behavior, availability, fused output, generation execution, and B200 test-list integration.

Priority: Normal

Estimated code review effort: 4 (Complex) | ~60 minutes

Sequence Diagram(s)

sequenceDiagram
  participant DeepseekV4Metadata
  participant PrimsTSSparseMlaFmha
  participant PrimTSDecodeWrapper
  participant OutputBuffers
  DeepseekV4Metadata->>PrimsTSSparseMlaFmha: provide token positions and sparse indices
  PrimsTSSparseMlaFmha->>PrimsTSSparseMlaFmha: validate request and prepare plan
  PrimsTSSparseMlaFmha->>PrimTSDecodeWrapper: launch planned decode
  PrimTSDecodeWrapper->>OutputBuffers: write output and scales
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Merge Risk: Minimal · up to 05eb7

No concrete merge-blocking risk remains in the supplied review scope.

Pre-merge checks: Passed 4 · Failed 1

Failed Failed checks: 1 warning

Check name Status Explanation Resolution
Docstring Coverage Warning Docstring coverage is 43.48% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 46 functions across 7 files. (1 skipped: … Write docstrings for the functions missing them to satisfy the coverage threshold.
Passed Passed checks: 4 passed
Check name Status Explanation
Title check Passed The title clearly summarizes the primary change: adding the PrimTS native sparse MLA FMHA backend for DeepSeek-V4 and enabling it by default on SM100.
Linked Issues check Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check Passed Check skipped because no linked issues were found for this pull request.
Description check Passed The pull request description is complete and follows the required structure. It clearly explains the motivation, implementation, scope, compatibility behavior, configuration knobs, vendor changes, per…
Full details: Description check

Explanation

The pull request description is complete and follows the required structure. It clearly explains the motivation, implementation, scope, compatibility behavior, configuration knobs, vendor changes, performance, startup impact, CI history, test coverage, and checklist status.

Full details: Docstring Coverage

Explanation

Docstring coverage is 43.48% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 46 functions across 7 files. (1 skipped: 1 unsupported.)

Resolution

Write docstrings for the functions missing them to satisfy the coverage threshold.

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Actionable comments posted: 1


  • 🪄 Fix comments: Fix CodeRabbit comments on this PR
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Inline comments:
Review comments at
@tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py:
- Around line 381-413: Update the `_pool_views` cache key in the view-building
flow to use the selected pool’s base pointer and `total_rows` instead of
`id(manager)`, retaining the attention type and compression ratio as needed to
distinguish pools. Ensure managers that reuse an object ID cannot retrieve a
cached view of freed memory.

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⛔ Files ignored due to path filters: 30
  • tensorrt_llm/_torch/attention/backends/prims_ts/__init__.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/constants.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/gather.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/layout.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/math.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/ops.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/output_quant.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/schedule.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/helpers/tile.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/kernel_policy.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/sparse_policy.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/sparse_views.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_2cta/config.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_2cta/kernel.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_2cta/parallel_reduction.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_2cta/resources.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_2cta/tasks.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/config.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/kernel.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/parallel_reduction.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/smem_p.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/smem_resources.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/tmem_corr.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/tmem_o.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/tmem_p.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/tmem_s.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/resources/tmem_softmax_stats.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/mla_decode/throughput_latency_1cta/tasks.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/kernels/separate_reduction.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
  • tensorrt_llm/_torch/attention/backends/prims_ts/mla_decode.py is excluded by !tensorrt_llm/_torch/attention/backends/prims_ts/**
📒 Files selected for processing: 8
  • 3rdparty/vendor_patches/flashinfer-prims-ts.patch
  • 3rdparty/vendor_sources.lock.yaml
  • tensorrt_llm/_torch/attention/backends/fmha/__init__.py
  • tensorrt_llm/_torch/attention/backends/fmha/prims_ts_sparse_mla.py
  • tensorrt_llm/_torch/attention/backends/fmha/registry.py
  • tensorrt_llm/_torch/attention/backends/sparse/deepseek_v4/metadata.py
  • tests/unittest/_torch/attention/sparse/deepseek_v4/test_prims_ts_sparse_mla_fmha.py
  • tests/unittest/_torch/attention/test_fmha_registry.py

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/bot run --disable-fail-fast --add-multi-gpu-test

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@yunruis
yunruis force-pushed the user/yunruis/dsv4-prims-ts-sparse-mla branch from 8e22202 to 5bcc368 Compare October 24, 2026 03:07
@yunruis
yunruis requested a review from a team as a code owner October 24, 2026 03:07
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yunruis requested review from arysef and nv-guomingz October 24, 2026 03:07
yunruis added a commit to yunruis/TensorRT-LLM that referenced this pull request Oct 24, 2026
…e opt-out and MTP rows, add release notes

Under the default launcher (`trtllm-llmapi-launch` and the `LLM()` MPI session)
every rank owns a private FlashInfer workspace, so the ranks of one host do not
share kernel compiles and each fans its warm-up out on its own. The per-rank
default of 4 precompile subprocesses therefore started 32 `cute.compile`
interpreters on a TP=8 node, each with a CUDA context. The default now follows
the ranks on the host: at most 4 per rank and 16 per host together (TP=8 runs 2
per rank); an explicit `TLLM_PRIMTS_WARM_WORKERS` is never capped. The module
note documents the host load.

The warm-up reads `max_num_requests`, `max_total_draft_tokens` and
`max_num_tokens` directly instead of through `getattr(..., 0)`, so a renamed
field fails at warm-up instead of silently shrinking the warmed set and moving
the MTP row counts' compiles to the first serving step.

Tests: the unified DeepSeek-V4 forward test now also runs with
`TLLM_FMHA_LIBS=-prims_ts_sparse_mla` and asserts that the TRTLLM-Gen fallback
serves generation with PrimTS never entered (the documented opt-out, and what
SM103 / fp8_ds_mla / NVFP4 deployments run); the module test's multi-token
generation cases (next_n 2 and 6, ragged 1/2/4) run with a spy asserting PrimTS
served them with one row per query token; a unit test asserts the warm set
covers `requests * (1 + draft)` rows and is bounded by the token budget; the
worker-count tests cover the per-host cap.

Release notes: the default flip, the opt-out, the first-launch compile cost
under per-rank workspaces, the `TLLM_PRIMTS_WARM_*` variables and the
`FLASHINFER_DISABLE_JIT=1` behavior.

Addresses the review by @brnguyen2 on NVIDIA#20209.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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/bot run --disable-fail-fast --add-multi-gpu-test

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yunruis commented Oct 24, 2026 •

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Thanks @brnguyen2 — all three addressed in c67aa5f (branch also rebased onto main f1d8a73):

  1. You are right about the per-rank workspaces. The description is corrected, and the default fan-out is now capped per host (4 per rank, 16 per host). Startup through the default LLM() MPI session (per-rank workspaces): the first start of a host costs about 9 min more with PrimTS (TP4 on 4x B100: 786 s vs 257 s warm fallback; TP8 on 8x B200: 872 s vs 327 s warm fallback, 1640 s vs 1071 s when the whole cache root is fresh), warm starts are the same or faster (294 s vs 327 s at TP8). My earlier +134 s figure compared a warm root against a fresh one and was wrong; the description has the corrected table. The cost is three back-to-back per-profile fan-outs (about 105 s of worker start-up each plus about 20 s per kernel), not the per-host cap: 4 or 8 workers per rank measure the same as 2, and in-process is 1040 s. Follow-up: one fan-out for all profiles and no dynamic-scale kernel compile, which should bring it to a few minutes.
  2. Added the opt-out (TLLM_FMHA_LIBS=-prims_ts_sparse_mla) test variant and MTP assertions on PrimTS (inline replies).
  3. Release notes added. There is no JIRA for this work, so the title stays [None].

The precompile machinery will be upstreamed to flashinfer; the vendor patch carries it until then.

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yunruis and others added 3 commits October 23, 2026 20:17
…th worker subprocesses

Without a compile cache, the first eager forward of each DeepSeek-V4 layer
profile warms every kernel variant the deployment can select (Flash: 12
variants, two kernels each; Pro: 19). FlashInfer's JitSpec.build_and_load()
holds the op-family file lock for the whole cute.compile, so the ranks of a
launch deduplicate but serialize: the warm-up wall clock is the sum of every
variant's compile time regardless of rank count (about 13 min for Flash on
B100, 10 min on B200), all of it inside LLM startup.

_warm_kernel_variants now probes the on-disk cache (a plan under the new
_compile_cache.probe_cached() mode raises KernelNotCached instead of
compiling) and, when a variant is missing, hands the deduplicated (rows,
extra) list to worker subprocesses first (prims_ts_precompile.py;
TLLM_PRIMTS_WARM_WORKERS, default 4, 0/1 disables; TLLM_PRIMTS_WARM_TIMEOUT
bounds the wait, default 1800 s). A worker runs the same wrapper.plan() under
_compile_cache.precompile_only(), which compiles through
JitSpecCuteDsl.compile_and_persist() -- cute.compile outside the module
lock, the artifact committed under it -- and returns a placeholder instead of
loading. A per-kernel file lock in FlashInfer's tmp directory makes every
kernel of a workspace compile once: worker i of N takes payload slots
i, i+N, ... first, then goes through the rest skipping kernels another
process holds (KernelBusy) and finishes with a blocking pass, so every worker
ends with every variant on disk whether the workspace is private to the rank
(TRT-LLM's default) or shared between ranks. Workers are plain interpreter
subprocesses with the MPI launcher environment removed (split_mpi_env();
importing tensorrt_llm initializes MPI) and the parent's exact sys.path,
because the cache key's cute_dsl_version is enumerated from it and a
different meta.json makes the parent treat the module as stale and wipe it.
Any failure (worker exit, timeout, cache disabled, FLASHINFER_DISABLE_JIT)
falls back to the in-process compile that ran before;
TLLM_PRIMTS_WARM_STRICT=1 turns it into an error for tests.

Measured on dlcluster 4u4g-gen-0097 (B100), cold FLASHINFER_WORKSPACE_BASE:
the 12 Flash variants take 770 s in-process versus 264 / 187 / 136 s with
4 / 8 / 12 workers, after which the serving process loads them in 2 s; the
DeepSeek-V4-Flash TP4 LLM becomes ready in 827 s instead of 1369 s. A warm
cache is unchanged (about 0.2 s per variant, no workers spawned).

Tests: the worker entry (own shard first, busy deferral), the runner with a
fake subprocess (environment, sys.path, slots, failure / cache-key mismatch /
timeout paths), the probe / persist / disabled modes of
build_and_load_attention_kernel, worker_count, and the adapter's
probe -> fan-out -> fallback -> strict behaviour.

AI-assisted.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Signed-off-by: yunruis <205571022+yunruis@users.noreply.github.com>
…equest check per geometry

Each eager DeepSeek-V4 decode layer paid about 140 us of host time in the
PrimTS sparse MLA adapter forward on B100 (4 ranks, eager, concurrency 8),
of which the wrapper's run() was about 100-120 us although the CUDA API
work inside it is 13 us (nsys: one cudaLaunchKernelExC, five
cuTensorMapEncodeTiled). The rest was Python: argument validation, pool
view construction, scalar tensors and the kernel's descriptor arguments,
rebuilt on every call although they only depend on the plan, the pools,
the scales and the sinks.

BatchSparseMLADecodePagedTSWrapper.run now records, at the end of a full
unfused BF16 launch with a caller-owned output, everything static for the
(pool storage, extra pool storage, sinks address, scales) tuple, and a
later validate=False call with the same tuple goes through _run_prepared:
it checks and views only the per-call query, index, length and output
tensors and launches the same compiled kernel with the recorded
arguments, byte-identical to the full path. One plan serves every layer
of a model and each layer has its own sinks parameter, so the prepared
launches are kept per key (bounded, cleared by plan()); a single slot
would be evicted at every layer and never hit.

The prepared launch is taken only for the shapes the adapter uses (one
query token per row, no packed query, no LSE, no fused output), and it
still checks the per-call tensors' device, contiguity and 16-byte
alignment. The wrapper change is a generic optimization of the vendored
FlashInfer tree; it ships in the vendor patch so the integration lands
together and will be sent upstream to flashinfer-ai/flashinfer as a
follow-up.

_resolve_sparse_mla_plan is memoized: it is a pure function of its
arguments, plan() copies the kernel before mutating it, and the warm-up
resolves it 128 times per profile.

The adapter runs the full _unsupported_reason re-check only when the
request geometry (metadata, query shape and dtype, index width, output
shape and dtype, fusion flag, token counts) differs from the last
accepted call; the manager already selected the library through
is_supported(). Attention sinks that are already contiguous FP32 per
head (DeepseekV4TrtllmAttention.attn_sink) are passed through, other
dtypes are converted once per source tensor.

Measured on dlcluster 4x B100 (exclusive node), DeepSeek-V4 Flash, TP4,
eager, before -> after:
  wrapper.run (1x B100 standalone, rows 32):      50 -> 20 us/call
  adapter forward per layer, host p50 (c8):      141 -> 91 us
  wrapper.run inside forward (cProfile, cum):    120 -> 48 us/call
  prepared-launch hits:                          0% -> 96% of calls
  decode ms/step (c8, 960 tokens, host-noisy):   132.3 -> 128.5
The remaining per-call cost is the adapter's own bookkeeping (pool views,
contract key, about 50 us) and the compiled launch (13 us of CUDA API).

Tests: test_prepared_launch_matches_the_full_path_per_layer (two sinks
sharing one plan both hit, bitwise equal to the full path, new pool or
sinks address falls back, plan() clears),
test_prepared_launch_single_pool_matches_the_full_path (SWA-only layers,
extra indices rejected), test_request_check_runs_once_per_geometry and
test_sinks_pass_through_or_are_prepared_once_per_layer.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Signed-off-by: yunruis <205571022+yunruis@users.noreply.github.com>
…e opt-out and MTP rows, add release notes

Under the default launcher (`trtllm-llmapi-launch` and the `LLM()` MPI session)
every rank owns a private FlashInfer workspace, so the ranks of one host do not
share kernel compiles and each fans its warm-up out on its own. The per-rank
default of 4 precompile subprocesses therefore started 32 `cute.compile`
interpreters on a TP=8 node, each with a CUDA context. The default now follows
the ranks on the host: at most 4 per rank and 16 per host together (TP=8 runs 2
per rank); an explicit `TLLM_PRIMTS_WARM_WORKERS` is never capped. The module
note documents the host load.

The warm-up reads `max_num_requests`, `max_total_draft_tokens` and
`max_num_tokens` directly instead of through `getattr(..., 0)`, so a renamed
field fails at warm-up instead of silently shrinking the warmed set and moving
the MTP row counts' compiles to the first serving step.

Tests: the unified DeepSeek-V4 forward test now also runs with
`TLLM_FMHA_LIBS=-prims_ts_sparse_mla` and asserts that the TRTLLM-Gen fallback
serves generation with PrimTS never entered (the documented opt-out, and what
SM103 / fp8_ds_mla / NVFP4 deployments run); the module test's multi-token
generation cases (next_n 2 and 6, ragged 1/2/4) run with a spy asserting PrimTS
served them with one row per query token; a unit test asserts the warm set
covers `requests * (1 + draft)` rows and is bounded by the token budget; the
worker-count tests cover the per-host cap.

Release notes: the default flip, the opt-out, the first-launch compile cost
under per-rank workspaces, the `TLLM_PRIMTS_WARM_*` variables and the
`FLASHINFER_DISABLE_JIT=1` behavior.

Addresses the review by @brnguyen2 on NVIDIA#20209.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Signed-off-by: yunruis <205571022+yunruis@users.noreply.github.com>
@yunruis
yunruis force-pushed the user/yunruis/dsv4-prims-ts-sparse-mla branch from 5bcc368 to c67aa5f Compare October 24, 2026 03:17
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/bot run --disable-fail-fast --add-multi-gpu-test

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PR_Github #80312 [ run ] completed with state FAILURE. Commit: c67aa5f
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PR_Github #80403 [ run ] completed with state FAILURE. Commit: c67aa5f
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/bot run --disable-fail-fast --add-multi-gpu-test

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PR_Github #80507 [ run ] completed with state SUCCESS. Commit: c67aa5f
/LLM/main/L0_MergeRequest_PR pipeline #66272 completed with status: 'SUCCESS'

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yunruis enabled auto-merge (squash) October 26, 2026 07:18
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yunruis removed the request for review from arysef October 26, 2026 07:19
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yunruis removed the request for review from yuanjingx87 October 26, 2026 07:30
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yunruis merged commit 178ac92 into NVIDIA:main Oct 26, 2026
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yuxianq added a commit that referenced this pull request Oct 26, 2026
Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com>
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