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1. verible verible Public

   Forked from chipsalliance/verible

   Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

   C++

2. xls xls Public

   Forked from google/xls

   XLS: Accelerated HW Synthesis

   C++

3. gz-sim gz-sim Public

   Forked from gazebosim/gz-sim

   Open source robotics simulator. The latest version of Gazebo.

   C++

4. navigation2 navigation2 Public

   Forked from ros-navigation/navigation2

   ROS 2 Navigation Framework and System

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5. FPGA-PID-Accelerator FPGA-PID-Accelerator Public

   RTL design:schedules many PID tasks across limited computing cores

   Verilog