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Optimise native CPU FFTs and modal diagnostic scheduling - #16
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Native CPU propagation was spending avoidable time in scalar FFTW codelets, long-row Raman plans and embedded transverse diagnostics at intermediate DOPRI5 stages. This change enables coherent NEON FFTW on Apple silicon, tunes persistent Raman planning/provider selection, and defers coarse modal diagnostics until their consumers need them.
Based on current
mainat174be2a, including merged #15. The diff contains only the native optimisation programme.Retained changes
SOLPROP_FFTW_PLAN=estimateremains available.Kernel schema 35, frontend signatures, canonical layouts, protected arithmetic and Accelerate BLAS are unchanged by this PR. GPU execution is unchanged. Plasma traversal, Cartesian tile and thread-sizing prototypes were rejected after bounded measurements; none is retained.
Lightweight performance evidence
Frozen baseline
9521a88versus tested native snapshotb3bdd0f, prescribed ten-step windows, alternating rounds. This is the approved lightweight campaign, not a standard-suite adoption verdict.The production-budget results satisfy the greater-than-5% and conservative-spread criteria. The ledger retains per-case ranges, setup costs, guards, noisy controls and roughly 1% GCC small-window costs. vDSP removal and the regressing Mac plasma traversal were rejected rather than averaged away.
These measurements predate integration with #15 and use their frozen dependency versions. No new timing claim is made for #15's startup or coupling changes. The merge changes no native source relative to the tested snapshot.
Validation
Detailed measurements and limitations are in
docs/dev/benchmarks.md, with build and policy documentation linked from the changelog. Baseline and rejected-prototype evidence remain preserved separately.