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fix(hip): skip the fused-path BF16-only marks when GGML_CUDA_DISABLE_FUSION is set - #834
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davide221 merged 1 commit intoOct 10, 2026
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…FUSION is set
On RDNA3.5 qwen4exp graphs the HC marking pass flags the combine-norm xn view and
the gate-mix dst as BF16-only. Both marks rely on ggml_cuda_hc_gate_mix, which only
runs when fusion is enabled; with GGML_CUDA_DISABLE_FUSION=1 the unfused xn*gate MUL
and gate-mix ops reach compute_forward's guard and every prefill of 512+ rows aborts
("MMB: ... reads/writes a BF16-only tensor ... through the unfused path").
Hoist the existing fusion_off flag (already used by the routed-GLU pass) and apply it
to those two passes too. The default fusion-on path is unchanged.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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October 10, 2026 06:33
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No issues found. Checked for bugs and logic errors in the changed code.
Reviewed 05515fb8 · 0 candidate issues checked, kept at ≥70% confidence · add the code-review label to review again
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Why
GGML_CUDA_DISABLE_FUSION=1is the switch we reach for when output looks wrong and we want to rule out a fused kernel. On Strix Halo (gfx1151, RDNA3.5) with a qwen4exp model it currently can't be used: every prefill of 512+ rows aborts inggml_cuda_compute_forwardwithCause
Before each graph runs, the qwen4exp HC marking pass in
ggml_backend_cuda_graph_computeflags some hyper-connection intermediates as BF16-only, so that they are stored only as BF16 and never in F32:HC_COMBINE_NORMxnview. One of the consumers it accepts is thexn*gateMUL, whichggml_cuda_hc_gate_mixfuses and which readsxnthrough the BF16 cache.dst, which is written as BF16 in place byggml_cuda_hc_gate_mix.Both marks assume
ggml_cuda_hc_gate_mixruns, but that kernel is only reached inside the!disable_fusionblock. With fusion off, the plain MUL and gate-mix ops touch the marked tensors, and the guard incompute_forwardaborts, as it should.The routed-GLU pass in the same block already accounts for this with a
fusion_offcheck. The two passes above were missed.Change
Hoist the existing
fusion_offflag to the top of the block and skip thexnand gate-mix marking passes when it is set. Unmarked tensors take the normal F32 path. The routed down-row F16 mark stays as it is: its only reader isHC_COMBINE_NORMitself, not a fused kernel.The default path (fusion on) is unchanged. The flags are evaluated once and the marking runs exactly as before.
Testing
ggml-cuda.cucompiles for gfx1151 (GGML_USE_HIP)GGML_CUDA_DISABLE_FUSION=1, prefill ≥512 rows: aborts before, runs afterThe on-device checks are pending: there's no qwen4exp model on the test box yet. This PR stays in draft until they're done.
🤖 Generated with Claude Code