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feat(core): support configurable f32/f64 precision for Cortex-M single-precision FPUs - #27

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feat/single-precision-fpu
Nov 2, 2026
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rahadbhuiya merged 7 commits into
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feat/single-precision-fpu

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Summary

Closes #23

Introduces a configurable floating-point precision architecture across aegis-filter. By default, the crate retains maximum double-precision f64 headroom for aerospace and desktop environments. Enabling the opt-in cargo feature single-precision switches core matrix arithmetic, filter states, covariances, and FFI bindings to single-precision f32.

This eliminates 5x–15x CPU software emulation penalties on ARM Cortex-M4 and Cortex-M33 flight controllers equipped only with single-precision hardware FPUs.

Key Changes

  1. Precision Abstraction (src/common.rs):
    • Added Real type alias (f64 by default, f32 under feature = "single-precision").
    • Extended FloatOps trait implementation to f32, including fast Newton-Raphson square root for #![no_std] targets.
  2. Core Modules Refactored to Real:
    • src/linear.rs: ScalarKalmanFilter and LinearKalmanFilter<S, M>
    • src/robust.rs: HInfinityFilter1D and AdaptiveFilter1D
    • src/unscented.rs: UnscentedKalmanFilter2D
    • src/eskf.rs: ErrorStateKalmanFilter, Vector3, and Quaternion
    • src/fusion.rs: MultiSensorFusion1D and SensorSource
    • src/stats.rs: WindowedStats<N>
    • src/ffi.rs: C-FFI wrapper structs and functions
  3. C-FFI Header (include/aegis_filter.h):
    • Introduced aegis_real typedef (defaults to double, switches to float when AEGIS_SINGLE_PRECISION is defined).
  4. CI & Verification (.github/workflows/ci.yml):
    • Added bare-metal compilation check for thumbv7em-none-eabihf with --features single-precision.
    • Added test suite validation with --features single-precision.

Verification

  • CI workflow runs both double-precision and single-precision bare-metal checks and unit tests.

@github-actions github-actions Bot added documentation Improvements or additions to documentation enhancement New feature or request ci Continuous integration and build workflows labels Nov 2, 2026
…e-precision FPUs

- Introduce Real type alias in src/common.rs (defaults to f64, switches to f32 with feature single-precision)
- Implement FloatOps for f32 with Newton-Raphson sqrt under #![no_std]
- Generalize filter state, covariance, and observation types across all modules (linear, robust, unscented, eskf, fusion, stats, ffi)
- Add AEGIS_SINGLE_PRECISION and aegis_real abstraction in include/aegis_filter.h
- Update CI workflow with bare-metal Cortex-M f32 compilation and test validation
- Closes #23
@rahadbhuiya
rahadbhuiya force-pushed the feat/single-precision-fpu branch from 514d85d to 6e87354 Compare November 2, 2026 06:29
@rahadbhuiya
rahadbhuiya merged commit 18c5d36 into main Nov 2, 2026
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@rahadbhuiya
rahadbhuiya deleted the feat/single-precision-fpu branch November 2, 2026 06:41
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feat(core): support configurable f32/f64 precision for Cortex-M single-precision FPUs

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