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Summary
Enable the existing two-bank capture/spectrum engine on ESP32-C5 for native USB, 256 bins, at 4 and 8 MS/s. Other profiles retain snapshot capture and their gap flags.
C5 circular capture works with the C61 dump registers/rate fields and C6 bank mapping. Pulsing the finite-capture trigger after circular start produces a short capture; the shared engine already uses the appropriate clear/start sequence without that pulse.
The important C5-specific constraint is whole-bank ownership: selecting the second destination also makes live heap/ROM data in its upper half inaccessible. This adds an 8 KiB LP-SRAM worker stack and static config/result handoff, reserves only the additional lower 64 KiB destination, and restores ownership before scheduling resumes. Existing SRAM linker assertions remain in place. Snapshot DSP/output reuses reserved bank 1 lower SRAM after finite capture instead of adding a second large BSS workspace or exhausting the remaining heap.
Also reduce C5 packet buffers for startup memory and match the existing bank-rotation targets’ interrupt/task-watchdog defaults. A sustained hardware run exposed a TG0 watchdog reset before the task-watchdog default was corrected.
Validation
Tested on one Waveshare ESP32-C5-LCD-1.47, ESP32-C5HF4 rev 1.0, 48 MHz crystal, 4 MB flash, no PSRAM; CPU 240 MHz, receiver 2412 MHz, pinned IDF 25fe69f946311abdaf9ad56591f25fedbc20ac98.
tools/check_spectrum.py --continuous-onlyallows reproducing sustained checks without running every snapshot profile. Detailed memory layout, results and commands are in docs/esp32c5-continuous.md.These are bounded measurements on one board/frequency. Hardware index/sentinel checks are not an external RF phase measurement, and this does not establish unlimited-duration stability, higher circular rates, other chip revisions, 5 GHz circular capture, physical UART fallback or LCD coexistence.