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[fpga] feat: 集成 ROB 优化与 PR10 修复并发布完整验证位流 - #10
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- program_arty.tcl / program_flash.tcl / backup_flash.tcl: check the return value of program_hw_devices / program_hw_cfgmem / readback_hw_cfgmem, which return 0 on failure instead of raising a Tcl error. Previously a failed JTAG program, flash program/verify, or flash readback still printed PASS and exited 0. - toy_a7_platform.sv: pass scu_bresp through unchanged instead of OR-reducing it, which turned SLVERR into EXOKAY on the B channel. - host/flash.py: replace assert-based integrity checks with explicit raises so verification is not compiled out under python -O.
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问题与结果
在当前Toy FPGA配置保留CPU、Sv39、FP16/32/64、Gemmini 8×8和23项Ball指令的前提下，合并ROB操作数BRAM优化与AXI/烧录修复。新增完整实现、RTL验证和可直接下载的UART/JTAG工程预发布，不改变默认寄存器ROB生成路径。
实现
完整验证与产物
下载说明：platforms/arty-a7-toy/ROB_PR10_DOWNLOADS.md。工程预发布：https://github.com/DangoSys/fpga/releases/tag/arty-a7-rob-pr10-2026-10-13 。提供完整UART包、位流、烧录Tcl、实现Tcl、源码/软件依赖/配置/许可包及摘要。
验收范围
用户选择当前ROB优化核心+#10修复，并确认本轮无法连接板卡，先上传实现/RTL验证的工程预发布。因此没有本次实板、真实DDR PHY、Flash冷启动、整模型或长期稳定性资格，不继承旧硬件结论。Linux/虚拟内存验证与物理总线错误同步trap保障不是同一能力。
验证输入提交5d20e94；发布源码9eaa676。位流SHA256：9f6f684361c049527fda09818cc8aa464f1067b75f3762305a27c5c738295942。只配置.bit仍需UART加载标准软件；旧Flash发布附件不替换。
队友从仓库直接运行
新增 platforms/arty-a7-toy/run_hardware.ps1 与中文 HARDWARE_TEST.md。队友指定串口和 Vivado 路径即可自动下载固定 ROB/PR10 UART 发布包、核对摘要，复用原 Linux/Gemmini 验证器完成 JTAG 配置、DDR 完整读回、Linux 启动和 15 程序回归；无需硬件/Linux 重建或研究服务器账号。
支持 -PrepareOnly（不访问硬件）和 -BundleZip（使用本地已下载包），缓存与每轮日志均写在 build/；真实验证设一小时超时。固定发布信息绑定原位流、镜像、源码和验证输入，不沿用旧位流默认哈希或旧 PASS。
本次已用实际 Release 包完成离线准备，并在 Windows PowerShell 5.1 从另一工作目录调用成功；源码/历史验证档案核验通过。未接板，不新增实板通过结论，也未替换既有 Release 资产。入口提交 ccb40f1；未合并时，中文指南提供取得 PR #10 的 Git 命令。