[fpga] feat: add standalone Arty A7 Pebble platform

[Cody-ic]

Summary

Add a standalone Arty A7-100T platform that runs a Chisel-generated RocketBB CPU, Buckyball frontend/DMA, SMatMul 8x16, MatAdd and ReLU with actual FPGA peripherals. The new board implementation provides AXI BRAM, UART MMIO, a CRC-checked serial program loader with host readback, MMCM/reset logic, pin constraints, bare-metal firmware and programming scripts.

The platform targets xc7a100tcsg324-1 at 50 MHz, with 128 KiB program/data BRAM and eight 512x128-bit scratchpad banks. It is independent of the K7 DDR/MIG and P2E harnesses. Existing chip configurations and build flows are unchanged.

The example explicitly pins Buckyball 1f3d545 and five dependency commits. Its bootstrap exports and verifies 264 original source blobs; upstream CPU, DMA and operator implementations remain unchanged. Generated RTL, dependencies, firmware binaries and FPGA build products are excluded from Git.

Validation

• Clean Chisel elaboration and source/hash audit passed; removing unused FireSim targetutils preserved byte-identical RTL.
• Four XSim interface suites and four Python host protocol tests passed.
• Full-system Verilator test passed in 1,724,701 cycles: cold resident boot before upload, serial upload/readback, CPU/MMIO/DMA, all three operators, echo, new input seed and reset.
• Vivado 2024.1 synthesis, placement, routing and bitstream generation passed. Routed WNS +1.004 ns, WHS +0.018 ns, TNS/THS 0.
• Resources: 43,405 LUT, 24,253 FF, 65.5 BRAM tiles, 12 DSP48E1 for the complete chip.
• All nine pins, IO standards and the 50 MHz clock audited; no latches/blackboxes; CDC 3 safe and 0 unsafe/unknown crossings; DRC 0 errors and 17 DSP pipeline performance warnings.
• Applicable installed formatting/lint hooks passed directly. The pre-commit wrapper could not fetch a hook repository through the server proxy.

The verification also fixed a test coverage gap: resident firmware now boots before any serial upload can mask a missing BRAM initialization image. Details and compact evidence are in examples/fpga/arty-a7/VALIDATION.md and validation/.

Remaining acceptance

Physical board programming and USB UART acceptance have not been performed. This is a bare-metal BRAM platform; DDR, Ethernet and Linux are outside this change. The accelerated UART simulation cycle count is a test duration, not an accelerator performance measurement.

[gitguardian]

⚠️ GitGuardian has uncovered 1 secret following the scan of your pull request.

Please consider investigating the findings and remediating the incidents. Failure to do so may lead to compromising the associated services or software components.

Since your pull request originates from a forked repository, GitGuardian is not able to associate the secrets uncovered with secret incidents on your GitGuardian dashboard.
Skipping this check run and merging your pull request will create secret incidents on your GitGuardian dashboard.

🔎 Detected hardcoded secret in your pull request

GitGuardian id	GitGuardian status	Secret	Commit	Filename
-	-	Generic High Entropy Secret	7b080eb	examples/fpga/arty-a7/UPSTREAM_MANIFEST.json	View secret

🛠 Guidelines to remediate hardcoded secrets

1. Understand the implications of revoking this secret by investigating where it is used in your code.
2. Replace and store your secret safely. Learn here the best practices.
3. Revoke and rotate this secret.
4. If possible, rewrite git history. Rewriting git history is not a trivial act. You might completely break other contributing developers' workflow and you risk accidentally deleting legitimate data.

To avoid such incidents in the future consider

• following these best practices for managing and storing secrets including API keys and other credentials
• install secret detection on pre-commit to catch secret before it leaves your machine and ease remediation.

---

^{🦉 GitGuardian detects secrets in your source code to help developers and security teams secure the modern development process. You are seeing this because you or someone else with access to this repository has authorized GitGuardian to scan your pull request.}