Skip to content

Simulated Jetson #34

Description

@maxwildersmith

Add a simulated jetson file that access data over the simulated I2C bus, waits a while and sends the 10.5 all ok signal, then waits a little longer to send a randomly generated benchmark result packet.

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

Labels

researchResearch assignment in prep for future featuresshortShould be done by the next meeting/within a week

Type

No type

Projects

No projects

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions