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Aideiv
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remove md
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#30:
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feat(fpga+arm): expose per-event flow to ARM via AXI4-Lite FLOW bundl…
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june10: add company-wide commit sprint planning doc
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communist manifesto
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fix: add TYPE_CHECKING import for EventFrameTemporalStack
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fix: indentation error in evasion_controller.py _determine_level
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fix: clean CI workflow - skip Vitis/g++ compilation, add config.yaml …
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fix: remove Python setup from FPGA testbench job
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fix: add Python setup to FPGA testbench CI job
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fix: CI workflow resilience + golden model test adjacency fix
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fix: rewrite testbench with correct types and format specifiers
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fix: CI compatibility - validate mode checks vkm.A key, get_adj_matri…
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testbench
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fix: resolve moderate and minor issues from SYSTEM_ANALYSIS.md
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fix: resolve 7 critical bugs identified in SYSTEM_ANALYSIS.md
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fix
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fix
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realign: symmetric FPGA/ARM box columns, straight right border
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final: symmetric FPGA/ARM boxes
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docs: realign DRONE MAIN LOOP diagram to consistent 74-char width
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ci: fix all 4 failing CI jobs
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fix: realign DRONE MAIN LOOP ASCII art box borders (PIPELINE 1 overflow)
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readme: move demo.gif visual above fold (after Abstract images)
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reorder: move VecKM Normal Flow API (+ Demo, Egomotion) above Archite…
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