[AdaWorldAPI]

D-DRIVER-ZC-0: one virtual access membrane, five zero-copy bus lenses

DOCS / BOARD / PRE-REGISTERED FALSIFIERS ONLY. No new runtime, public API, F###, row-ID map, register ISA, GPU driver, remote endpoint or speedup claim. Do not auto-merge.

Operator insight

Apply the ndarray SIMD polyfill architectural move to data access. Rather than auditing approximately 17,000 call sites for repeated copies, use one typed, source-owned BIND → PROJECT → STREAM → EXECUTE → RELEASE contract over the existing sealed DR address/frame. The driver is a virtual access membrane, not a replacement cognitive shader or CPU ISA.

Five views XX, XY, XZ, YY, ZZ project typed roles from the same witnessed canonical X/Y/Z SoA address; they do not build five stored bus matrices or materialize row/PSCustomObject values in the admitted fold. Foreign global→local navigation is counted once under owner admission, never a silent hash-table substitute.

Three separate proof scopes

1. Resident borrowed source: no owned canonical payload copies or row reconstruction on the admitted hot path; scratch and result masks are separately counted.
2. Virtual bus geometry: multiple typed lenses share one source address; correct composition keeps intermediate values virtual under existing mask-risc scratch epochs.
3. Data-owner remote execution: a remote caller sends a typed instruction and receives only admitted result bytes; no network/RDMA zero-copy or universal O(1) claim.

Storage page fetch/decompression, Lance S-INGRESS, network serialization and explicit result egress remain physical costs. Same-address fixed-field access can be O(1) per resolved resident row; global routing, K-row folds, all-pairs relations and N-row output are not generally O(1). A correct zero-allocation calculation can still fail layout/scope semantics.

Existing evidence and ownership

• The zero-copy lens law is the controlling operator ruling. No implicit copied value/array escape hatch.
• D-DRISA-1 (lab): a sealed DR frame as a local register file over borrowed SoA #1955 is merged: D-DRISA-1 local borrowed register/SoA fixture, frame/layout/source and reuse; no bus, disk or remote proof.
• D-DRISA-3 (lab): threshold, Kleene and Bag on the shipped carry words (stacked on #1955) #1956 is merged: Abakus carry words exact but 1.5–4.8× slower than native alternatives across eight measured shapes; do not force Abakus as default.
• lab: D-GLOBAL-WHERE P1/P2 — criteria-aware WHERE, DR composition, Lance selective read, three parity verdicts #1950 shows Lance ingress and prepared-route costs, but lab: D-GLOBAL-WHERE P1/P2 — criteria-aware WHERE, DR composition, Lance selective read, three parity verdicts #1950's binding included gathered copied lanes and DR→Lance is still BLOCKED_D4.
• docs(D-DRISA-0): remote DR register / Abakus ALU / async cognitive shader staged architecture #1953 is merged architecture. This new plan does not implement or replace D-DRISA-2/4 async driver stages.
• EXO-46/89/151/140 source/foreign lease and D4/S-INGRESS/EXO-114 physical authority remain gated. EXO-104/105/109 own tuple and oracle risks.

The seven changed files

• .claude/plans/d-driver-zc-virtual-bus-contract-v1.md: architectural model, precise ZC-A/B/C law, logical buses, source and lifetime witnesses, restricted "Thinking Hard Drive" theorem schema, clear anti-hype conditions.
• .claude/plans/d-driver-zc-staged-pr-charter-v1.md: ZC-0 through ZC-7 independent PR intentions with exact prerequisites, test fixtures, owners and STOP conditions. Only ZC-0 is opened.
• .claude/plans/d-driver-zc-falsifier-matrix-v1.md: 47 independently proposed tests, V1–12, Z1–10, F1–9, S1–8, E1–8. None executed or overcredited.
• Permanent board entry plus STATUS_BOARD, INTEGRATION_PLANS and generated entries/README index, preserving all existing curated findings.

What review should decide

1. Can a sealed, owner-validated access capability enforce no intermediate owned canonical values for a declared migrated consumer root, without auditing all historical callers individually?
2. Can five virtual bus roles and multi-step compositions share the same DR binding/lane owners without inventing new storage or semantic operators?
3. Is local co-addressing plus bound-once reuse sufficient before considering an EXO-46-owned source index?
4. Which exact owner admission is required for cross-source navigation, result continuation and storage-backed execution?

Deliberately deferred by operator: Do not investigate/consolidate the migrated ladybug-rs/cognitive-shader-driver / P64 / StreamDTO / BusDTO / PerturbationDTO stack in this PR. A future one-canonical-surface decision is separate.

Coordination: EXO-154 is the new zero-copy bus work tracker; EXO-153 is existing D-DRISA program; EXO-50 append-only handoff, not operator authorization.

Please review as architecture/pre-registration only. No implementation or merge is authorized by a passing check.

[coderabbitai]

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Review	Status	Commit	Review trigger
📝 Code Review	✅ Completed 2026-11-04T10:02:13.334493Z	f45cefb	Draft marked ready

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