[AdaWorldAPI]

What

lance-graph's R2IL plan held W2 until OGAR, as the mint authority, chose how a custom address space enters the 0xC4 address. This PR records the choice in the ledger as D-R2IL-SPACE-AXIS, next to the existing 0xC4 binary-lifting entries.

Decided: option 3 of the three W0 named. A custom address space moves out of the classid into the payload or edge, keyed by the architecture's identity and version. The classid's space discriminant carries only the architecture-invariant fixed spaces 0–3.

Basis, measured

• W0's census found 0 custom spaces in 94,536 x86 rows.
• On the real 6502 spec there is 1 custom space, OTHER, once r2sleigh docs(openproject): two-arm pattern + nexgen convergence + knowable_from pin #16 stops the case-sensitive alias map from minting the 6502's RAM as Custom(1).
• Option 1, the architecture in every address: would spend classid bits on every row for that one case.
• Option 2, the raw SLEIGH space id: is a per-architecture counter, so it still collides across architectures.

The entry carries DECISION, BASIS, SCOPE and REVISIT WHEN. Nothing is minted. The carving itself belongs to ruff_r2il facet.rs PR 3.

Related

Repo	PR	What it does
lance-graph	#1443	Updates the plan's W2 row and Q2/Q3, and adds the board entry with the measurement
r2sleigh	#16	The case-insensitive space-name fix

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[chatgpt-codex-connector]

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Review	Status	Commit	Review trigger
📝 Code Review	✅ Completed 2026-10-10T10:16:40.958569Z	568f9bf	PR opened

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