From 5d4b214154f3c4572c196ca04f05252f757542a3 Mon Sep 17 00:00:00 2001 From: Tobias Frauenschlaeger Date: Tue, 27 Oct 2026 17:17:23 +0000 Subject: [PATCH] Do not require for aarch64 CPU feature detection The aarch64 Linux path in cpuid.c included the kernel header for the HWCAP_* bits. On musl distributions such as Alpine that header only exists with the linux-headers package installed, so --enable-armasm and --enable-all-asm failed on aarch64 while x86 builds needed nothing extra. Take the bits from and define any the C library lacks, the same way the 32-bit ARM path already does. musl does not define HWCAP2_SME, so without the fallback SME would never be detected there. With every bit now defined, the HWCAP_ASIMDRDM, HWCAP_SVE and HWCAP2_SME guards around their checks are dropped. The Fil-C workflow gave the missing header as the reason its aarch64 legs build with --disable-asm. With this change the aarch64 asm build compiles under Fil-C, but sp_div_word's inline assembly panics at run time: v0.684 has no aarch64 inline assembly, and v0.687 rejects the shifted register operands in sp_div_word ("x5, lsr 1" and twice "%[hi], lsl 32"). The comment now names sp_div_word instead. --- .github/workflows/fil-c.yml | 9 ++------ wolfcrypt/src/cpuid.c | 46 +++++++++++++++++++++++++++++++------ 2 files changed, 41 insertions(+), 14 deletions(-) diff --git a/.github/workflows/fil-c.yml b/.github/workflows/fil-c.yml index 698afe5f17d..55752c09ff7 100644 --- a/.github/workflows/fil-c.yml +++ b/.github/workflows/fil-c.yml @@ -40,13 +40,8 @@ jobs: # says nothing about them. The C implementations of the same # algorithms are covered by the other legs. # - # There is no aarch64 counterpart to the 'default, asm' leg either. - # Leaving assembly on for an aarch64 host makes configure define - # WOLFSSL_AARCH64_BUILD, so cpuid.h defines HAVE_CPUID_AARCH64 and - # cpuid.c includes , a Linux kernel header that Fil-C's - # sysroot does not ship. That is a property of the sysroot, not of - # wolfSSL, and there is no way to keep the assembly while dropping the - # CPU id, so the aarch64 legs stay on --disable-asm. + # No aarch64 'default, asm' leg, since Fil-C panics on the inline + # assembly of sp_div_word in sp_int.c. include: - name: 'default' config: '' diff --git a/wolfcrypt/src/cpuid.c b/wolfcrypt/src/cpuid.c index d4ceb4c9d9f..bd20dea294f 100644 --- a/wolfcrypt/src/cpuid.c +++ b/wolfcrypt/src/cpuid.c @@ -338,7 +338,44 @@ * posts/runtime-detection-of-cpu-features-on-an-armv8-a-cpu */ #include - #include + + /* Kernel values, for C libraries that lack them. */ + #ifndef AT_HWCAP2 + #define AT_HWCAP2 26 + #endif + #ifndef HWCAP_ASIMD + #define HWCAP_ASIMD (1 << 1) + #endif + #ifndef HWCAP_AES + #define HWCAP_AES (1 << 3) + #endif + #ifndef HWCAP_PMULL + #define HWCAP_PMULL (1 << 4) + #endif + #ifndef HWCAP_SHA2 + #define HWCAP_SHA2 (1 << 6) + #endif + #ifndef HWCAP_ASIMDRDM + #define HWCAP_ASIMDRDM (1 << 12) + #endif + #ifndef HWCAP_SHA3 + #define HWCAP_SHA3 (1 << 17) + #endif + #ifndef HWCAP_SM3 + #define HWCAP_SM3 (1 << 18) + #endif + #ifndef HWCAP_SM4 + #define HWCAP_SM4 (1 << 19) + #endif + #ifndef HWCAP_SHA512 + #define HWCAP_SHA512 (1 << 21) + #endif + #ifndef HWCAP_SVE + #define HWCAP_SVE (1 << 22) + #endif + #ifndef HWCAP2_SME + #define HWCAP2_SME (1 << 23) + #endif static WC_INLINE void cpuid_set_flags(void) { @@ -364,7 +401,7 @@ if (hwcaps & HWCAP_SHA512) new_cpuid_flags |= CPUID_SHA512; #endif - #if defined(HWCAP_ASIMDRDM) && !defined(WOLFSSL_AARCH64_NO_SQRDMLSH) + #ifndef WOLFSSL_AARCH64_NO_SQRDMLSH if (hwcaps & HWCAP_ASIMDRDM) new_cpuid_flags |= CPUID_RDM; #endif @@ -380,17 +417,12 @@ if (hwcaps & HWCAP_SM4) new_cpuid_flags |= CPUID_SM4; #endif - #ifdef HWCAP_SVE if (hwcaps & HWCAP_SVE) new_cpuid_flags |= CPUID_SVE; - #endif - #ifdef HWCAP2_SME /* SME is reported in the second HWCAP word. */ if (getauxval(AT_HWCAP2) & HWCAP2_SME) new_cpuid_flags |= CPUID_SME; - #endif - (void)hwcaps; (void)wolfSSL_Atomic_Uint_CompareExchange (&cpuid_flags, &old_cpuid_flags, new_cpuid_flags); }