diff --git a/platform/aarch64/sysoul_x3300-scmi/README.md b/platform/aarch64/sysoul_x3300-scmi/README.md new file mode 100644 index 000000000..925ef6efd --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/README.md @@ -0,0 +1,102 @@ +# sysoul_x3300-scmi — RK3588 Linux Multi-Zone (NPU + GPU + VOP/HDMI) + +## Overview + +The `sysoul_x3300-scmi` platform is the **Linux / VirtIO-SCMI variant** of +the `sysoul_x3300` platform (the original Android configuration stays in +`platform/aarch64/sysoul_x3300`). It targets the same **Rockchip RK3588** +SoC board with a multi-zone Linux deployment: + +- **Zone 0 (root)**: runs the root Linux, the `hvisor.ko` driver and + `hvisor-tool`, which provide the VirtIO-SCMI back-end, virtio console, + block and network devices for the non-root zones. +- **Zone 1**: dedicated to the **NPU** (Cortex-A76 cores 6, 7). +- **Zone 2**: dedicated to the **GPU + VOP + HDMI display** (cores 4, 5). + +## Zone Layout + +| Zone | CPUs | Devices | SCMI resources | +|------|------|---------|----------------| +| **Zone 1 (npu)** | 6, 7 | RKNPU, virtio-blk/net/console | clocks 0-7, resets 0-5, power 0-2 | +| **Zone 2 (gpu)** | 4, 5 | Mali GPU, VOP2, HDMI0, HD-PHY, VOP IOMMU | clocks 8-11, power 3 | + +## Configurations (`configs/`) + +| File | Purpose | +|------|---------| +| `zones-npu-gpu-virtio.json` | Launch Zone 1 (NPU) and Zone 2 (GPU) simultaneously | +| `zone1-linux-npu.json` | NPU zone (Zone 1) | +| `zone2-linux-gpu-hdmi.json` | GPU + VOP + HDMI display zone (Zone 2, 2 GB RAM) | + +## Device Trees (`image/dts/`) + +| File | Purpose | +|------|---------| +| `sysoul_iron.dts` | Board-level device tree (used by u-boot and the root zone) | +| `zone0.dts` | Root zone; declares the `hvisor_virtio_device` node listing the SCMI-exposed clocks/resets/power domains | +| `zone1-linux-npu.dts` | NPU zone: NPU + reserved DMA pool | +| `zone2-linux-gpu-hdmi.dts` | GPU + display zone: GPU, VOP2, HDMI0, hdmiphy, VOP IOMMU | + +## Zone 1: NPU Passthrough + +| Resource | Details | +|----------|---------| +| MMIO | `0xfdab0000` + `0xfdac0000` + `0xfdad0000` (3 × 64 KB) | +| IRQs (INTID) | 0x8e, 0x8f, 0x90 | +| SCMI | clocks 0-7, resets 0-5, power domains 0-2 | +| DMA | Reserved memory pool at `0x38000000` (64 MB, shared-dma-pool, no-IOMMU mode) | + +The NPU uses a `shared-dma-pool` reserved region instead of the +`rockchip,iommu-v2` IOMMU. + +## Zone 2: GPU + VOP + HDMI Passthrough + +| Resource | Details | +|----------|---------| +| GPU MMIO | `0xfb000000` (2 MB), GPU GRF `0xfd5a0000`, PVTM `0xfdb30000` | +| GPU IRQs (INTID) | JOB=0x7e, MMU=0x7d, GPU=0x7c | +| GPU SCMI | clocks 8-11, power domain 3 | +| RAM | 2 GB at `0x58000000` – `0xd8000000` (IOVAs == PAs via `dma-ranges`) | +| VOP2 | `0xfdd90000`, VOP IOMMU `0xfdd97e00` (passthrough, translated) | +| HDMI | HDMI0 TX `0xfde80000`, HD-PHY `0xfed60000`, plus sys/ioc GRF | + +The display pipeline (VOP2 + HDMI0 + hdptx-phy) is fully passed through and +**translated by the VOP IOMMU**, with the display clocks (including +`hdmi0_phy_pll`) delivered through VirtIO-SCMI. The zone2 DTS keeps +`hdmiphy0` disabled on the root side so the clock is not touched by zone0. + +### Display notes (verified on hardware) + +- The vop2 `plane-mask` of the display zone is `0x3cf` (all 12 windows + assigned to VP0). u-boot leaves stale VOP windows enabled (e.g. Esmart1/3 + pointing at its logo buffer); the vop2 driver only disables windows that + belong to the driven VP's plane mask, and only when the mode changes. + Assigning every window to VP0 lets any mode switch disable all of them, + otherwise stale windows keep faulting through the IOMMU and the screen + stays green. +- Do **not** set `iommu.passthrough=1` for this zone: the VOP IOMMU must + translate the front buffers, and passthrough leaves the iommu group + domain in a state that breaks re-attach after a mode switch. +- glmark2 runs fullscreen at 4K60 directly after boot (no pre-mode-switch + needed): `glmark2-es2-drm`. + +## Build & Deploy + +```bash +make all BID=aarch64/sysoul_x3300-scmi +``` + +Compile the device trees with `dtc` (see `image/dts/Makefile`), then boot +via u-boot: load `hvisor.bin` with `bootm`, which starts the root zone; +the zones are launched by `hvisor-tool` on the root zone using the JSON +configs above (adjust `kernel_filepath` / `dtb_filepath` to the deployed +file names). + +## Verification + +- **Zone 1 (NPU)**: check `rknpu` probe in the zone kernel and run an NPU + workload (e.g. rknn-toolkit-lite). +- **Zone 2 (GPU/display)**: `glmark2-es2-drm` should report 4K60 FPS with + no `Page fault` / `POST_BUF_EMPTY` in dmesg; `modetest -M rockchip -s + @:` mode switches should complete without + `-EBUSY` or `rk_iommu_force_reset` timeouts. diff --git a/platform/aarch64/sysoul_x3300-scmi/board.rs b/platform/aarch64/sysoul_x3300-scmi/board.rs new file mode 100644 index 000000000..cb75bec37 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/board.rs @@ -0,0 +1,503 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use crate::pci_dev; +use crate::{ + arch::{ + mmu::MemoryType, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, + }, + config::*, + pci::vpci_dev::VpciDevType, +}; + +pub const BOARD_NAME: &str = "sysoul-x3300"; + +pub const BOARD_NCPUS: usize = 8; +pub const BOARD_UART_BASE: u64 = 0xfeb5_0000; + +#[rustfmt::skip] +pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ + 0x000, // cpu0 + 0x100, // cpu1 + 0x200, // cpu2 + 0x300, // cpu3 + 0x400, // cpu4 + 0x500, // cpu5 + 0x600, // cpu6 + 0x700, // cpu7 +]; + +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b111; BOARD_NCPUS]; + +/// The physical memory layout of the board. +/// Each address should align to 2M (0x20_0000). +/// Addresses must be in ascending order. +#[rustfmt::skip] +pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ + // ( start, end, type) + ( 0x0000_0000, 0x0020_0000, MemoryType::Device), // Includes low-address SRAM, marked as Device + ( 0x0020_0000, 0x0840_0000, MemoryType::Normal), + ( 0x0940_0000, 0xf000_0000, MemoryType::Normal), + ( 0xf000_0000, 0x1_0000_0000, MemoryType::Device), // Dense device region, marked as Device. + (0x1_0000_0000, 0x3_fc00_0000, MemoryType::Normal), + // (0x3_fc50_0000, 0x3_fff0_0000, MemoryType::Normal), + (0x3_fc40_0000, 0x4_0000_0000, MemoryType::Normal), // aligned to 2 MiB + (0x4_f000_0000, 0x5_0000_0000, MemoryType::Normal), +]; + +pub const ROOT_ZONE_DTB_ADDR: u64 = 0x2000_0000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x2040_0000; +pub const ROOT_ZONE_ENTRY: u64 = 0x2040_0000; +pub const ROOT_ZONE_CPUS: u64 = (1 << 2) - 1; + +pub const ROOT_ZONE_NAME: &str = "root-linux"; + +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ + // /proc/iomem System RAM + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0020_0000, + virtual_start: 0x0020_0000, + size: 0x0820_0000, + }, + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x0940_0000, + // virtual_start: 0x0940_0000, + // size: 0xe6c0_0000, + // }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0940_0000, + virtual_start: 0x0940_0000, + size: 0x06c0_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x1000_0000, + virtual_start: 0x1000_0000, + size: 0x1000_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2000_0000, + virtual_start: 0x2000_0000, + size: 0x2000_0000, + }, // zone0 kernel/dtb area + // Zone1 RAM: 0x3000_0000 - 0x4000_0000 (assigned to zone1) + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x4000_0000, + virtual_start: 0x4000_0000, + size: 0xb000_0000, + }, + // Zone1 RAM (large block) + Zone0 RAM + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x1_0000_0000, + virtual_start: 0x1_0000_0000, + size: 0x2_fc00_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x3_fc50_0000, + virtual_start: 0x3_fc50_0000, + size: 0x03a0_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x4_f000_0000, + virtual_start: 0x4_f000_0000, + size: 0x1000_0000, + }, + // Ramoops + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0011_0000, + virtual_start: 0x0011_0000, + size: 0x000f_0000, + }, + // /proc/iomem Devices I/O + // GPU region (0xfb00_0000-0xfb20_0000) moved to zone1 + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0xfb00_0000, + // virtual_start: 0xfb00_0000, + // size: 0x0020_0000, + // }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfc00_0000, + virtual_start: 0xfc00_0000, + size: 0x15a_4000, // fc000000..fd5a4000 + }, + // VOP-GRF: keep in root zone for DDR MCU access + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd5a_4000, + virtual_start: 0xfd5a_4000, + size: 0x2000, // fd5a4000..fd5a6000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd5a_6000, + virtual_start: 0xfd5a_6000, + size: 0x7ea_000, // fd5a6000..fdd90000 + }, + // VOP: keep in root zone for DDR MCU line-flag synchronization + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfdd9_0000, + virtual_start: 0xfdd9_0000, + size: 0x8000, // fdd90000..fdd98000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfdd9_8000, + virtual_start: 0xfdd9_8000, + size: 0x26_8000, // fdd98000..fe000000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfe00_0000, + virtual_start: 0xfe00_0000, + size: 0x0060_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfea0_0000, + virtual_start: 0xfea0_0000, + size: 0x0050_0000, + }, + // SRAM and Other Devices + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x0010_f000, + virtual_start: 0x0010_f000, + // size: 0x0100, // 10f000.sram + size: 0x1000, // aligned with page size + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xff00_1000, + virtual_start: 0xff00_1000, + size: 0x000e_e000, //ff001000.sram + }, + // Unknown Region, maybe we should ask vendor for help + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x0010_0000, + virtual_start: 0x0010_0000, + size: 0xf000, + }, + // Unknown Region, maybe we should ask vendor for help + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xa_0000_0000, + virtual_start: 0xa_0000_0000, + size: 0x1_0000_0000, + }, +]; + +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 0x27, // arm-pmu + 0x69, // dmc + 0x2d, // timer + 0x2e, // timer + 0x2b, // timer + 0x2a, // timer + // GPU IRQs moved to zone1: + // 0x7e, // gpu@fb000000 + // 0x7d, // gpu@fb000000 + // 0x7c, // gpu@fb000000 + 0xfc, // usb@fc000000 + 0xf7, // usb@fc800000 + 0xf8, // usb@fc840000 + 0xfa, // usb@fc880000 + 0xfb, // usb@fc8c0000 + 0x191, // iommu@fc900000 + 0x193, // iommu@fc900000 + 0x196, // iommu@fc900000 + 0x18f, // iommu@fc900000 + 0x19d, // iommu@fcb00000 + 0x19f, // iommu@fcb00000 + 0x1a2, // iommu@fcb00000 + 0x19b, // iommu@fcb00000 + 0xfe, // usb@fcd00000 + 0x1a9, // usb2-phy@0 + 0x1a7, // usb2-phy@8000 + 0x1a8, // usb2-phy@c000 + 0x15d, // i2c@fd880000 + 0x16b, // serial@fd890000 + 0x178, // pwm@fd8b0000 + 0x178, // pwm@fd8b0010 + 0x178, // pwm@fd8b0020 + 0x178, // pwm@fd8b0030 + 0x179, // pwm@fd8b0030 + // NPU IRQs moved to zone1: + // 0x8e, // npu@fdab0000 + // 0x8f, // npu@fdab0000 + // 0x90, // npu@fdab0000 + // 0x8e, // iommu@fdab9000 + // 0x8f, // iommu@fdab9000 + // 0x90, // iommu@fdab9000 + 0x98, // vepu@fdb50000 + 0x97, // vdpu@fdb50400 + 0x96, // iommu@fdb50800 + 0x97, // avsd-plus@fdb51000 + 0x92, // rga@fdb60000 + 0x92, // iommu@fdb60f00 + 0x93, // rga@fdb70000 + 0x93, // iommu@fdb70f00 + 0x94, // rga@fdb80000 + 0xa1, // jpegd@fdb90000 + 0xa2, // iommu@fdb90480 + 0x9a, // jpege-core@fdba0000 + 0x99, // iommu@fdba0800 + 0x9c, // jpege-core@fdba4000 + 0x9b, // iommu@fdba4800 + 0x9e, // jpege-core@fdba8000 + 0x9d, // iommu@fdba8800 + 0xa0, // jpege-core@fdbac000 + 0x9f, // iommu@fdbac800 + 0x95, // iep@fdbb0000 + 0x95, // iommu@fdbb0800 + 0x85, // rkvenc-core@fdbd0000 + 0x83, // iommu@fdbdf000 + 0x84, // iommu@fdbdf000 + 0x88, // rkvenc-core@fdbe0000 + 0x86, // iommu@fdbef000 + 0x87, // iommu@fdbef000 + 0x7f, // rkvdec-core@fdc38000 + 0x80, // iommu@fdc38700 + 0x81, // rkvdec-core@fdc48000 + 0x82, // iommu@fdc48700 + 0x8c, // av1d@fdc70000 + 0x8b, // av1d@fdc70000 + 0x8a, // av1d@fdc70000 + 0x8d, // iommu@fdca0000 + 0xa7, // rkisp-unite@fdcb0000 + 0xa9, // rkisp-unite@fdcb0000 + 0xaa, // rkisp-unite@fdcb0000 + 0xa3, // rkisp@fdcb0000 + 0xa5, // rkisp@fdcb0000 + 0xa6, // rkisp@fdcb0000 + 0xa4, // rkisp-unite-mmu@fdcb7f00 + 0xa8, // rkisp-unite-mmu@fdcb7f00 + 0xa4, // iommu@fdcb7f00 + 0xa7, // rkisp@fdcc0000 + 0xa9, // rkisp@fdcc0000 + 0xaa, // rkisp@fdcc0000 + 0xa8, // iommu@fdcc7f00 + 0xab, // rkispp@fdcd0000 + 0xac, // iommu@fdcd0f00 + 0xad, // rkispp@fdcd8000 + 0xae, // iommu@fdcd8f00 + 0xbb, // rkcif@fdce0000 + 0x91, // iommu@fdce0800 + 0xaf, // mipi0-csi2@fdd10000 + 0xb0, // mipi0-csi2@fdd10000 + 0xb1, // mipi1-csi2@fdd20000 + 0xb2, // mipi1-csi2@fdd20000 + 0xb3, // mipi2-csi2@fdd30000 + 0xb4, // mipi2-csi2@fdd30000 + 0xb5, // mipi3-csi2@fdd40000 + 0xb6, // mipi3-csi2@fdd40000 + // 0xbc, // vop@fdd90000 — moved to zone1 + // 0xbc, // iommu@fdd97e00 — moved to zone1 + 0xe3, // spdif-tx@fddb0000 + 0xd8, // i2s@fddc0000 + 0xe4, // spdif-tx@fdde0000 + 0xd9, // i2s@fddf0000 + 0xdd, // i2s@fddfc000 + 0xe7, // spdif-rx@fde08000 + 0xc7, // dsi@fde20000 + 0xc8, // dsi@fde30000 + 0xbf, // hdcp@fde40000 + 0xc1, // dp@fde50000 + 0xc0, // hdcp@fde70000 + // 0xc9, // hdmi@fde80000 — moved to zone1 + // 0xca, // hdmi@fde80000 — moved to zone1 + // 0xcb, // hdmi@fde80000 — moved to zone1 + // 0xcc, // hdmi@fde80000 — moved to zone1 + // 0x188, // hdmi@fde80000 — moved to zone1 + 0xc3, // edp@fdec0000 + 0x118, // pcie@fe180000 + 0x117, // pcie@fe180000 + 0x116, // pcie@fe180000 + 0x115, // pcie@fe180000 + 0x114, // pcie@fe180000 + 0x115, // legacy-interrupt-controller + 0x11d, // pcie@fe190000 + 0x11c, // pcie@fe190000 + 0x11b, // pcie@fe190000 + 0x11a, // pcie@fe190000 + 0x119, // pcie@fe190000 + 0x11a, // legacy-interrupt-controller + 0x10a, // ethernet@fe1c0000 + 0x109, // ethernet@fe1c0000 + 0x131, // sata@fe210000 + 0x133, // sata@fe230000 + 0xee, // spi@fe2b0000 + 0xeb, // mmc@fe2c0000 + 0xec, // mmc@fe2d0000 + 0xed, // mmc@fe2e0000 + 0xf1, // crypto@fe370000 + 0x1b0, // rng@fe378000 + 0xd4, // i2s@fe470000 + 0xd5, // i2s@fe480000 + 0xd6, // i2s@fe490000 + 0xd7, // i2s@fe4a0000 + 0xea, // vad@fe4d0000 + 0xe1, // spdif-tx@fe4e0000 + 0xe2, // spdif-tx@fe4f0000 + 0x29, // interrupt-controller@fe600000 + 0x76, // dma-controller@fea10000 + 0x77, // dma-controller@fea10000 + 0x78, // dma-controller@fea30000 + 0x79, // dma-controller@fea30000 + 0x175, // can@fea50000 + 0x176, // can@fea60000 + 0x177, // can@fea70000 + 0x75, // decompress@fea80000 + 0x15e, // i2c@fea90000 + 0x15f, // i2c@feaa0000 + 0x160, // i2c@feab0000 + 0x161, // i2c@feac0000 + 0x162, // i2c@fead0000 + 0x141, // timer@feae0000 + 0x15b, // watchdog@feaf0000 + 0x166, // spi@feb00000 + 0x167, // spi@feb10000 + 0x168, // spi@feb20000 + 0x169, // spi@feb30000 + 0x16c, // serial@feb40000 + 0x16d, // serial@feb50000 + 0x16e, // serial@feb60000 + 0x16f, // serial@feb70000 + 0x170, // serial@feb80000 + 0x171, // serial@feb90000 + 0x172, // serial@feba0000 + 0x173, // serial@febb0000 + 0x174, // serial@febc0000 + 0x17a, // pwm@febd0000 + 0x17a, // pwm@febd0010 + 0x17a, // pwm@febd0020 + 0x17a, // pwm@febd0030 + 0x17b, // pwm@febd0030 + 0x17c, // pwm@febe0000 + 0x17c, // pwm@febe0010 + 0x17c, // pwm@febe0020 + 0x17c, // pwm@febe0030 + 0x17d, // pwm@febe0030 + 0x17e, // pwm@febf0000 + 0x17e, // pwm@febf0010 + 0x17e, // pwm@febf0020 + 0x17e, // pwm@febf0030 + 0x17f, // pwm@febf0030 + 0x1ad, // tsadc@fec00000 + 0x1ae, // saradc@fec10000 + 0x5d, // mailbox@fec60000 + 0x5e, // mailbox@fec60000 + 0x5f, // mailbox@fec60000 + 0x60, // mailbox@fec60000 + 0x65, // mailbox@fec70000 + 0x66, // mailbox@fec70000 + 0x67, // mailbox@fec70000 + 0x68, // mailbox@fec70000 + 0x163, // i2c@fec80000 + 0x164, // i2c@fec90000 + 0x165, // i2c@feca0000 + 0x16a, // spi@fecb0000 + 0x6d, // mailbox@fece0000 + 0x6e, // mailbox@fece0000 + 0x6f, // mailbox@fece0000 + 0x70, // mailbox@fece0000 + 0x7a, // dma-controller@fed10000 + 0x7b, // dma-controller@fed10000 + 0x135, // gpio@fd8a0000 + 0x136, // gpio@fec20000 + 0x137, // gpio@fec30000 + 0x138, // gpio@fec40000 + 0x139, // gpio@fec50000 + 0xfd, // usb@fc400000 + 0x1aa, // usb2-phy@4000 + 0xb7, // mipi4-csi2@fdd50000 + 0xb8, // mipi4-csi2@fdd50000 + 0xb9, // mipi5-csi2@fdd60000 + 0xba, // mipi5-csi2@fdd60000 + 0xe6, // spdif-tx@fddb8000 + 0xdc, // i2s@fddc8000 + 0xe5, // spdif-tx@fdde8000 + 0xda, // i2s@fddf4000 + 0xdb, // i2s@fddf8000 + 0xde, // i2s@fde00000 + 0xe8, // spdif-rx@fde10000 + 0xe9, // spdif-rx@fde18000 + 0xc2, // dp@fde60000 + // 0xcd, // hdmi@fdea0000 — moved to zone1 + // 0xce, // hdmi@fdea0000 — moved to zone1 + // 0xcf, // hdmi@fdea0000 — moved to zone1 + // 0xd0, // hdmi@fdea0000 — moved to zone1 + // 0x189, // hdmi@fdea0000 — moved to zone1 + 0xc4, // edp@fded0000 + 0xd1, // hdmirx-controller@fdee0000 + 0x1d4, // hdmirx-controller@fdee0000 + 0xd3, // hdmirx-controller@fdee0000 + 0x127, // pcie@fe150000 + 0x126, // pcie@fe150000 + 0x125, // pcie@fe150000 + 0x124, // pcie@fe150000 + 0x123, // pcie@fe150000 + 0x124, // legacy-interrupt-controller + 0x122, // pcie@fe160000 + 0x121, // pcie@fe160000 + 0x120, // pcie@fe160000 + 0x11f, // pcie@fe160000 + 0x11e, // pcie@fe160000 + 0x11f, // legacy-interrupt-controller + 0x113, // pcie@fe170000 + 0x112, // pcie@fe170000 + 0x111, // pcie@fe170000 + 0x110, // pcie@fe170000 + 0x10f, // pcie@fe170000 + 0x110, // legacy-interrupt-controller + 0x103, // ethernet@fe1b0000 + 0x102, // ethernet@fe1b0000 + 0x132, // sata@fe220000 + 0x1c7, // fiq-debugger + 0x40, // hvisor_virtio_device +]); + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + is_aarch32: 0, + uefi_config: UefiConfig::NoUefi, + gic_config: GicConfig::Gicv3(Gicv3Config { + gicd_base: 0xfe60_0000, + gicd_size: 0x0001_0000, + gicr_base: 0xfe68_0000, + gicr_size: 0x0010_0000, + gits_base: 0x0, + gits_size: 0x0, + }), +}; + +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; + +pub const ROOT_PCI_DEVS: [HvPciDevConfig; 0] = []; diff --git a/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml b/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml new file mode 100644 index 000000000..85e2f56c7 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml @@ -0,0 +1,7 @@ +[target.aarch64-unknown-none] +runner = "platform/__ARCH__/__BOARD__/test/runner.sh" +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Ctarget-feature=+a72,+v8a,+strict-align,-neon,-fp-armv8", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json b/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json new file mode 100644 index 000000000..0bdd11420 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json @@ -0,0 +1,104 @@ +{ + "arch": "arm64", + "name": "zone1-npu", + "zone_id": 1, + "cpus": [ + 6, + 7 + ], + "memory_regions": [ + { + "type": "io", + "physical_start": "0x00100000", + "virtual_start": "0x00100000", + "size": "0xf000" + }, + { + "type": "ram", + "physical_start": "0x30000000", + "virtual_start": "0x30000000", + "size": "0x10000000" + }, + { + "type": "ram", + "physical_start": "0x100000000", + "virtual_start": "0x100000000", + "size": "0x1fc000000" + }, + { + "type": "virtio", + "physical_start": "0xff9c0000", + "virtual_start": "0xff9c0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xff9d0000", + "virtual_start": "0xff9d0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xff9e0000", + "virtual_start": "0xff9e0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa00000", + "virtual_start": "0xffa00000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdab0000", + "virtual_start": "0xfdab0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfdac0000", + "virtual_start": "0xfdac0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfdad0000", + "virtual_start": "0xfdad0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd588000", + "virtual_start": "0xfd588000", + "size": "0x1000" + } + ], + "interrupts": [ + "0x44", + "0x41", + "0x42", + "0x43", + "0x45", + "0x8e", + "0x8f", + "0x90" + ], + "ivc_configs": [], + "kernel_filepath": "./202605-Image", + "dtb_filepath": "./202608-sysoul_iron_zone1-linux-npu.dtb", + "kernel_load_paddr": "0x30400000", + "dtb_load_paddr": "0x30000000", + "entry_point": "0x30400000", + "kernel_args": "", + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfe600000", + "gicd_size": "0x10000", + "gicr_base": "0xfe680000", + "gicr_size": "0x100000", + "gits_base": "0x0", + "gits_size": "0x0" + }, + "pci_config": [] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json b/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json new file mode 100644 index 000000000..015a354a9 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json @@ -0,0 +1,151 @@ +{ + "arch": "arm64", + "name": "zone2-gpu-hdmi", + "zone_id": 2, + "cpus": [ + 4, + 5 + ], + "memory_regions": [ + { + "type": "io", + "physical_start": "0x00100000", + "virtual_start": "0x00100000", + "size": "0xf000" + }, + { + "type": "ram", + "physical_start": "0x58000000", + "virtual_start": "0x58000000", + "size": "0x80000000" + }, + { + "type": "io", + "physical_start": "0xfb000000", + "virtual_start": "0xfb000000", + "size": "0x200000" + }, + { + "type": "io", + "physical_start": "0xfd5a0000", + "virtual_start": "0xfd5a0000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdb30000", + "virtual_start": "0xfdb30000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdd90000", + "virtual_start": "0xfdd90000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfde80000", + "virtual_start": "0xfde80000", + "size": "0x20000" + }, + { + "type": "io", + "physical_start": "0xfed60000", + "virtual_start": "0xfed60000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd5a8000", + "virtual_start": "0xfd5a8000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5a6000", + "virtual_start": "0xfd5a6000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5e0000", + "virtual_start": "0xfd5e0000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5f0000", + "virtual_start": "0xfd5f0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd58c000", + "virtual_start": "0xfd58c000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa10000", + "virtual_start": "0xffa10000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa20000", + "virtual_start": "0xffa20000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa30000", + "virtual_start": "0xffa30000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa50000", + "virtual_start": "0xffa50000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5a4000", + "virtual_start": "0xfd5a4000", + "size": "0x2000" + } + ], + "interrupts": [ + "0x66", + "0x67", + "0x68", + "0x69", + "0x7e", + "0x7d", + "0x7c", + "0xbc", + "0xc9", + "0xca", + "0xcb", + "0xcc", + "0x188" + ], + "ivc_configs": [], + "kernel_filepath": "./202605-Image", + "dtb_filepath": "./202608-sysoul_iron_zone2-linux-gpu-hdmi.dtb", + "kernel_load_paddr": "0x58400000", + "dtb_load_paddr": "0x58000000", + "entry_point": "0x58400000", + "kernel_args": "", + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfe600000", + "gicd_size": "0x10000", + "gicr_base": "0xfe680000", + "gicr_size": "0x100000", + "gits_base": "0x0", + "gits_size": "0x0" + }, + "pci_config": [] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json b/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json new file mode 100644 index 000000000..cbb2102f3 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json @@ -0,0 +1,180 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x30000000", + "zonex_ipa": "0x30000000", + "size": "0x10000000" + }, + { + "zone0_ipa": "0x100000000", + "zonex_ipa": "0x100000000", + "size": "0x1fc000000" + } + ], + "devices": [ + { + "type": "scmi", + "addr": "0xff9c0000", + "len": "0x200", + "irq": "0x44", + "status": "enable", + "clock_ids": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7 + ], + "reset_ids": [ + 0, + 1, + 2, + 3, + 4, + 5 + ], + "power_ids": [ + 0, + 1, + 2 + ] + }, + { + "type": "blk", + "addr": "0xff9d0000", + "len": "0x200", + "irq": "0x41", + "img": "202605-rootfs.img", + "status": "enable" + }, + { + "type": "console", + "addr": "0xff9e0000", + "len": "0x200", + "irq": "0x42", + "status": "enable" + }, + { + "type": "net", + "addr": "0xffa00000", + "len": "0x200", + "irq": "0x45", + "tap": "tap0", + "mac": [ + "0x00", + "0x11", + "0x22", + "0x33", + "0x44", + "0x55" + ], + "status": "enable" + } + ] + }, + { + "id": 2, + "memory_region": [ + { + "zone0_ipa": "0x58000000", + "zonex_ipa": "0x58000000", + "size": "0x80000000" + } + ], + "devices": [ + { + "type": "scmi", + "addr": "0xffa10000", + "len": "0x200", + "irq": "0x66", + "status": "enable", + "clock_ids": [ + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 35, + 36 + ], + "power_ids": [ + 3, + 4, + 5 + ], + "reset_ids": [ + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16, + 17, + 18, + 19, + 20, + 21, + 22 + ] + }, + { + "type": "blk", + "addr": "0xffa20000", + "len": "0x200", + "irq": "0x67", + "img": "202605-rootfs-gpu.img", + "status": "enable" + }, + { + "type": "console", + "addr": "0xffa30000", + "len": "0x200", + "irq": "0x68", + "status": "enable" + }, + { + "type": "net", + "addr": "0xffa50000", + "len": "0x200", + "irq": "0x69", + "tap": "tap1", + "mac": [ + "0x00", + "0x11", + "0x22", + "0x33", + "0x44", + "0x66" + ], + "status": "enable" + } + ] + } + ] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile b/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile new file mode 100644 index 000000000..2f795e7fe --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts new file mode 100644 index 000000000..367728f2d --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts @@ -0,0 +1,6128 @@ +/dts-v1/; + +/ { + serial-number = "c377a354961ceca2"; + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Rockchip RK3588 XIUOS Board"; + + memory { + reg = <0x0 0x200000 0x0 0x8200000 0x0 0x9400000 0x0 0xe6c00000 0x1 0x0 0x2 0xfc000000 0x3 0xfc500000 0x0 0x3a00000 0x4 0xf0000000 0x0 0x10000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + device_type = "memory"; + }; + + aliases { + csi2dcphy0 = "/csi2-dcphy0"; + csi2dcphy1 = "/csi2-dcphy1"; + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + dsi0 = "/dsi@fde20000"; + dsi1 = "/dsi@fde30000"; + ethernet1 = "/ethernet@fe1c0000"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + i2c0 = "/i2c@fd880000"; + i2c1 = "/i2c@fea90000"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + i2c4 = "/i2c@feac0000"; + i2c5 = "/i2c@fead0000"; + i2c6 = "/i2c@fec80000"; + i2c7 = "/i2c@fec90000"; + i2c8 = "/i2c@feca0000"; + rkcif_mipi_lvds0 = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + jpege0 = "/jpege-core@fdba0000"; + jpege1 = "/jpege-core@fdba4000"; + jpege2 = "/jpege-core@fdba8000"; + jpege3 = "/jpege-core@fdbac000"; + serial0 = "/serial@fd890000"; + serial1 = "/serial@feb40000"; + serial2 = "/serial@feb50000"; + serial3 = "/serial@feb60000"; + serial4 = "/serial@feb70000"; + serial5 = "/serial@feb80000"; + serial6 = "/serial@feb90000"; + serial7 = "/serial@feba0000"; + serial8 = "/serial@febb0000"; + serial9 = "/serial@febc0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + spi3 = "/spi@feb30000"; + spi4 = "/spi@fecb0000"; + spi5 = "/spi@fe2b0000"; + hdcp0 = "/hdcp@fde40000"; + hdcp1 = "/hdcp@fde70000"; + csi2dphy3 = "/csi2-dphy3"; + csi2dphy4 = "/csi2-dphy4"; + csi2dphy5 = "/csi2-dphy5"; + dp0 = "/dp@fde50000"; + dp1 = "/dp@fde60000"; + edp0 = "/edp@fdec0000"; + edp1 = "/edp@fded0000"; + ethernet0 = "/ethernet@fe1b0000"; + hdptx0 = "/phy@fed60000"; + hdptx1 = "/phy@fed70000"; + hdptxhdmi0 = "/hdmiphy@fed60000"; + hdptxhdmi1 = "/hdmiphy@fed70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi1 = "/hdmi@fdea0000"; + hdmirx0 = "/hdmirx-controller@fdee0000"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + usbdp0 = "/phy@fed80000"; + usbdp1 = "/phy@fed90000"; + mmc0 = "/mmc@fe2e0000"; + mmc1 = "/mmc@fe2c0000"; + mmc2 = "/mmc@fe2d0000"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + spll { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x29d7ab80>; + clock-output-names = "spll"; + }; + + xin32k { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + }; + + hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x264>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x5>; + }; + + aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08b0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x26d>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x4>; + }; + + hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a8 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x264>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c087c 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x141>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x3>; + }; + + aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a8 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x263>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0868 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1e1>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0868 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1e0>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a4 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a4 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08b0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08c0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1c5>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08c0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1c4>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x26c>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x263>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0910 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0910 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c092c 0x0 0x10>; + clock-names = "link"; + clocks = <0x3>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x4>; + clocks = <0x4>; + clock-names = "link"; + #clock-cells = <0x0>; + phandle = <0x5f>; + }; + + pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x4>; + clocks = <0x5>; + clock-names = "link"; + #clock-cells = <0x0>; + phandle = <0x60>; + }; + + mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s2_mclkin"; + }; + + mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s3_mclkin"; + }; + + mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x39>; + #clock-cells = <0x0>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0x0>; + rockchip,bit-set-to-disable; + phandle = <0x139>; + }; + + mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x291>; + #clock-cells = <0x0>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <0x1>; + rockchip,bit-set-to-disable; + }; + + mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x28>; + #clock-cells = <0x0>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <0x2>; + rockchip,bit-set-to-disable; + }; + + mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x2e>; + #clock-cells = <0x0>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <0x7>; + rockchip,bit-set-to-disable; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x6>; + }; + + core1 { + cpu = <0x7>; + }; + + core2 { + cpu = <0x8>; + }; + + core3 { + cpu = <0x9>; + }; + }; + + cluster1 { + core0 { + cpu = <0xa>; + }; + + core1 { + cpu = <0xb>; + }; + }; + + cluster2 { + core0 { + cpu = <0xc>; + }; + + core1 { + cpu = <0xd>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x11>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x64>; + cpu-supply = <0x12>; + mem-supply = <0x12>; + phandle = <0x6>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x13>; + phandle = <0x7>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x14>; + phandle = <0x8>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x15>; + phandle = <0x9>; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x2>; + operating-points-v2 = <0x16>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x17>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x12c>; + cpu-supply = <0x18>; + mem-supply = <0x18>; + phandle = <0xa>; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x2>; + operating-points-v2 = <0x16>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x19>; + phandle = <0xb>; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x3>; + operating-points-v2 = <0x1a>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x12c>; + cpu-supply = <0x1c>; + mem-supply = <0x1c>; + phandle = <0xc>; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x3>; + operating-points-v2 = <0x1a>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0xd>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x14>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x15>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x1f 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + rockchip,pvtm-voltage-sel = <0x0 0x582 0x0 0x583 0x59a 0x1 0x59b 0x5b2 0x2 0x5b3 0x5ca 0x3 0x5cb 0x5e2 0x4 0x5e3 0x5fa 0x5 0x5fb 0x270f 0x6>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x159b40>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xf4 0xf4>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <0x21>; + rockchip,dsu-grf = <0x22>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,reboot-freq = <0x159b40>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x188940>; + phandle = <0xf>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-1608000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1704000000 { + opp-supported-hw = <0x2 0xffff>; + opp-hz = <0x0 0x6590fa00>; + opp-microvolt = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L1 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L2 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L3 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L4 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L5 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L6 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x23 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x3>; + rockchip,grf = <0x24>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x16>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = <0x0 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = <0x0 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = <0x0 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = <0x0 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x25 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x3>; + rockchip,grf = <0x26>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x1a>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = <0x0 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = <0x0 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = <0x0 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = <0x0 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x1 0x7 0x8>; + interrupt-affinity = <0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x27 0x28 0x29>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + csi2-dphy0 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <0x2c>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0x2d>; + data-lanes = <0x1 0x2 0x3 0x4>; + phandle = <0x13f>; + }; + }; + + port@1 { + reg = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x2e>; + phandle = <0xbd>; + }; + }; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <0x2f>; + memory-region = <0x30>; + memory-region-names = "drm-logo"; + + route { + route-dsi0 { + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x0>; + video,flags = <0xa>; + video,vrefresh = <0x4b>; + video,crtc_vsync_end = <0x265>; + video,crtc_hsync_end = <0x4aa>; + video,vdisplay = <0x258>; + video,hdisplay = <0x400>; + video,clock = <0xfde8>; + logo,ymirror = <0x0>; + logo,bpp = <0x10>; + logo,height = <0x10e>; + logo,width = <0x28e>; + logo,offset = <0x61000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x32>; + }; + + route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x35>; + }; + }; + }; + + dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = <0x0 0x49 0x4>; + interrupt-names = "complete"; + devfreq-events = <0x39>; + clocks = <0xe 0x4>; + clock-names = "dmc_clk"; + operating-points-v2 = <0x3a>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x1 0x4 0x8 0x8 0x2 0x1 0x10 0x4 0x10000 0x4 0x80000 0x4 0x1000 0x8 0x4000 0x8 0x2000 0x8 0xc00 0x8 0x40000 0x8>; + auto-freq-en = <0x1>; + status = "okay"; + center-supply = <0x3b>; + mem-supply = <0x3c>; + }; + + dmc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x3d>; + nvmem-cell-names = "leakage"; + rockchip,leakage-voltage-sel = <0x1 0x1f 0x0 0x20 0x2c 0x1 0x2d 0x39 0x2 0x3a 0xfe 0x3>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + phandle = <0x3a>; + + opp-528000000 { + opp-hz = <0x0 0x1f78a400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xb71b0>; + }; + + opp-1068000000 { + opp-hz = <0x0 0x3fa86300>; + opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xb71b0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xb71b0>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>; + }; + + opp-1560000000 { + opp-hz = <0x0 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xb71b0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + + opp-2750000000 { + opp-hz = <0x0 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + shmem = <0x3e>; + arm,smc-id = <0x82000010>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x1>; + assigned-clocks = <0xe 0x0 0xe 0x2 0xe 0x3>; + assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; + phandle = <0xe>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <0x1>; + phandle = <0x10d>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "okay"; + phandle = <0xa6>; + }; + + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0xc>; + rockchip,resetgroup-count = <0x1>; + status = "okay"; + phandle = <0xa1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x3f>; + iommus = <0x40>; + status = "okay"; + phandle = <0x45>; + + port { + endpoint { + remote-endpoint = <0x44>; + phandle = <0xbe>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x45>; + status = "okay"; + + port { + endpoint { + remote-endpoint = <0x46>; + phandle = <0x49>; + }; + }; + }; + + rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x48>; + status = "okay"; + + port { + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x49>; + phandle = <0x46>; + }; + }; + }; + + rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "okay"; + phandle = <0xac>; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <0x1>; + rockchip,sleep-mode-config = <0x5000604>; + rockchip,wakeup-config = <0x100>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + sustainable-power = <0x834>; + thermal-sensors = <0x4d 0x0>; + + trips { + trip-point-0 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + }; + + trip-point-1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x4e>; + }; + + soc-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <0x4e>; + cooling-device = <0x6 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map1 { + trip = <0x4e>; + cooling-device = <0xa 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map2 { + trip = <0x4e>; + cooling-device = <0xc 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map3 { + trip = <0x4e>; + cooling-device = <0x4f 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + }; + }; + + bigcore0-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x1>; + }; + + bigcore1-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x2>; + }; + + littlecore-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x3>; + }; + + center-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x4>; + }; + + gpu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x5>; + }; + + npu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x10f000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x10f000 0x100>; + + sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + phandle = <0x3e>; + }; + }; + + gpu@fb000000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xfb000000 0x0 0x200000>; + interrupts = <0x0 0x5e 0x4 0x0 0x5d 0x4 0x0 0x5c 0x4>; + interrupt-names = "GPU\0MMU\0JOB"; + clocks = <0xe 0x5 0x2 0x115 0x2 0x116 0x2 0x114>; + clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu"; + assigned-clocks = <0xe 0x5>; + assigned-clock-rates = <0xbebc200>; + power-domains = <0x50 0xc>; + operating-points-v2 = <0x51>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0xba6>; + upthreshold = <0x1e>; + downdifferential = <0xa>; + status = "okay"; + mali-supply = <0x52>; + mem-supply = <0x52>; + phandle = <0x4f>; + }; + + gpu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x53 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0xc3500>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + clocks = <0x2 0x114>; + clock-names = "clk"; + rockchip,grf = <0x54>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0x61a80>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0xc3500>; + phandle = <0x51>; + + opp-300000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x1a3 0x2 0x1a2 0x2 0x1a1>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <0x0 0xdc 0x4>; + power-domains = <0x50 0x1f>; + resets = <0x2 0x2a4>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <0x55 0x56>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + }; + }; + + usb@fc800000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <0x0 0xd7 0x4>; + clocks = <0x2 0x19d 0x2 0x19e 0x57>; + clock-names = "usbhost\0arbiter\0utmi"; + companion = <0x58>; + phys = <0x59>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + }; + + usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <0x0 0xd8 0x4>; + clocks = <0x2 0x19d 0x2 0x19e 0x57>; + clock-names = "usbhost\0arbiter\0utmi"; + phys = <0x59>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + phandle = <0x58>; + }; + + usb@fc880000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <0x0 0xda 0x4>; + clocks = <0x2 0x19f 0x2 0x1a0 0x5a>; + clock-names = "usbhost\0arbiter\0utmi"; + companion = <0x5b>; + phys = <0x5c>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + }; + + usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <0x0 0xdb 0x4>; + clocks = <0x2 0x19f 0x2 0x1a0 0x5a>; + clock-names = "usbhost\0arbiter\0utmi"; + phys = <0x5c>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + phandle = <0x5b>; + }; + + usbhost3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x179 0x2 0x178 0x2 0x177 0x2 0x17a 0x2 0x166 0x2 0x181>; + clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <0x0 0xde 0x4>; + resets = <0x2 0x237>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <0x5d 0x4>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + }; + }; + + syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd588000 0x0 0x2000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + mode-quiescent = <0x5242c30e>; + }; + }; + + syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf\0syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + phandle = <0xf7>; + }; + + syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + phandle = <0xb1>; + }; + + syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + phandle = <0x24>; + }; + + syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + phandle = <0x26>; + }; + + syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf\0syscon"; + reg = <0x0 0xfd594000 0x0 0x100>; + phandle = <0x21>; + }; + + syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf\0syscon"; + reg = <0x0 0xfd598000 0x0 0x100>; + phandle = <0x22>; + }; + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x0 0xfd5a0000 0x0 0x100>; + phandle = <0x54>; + }; + + syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf\0syscon"; + reg = <0x0 0xfd5a2000 0x0 0x100>; + phandle = <0x9f>; + }; + + syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf\0syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + phandle = <0xc0>; + }; + + syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <0x5f>; + phandle = <0xe7>; + }; + + syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <0x60>; + phandle = <0xc1>; + }; + + syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf\0syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + phandle = <0x61>; + }; + + syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf\0syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + phandle = <0x63>; + }; + + syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + phandle = <0x178>; + }; + + syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + phandle = <0x1af>; + }; + + syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + phandle = <0x179>; + }; + + syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + phandle = <0x17a>; + }; + + syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + phandle = <0x174>; + }; + + syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + phandle = <0x173>; + + usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <0x0 0x189 0x4>; + resets = <0x2 0xc0047 0x2 0x488>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0x0>; + rockchip,usbctrl-grf = <0x61>; + status = "okay"; + phandle = <0x175>; + + otg-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x55>; + }; + }; + }; + + syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0x0 0x187 0x4>; + resets = <0x2 0xc0049 0x2 0x48a>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0x0>; + status = "okay"; + phandle = <0x57>; + + host-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x59>; + }; + }; + }; + + syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0x0 0x188 0x4>; + resets = <0x2 0xc004a 0x2 0x48b>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0x0>; + status = "okay"; + phandle = <0x5a>; + + host-port { + #phy-cells = <0x0>; + status = "okay"; + phy-supply = <0x62>; + phandle = <0x5c>; + }; + }; + }; + + syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + phandle = <0x172>; + }; + + syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + phandle = <0x176>; + }; + + syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + phandle = <0x177>; + }; + + syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc\0syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + phandle = <0x17b>; + }; + + clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <0x63>; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + assigned-clocks = <0x2 0x9 0x2 0x5 0x2 0x8 0x2 0x7 0x2 0xd8 0x2 0xda 0x2 0xd9 0x2 0x10e 0x2 0x10f 0x2 0x110 0x2 0x299 0x2 0x29a 0x2 0x7b 0x2 0xec 0x2 0x114 0x2 0x208 0x2 0x20e>; + assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00>; + phandle = <0x2>; + }; + + i2c@fd880000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + clocks = <0x2 0x287 0x2 0x286>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x13d 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x64>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x18>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x1c>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + serial@fd890000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <0x0 0x14b 0x4>; + clocks = <0x2 0x2ae 0x2 0x2af>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0x66 0x6 0x66 0x7>; + pinctrl-names = "default"; + pinctrl-0 = <0x67>; + status = "okay"; + }; + + pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + interrupts = <0x0 0x158 0x4>; + #pwm-cells = <0x3>; + pinctrl-names = "active"; + pinctrl-0 = <0x69>; + clocks = <0x2 0x2a5 0x2 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1b3>; + }; + + power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + phandle = <0xc2>; + + power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + phandle = <0x50>; + + power-domain@8 { + reg = <0x8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + power-domain@9 { + reg = <0x9>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130 0x2 0x126>; + pm_qos = <0x6c 0x6d 0x6e>; + + power-domain@10 { + reg = <0xa>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>; + pm_qos = <0x6f>; + }; + + power-domain@11 { + reg = <0xb>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>; + pm_qos = <0x70>; + }; + }; + }; + + power-domain@12 { + reg = <0xc>; + clocks = <0x2 0x114 0x2 0x115 0x2 0x116>; + pm_qos = <0x71 0x72 0x73 0x74>; + }; + + power-domain@13 { + reg = <0xd>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + power-domain@14 { + reg = <0xe>; + clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190 0x2 0x18e>; + pm_qos = <0x75>; + }; + + power-domain@15 { + reg = <0xf>; + clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc 0x2 0x195>; + pm_qos = <0x76>; + }; + + power-domain@16 { + reg = <0x10>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1c4 0x2 0x1c5>; + pm_qos = <0x77 0x78 0x79>; + + power-domain@17 { + reg = <0x11>; + clocks = <0x2 0x1c9 0x2 0x1c4 0x2 0x1c5 0x2 0x1ca>; + pm_qos = <0x7a 0x7b 0x7c>; + }; + }; + }; + + power-domain@21 { + reg = <0x15>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1be 0x2 0x1bd 0x2 0x1bc 0x2 0x1bf 0x2 0x1aa 0x2 0x1a9 0x2 0x1ac 0x2 0x1ad 0x2 0x1ae 0x2 0x1af 0x2 0x1b0 0x2 0x1b1 0x2 0x1b2 0x2 0x1b3 0x2 0x1b4 0x2 0x1b5 0x2 0x1b7 0x2 0x1b6>; + pm_qos = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84>; + + power-domain@23 { + reg = <0x17>; + clocks = <0x2 0x4b 0x2 0x49 0x2 0x1be>; + pm_qos = <0x85>; + }; + + power-domain@14 { + reg = <0xe>; + clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190>; + pm_qos = <0x75>; + }; + + power-domain@15 { + reg = <0xf>; + clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc>; + pm_qos = <0x76>; + }; + + power-domain@22 { + reg = <0x16>; + clocks = <0x2 0x1ba 0x2 0x1b9>; + pm_qos = <0x86>; + }; + }; + + power-domain@24 { + reg = <0x18>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x26e 0x2 0x26d 0x2 0x270>; + pm_qos = <0x87 0x88>; + + power-domain@25 { + reg = <0x19>; + clocks = <0x2 0x1f6 0x2 0x1f7 0x2 0x1f5 0x2 0x1f3 0x2 0x1ee 0x2 0x1ed 0x2 0x26d>; + pm_qos = <0x89>; + }; + }; + + power-domain@26 { + reg = <0x1a>; + clocks = <0x2 0x22e 0x2 0x22f 0x2 0x22d 0x2 0x218 0x2 0x217 0x2 0x22b 0x2 0x264>; + pm_qos = <0x8a 0x8b>; + }; + + power-domain@27 { + reg = <0x1b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1e1 0x2 0x1e2 0x2 0x1df 0x2 0x1de 0x2 0x1e5 0x2 0x1e4>; + pm_qos = <0x8c 0x8d 0x8e 0x8f>; + + power-domain@28 { + reg = <0x1c>; + clocks = <0x2 0x121 0x2 0x120 0x2 0x1e1 0x2 0x1e2>; + pm_qos = <0x90 0x91>; + }; + + power-domain@29 { + reg = <0x1d>; + clocks = <0x2 0x1d6 0x2 0x1d5 0x2 0x1d9 0x2 0x1d8 0x2 0x1e2>; + pm_qos = <0x92 0x93>; + }; + }; + + power-domain@30 { + reg = <0x1e>; + clocks = <0x2 0x189 0x2 0x18a>; + pm_qos = <0x94>; + }; + + power-domain@31 { + reg = <0x1f>; + clocks = <0x2 0x166 0x2 0x19b 0x2 0x19c 0x2 0x19d 0x2 0x19e 0x2 0x19f 0x2 0x1a0>; + pm_qos = <0x95 0x96 0x97 0x98>; + }; + + power-domain@33 { + reg = <0x21>; + clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>; + }; + + power-domain@34 { + reg = <0x22>; + clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>; + }; + + power-domain@37 { + reg = <0x25>; + clocks = <0x2 0x199 0x2 0x140>; + pm_qos = <0x99>; + }; + + power-domain@38 { + reg = <0x26>; + clocks = <0x2 0x3c 0x2 0x3d>; + }; + + power-domain@40 { + reg = <0x28>; + pm_qos = <0x9a>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x0 0xfda40000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@0 { + reg = <0x0>; + clocks = <0x2 0x2c6 0x2 0x15>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x0 0xfda50000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@1 { + reg = <0x1>; + clocks = <0x2 0x2c8 0x2 0x17>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x0 0xfda60000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@2 { + reg = <0x2>; + clocks = <0x2 0x2ca 0x2 0x1b>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x0 0xfdaf0000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@3 { + reg = <0x3>; + clocks = <0x2 0x12b 0x2 0x129>; + clock-names = "clk\0pclk"; + resets = <0x2 0x1de 0x2 0x1dc>; + reset-names = "rts\0rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x0 0xfdb30000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@4 { + reg = <0x4>; + clocks = <0x2 0x118>; + clock-names = "clk"; + resets = <0x2 0x430 0x2 0x42f>; + reset-names = "rts\0rst-p"; + }; + }; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x0 0xfdab0000 0x0 0x10000 0x0 0xfdac0000 0x0 0x10000 0x0 0xfdad0000 0x0 0x10000>; + interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>; + interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq"; + clocks = <0xe 0x6 0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125 0x2 0x131>; + clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk"; + assigned-clocks = <0xe 0x6>; + assigned-clock-rates = <0xbebc200>; + resets = <0x2 0x1e6 0x2 0x1b0 0x2 0x1c0 0x2 0x1e8 0x2 0x1b2 0x2 0x1c2>; + reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2"; + power-domains = <0x50 0x9 0x50 0xa 0x50 0xb>; + power-domain-names = "npu0\0npu1\0npu2"; + operating-points-v2 = <0x9b>; + iommus = <0x9c>; + status = "okay"; + rknpu-supply = <0x9d>; + mem-supply = <0x9d>; + }; + + npu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x9e 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0xc3500>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + clocks = <0x2 0x12a>; + clock-names = "pclk"; + rockchip,grf = <0x9f>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-read-margin = <0x4>; + intermediate-threshold-freq = <0x7a120>; + rockchip,init-freq = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0xc3500>; + phandle = <0x9b>; + + opp-300000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x11e1a300>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x17d78400>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x1dcd6500>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdab9000 0x0 0x100 0x0 0xfdaba000 0x0 0x100 0x0 0xfdaca000 0x0 0x100 0x0 0xfdada000 0x0 0x100>; + interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>; + interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu"; + clocks = <0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125>; + clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2"; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0x9c>; + }; + + vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdb50000 0x0 0x400>; + interrupts = <0x0 0x78 0x4>; + interrupt-names = "irq_vepu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdb50400 0x0 0x400>; + interrupts = <0x0 0x77 0x4>; + interrupt-names = "irq_vdpu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb50800 0x0 0x40>; + interrupts = <0x0 0x76 0x4>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa0>; + }; + + avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xfdb51000 0x0 0x200>; + interrupts = <0x0 0x77 0x4>; + interrupt-names = "irq_avsd"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + power-domains = <0x50 0x15>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + status = "okay"; + }; + + rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x0 0xfdb60000 0x0 0x1000>; + interrupts = <0x0 0x72 0x4>; + interrupt-names = "rga3_core0_irq"; + clocks = <0x2 0x1ba 0x2 0x1b9 0x2 0x1bb>; + clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0"; + power-domains = <0x50 0x16>; + iommus = <0xa2>; + status = "okay"; + }; + + iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <0x0 0x72 0x4>; + interrupt-names = "rga3_0_mmu"; + clocks = <0x2 0x1ba 0x2 0x1b9>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x16>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa2>; + }; + + rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x0 0xfdb70000 0x0 0x1000>; + interrupts = <0x0 0x73 0x4>; + interrupt-names = "rga3_core1_irq"; + clocks = <0x2 0x18a 0x2 0x189 0x2 0x18b>; + clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1"; + power-domains = <0x50 0x1e>; + iommus = <0xa3>; + status = "okay"; + }; + + iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <0x0 0x73 0x4>; + interrupt-names = "rga3_1_mmu"; + clocks = <0x2 0x18a 0x2 0x189>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1e>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa3>; + }; + + rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xfdb80000 0x0 0x1000>; + interrupts = <0x0 0x74 0x4>; + interrupt-names = "rga2_irq"; + clocks = <0x2 0x1b7 0x2 0x1b6 0x2 0x1b8>; + clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2"; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfdb90000 0x0 0x400>; + interrupts = <0x0 0x81 0x4>; + interrupt-names = "irq_jpegd"; + clocks = <0x2 0x1b4 0x2 0x1b5>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x23c34600 0x0>; + assigned-clocks = <0x2 0x1b4>; + assigned-clock-rates = <0x23c34600>; + resets = <0x2 0x2d2 0x2 0x2d3>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + iommus = <0xa4>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x1>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb90480 0x0 0x40>; + interrupts = <0x0 0x82 0x4>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <0x2 0x1b4 0x2 0x1b5>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa4>; + }; + + jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba0000 0x0 0x400>; + interrupts = <0x0 0x7a 0x4>; + interrupt-names = "irq_jpege0"; + clocks = <0x2 0x1ac 0x2 0x1ad>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1ac>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2ca 0x2 0x2cb>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa5>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = <0x0 0x79 0x4>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <0x2 0x1ac 0x2 0x1ad>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa5>; + }; + + jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba4000 0x0 0x400>; + interrupts = <0x0 0x7c 0x4>; + interrupt-names = "irq_jpege1"; + clocks = <0x2 0x1ae 0x2 0x1af>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1ae>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2cc 0x2 0x2cd>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa7>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = <0x0 0x7b 0x4>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <0x2 0x1ae 0x2 0x1af>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa7>; + }; + + jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba8000 0x0 0x400>; + interrupts = <0x0 0x7e 0x4>; + interrupt-names = "irq_jpege2"; + clocks = <0x2 0x1b0 0x2 0x1b1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1b0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2ce 0x2 0x2cf>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa8>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = <0x0 0x7d 0x4>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <0x2 0x1b0 0x2 0x1b1>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa8>; + }; + + jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdbac000 0x0 0x400>; + interrupts = <0x0 0x80 0x4>; + interrupt-names = "irq_jpege3"; + clocks = <0x2 0x1b2 0x2 0x1b3>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1b2>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2d0 0x2 0x2d1>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa9>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = <0x0 0x7f 0x4>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <0x2 0x1b2 0x2 0x1b3>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa9>; + }; + + iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = <0x0 0x75 0x4>; + interrupt-names = "irq_iep"; + clocks = <0x2 0x1aa 0x2 0x1a9 0x2 0x1ab>; + clock-names = "aclk\0hclk\0sclk"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1aa>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2d5 0x2 0x2d4 0x2 0x2d6>; + reset-names = "rst_a\0rst_h\0rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <0x50 0x15>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x6>; + iommus = <0xaa>; + status = "okay"; + }; + + iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = <0x0 0x75 0x4>; + interrupt-names = "irq_iep_mmu"; + clocks = <0x2 0x1aa 0x2 0x1a9>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + phandle = <0xaa>; + }; + + rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbd0000 0x0 0x6000>; + interrupts = <0x0 0x65 0x4>; + interrupt-names = "irq_rkvenc0"; + clocks = <0x2 0x1c5 0x2 0x1c4 0x2 0x1c6>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x23c34600 0x0 0x2faf0800>; + assigned-clocks = <0x2 0x1c5 0x2 0x1c6>; + assigned-clock-rates = <0x23c34600 0x2faf0800>; + resets = <0x2 0x2f5 0x2 0x2f4 0x2 0x2f6>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xab>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xac>; + rockchip,taskqueue-node = <0x7>; + rockchip,task-capacity = <0x8>; + power-domains = <0x50 0x10>; + operating-points-v2 = <0xad>; + status = "okay"; + venc-supply = <0xae>; + mem-supply = <0xae>; + }; + + iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbdf000 0x0 0x40 0x0 0xfdbdf040 0x0 0x40>; + interrupts = <0x0 0x63 0x4 0x0 0x64 0x4>; + interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1"; + clocks = <0x2 0x1c5 0x2 0x1c4>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x0>; + power-domains = <0x50 0x10>; + status = "okay"; + phandle = <0xab>; + }; + + rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbe0000 0x0 0x6000>; + interrupts = <0x0 0x68 0x4>; + interrupt-names = "irq_rkvenc1"; + clocks = <0x2 0x1ca 0x2 0x1c9 0x2 0x1cb>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x23c34600 0x0 0x2faf0800>; + assigned-clocks = <0x2 0x1ca 0x2 0x1cb>; + assigned-clock-rates = <0x23c34600 0x2faf0800>; + resets = <0x2 0x305 0x2 0x304 0x2 0x306>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xaf>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xac>; + rockchip,taskqueue-node = <0x7>; + rockchip,task-capacity = <0x8>; + power-domains = <0x50 0x11>; + operating-points-v2 = <0xad>; + status = "okay"; + venc-supply = <0xae>; + mem-supply = <0xae>; + }; + + iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbef000 0x0 0x40 0x0 0xfdbef040 0x0 0x40>; + interrupts = <0x0 0x66 0x4 0x0 0x67 0x4>; + interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1"; + clocks = <0x2 0x1ca 0x2 0x1c9>; + lock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x0>; + power-domains = <0x50 0x11>; + status = "okay"; + phandle = <0xaf>; + }; + + venc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xb0>; + nvmem-cell-names = "leakage"; + rockchip,leakage-voltage-sel = <0x1 0x8 0x0 0x9 0x14 0x1 0x15 0xfe 0x2>; + rockchip,grf = <0xb1>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + phandle = <0xad>; + + opp-800000000 { + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L0 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + }; + + rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x0 0xfdc30000 0x0 0x100>; + reg-names = "ccu"; + clocks = <0x2 0x18e>; + clock-names = "aclk_ccu"; + assigned-clocks = <0x2 0x18e>; + assigned-clock-rates = <0x23c34600>; + resets = <0x2 0x282>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + rockchip,ccu-mode = <0x1>; + power-domains = <0x50 0xe>; + status = "okay"; + phandle = <0xb3>; + }; + + rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc38100 0x0 0x400 0x0 0xfdc38000 0x0 0x100>; + reg-names = "regs\0link"; + interrupts = <0x0 0x5f 0x4>; + interrupt-names = "irq_rkvdec0"; + clocks = <0x2 0x190 0x2 0x18f 0x2 0x193 0x2 0x191 0x2 0x192>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x2 0x190 0x2 0x193 0x2 0x191 0x2 0x192>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x2 0x284 0x2 0x283 0x2 0x289 0x2 0x287 0x2 0x288>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xb2>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xb3>; + rockchip,core-mask = <0x10001>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x9>; + rockchip,sram = <0xb4>; + rockchip,rcb-iova = <0xfff00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x50 0xe>; + status = "okay"; + }; + + iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc38700 0x0 0x40 0x0 0xfdc38740 0x0 0x40>; + interrupts = <0x0 0x60 0x4>; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <0x2 0x190 0x2 0x18f>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x0>; + power-domains = <0x50 0xe>; + status = "okay"; + phandle = <0xb2>; + }; + + rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc48100 0x0 0x400 0x0 0xfdc48000 0x0 0x100>; + reg-names = "regs\0link"; + interrupts = <0x0 0x61 0x4>; + interrupt-names = "irq_rkvdec1"; + clocks = <0x2 0x195 0x2 0x194 0x2 0x198 0x2 0x196 0x2 0x197>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x2 0x195 0x2 0x198 0x2 0x196 0x2 0x197>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x2 0x293 0x2 0x292 0x2 0x298 0x2 0x296 0x2 0x297>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xb5>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xb3>; + rockchip,core-mask = <0x20002>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x9>; + rockchip,sram = <0xb6>; + rockchip,rcb-iova = <0xffe00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x50 0xf>; + status = "okay"; + }; + + iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc48700 0x0 0x40 0x0 0xfdc48740 0x0 0x40>; + interrupts = <0x0 0x62 0x4>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <0x2 0x195 0x2 0x194>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x0>; + power-domains = <0x50 0xf>; + status = "okay"; + phandle = <0xb5>; + }; + + iommu@fdca0000 { + compatible = "rockchip,iommu-av1"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = <0x0 0x6d 0x4>; + interrupt-names = "irq_av1d_mmu"; + clocks = <0x2 0x49 0x2 0x4b>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + power-domains = <0x50 0x17>; + status = "okay"; + phandle = <0xb7>; + }; + + rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcb0000 0x0 0x7f00>; + interrupts = <0x0 0x83 0x4 0x0 0x85 0x4 0x0 0x86 0x4>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x2 0x1de 0x2 0x1df 0x2 0x1db 0x2 0x1dc 0x2 0x1dd>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x50 0x1b>; + iommus = <0xb9>; + status = "okay"; + phandle = <0x48>; + }; + + iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = <0x0 0x84 0x4>; + interrupt-names = "isp0_mmu"; + clocks = <0x2 0x1de 0x2 0x1df>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1b>; + #iommu-cells = <0x0>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0xb9>; + }; + + rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x0 0xfdce0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = <0x0 0x9b 0x4>; + interrupt-names = "cif-intr"; + clocks = <0x2 0x1e4 0x2 0x1e5 0x2 0x1e3 0x2 0x1cd 0x2 0x1ce>; + clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_host0\0iclk_host1"; + resets = <0x2 0x317 0x2 0x318 0x2 0x316 0x2 0x334 0x2 0x335 0x2 0x336 0x2 0x337 0x2 0x338 0x2 0x339>; + reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_host0\0rst_cif_host1\0rst_cif_host2\0rst_cif_host3\0rst_cif_host4\0rst_cif_host5"; + assigned-clocks = <0x2 0x1e3>; + assigned-clock-rates = <0x23c34600>; + power-domains = <0x50 0x1b>; + rockchip,grf = <0xb1>; + iommus = <0x40>; + status = "okay"; + phandle = <0x3f>; + }; + + iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdce0800 0x0 0x100 0x0 0xfdce0900 0x0 0x100>; + interrupts = <0x0 0x71 0x4>; + interrupt-names = "cif_mmu"; + clocks = <0x2 0x1e4 0x2 0x1e5>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1b>; + rockchip,disable-mmu-reset; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0x40>; + }; + + mipi2-csi2@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x0 0x93 0x4 0x0 0x94 0x4>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x2 0x1d1>; + clock-names = "pclk_csi2host"; + resets = <0x2 0x326>; + reset-names = "srst_csihost_p"; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xbd>; + phandle = <0x2e>; + }; + }; + + port@1 { + reg = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xbe>; + phandle = <0x44>; + }; + }; + }; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200 0x0 0xfdd95000 0x0 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x0 0x9c 0x4>; + clocks = <0x2 0x270 0x2 0x26f 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x2 0x26e 0x2 0x271 0x2 0x272 0x2 0x273>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2"; + assigned-clocks = <0x2 0x270>; + assigned-clock-rates = <0x2faf0800>; + resets = <0x2 0x349 0x2 0x348 0x2 0x34d 0x2 0x350 0x2 0x351 0x2 0x352>; + reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3"; + iommus = <0xbf>; + power-domains = <0x50 0x18>; + rockchip,grf = <0xb1>; + rockchip,vop-grf = <0xc0>; + rockchip,vo1-grf = <0xc1>; + rockchip,pmu = <0xc2>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + phandle = <0x2f>; + + port@0 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x0>; + rockchip,plane-mask = <0x5>; + rockchip,primary-plane = <0x2>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xc3>; + phandle = <0xe9>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xc4>; + phandle = <0xf5>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xc5>; + phandle = <0x35>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xc6>; + phandle = <0x18c>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xc7>; + phandle = <0x197>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xc8>; + phandle = <0x194>; + }; + }; + + port@1 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + rockchip,plane-mask = <0xa>; + rockchip,primary-plane = <0x3>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xc9>; + phandle = <0x31>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xca>; + phandle = <0xf6>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xcb>; + phandle = <0xf2>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xcc>; + phandle = <0x37>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xcd>; + phandle = <0x198>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xce>; + phandle = <0x38>; + }; + }; + + port@2 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + assigned-clocks = <0x2 0x273>; + assigned-clock-parents = <0x2 0x4>; + rockchip,plane-mask = <0x140>; + rockchip,primary-plane = <0x8>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xcf>; + phandle = <0xea>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xd0>; + phandle = <0x34>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xd1>; + phandle = <0xf3>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xd2>; + phandle = <0xdc>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xd3>; + phandle = <0xe3>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xd4>; + phandle = <0x18d>; + }; + + endpoint@6 { + reg = <0x6>; + remote-endpoint = <0xd5>; + phandle = <0x199>; + }; + + endpoint@7 { + reg = <0x7>; + remote-endpoint = <0xd6>; + phandle = <0x195>; + }; + }; + + port@3 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x3>; + rockchip,plane-mask = <0x280>; + rockchip,primary-plane = <0x9>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xd7>; + phandle = <0x32>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xd8>; + phandle = <0x33>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xd9>; + phandle = <0x36>; + }; + }; + }; + }; + + iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdd97e00 0x0 0x100 0x0 0xfdd97f00 0x0 0x100>; + interrupts = <0x0 0x9c 0x4>; + interrupt-names = "vop_mmu"; + clocks = <0x2 0x270 0x2 0x26f>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + phandle = <0xbf>; + }; + + dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = <0x0 0xa7 0x4>; + clocks = <0x2 0x278 0x2 0x27a>; + clock-names = "pclk\0sys_clk"; + resets = <0x2 0x354>; + reset-names = "apb"; + power-domains = <0x50 0x18>; + phys = <0x2a>; + phy-names = "dcphy"; + rockchip,grf = <0xc0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0x32>; + status = "okay"; + phandle = <0xd7>; + }; + }; + + port@1 { + reg = <0x1>; + + endpoint { + remote-endpoint = <0xdd>; + phandle = <0xe2>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x0>; + backlight = <0xde>; + reset-delay-ms = <0xa>; + enable-delay-ms = <0xa>; + prepare-delay-ms = <0xa>; + unprepare-delay-ms = <0xa>; + disable-delay-ms = <0x3c>; + dsi,flags = <0xa03>; + dsi,format = <0x0>; + dsi,lanes = <0x4>; + panel-init-sequence = [13 00 02 80 ac 13 00 02 81 b8 13 00 02 82 09 13 00 02 83 78 13 00 02 84 7f 13 00 02 85 bb 13 00 02 86 70]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xdf>; + pinctrl-names = "default"; + pinctrl-0 = <0xe0>; + + display-timings { + native-mode = <0xe1>; + + timing0 { + clock-frequency = <0x3dfd240>; + hactive = <0x400>; + vactive = <0x258>; + hfront-porch = <0xa0>; + hsync-len = <0xa>; + hback-porch = <0xa0>; + vfront-porch = <0xc>; + vsync-len = <0x1>; + vback-porch = <0x17>; + hsync-active = <0x0>; + vsync-active = <0x0>; + de-active = <0x0>; + pixelclk-active = <0x0>; + phandle = <0xe1>; + }; + }; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + endpoint { + remote-endpoint = <0xe2>; + phandle = <0xdd>; + }; + }; + }; + }; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfde80000 0x0 0x20000>; + interrupts = <0x0 0xa9 0x4 0x0 0xaa 0x4 0x0 0xab 0x4 0x0 0xac 0x4 0x0 0x168 0x4>; + clocks = <0x2 0x221 0x2 0x265 0x2 0x222 0x2 0x223 0x2 0x246 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x5 0xeb>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x2 0x3d0 0x2 0x49c>; + reset-names = "ref\0hdp"; + power-domains = <0x50 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0xec 0xed 0xee 0xef>; + reg-io-width = <0x4>; + rockchip,grf = <0xb1>; + rockchip,vo1_grf = <0xc1>; + phys = <0xf0>; + phy-names = "hdmi"; + #sound-dai-cells = <0x0>; + status = "okay"; + enable-gpios = <0xf1 0x9 0x0>; + phandle = <0x1b5>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x35>; + status = "okay"; + phandle = <0xc5>; + }; + }; + }; + }; + + qos@fdf35000 { + compatible = "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + phandle = <0x71>; + }; + + qos@fdf35200 { + compatible = "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + phandle = <0x72>; + }; + + qos@fdf35400 { + compatible = "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + phandle = <0x73>; + }; + + qos@fdf35600 { + compatible = "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + phandle = <0x74>; + }; + + qos@fdf36000 { + compatible = "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + phandle = <0x94>; + }; + + qos@fdf39000 { + compatible = "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + phandle = <0x99>; + }; + + qos@fdf3d800 { + compatible = "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + phandle = <0x9a>; + }; + + qos@fdf3e000 { + compatible = "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + phandle = <0x96>; + }; + + qos@fdf3e200 { + compatible = "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + phandle = <0x95>; + }; + + qos@fdf3e400 { + compatible = "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + phandle = <0x97>; + }; + + qos@fdf3e600 { + compatible = "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + phandle = <0x98>; + }; + + qos@fdf40000 { + compatible = "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + phandle = <0x92>; + }; + + qos@fdf40200 { + compatible = "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + phandle = <0x93>; + }; + + qos@fdf40400 { + compatible = "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + phandle = <0x8c>; + }; + + qos@fdf40500 { + compatible = "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + phandle = <0x8d>; + }; + + qos@fdf40600 { + compatible = "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + phandle = <0x8e>; + }; + + qos@fdf40800 { + compatible = "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + phandle = <0x8f>; + }; + + qos@fdf41000 { + compatible = "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + phandle = <0x90>; + }; + + qos@fdf41100 { + compatible = "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + phandle = <0x91>; + }; + + qos@fdf60000 { + compatible = "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + phandle = <0x77>; + }; + + qos@fdf60200 { + compatible = "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + phandle = <0x78>; + }; + + qos@fdf60400 { + compatible = "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + phandle = <0x79>; + }; + + qos@fdf61000 { + compatible = "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + phandle = <0x7a>; + }; + + qos@fdf61200 { + compatible = "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + phandle = <0x7b>; + }; + + qos@fdf61400 { + compatible = "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + phandle = <0x7c>; + }; + + qos@fdf62000 { + compatible = "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + phandle = <0x75>; + }; + + qos@fdf63000 { + compatible = "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + phandle = <0x76>; + }; + + qos@fdf64000 { + compatible = "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + phandle = <0x85>; + }; + + qos@fdf66000 { + compatible = "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + phandle = <0x7d>; + }; + + qos@fdf66200 { + compatible = "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + phandle = <0x7e>; + }; + + qos@fdf66400 { + compatible = "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + phandle = <0x7f>; + }; + + qos@fdf66600 { + compatible = "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + phandle = <0x80>; + }; + + qos@fdf66800 { + compatible = "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + phandle = <0x81>; + }; + + qos@fdf66a00 { + compatible = "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + phandle = <0x82>; + }; + + qos@fdf66c00 { + compatible = "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + phandle = <0x83>; + }; + + qos@fdf66e00 { + compatible = "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + phandle = <0x84>; + }; + + qos@fdf67000 { + compatible = "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + phandle = <0x86>; + }; + + qos@fdf67200 { + compatible = "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos@fdf70000 { + compatible = "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + phandle = <0x6f>; + }; + + qos@fdf71000 { + compatible = "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + phandle = <0x70>; + }; + + qos@fdf72000 { + compatible = "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + phandle = <0x6c>; + }; + + qos@fdf72200 { + compatible = "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + phandle = <0x6d>; + }; + + qos@fdf72400 { + compatible = "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + phandle = <0x6e>; + }; + + qos@fdf80000 { + compatible = "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + phandle = <0x89>; + }; + + qos@fdf81000 { + compatible = "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + phandle = <0x8a>; + }; + + qos@fdf81200 { + compatible = "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + phandle = <0x8b>; + }; + + qos@fdf82000 { + compatible = "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + phandle = <0x87>; + }; + + qos@fdf82200 { + compatible = "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + phandle = <0x88>; + }; + + dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x0 0xfe060000 0x0 0x10000>; + rockchip,pmu_grf = <0xf7>; + status = "okay"; + phandle = <0x39>; + }; + + ethernet@fe1c0000 { + local-mac-address = [46 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <0x0 0xea 0x4 0x0 0xe9 0x4>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xb1>; + rockchip,php_grf = <0x63>; + clocks = <0x2 0x144 0x2 0x145 0x2 0x168 0x2 0x16d 0x2 0x143>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x2 0x20b>; + reset-names = "stmmaceth"; + power-domains = <0x50 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0xfc>; + snps,mtl-rx-config = <0xfd>; + snps,mtl-tx-config = <0xfe>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0xff 0xf 0x1>; + snps,reset-active-low; + snps,reset-delays-us = <0x0 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x100 0x101 0x102 0x103 0x104>; + tx_delay = <0x44>; + phy-handle = <0x105>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + phandle = <0x105>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x4>; + snps,rd_osr_lmt = <0x8>; + snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>; + phandle = <0xfc>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x2>; + phandle = <0xfd>; + + queue0 { + }; + + queue1 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x2>; + phandle = <0xfe>; + + queue0 { + }; + + queue1 { + }; + }; + }; + + mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <0x0 0xcb 0x4>; + clocks = <0xe 0x17 0xe 0x9 0x2 0x2c2 0x2 0x2c3>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x106 0x107 0x108 0x109>; + power-domains = <0x50 0x28>; + status = "okay"; + no-sdio; + no-mmc; + bus-width = <0x4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <0x10a>; + vmmc-supply = <0x10b>; + }; + + mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <0x0 0xcd 0x4>; + assigned-clocks = <0x2 0x13b 0x2 0x13c 0x2 0x13a>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x2 0x13a 0x2 0x138 0x2 0x139 0x2 0x13b 0x2 0x13c>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x2 0x1f6 0x2 0x1f4 0x2 0x1f5 0x2 0x1f7 0x2 0x1f8>; + reset-names = "core\0bus\0axi\0block\0timer"; + max-frequency = <0xbebc200>; + status = "okay"; + bus-width = <0x8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + }; + + rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <0x0 0x190 0x4>; + clocks = <0xe 0xc>; + clock-names = "hclk_trng"; + resets = <0x10d 0x30>; + reset-names = "reset"; + status = "okay"; + }; + + i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <0x0 0xb4 0x4>; + clocks = <0x2 0x33 0x2 0x37 0x2 0x30>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x2 0x31 0x2 0x35>; + assigned-clock-parents = <0x2 0x5 0x2 0x5>; + dmas = <0x66 0x0 0x66 0x1>; + dma-names = "tx\0rx"; + power-domains = <0x50 0x26>; + resets = <0x2 0x77 0x2 0x7a>; + reset-names = "tx-m\0rx-m"; + rockchip,clk-trcm = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + #sound-dai-cells = <0x0>; + status = "okay"; + phandle = <0x1c8>; + }; + + hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x0 0xfe5a0000 0x0 0x100>; + #hwlock-cells = <0x1>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0xfe600000 0x0 0x10000 0x0 0xfe680000 0x0 0x100000>; + interrupts = <0x1 0x9 0x4>; + phandle = <0x1>; + + msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + phandle = <0xf9>; + }; + + msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x1>; + reg = <0x0 0xfe660000 0x0 0x20000>; + phandle = <0x19c>; + }; + }; + + dma-controller@fea10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <0x0 0x56 0x4 0x0 0x57 0x4>; + clocks = <0x2 0x78>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0x66>; + }; + + dma-controller@fea30000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <0x0 0x58 0x4 0x0 0x59 0x4>; + clocks = <0x2 0x79>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0xda>; + }; + + i2c@fea90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <0x2 0x8d 0x2 0x85>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x13e 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x136>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x9d>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + i2c@feab0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <0x2 0x8f 0x2 0x87>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x140 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x138>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + es8311@19 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x19>; + #sound-dai-cells = <0x0>; + adc-pga-gain = <0x6>; + adc-volume = <0xbf>; + dac-volume = <0xbf>; + aec-mode = "adc left, adc right"; + clocks = <0x139>; + clock-names = "mclk"; + assigned-clocks = <0x139>; + assigned-clock-rates = <0xbb8000>; + pinctrl-names = "default"; + pinctrl-0 = <0x13a>; + phandle = <0x1c9>; + }; + }; + + i2c@feac0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <0x2 0x90 0x2 0x88>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x141 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x13b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + imx415@36 { + compatible = "sony,imx415"; + reg = <0x36>; + clocks = <0x2 0x100>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x13c>; + power-domains = <0x50 0x1b>; + reset-gpios = <0x13d 0x16 0x1>; + avdd-supply = <0x13e>; + rockchip,camera-module-index = <0x0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + + port { + endpoint { + remote-endpoint = <0x13f>; + data-lanes = <0x1 0x2 0x3 0x4>; + phandle = <0x2d>; + }; + }; + }; + + gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0x140>; + touch-gpio = <0x141 0x0 0x8>; + reset-gpio = <0x141 0x1 0x0>; + max-x = <0x400>; + max-y = <0x258>; + tp-size = <0x38f>; + status = "okay"; + }; + }; + + timer@feae0000 { + compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <0x0 0x121 0x4>; + clocks = <0x2 0x5c 0x2 0x5f>; + clock-names = "pclk\0timer"; + }; + + watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <0x2 0x6c 0x2 0x6b>; + clock-names = "tclk\0pclk"; + interrupts = <0x0 0x13b 0x4>; + status = "okay"; + }; + + spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <0x0 0x146 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0xa3 0x2 0x9e>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x66 0xe 0x66 0xf>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x143 0x144>; + num-cs = <0x1>; + status = "okay"; + max-freq = <0x2faf080>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0x0>; + spi-max-frequency = <0x2faf080>; + }; + }; + + spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <0x0 0x148 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0xa5 0x2 0xa0>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xda 0xf 0xda 0x10>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x148 0x149>; + num-cs = <0x1>; + status = "okay"; + assigned-clocks = <0x2 0xa5>; + assigned-clock-rates = <0xbebc200>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <0xf4240>; + reg = <0x0>; + interrupt-parent = <0x13d>; + interrupts = <0x7 0x8>; + pinctrl-names = "default\0pmic-power-off"; + pinctrl-0 = <0x14a 0x14b 0x14c 0x14d>; + pinctrl-1 = <0x14e>; + low_voltage_threshold = <0xbb8>; + shutdown_voltage_threshold = <0xa8c>; + shutdown_temperture_threshold = <0xa0>; + hotdie_temperture_threshold = <0x73>; + pmic-reset-func = <0x1>; + vcc1-supply = <0x65>; + vcc2-supply = <0x65>; + vcc3-supply = <0x65>; + vcc4-supply = <0x65>; + vcc5-supply = <0x65>; + vcc6-supply = <0x65>; + vcc7-supply = <0x65>; + vcc8-supply = <0x65>; + vcc9-supply = <0x65>; + vcc10-supply = <0x65>; + vcc11-supply = <0x14f>; + vcc12-supply = <0x65>; + vcc13-supply = <0x150>; + vcc14-supply = <0x150>; + vcca-supply = <0x65>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806 { + gpio-controller; + #gpio-cells = <0x2>; + + rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x14b>; + }; + + rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + phandle = <0x14e>; + }; + + rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x14c>; + }; + + rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + phandle = <0x14d>; + }; + + rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <0x190>; + phandle = <0x52>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_cpu_lit_s0"; + phandle = <0x12>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_log_s0"; + phandle = <0x3c>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-init-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_vdenc_s0"; + phandle = <0xae>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_ddr_s0"; + phandle = <0x3b>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1e8480>; + regulator-max-microvolt = <0x1e8480>; + regulator-name = "vdd_2v0_pldo_s3"; + phandle = <0x14f>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1e8480>; + }; + }; + + DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s3"; + phandle = <0x1c6>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s3"; + phandle = <0x1c7>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s0"; + phandle = <0x16b>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd_s0"; + phandle = <0x10a>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcc77c>; + regulator-max-microvolt = <0xcc77c>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; + + serial@feb60000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <0x0 0x14e 0x4>; + clocks = <0x2 0xbf 0x2 0xad>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0x66 0xc 0x66 0xd>; + pinctrl-names = "default"; + pinctrl-0 = <0x156>; + status = "okay"; + }; + + serial@feb70000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <0x0 0x14f 0x4>; + clocks = <0x2 0xc3 0x2 0xae>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0xda 0x9 0xda 0xa>; + pinctrl-names = "default"; + pinctrl-0 = <0x157>; + status = "okay"; + }; + + serial@feba0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <0x0 0x152 0x4>; + clocks = <0x2 0xcf 0x2 0xb1>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0xdb 0x7 0xdb 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <0x15a>; + status = "okay"; + }; + + tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <0x0 0x18d 0x4>; + clocks = <0x2 0xaa 0x2 0xa9>; + clock-names = "tsadc\0apb_pclk"; + assigned-clocks = <0x2 0xaa>; + assigned-clock-rates = <0x1e8480>; + resets = <0x2 0xc1 0x2 0xc0>; + reset-names = "tsadc\0tsadc-apb"; + #thermal-sensor-cells = <0x1>; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x0>; + rockchip,hw-tshut-polarity = <0x0>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x169>; + pinctrl-1 = <0x16a>; + status = "okay"; + phandle = <0x4d>; + }; + + saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <0x0 0x18e 0x4>; + #io-channel-cells = <0x1>; + clocks = <0x2 0x9d 0x2 0x9c>; + clock-names = "saradc\0apb_pclk"; + resets = <0x2 0xbe>; + reset-names = "saradc-apb"; + status = "okay"; + vref-supply = <0x16b>; + phandle = <0x1b2>; + }; + + otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + #address-cells = <0x1>; + #size-cells = <0x1>; + clocks = <0x2 0x96 0x2 0x95 0x2 0x97 0x2 0x99>; + clock-names = "otpc\0apb\0arb\0phy"; + resets = <0x2 0x12a 0x2 0x129 0x2 0x12b>; + reset-names = "otpc\0apb\0arb"; + + cpu-code@2 { + reg = <0x2 0x2>; + phandle = <0x29>; + }; + + specification-serial-number@6 { + reg = <0x6 0x1>; + bits = <0x0 0x5>; + phandle = <0x20>; + }; + + id@7 { + reg = <0x7 0x10>; + phandle = <0x27>; + }; + + cpu-version@1c { + reg = <0x1c 0x1>; + bits = <0x3 0x3>; + phandle = <0x28>; + }; + + cpub0-leakage@17 { + reg = <0x17 0x1>; + phandle = <0x23>; + }; + + cpub1-leakage@18 { + reg = <0x18 0x1>; + phandle = <0x25>; + }; + + cpul-leakage@19 { + reg = <0x19 0x1>; + phandle = <0x1f>; + }; + + log-leakage@1a { + reg = <0x1a 0x1>; + phandle = <0x3d>; + }; + + gpu-leakage@1b { + reg = <0x1b 0x1>; + phandle = <0x53>; + }; + + npu-leakage@28 { + reg = <0x28 0x1>; + phandle = <0x9e>; + }; + + codec-leakage@29 { + reg = <0x29 0x1>; + phandle = <0xb0>; + }; + }; + + dma-controller@fed10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <0x0 0x5a 0x4 0x0 0x5b 0x4>; + clocks = <0x2 0x7a>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0xdb>; + }; + + hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <0x2 0x2b5 0x2 0x267>; + clock-names = "ref\0apb"; + resets = <0x2 0x48e 0x2 0x485 0x2 0xc003b 0x2 0xc003c 0x2 0xc003d 0x2 0x48c 0x2 0x48d>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x172>; + #phy-cells = <0x0>; + status = "okay"; + phandle = <0xf0>; + + clk-port { + #clock-cells = <0x0>; + status = "okay"; + phandle = <0xeb>; + }; + }; + + phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <0x173>; + rockchip,usb-grf = <0x61>; + rockchip,usbdpphy-grf = <0x174>; + rockchip,vo-grf = <0xe7>; + clocks = <0x2 0x2b6 0x2 0x27f 0x2 0x269 0x175>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x2 0x28 0x2 0x29 0x2 0x2a 0x2 0x2b 0x2 0x482>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + + dp-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0xe8>; + }; + + u3-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x56>; + }; + }; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <0x176>; + clocks = <0x2 0x108 0x2 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x2 0xc0043 0x2 0x3e 0x2 0x3f 0x2 0xc0044>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x2a>; + }; + + csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <0x2 0x10c>; + clock-names = "pclk"; + resets = <0x2 0x17 0x2 0x16>; + reset-names = "srst_csiphy0\0srst_p_csiphy0"; + rockchip,grf = <0x178>; + rockchip,sys_grf = <0xb1>; + status = "okay"; + phandle = <0x2c>; + }; + + phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <0x1>; + clocks = <0x2 0x2bf 0x2 0x187 0x2 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x2 0x2bf>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x2 0x20007 0x2 0x4d8>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x63>; + rockchip,pipe-phy-grf = <0x17a>; + rockchip,pcie1ln-sel-bits = <0x100 0x1 0x1 0x0>; + status = "okay"; + phandle = <0x5d>; + }; + + sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0xff001000 0xef000>; + + rkvdec-sram@0 { + reg = <0x0 0x78000>; + phandle = <0xb4>; + }; + + rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + phandle = <0xb6>; + }; + }; + + pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <0x17b>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + phandle = <0x17c>; + + gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <0x0 0x115 0x4>; + clocks = <0x2 0x284 0x2 0x285>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x13d>; + }; + + gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <0x0 0x116 0x4>; + clocks = <0x2 0x7d 0x2 0x7e>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x20 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x141>; + }; + + gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <0x0 0x117 0x4>; + clocks = <0x2 0x7f 0x2 0x80>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x40 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x1a4>; + }; + + gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <0x0 0x118 0x4>; + clocks = <0x2 0x81 0x2 0x82>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x60 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0xff>; + }; + + gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <0x0 0x119 0x4>; + clocks = <0x2 0x83 0x2 0x84>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x80 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0xf1>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x182>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x17d>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x2>; + phandle = <0x185>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x1>; + phandle = <0x184>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x2>; + phandle = <0x17e>; + }; + + pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <0x6>; + phandle = <0x183>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x181>; + }; + + pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <0x1>; + input-schmitt-enable; + phandle = <0x180>; + }; + + pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <0x5>; + input-schmitt-enable; + phandle = <0x17f>; + }; + + auddsm { + auddsm-pins { + rockchip,pins = <0x3 0x1 0x4 0x17d 0x3 0x2 0x4 0x17d 0x3 0x3 0x4 0x17d 0x3 0x4 0x4 0x17d>; + phandle = <0x132>; + }; + }; + + bt1120 { + bt1120-pins { + rockchip,pins = <0x4 0x8 0x2 0x17d 0x4 0x0 0x2 0x17d 0x4 0x1 0x2 0x17d 0x4 0x2 0x2 0x17d 0x4 0x3 0x2 0x17d 0x4 0x4 0x2 0x17d 0x4 0x5 0x2 0x17d 0x4 0x6 0x2 0x17d 0x4 0x7 0x2 0x17d 0x4 0xa 0x2 0x17d 0x4 0xb 0x2 0x17d 0x4 0xc 0x2 0x17d 0x4 0xd 0x2 0x17d 0x4 0xe 0x2 0x17d 0x4 0xf 0x2 0x17d 0x4 0x10 0x2 0x17d 0x4 0x11 0x2 0x17d>; + phandle = <0x5e>; + }; + }; + + can0 { + can0m0-pins { + rockchip,pins = <0x0 0x10 0xb 0x17d 0x0 0xf 0xb 0x17d>; + phandle = <0x133>; + }; + }; + + can1 { + can1m0-pins { + rockchip,pins = <0x3 0xd 0x9 0x17d 0x3 0xe 0x9 0x17d>; + phandle = <0x134>; + }; + }; + + can2 { + can2m0-pins { + rockchip,pins = <0x3 0x14 0x9 0x17d 0x3 0x15 0x9 0x17d>; + phandle = <0x135>; + }; + }; + + gmac1 { + gmac1-miim { + rockchip,pins = <0x3 0x12 0x1 0x17d 0x3 0x13 0x1 0x17d>; + phandle = <0x100>; + }; + + gmac1-rx-bus2 { + rockchip,pins = <0x3 0x7 0x1 0x17d 0x3 0x8 0x1 0x17d 0x3 0x9 0x1 0x17d>; + phandle = <0x102>; + }; + + gmac1-tx-bus2 { + rockchip,pins = <0x3 0xb 0x1 0x17d 0x3 0xc 0x1 0x17d 0x3 0xd 0x1 0x17d>; + phandle = <0x101>; + }; + + gmac1-rgmii-clk { + rockchip,pins = <0x3 0x5 0x1 0x17d 0x3 0x4 0x1 0x17d>; + phandle = <0x103>; + }; + + gmac1-rgmii-bus { + rockchip,pins = <0x3 0x2 0x1 0x17d 0x3 0x3 0x1 0x17d 0x3 0x0 0x1 0x17d 0x3 0x1 0x1 0x17d>; + phandle = <0x104>; + }; + }; + + hdmi { + hdmim0-tx0-cec { + rockchip,pins = <0x4 0x11 0x5 0x17d>; + phandle = <0xec>; + }; + + hdmim0-tx0-hpd { + rockchip,pins = <0x1 0x5 0x5 0x17d>; + phandle = <0xed>; + }; + + hdmim0-tx0-scl { + rockchip,pins = <0x4 0xf 0x5 0x17f>; + phandle = <0xee>; + }; + + hdmim0-tx0-sda { + rockchip,pins = <0x4 0x10 0x5 0x180>; + phandle = <0xef>; + }; + + hdmim0-tx1-hpd { + rockchip,pins = <0x1 0x6 0x5 0x17d>; + phandle = <0x190>; + }; + + hdmim1-rx { + rockchip,pins = <0x3 0x19 0x5 0x17d 0x3 0x1a 0x5 0x181 0x3 0x1b 0x5 0x181 0x3 0x1c 0x5 0x17d>; + phandle = <0x19a>; + }; + + hdmim1-tx1-scl { + rockchip,pins = <0x3 0x16 0x5 0x17f>; + phandle = <0x191>; + }; + + hdmim1-tx1-sda { + rockchip,pins = <0x3 0x15 0x5 0x180>; + phandle = <0x192>; + }; + + hdmim2-tx1-cec { + rockchip,pins = <0x3 0x14 0x5 0x17d>; + phandle = <0x18f>; + }; + }; + + i2c0 { + i2c0m2-xfer { + rockchip,pins = <0x0 0x19 0x3 0x181 0x0 0x1a 0x3 0x181>; + phandle = <0x64>; + }; + }; + + i2c1 { + i2c1m2-xfer { + rockchip,pins = <0x0 0x1c 0x9 0x181 0x0 0x1d 0x9 0x181>; + phandle = <0x136>; + }; + }; + + i2c2 { + i2c2m0-xfer { + rockchip,pins = <0x0 0xf 0x9 0x181 0x0 0x10 0x9 0x181>; + phandle = <0x137>; + }; + }; + + i2c3 { + i2c3m0-xfer { + rockchip,pins = <0x1 0x11 0x9 0x181 0x1 0x10 0x9 0x181>; + phandle = <0x138>; + }; + }; + + i2c4 { + i2c4m3-xfer { + rockchip,pins = <0x1 0x3 0x9 0x181 0x1 0x2 0x9 0x181>; + phandle = <0x13b>; + }; + }; + + i2c5 { + i2c5m0-xfer { + rockchip,pins = <0x3 0x17 0x9 0x181 0x3 0x18 0x9 0x181>; + phandle = <0x142>; + }; + }; + + i2c6 { + i2c6m0-xfer { + rockchip,pins = <0x0 0x18 0x9 0x181 0x0 0x17 0x9 0x181>; + phandle = <0x16c>; + }; + }; + + i2c7 { + i2c7m0-xfer { + rockchip,pins = <0x1 0x18 0x9 0x181 0x1 0x19 0x9 0x181>; + phandle = <0x16d>; + }; + }; + + i2c8 { + i2c8m0-xfer { + rockchip,pins = <0x4 0x1a 0x9 0x181 0x4 0x1b 0x9 0x181>; + phandle = <0x16e>; + }; + }; + + i2s0 { + i2s0-lrck { + rockchip,pins = <0x1 0x15 0x1 0x17d>; + phandle = <0x10e>; + }; + + i2s0-mclk { + rockchip,pins = <0x1 0x12 0x1 0x17d>; + phandle = <0x13a>; + }; + + i2s0-sclk { + rockchip,pins = <0x1 0x13 0x1 0x17d>; + phandle = <0x10f>; + }; + + i2s0-sdi0 { + rockchip,pins = <0x1 0x1c 0x2 0x17d>; + phandle = <0x110>; + }; + + i2s0-sdo0 { + rockchip,pins = <0x1 0x17 0x1 0x17d>; + phandle = <0x111>; + }; + }; + + i2s1 { + i2s1m0-lrck { + rockchip,pins = <0x4 0x2 0x3 0x17d>; + phandle = <0x112>; + }; + + i2s1m0-sclk { + rockchip,pins = <0x4 0x1 0x3 0x17d>; + phandle = <0x113>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x4 0x5 0x3 0x17d>; + phandle = <0x114>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x4 0x6 0x3 0x17d>; + phandle = <0x115>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x4 0x7 0x3 0x17d>; + phandle = <0x116>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x4 0x8 0x3 0x17d>; + phandle = <0x117>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x4 0x9 0x3 0x17d>; + phandle = <0x118>; + }; + + i2s1m0-sdo1 { + rockchip,pins = <0x4 0xa 0x3 0x17d>; + phandle = <0x119>; + }; + + i2s1m0-sdo2 { + rockchip,pins = <0x4 0xb 0x3 0x17d>; + phandle = <0x11a>; + }; + + i2s1m0-sdo3 { + rockchip,pins = <0x4 0xc 0x3 0x17d>; + phandle = <0x11b>; + }; + }; + + i2s2 { + i2s2m1-lrck { + rockchip,pins = <0x3 0xe 0x3 0x17d>; + phandle = <0x11c>; + }; + + i2s2m1-sclk { + rockchip,pins = <0x3 0xd 0x3 0x17d>; + phandle = <0x11d>; + }; + + i2s2m1-sdi { + rockchip,pins = <0x3 0xa 0x3 0x17d>; + phandle = <0x11e>; + }; + + i2s2m1-sdo { + rockchip,pins = <0x3 0xb 0x3 0x17d>; + phandle = <0x11f>; + }; + }; + + i2s3 { + i2s3-lrck { + rockchip,pins = <0x3 0x2 0x3 0x17d>; + phandle = <0x120>; + }; + + i2s3-sclk { + rockchip,pins = <0x3 0x1 0x3 0x17d>; + phandle = <0x121>; + }; + + i2s3-sdi { + rockchip,pins = <0x3 0x4 0x3 0x17d>; + phandle = <0x122>; + }; + + i2s3-sdo { + rockchip,pins = <0x3 0x3 0x3 0x17d>; + phandle = <0x123>; + }; + }; + + mipi { + mipim0-camera1-clk { + rockchip,pins = <0x1 0xe 0x2 0x17d>; + phandle = <0x13c>; + }; + }; + + pdm0 { + pdm0m0-clk { + rockchip,pins = <0x1 0x16 0x3 0x17d>; + phandle = <0x124>; + }; + + pdm0m0-clk1 { + rockchip,pins = <0x1 0x14 0x3 0x17d>; + phandle = <0x125>; + }; + + pdm0m0-sdi0 { + rockchip,pins = <0x1 0x1d 0x3 0x17d>; + phandle = <0x126>; + }; + + pdm0m0-sdi1 { + rockchip,pins = <0x1 0x19 0x3 0x17d>; + phandle = <0x127>; + }; + + pdm0m0-sdi2 { + rockchip,pins = <0x1 0x1a 0x3 0x17d>; + phandle = <0x128>; + }; + + pdm0m0-sdi3 { + rockchip,pins = <0x1 0x1b 0x3 0x17d>; + phandle = <0x129>; + }; + }; + + pdm1 { + pdm1m0-clk { + rockchip,pins = <0x4 0x1d 0x2 0x17d>; + phandle = <0x12a>; + }; + + pdm1m0-clk1 { + rockchip,pins = <0x4 0x1c 0x2 0x17d>; + phandle = <0x12b>; + }; + + pdm1m0-sdi0 { + rockchip,pins = <0x4 0x1b 0x2 0x17d>; + phandle = <0x12c>; + }; + + pdm1m0-sdi1 { + rockchip,pins = <0x4 0x1a 0x2 0x17d>; + phandle = <0x12d>; + }; + + pdm1m0-sdi2 { + rockchip,pins = <0x4 0x19 0x2 0x17d>; + phandle = <0x12e>; + }; + + pdm1m0-sdi3 { + rockchip,pins = <0x4 0x18 0x2 0x17d>; + phandle = <0x12f>; + }; + }; + + pmic { + pmic-pins { + rockchip,pins = <0x0 0x7 0x0 0x182 0x0 0x2 0x1 0x17d 0x0 0x3 0x1 0x17d 0x0 0x11 0x1 0x17d 0x0 0x12 0x1 0x17d 0x0 0x13 0x1 0x17d 0x0 0x1e 0x1 0x17d>; + phandle = <0x14a>; + }; + }; + + pwm0 { + pwm0m0-pins { + rockchip,pins = <0x0 0xf 0x3 0x17d>; + phandle = <0x68>; + }; + }; + + pwm1 { + pwm1m0-pins { + rockchip,pins = <0x0 0x10 0x3 0x17d>; + phandle = <0x69>; + }; + }; + + pwm2 { + pwm2m0-pins { + rockchip,pins = <0x0 0x14 0x3 0x17d>; + phandle = <0x6a>; + }; + }; + + pwm3 { + pwm3m0-pins { + rockchip,pins = <0x0 0x1c 0x3 0x17d>; + phandle = <0x6b>; + }; + }; + + pwm4 { + pwm4m0-pins { + rockchip,pins = <0x0 0x15 0xb 0x17d>; + phandle = <0x15d>; + }; + }; + + pwm5 { + pwm5m0-pins { + rockchip,pins = <0x0 0x9 0x3 0x17d>; + phandle = <0x15e>; + }; + }; + + pwm6 { + pwm6m0-pins { + rockchip,pins = <0x0 0x17 0xb 0x17d>; + phandle = <0x15f>; + }; + }; + + pwm7 { + pwm7m0-pins { + rockchip,pins = <0x0 0x18 0xb 0x17d>; + phandle = <0x160>; + }; + }; + + pwm8 { + pwm8m0-pins { + rockchip,pins = <0x3 0x7 0xb 0x17d>; + phandle = <0x161>; + }; + }; + + pwm9 { + pwm9m0-pins { + rockchip,pins = <0x3 0x8 0xb 0x17d>; + phandle = <0x162>; + }; + }; + + pwm10 { + pwm10m0-pins { + rockchip,pins = <0x3 0x0 0xb 0x17d>; + phandle = <0x163>; + }; + }; + + pwm11 { + pwm11m0-pins { + rockchip,pins = <0x3 0x1 0xb 0x17d>; + phandle = <0x164>; + }; + }; + + pwm12 { + pwm12m0-pins { + rockchip,pins = <0x3 0xd 0xb 0x17d>; + phandle = <0x165>; + }; + }; + + pwm13 { + pwm13m0-pins { + rockchip,pins = <0x3 0xe 0xb 0x17d>; + phandle = <0x166>; + }; + }; + + pwm14 { + pwm14m0-pins { + rockchip,pins = <0x3 0x12 0xb 0x17d>; + phandle = <0x167>; + }; + }; + + pwm15 { + pwm15m0-pins { + rockchip,pins = <0x3 0x13 0xb 0x17d>; + phandle = <0x168>; + }; + }; + + sdio { + sdiom1-pins { + rockchip,pins = <0x3 0x5 0x2 0x17d 0x3 0x4 0x2 0x182 0x3 0x0 0x2 0x182 0x3 0x1 0x2 0x182 0x3 0x2 0x2 0x182 0x3 0x3 0x2 0x182>; + phandle = <0x10c>; + }; + }; + + sdmmc { + sdmmc-bus4 { + rockchip,pins = <0x4 0x18 0x1 0x17e 0x4 0x19 0x1 0x17e 0x4 0x1a 0x1 0x17e 0x4 0x1b 0x1 0x17e>; + phandle = <0x109>; + }; + + sdmmc-clk { + rockchip,pins = <0x4 0x1d 0x1 0x17e>; + phandle = <0x106>; + }; + + sdmmc-cmd { + rockchip,pins = <0x4 0x1c 0x1 0x17e>; + phandle = <0x107>; + }; + + sdmmc-det { + rockchip,pins = <0x0 0x4 0x1 0x182>; + phandle = <0x108>; + }; + + sd-s0-pwr { + rockchip,pins = <0x0 0xf 0x0 0x182>; + phandle = <0x1c5>; + }; + }; + + spdif0 { + spdif0m0-tx { + rockchip,pins = <0x1 0xe 0x3 0x17d>; + phandle = <0x130>; + }; + }; + + spdif1 { + spdif1m0-tx { + rockchip,pins = <0x1 0xf 0x3 0x17d>; + phandle = <0x131>; + }; + }; + + spi0 { + spi0m3-pins { + rockchip,pins = <0x3 0x1b 0x8 0x183 0x3 0x19 0x8 0x183 0x3 0x1a 0x8 0x183>; + phandle = <0x144>; + }; + + spi0m3-cs0 { + rockchip,pins = <0x3 0x1c 0x8 0x183>; + phandle = <0x143>; + }; + }; + + spi1 { + spi1m1-pins { + rockchip,pins = <0x3 0x11 0x8 0x183 0x3 0x10 0x8 0x183 0x3 0xf 0x8 0x183>; + phandle = <0x147>; + }; + + spi1m1-cs0 { + rockchip,pins = <0x3 0x12 0x8 0x183>; + phandle = <0x145>; + }; + + spi1m1-cs1 { + rockchip,pins = <0x3 0x13 0x8 0x183>; + phandle = <0x146>; + }; + }; + + spi2 { + spi2m2-pins { + rockchip,pins = <0x0 0x5 0x1 0x184 0x0 0xb 0x1 0x184 0x0 0x6 0x1 0x184>; + phandle = <0x149>; + }; + + spi2m2-cs0 { + rockchip,pins = <0x0 0x9 0x1 0x184>; + phandle = <0x148>; + }; + }; + + spi3 { + spi3m1-pins { + rockchip,pins = <0x4 0xf 0x8 0x183 0x4 0xd 0x8 0x183 0x4 0xe 0x8 0x183>; + phandle = <0x153>; + }; + + spi3m1-cs0 { + rockchip,pins = <0x4 0x10 0x8 0x183>; + phandle = <0x151>; + }; + + spi3m1-cs1 { + rockchip,pins = <0x4 0x11 0x8 0x183>; + phandle = <0x152>; + }; + }; + + spi4 { + spi4m0-pins { + rockchip,pins = <0x1 0x12 0x8 0x183 0x1 0x10 0x8 0x183 0x1 0x11 0x8 0x183>; + phandle = <0x171>; + }; + + spi4m0-cs0 { + rockchip,pins = <0x1 0x13 0x8 0x183>; + phandle = <0x16f>; + }; + + spi4m0-cs1 { + rockchip,pins = <0x1 0x14 0x8 0x183>; + phandle = <0x170>; + }; + }; + + tsadc { + tsadc-shut { + rockchip,pins = <0x0 0x1 0x2 0x17d>; + phandle = <0x16a>; + }; + }; + + uart0 { + uart0m2-xfer { + rockchip,pins = <0x4 0x4 0xa 0x182 0x4 0x3 0xa 0x182>; + phandle = <0x67>; + }; + }; + + uart1 { + uart1m1-xfer { + rockchip,pins = <0x1 0xf 0xa 0x182 0x1 0xe 0xa 0x182>; + phandle = <0x154>; + }; + }; + + uart2 { + uart2m0-xfer { + rockchip,pins = <0x0 0xe 0xa 0x182 0x0 0xd 0xa 0x182>; + phandle = <0x1c2>; + }; + + uart2m1-xfer { + rockchip,pins = <0x4 0x19 0xa 0x182 0x4 0x18 0xa 0x182>; + phandle = <0x155>; + }; + }; + + uart3 { + uart3m2-xfer { + rockchip,pins = <0x4 0x6 0xa 0x182 0x4 0x5 0xa 0x182>; + phandle = <0x156>; + }; + }; + + uart4 { + uart4m2-xfer { + rockchip,pins = <0x1 0xa 0xa 0x182 0x1 0xb 0xa 0x182>; + phandle = <0x157>; + }; + }; + + uart5 { + uart5m1-xfer { + rockchip,pins = <0x3 0x15 0xa 0x182 0x3 0x14 0xa 0x182>; + phandle = <0x158>; + }; + }; + + uart6 { + uart6m1-xfer { + rockchip,pins = <0x1 0x0 0xa 0x182 0x1 0x1 0xa 0x182>; + phandle = <0x159>; + }; + }; + + uart7 { + uart7m2-xfer { + rockchip,pins = <0x1 0xc 0xa 0x182 0x1 0xd 0xa 0x182>; + phandle = <0x15a>; + }; + }; + + uart8 { + uart8m1-xfer { + rockchip,pins = <0x3 0x3 0xa 0x182 0x3 0x2 0xa 0x182>; + phandle = <0x15b>; + }; + }; + + uart9 { + uart9m1-xfer { + rockchip,pins = <0x4 0xd 0xa 0x182 0x4 0xc 0xa 0x182>; + phandle = <0x15c>; + }; + }; + + gpio-func { + tsadc-gpio-func { + rockchip,pins = <0x0 0x1 0x0 0x17d>; + phandle = <0x169>; + }; + }; + + gmac0 { + gmac0-miim { + rockchip,pins = <0x4 0x14 0x1 0x17d 0x4 0x15 0x1 0x17d>; + phandle = <0x1a5>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x2 0x11 0x1 0x17d 0x2 0x12 0x1 0x17d 0x4 0x12 0x1 0x17d>; + phandle = <0x1a7>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x2 0xe 0x1 0x17d 0x2 0xf 0x1 0x17d 0x2 0x10 0x1 0x17d>; + phandle = <0x1a6>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x2 0x8 0x1 0x17d 0x2 0xb 0x1 0x17d>; + phandle = <0x1a8>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x2 0x6 0x1 0x17d 0x2 0x7 0x1 0x17d 0x2 0x9 0x1 0x17d 0x2 0xa 0x1 0x17d>; + phandle = <0x1a9>; + }; + }; + + cam { + mipidphy0-pwr { + rockchip,pins = <0x1 0x1a 0x0 0x17d>; + phandle = <0x1c3>; + }; + }; + + lcd { + lcd-rst-gpio { + rockchip,pins = <0x2 0xc 0x0 0x17d>; + phandle = <0xe0>; + }; + }; + + touch { + touch-gpio { + rockchip,pins = <0x1 0x1 0x0 0x182 0x1 0x0 0x0 0x17d>; + phandle = <0x140>; + }; + }; + }; + + usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x1a6 0x2 0x1a5 0x2 0x1a4>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <0x0 0xdd 0x4>; + power-domains = <0x50 0x1f>; + resets = <0x2 0x2a7>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <0x189 0x18a>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + }; + }; + + syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf\0syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + phandle = <0x1b1>; + }; + + syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + phandle = <0x1b0>; + }; + + syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + phandle = <0x1ad>; + }; + + syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + phandle = <0x1ac>; + + usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <0x0 0x18a 0x4>; + resets = <0x2 0xc0048 0x2 0x489>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0x0>; + rockchip,usbctrl-grf = <0x61>; + status = "okay"; + phandle = <0x1ae>; + + otg-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x189>; + }; + }; + }; + + syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + phandle = <0x1ab>; + }; + + ethernet@fe1b0000 { + local-mac-address = [42 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <0x0 0xe3 0x4 0x0 0xe2 0x4>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xb1>; + rockchip,php_grf = <0x63>; + clocks = <0x2 0x144 0x2 0x145 0x2 0x167 0x2 0x16c 0x2 0x142>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x2 0x20a>; + reset-names = "stmmaceth"; + power-domains = <0x50 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x1a1>; + snps,mtl-rx-config = <0x1a2>; + snps,mtl-tx-config = <0x1a3>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0x1a4 0xb 0x1>; + snps,reset-active-low; + snps,reset-delays-us = <0x0 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x1a5 0x1a6 0x1a7 0x1a8 0x1a9>; + tx_delay = <0x44>; + phy-handle = <0x1aa>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + phandle = <0x1aa>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x4>; + snps,rd_osr_lmt = <0x8>; + snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>; + phandle = <0x1a1>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x2>; + phandle = <0x1a2>; + + queue0 { + }; + + queue1 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x2>; + phandle = <0x1a3>; + + queue0 { + }; + + queue1 { + }; + }; + }; + + phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <0x1ac>; + rockchip,usb-grf = <0x61>; + rockchip,usbdpphy-grf = <0x1ad>; + rockchip,vo-grf = <0xe7>; + clocks = <0x2 0x2b6 0x2 0x280 0x2 0x26a 0x1ae>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x2 0x2f 0x2 0x30 0x2 0x31 0x2 0x32 0x2 0x484>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + + dp-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x18b>; + }; + + u3-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x18a>; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <0x1b2 0x1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + + vol-up-key { + label = "volume up"; + linux,code = <0x73>; + press-threshold-microvolt = <0x4268>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <0x72>; + press-threshold-microvolt = <0x65ce8>; + }; + + menu-key { + label = "menu"; + linux,code = <0x8b>; + press-threshold-microvolt = <0xd9490>; + }; + + back-key { + label = "back"; + linux,code = <0x9e>; + press-threshold-microvolt = <0x12d838>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + pwms = <0x1b3 0x0 0x61a8 0x0>; + status = "okay"; + phandle = <0xde>; + }; + + hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <0x1b4>; + rockchip,codec = <0x1b5>; + rockchip,jack-det; + }; + + leds { + compatible = "gpio-leds"; + + work { + gpios = <0xff 0xf 0x0>; + linux,default-trigger = "heartbeat"; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b00>; + regulator-max-microvolt = <0xb71b00>; + phandle = <0x1c0>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c0>; + phandle = <0x65>; + }; + + vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c0>; + phandle = <0x1c1>; + }; + + vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c1>; + phandle = <0x1c4>; + }; + + chosen { + bootargs = "storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal androidboot.verifiedbootstate=orange ro rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1 rockchip_pm_domains.always_on=1"; + }; + + cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd10c000 0x0 0x1000 0x0 0xfd10d000 0x0 0x1000 0x0 0xfd10e000 0x0 0x1000 0x0 0xfd10f000 0x0 0x1000 0x0 0xfd12c000 0x0 0x1000 0x0 0xfd12d000 0x0 0x1000 0x0 0xfd12e000 0x0 0x1000 0x0 0xfd12f000 0x0 0x1000>; + }; + + debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd104000 0x0 0x1000 0x0 0xfd105000 0x0 0x1000 0x0 0xfd106000 0x0 0x1000 0x0 0xfd107000 0x0 0x1000 0x0 0xfd124000 0x0 0x1000 0x0 0xfd125000 0x0 0x1000 0x0 0xfd126000 0x0 0x1000 0x0 0xfd127000 0x0 0x1000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x2>; + rockchip,wake-irq = <0x0>; + rockchip,irq-mode-enable = <0x1>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x0 0x1a7 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c2>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + linux,cma-default; + }; + + drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0xedf00000 0x0 0xb8000>; + phandle = <0x30>; + }; + + drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x0>; + pmsg-size = <0x50000>; + }; + }; + + vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <0x141 0x1a 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c3>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + phandle = <0x13e>; + }; + + vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0xf1 0x1 0x0>; + vin-supply = <0x1c4>; + pinctrl-names = "default"; + phandle = <0x62>; + }; + + vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <0x13d 0xf 0x1>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c5>; + regulator-always-on; + regulator-max-microvolt = <0x2dc6c0>; + regulator-min-microvolt = <0x2dc6c0>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <0x1c6>; + phandle = <0x10b>; + }; + + vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x10c8e0>; + regulator-max-microvolt = <0x10c8e0>; + vin-supply = <0x65>; + phandle = <0x150>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <0x1a4 0x15 0x0>; + vin-supply = <0x1c7>; + phandle = <0xdf>; + }; + + i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,name = "rockchip,es8311"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <0x1c8>; + }; + + codec { + sound-dai = <0x1c9>; + }; + }; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts new file mode 100644 index 000000000..7eec33cb7 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts @@ -0,0 +1,14132 @@ +/dts-v1/; + +/ { + serial-number = "c377a354961ceca2"; + compatible = "rockchip,rk3588-evb7-v11\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 EVB7 V11 Board"; + + memory { + reg = <0x00 0x200000 0x00 0x8200000 + 0x00 0x9400000 0x00 0xe6c00000 + 0x01 0x00 0x02 0xfc000000 + 0x03 0xfc500000 0x00 0x3a00000 + 0x04 0xf0000000 0x00 0x10000000 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + device_type = "memory"; + }; + + aliases { + csi2dcphy0 = "/csi2-dcphy0"; + csi2dcphy1 = "/csi2-dcphy1"; + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + csi2dphy3 = "/csi2-dphy3"; + csi2dphy4 = "/csi2-dphy4"; + csi2dphy5 = "/csi2-dphy5"; + dsi0 = "/dsi@fde20000"; + dsi1 = "/dsi@fde30000"; + ethernet1 = "/ethernet@fe1c0000"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + i2c0 = "/i2c@fd880000"; + i2c1 = "/i2c@fea90000"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + i2c4 = "/i2c@feac0000"; + i2c5 = "/i2c@fead0000"; + i2c6 = "/i2c@fec80000"; + i2c7 = "/i2c@fec90000"; + i2c8 = "/i2c@feca0000"; + rkcif_mipi_lvds0 = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + jpege0 = "/jpege-core@fdba0000"; + jpege1 = "/jpege-core@fdba4000"; + jpege2 = "/jpege-core@fdba8000"; + jpege3 = "/jpege-core@fdbac000"; + serial0 = "/serial@fd890000"; + serial1 = "/serial@feb40000"; + serial2 = "/serial@feb50000"; + serial3 = "/serial@feb60000"; + serial4 = "/serial@feb70000"; + serial5 = "/serial@feb80000"; + serial6 = "/serial@feb90000"; + serial7 = "/serial@feba0000"; + serial8 = "/serial@febb0000"; + serial9 = "/serial@febc0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + spi3 = "/spi@feb30000"; + spi4 = "/spi@fecb0000"; + spi5 = "/spi@fe2b0000"; + hdcp0 = "/hdcp@fde40000"; + hdcp1 = "/hdcp@fde70000"; + dp0 = "/dp@fde50000"; + dp1 = "/dp@fde60000"; + edp0 = "/edp@fdec0000"; + edp1 = "/edp@fded0000"; + ethernet0 = "/ethernet@fe1b0000"; + hdptx0 = "/phy@fed60000"; + hdptx1 = "/phy@fed70000"; + hdptxhdmi0 = "/hdmiphy@fed60000"; + hdptxhdmi1 = "/hdmiphy@fed70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi1 = "/hdmi@fdea0000"; + hdmirx0 = "/hdmirx-controller@fdee0000"; + usbdp0 = "/phy@fed80000"; + usbdp1 = "/phy@fed90000"; + mmc0 = "/mmc@fe2e0000"; + mmc1 = "/mmc@fe2c0000"; + mmc2 = "/mmc@fe2d0000"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + spll { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x29d7ab80>; + clock-output-names = "spll"; + phandle = <0x20c>; + }; + + xin32k { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + phandle = <0x20d>; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + phandle = <0x20e>; + }; + + hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x05>; + }; + + aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20f>; + }; + + hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26d>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x04>; + }; + + hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x210>; + }; + + hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c087c 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x141>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x03>; + }; + + aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x6b>; + }; + + hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e1>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x211>; + }; + + aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e0>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x212>; + }; + + aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x213>; + }; + + hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x214>; + }; + + aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x215>; + }; + + hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x216>; + }; + + aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x217>; + }; + + aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c5>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x218>; + }; + + hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c4>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x219>; + }; + + aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26c>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21a>; + }; + + aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21b>; + }; + + pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21c>; + }; + + aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21d>; + }; + + hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c092c 0x00 0x10>; + clock-names = "link"; + clocks = <0x03>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21e>; + }; + + pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x04>; + clocks = <0x04>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x73>; + }; + + pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x04>; + clocks = <0x05>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x74>; + }; + + mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s0_mclkin"; + phandle = <0x21f>; + }; + + mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s1_mclkin"; + phandle = <0x220>; + }; + + mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s2_mclkin"; + phandle = <0x221>; + }; + + mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s3_mclkin"; + phandle = <0x222>; + }; + + mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x39>; + #clock-cells = <0x00>; + clock-output-names = "i2s0_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x00>; + rockchip,bit-set-to-disable; + phandle = <0x197>; + }; + + mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <0x01>; + rockchip,bit-set-to-disable; + phandle = <0x223>; + }; + + mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58a000 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <0x06>; + phandle = <0x224>; + }; + + mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x28>; + #clock-cells = <0x00>; + clock-output-names = "i2s2_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x02>; + rockchip,bit-set-to-disable; + phandle = <0x225>; + }; + + mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x2e>; + #clock-cells = <0x00>; + clock-output-names = "i2s3_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x07>; + rockchip,bit-set-to-disable; + phandle = <0x226>; + }; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x07>; + }; + + core1 { + cpu = <0x08>; + }; + + core2 { + cpu = <0x09>; + }; + + core3 { + cpu = <0x0a>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x0b>; + }; + + core1 { + cpu = <0x0c>; + }; + }; + + cluster2 { + + core0 { + cpu = <0x0d>; + }; + + core1 { + cpu = <0x0e>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0f 0x00>; + operating-points-v2 = <0x10>; + cpu-idle-states = <0x11>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x12>; + #cooling-cells = <0x02>; + dynamic-power-coefficient = <0x64>; + cpu-supply = <0x13>; + mem-supply = <0x13>; + phandle = <0x07>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0f 0x00>; + operating-points-v2 = <0x10>; + cpu-idle-states = <0x11>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x14>; + phandle = <0x08>; + }; + + // cpu@200 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x200>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x212>; + // clocks = <0x0f 0x00>; + // operating-points-v2 = <0x10>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x8000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x80>; + // d-cache-size = <0x8000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x80>; + // next-level-cache = <0x15>; + // phandle = <0x09>; + // }; + + // cpu@300 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x300>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x212>; + // clocks = <0x0f 0x00>; + // operating-points-v2 = <0x10>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x8000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x80>; + // d-cache-size = <0x8000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x80>; + // next-level-cache = <0x16>; + // phandle = <0x0a>; + // }; + + // cpu@400 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x400>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x02>; + // operating-points-v2 = <0x17>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x18>; + // #cooling-cells = <0x02>; + // dynamic-power-coefficient = <0x12c>; + // cpu-supply = <0x19>; + // mem-supply = <0x19>; + // phandle = <0x0b>; + // }; + + // cpu@500 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x500>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x02>; + // operating-points-v2 = <0x17>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1a>; + // phandle = <0x0c>; + // }; + + // cpu@600 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x600>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x03>; + // operating-points-v2 = <0x1b>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1c>; + // #cooling-cells = <0x02>; + // dynamic-power-coefficient = <0x12c>; + // cpu-supply = <0x1d>; + // mem-supply = <0x1d>; + // phandle = <0x0d>; + // }; + + // cpu@700 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x700>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x03>; + // operating-points-v2 = <0x1b>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1e>; + // phandle = <0x0e>; + // }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x11>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x12>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x14>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x15>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x16>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x18>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1a>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1c>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1e>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1f>; + }; + }; + + cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x20 0x21 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x555 0x00 0x556 0x56b 0x01 0x56c 0x581 0x02 0x582 0x597 0x03 0x598 0x5ad 0x04 0x5ae 0x5c3 0x05 0x5c4 0x270f 0x06>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x532 0x00 0x533 0x555 0x01 0x556 0x56e 0x02 0x56f 0x582 0x03 0x583 0x59a 0x04 0x59b 0x5b2 0x05 0x5b3 0x5ca 0x06 0x5cb 0x5e2 0x07 0x5e3 0x5fa 0x08 0x5fb 0x270f 0x09>; + rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x159b40>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xf4 0xf4>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <0x24>; + rockchip,dsu-grf = <0x25>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,reboot-freq = <0x159b40>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x188940>; + phandle = <0x10>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L6 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L6 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L9 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L8 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L9 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-1296000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x4d3f6400>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L1 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L2 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1704000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6590fa00>; + opp-microvolt = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L1 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L2 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L3 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L4 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L5 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L6 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x26 0x27 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x603 0x00 0x604 0x61c 0x01 0x61d 0x635 0x02 0x636 0x64e 0x03 0x64f 0x66c 0x04 0x66d 0x68a 0x05 0x68b 0x6a8 0x06 0x6a9 0x270f 0x07>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x5f5 0x00 0x5f6 0x609 0x01 0x60a 0x61d 0x02 0x61e 0x63b 0x03 0x63c 0x64f 0x04 0x650 0x668 0x05 0x669 0x68b 0x06 0x68c 0x6ae 0x07 0x6af 0x6cf 0x08 0x6d0 0x6f0 0x09 0x6f1 0x270f 0x0a>; + rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x03>; + rockchip,grf = <0x28>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x17>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xe9 0x13>; + opp-hz = <0x00 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xe9 0x24>; + opp-hz = <0x00 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xe9 0x48>; + opp-hz = <0x00 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xe9 0x80>; + opp-hz = <0x00 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L8 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L10 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L3 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L4 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L6 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L9 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L10 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L8 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L9 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L10 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xf4240 0xe4e1c 0xe4e1c 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L8 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L9 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L10 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x29 0x2a 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x603 0x00 0x604 0x61c 0x01 0x61d 0x635 0x02 0x636 0x64e 0x03 0x64f 0x66c 0x04 0x66d 0x68a 0x05 0x68b 0x6a8 0x06 0x6a9 0x270f 0x07>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x5f5 0x00 0x5f6 0x609 0x01 0x60a 0x61d 0x02 0x61e 0x63b 0x03 0x63c 0x64f 0x04 0x650 0x668 0x05 0x669 0x68b 0x06 0x68c 0x6ae 0x07 0x6af 0x6cf 0x08 0x6d0 0x6f0 0x09 0x6f1 0x270f 0x0a>; + rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x03>; + rockchip,grf = <0x2b>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x1b>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xe9 0x13>; + opp-hz = <0x00 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xe9 0x24>; + opp-hz = <0x00 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xe9 0x48>; + opp-hz = <0x00 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xe9 0x80>; + opp-hz = <0x00 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L8 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L10 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L3 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L4 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L6 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L9 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L10 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L8 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L9 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L10 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xf4240 0xe4e1c 0xe4e1c 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L8 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L9 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L10 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e>; + phandle = <0x227>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x2c 0x2d 0x2e>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + csi2-dcphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x228>; + }; + + csi2-dcphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x229>; + }; + + csi2-dphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "okay"; + phandle = <0x22a>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x33>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0x15c>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x34>; + phandle = <0x4e>; + }; + }; + }; + }; + + csi2-dphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22b>; + }; + + csi2-dphy2 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22c>; + }; + + csi2-dphy3 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22d>; + }; + + csi2-dphy4 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22e>; + }; + + csi2-dphy5 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22f>; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <0x35>; + clocks = <0x36 0x37>; + clock-names = "hdmi0_phy_pll\0hdmi1_phy_pll"; + memory-region = <0x38>; + memory-region-names = "drm-logo"; + phandle = <0x230>; + + route { + + route-dp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x39>; + phandle = <0x231>; + }; + + route-dsi0 { + overscan,win_scale = <0x00>; + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x00>; + video,flags = <0x0a>; + video,vrefresh = <0x3c>; + video,crtc_vsync_end = <0x791>; + video,crtc_hsync_end = <0x44b>; + video,vdisplay = <0x780>; + video,hdisplay = <0x438>; + video,clock = <0x203a0>; + logo,ymirror = <0x00>; + logo,bpp = <0x18>; + logo,height = <0x1f5>; + logo,width = <0x1f4>; + logo,offset = <0x228000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3a>; + phandle = <0x232>; + }; + + route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3b>; + phandle = <0x233>; + }; + + route-edp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3c>; + phandle = <0x234>; + }; + + route-edp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + phandle = <0x235>; + }; + + route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3d>; + phandle = <0x236>; + }; + + route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3e>; + phandle = <0x237>; + }; + + route-dp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3f>; + phandle = <0x238>; + }; + + route-hdmi1 { + overscan,win_scale = <0x00>; + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x02>; + video,flags = <0x05>; + video,vrefresh = <0x3c>; + video,crtc_vsync_end = <0x441>; + video,crtc_hsync_end = <0x804>; + video,vdisplay = <0x438>; + video,hdisplay = <0x780>; + video,clock = <0x24414>; + logo,ymirror = <0x00>; + logo,bpp = <0x18>; + logo,height = <0x1f5>; + logo,width = <0x1f4>; + logo,offset = <0x228000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x40>; + phandle = <0x239>; + }; + }; + }; + + dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = <0x00 0x49 0x04>; + interrupt-names = "complete"; + devfreq-events = <0x41>; + clocks = <0x0f 0x04>; + clock-names = "dmc_clk"; + operating-points-v2 = <0x42>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x80000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08 0x40000 0x08 0x200000 0x08>; + auto-freq-en = <0x01>; + status = "okay"; + center-supply = <0x43>; + mem-supply = <0x44>; + phandle = <0x23a>; + }; + + dmc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x45 0x46 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + phandle = <0x42>; + + opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x1f78a400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x3fa86300>; + opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xc3500>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xc3500>; + }; + + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xc3500>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xc3500>; + }; + + opp-2750000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xc3500>; + }; + + opp-b-1848000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6e263e00>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1f78a400>; + opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3fa86300>; + opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-2750000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + }; + + dmcdbg { + compatible = "rockchip,rk3588-dmcdbg"; + status = "disabled"; + phandle = <0x23b>; + }; + + firmware { + + scmi { + compatible = "arm,scmi-smc"; + shmem = <0x47>; + arm,smc-id = <0x82000010>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x23c>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + assigned-clocks = <0x0f 0x00 0x0f 0x02 0x0f 0x03>; + assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; + phandle = <0x0f>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <0x01>; + phandle = <0x128>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + phandle = <0x23d>; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + phandle = <0x23e>; + }; + }; + + jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "okay"; + phandle = <0xbd>; + }; + + mipi-dcphy-dummy { + status = "disabled"; + phandle = <0x23f>; + }; + + mipi0-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x240>; + }; + + mipi1-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x241>; + }; + + mipi2-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "okay"; + phandle = <0x242>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x4e>; + phandle = <0x34>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x4f>; + phandle = <0x54>; + }; + }; + }; + }; + + mipi3-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x243>; + }; + + mipi4-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x244>; + }; + + mipi5-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x245>; + }; + + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0x0c>; + rockchip,resetgroup-count = <0x01>; + status = "okay"; + phandle = <0xb8>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif-dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x51>; + }; + + rkcif-dvp-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x51>; + status = "disabled"; + phandle = <0x246>; + }; + + rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x52>; + }; + + rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x247>; + }; + + rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x248>; + }; + + rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x249>; + }; + + rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x24a>; + }; + + rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x53>; + }; + + rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24b>; + }; + + rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24c>; + }; + + rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24d>; + }; + + rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24e>; + }; + + rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "okay"; + phandle = <0x55>; + + port { + + endpoint { + remote-endpoint = <0x54>; + phandle = <0x4f>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "okay"; + phandle = <0x24f>; + + port { + + endpoint { + remote-endpoint = <0x56>; + phandle = <0x5b>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x250>; + }; + + rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x251>; + }; + + rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x252>; + }; + + rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x57>; + }; + + rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x253>; + }; + + rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x254>; + }; + + rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x255>; + }; + + rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x256>; + }; + + rkcif-mipi-lvds4 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x58>; + }; + + rkcif-mipi-lvds4-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x257>; + }; + + rkcif-mipi-lvds4-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x258>; + }; + + rkcif-mipi-lvds4-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x259>; + }; + + rkcif-mipi-lvds4-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x25a>; + }; + + rkcif-mipi-lvds5 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x59>; + }; + + rkcif-mipi-lvds5-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x59>; + status = "disabled"; + phandle = <0x25b>; + }; + + rkcif-mipi-lvds5-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x59>; + status = "disabled"; + phandle = <0x25c>; + }; + + rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "okay"; + phandle = <0x25d>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x5b>; + phandle = <0x56>; + }; + }; + }; + + rkisp0-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x25e>; + }; + + rkisp0-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x25f>; + }; + + rkisp0-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x260>; + }; + + rkisp1-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x261>; + }; + + rkisp1-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x262>; + }; + + rkisp1-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x263>; + }; + + rkisp1-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x264>; + }; + + rkispp0-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <0x5d>; + status = "disabled"; + phandle = <0x265>; + }; + + rkispp1-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <0x5e>; + status = "disabled"; + phandle = <0x266>; + }; + + rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "okay"; + phandle = <0xc3>; + }; + + rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "okay"; + phandle = <0x267>; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <0x01>; + rockchip,sleep-mode-config = <0x1000608>; + rockchip,wakeup-config = <0x100>; + power-domains = <0x06 0x1f>; + phandle = <0x268>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + phandle = <0x269>; + }; + + thermal-zones { + phandle = <0x26a>; + + soc-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + sustainable-power = <0x834>; + thermal-sensors = <0x5f 0x00>; + phandle = <0x26b>; + + trips { + + trip-point-0 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x26c>; + }; + + trip-point-1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x60>; + }; + + soc-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x26d>; + }; + }; + + cooling-maps { + + map0 { + trip = <0x60>; + cooling-device = <0x07 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map1 { + trip = <0x60>; + cooling-device = <0x0b 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map2 { + trip = <0x60>; + cooling-device = <0x0d 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map3 { + trip = <0x60>; + cooling-device = <0x61 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + }; + }; + + bigcore0-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x01>; + phandle = <0x26e>; + + trips { + + bigcore0-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x26f>; + }; + }; + }; + + bigcore1-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x02>; + phandle = <0x270>; + + trips { + + bigcore1-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x271>; + }; + }; + }; + + littlecore-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x03>; + phandle = <0x272>; + + trips { + + litcore-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x273>; + }; + }; + }; + + center-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x04>; + phandle = <0x274>; + + trips { + + center-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x275>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x05>; + phandle = <0x276>; + + trips { + + gpu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x277>; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x06>; + phandle = <0x278>; + + trips { + + npu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x279>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x00 0x10f000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x10f000 0x100>; + + sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x100>; + phandle = <0x47>; + }; + }; + + gpu@fb000000 { + compatible = "arm,mali-valhall"; + reg = <0x00 0xfb000000 0x00 0x200000>; + interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>; + interrupt-names = "GPU\0MMU\0JOB"; + clocks = <0x0f 0x05 0x02 0x115 0x02 0x116 0x02 0x114>; + clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu"; + assigned-clocks = <0x0f 0x05>; + assigned-clock-rates = <0xbebc200>; + power-domains = <0x06 0x0c>; + operating-points-v2 = <0x62>; + #cooling-cells = <0x02>; + dynamic-power-coefficient = <0xba6>; + upthreshold = <0x1e>; + downdifferential = <0x0a>; + status = "okay"; + mali-supply = <0x63>; + mem-supply = <0x63>; + phandle = <0x61>; + }; + + gpu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x64 0x65 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x04>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x31f 0x00 0x320 0x333 0x01 0x334 0x34c 0x02 0x34d 0x365 0x03 0x366 0x37e 0x04 0x37f 0x270f 0x05>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x2f3 0x00 0x2f4 0x307 0x01 0x308 0x31b 0x02 0x31c 0x32f 0x03 0x330 0x343 0x04 0x344 0x35c 0x05 0x35d 0x375 0x06 0x376 0x38e 0x07 0x38f 0x270f 0x08>; + rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = "\0\f5"; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + rockchip,opp-clocks = <0x02 0x114>; + rockchip,grf = <0x66>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0x61a80>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = "\0\f5"; + phandle = <0x62>; + + opp-300000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt-L0 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L1 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt-L0 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L5 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L8 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-b-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L3 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L4 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L7 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L8 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + }; + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-850000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x32a9f880>; + opp-microvolt = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-1000000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x27a>; + + usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfc000000 0x00 0x400000>; + interrupts = <0x00 0xdc 0x04>; + power-domains = <0x06 0x1f>; + resets = <0x02 0x2a4>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <0x67 0x68>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + usb-role-switch; + phandle = <0x27b>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x69>; + phandle = <0x192>; + }; + }; + }; + }; + + usb@fc800000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc800000 0x00 0x40000>; + interrupts = <0x00 0xd7 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x6a 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x6c>; + phys = <0x6d>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x27c>; + }; + + usb@fc840000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc840000 0x00 0x40000>; + interrupts = <0x00 0xd8 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x6a 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x6d>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x6c>; + }; + + usb@fc880000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc880000 0x00 0x40000>; + interrupts = <0x00 0xda 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6e 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x6f>; + phys = <0x70>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x27d>; + }; + + usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc8c0000 0x00 0x40000>; + interrupts = <0x00 0xdb 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6e 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x70>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x6f>; + }; + + iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0xfc900000 0x00 0x200000>; + interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>; + interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; + #iommu-cells = <0x01>; + status = "disabled"; + phandle = <0x27e>; + }; + + iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0xfcb00000 0x00 0x200000>; + interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>; + interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; + #iommu-cells = <0x01>; + status = "disabled"; + phandle = <0x27f>; + }; + + usbhost3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>; + clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x280>; + + usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfcd00000 0x00 0x400000>; + interrupts = <0x00 0xde 0x04>; + resets = <0x02 0x237>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <0x71 0x04>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + phandle = <0x281>; + }; + }; + + syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd588000 0x00 0x2000>; + phandle = <0x282>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + mode-quiescent = <0x5242c30e>; + mode-winusb = <0x5242c30f>; + phandle = <0x283>; + }; + }; + + syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf\0syscon"; + reg = <0x00 0xfd58a000 0x00 0x2000>; + phandle = <0x110>; + }; + + syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd58c000 0x00 0x1000>; + phandle = <0xc9>; + + rgb { + compatible = "rockchip,rk3588-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <0x72>; + status = "disabled"; + phandle = <0x284>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x3e>; + status = "disabled"; + phandle = <0xf3>; + }; + }; + }; + }; + }; + + syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; + reg = <0x00 0xfd590000 0x00 0x100>; + phandle = <0x28>; + }; + + syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; + reg = <0x00 0xfd592000 0x00 0x100>; + phandle = <0x2b>; + }; + + syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf\0syscon"; + reg = <0x00 0xfd594000 0x00 0x100>; + phandle = <0x24>; + }; + + syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf\0syscon"; + reg = <0x00 0xfd598000 0x00 0x100>; + phandle = <0x25>; + }; + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x00 0xfd5a0000 0x00 0x100>; + phandle = <0x66>; + }; + + syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf\0syscon"; + reg = <0x00 0xfd5a2000 0x00 0x100>; + phandle = <0xb6>; + }; + + syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf\0syscon"; + reg = <0x00 0xfd5a4000 0x00 0x2000>; + phandle = <0xda>; + }; + + syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a6000 0x00 0x2000>; + clocks = <0x73>; + phandle = <0x102>; + }; + + syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a8000 0x00 0x100>; + clocks = <0x74>; + phandle = <0xdb>; + }; + + syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf\0syscon"; + reg = <0x00 0xfd5ac000 0x00 0x4000>; + phandle = <0x75>; + }; + + syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf\0syscon"; + reg = <0x00 0xfd5b0000 0x00 0x1000>; + phandle = <0x77>; + }; + + syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b4000 0x00 0x1000>; + phandle = <0x1a5>; + }; + + syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b5000 0x00 0x1000>; + phandle = <0x1a6>; + }; + + syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5bc000 0x00 0x100>; + phandle = <0x1a7>; + }; + + syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5c4000 0x00 0x100>; + phandle = <0x1a8>; + }; + + syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x00 0xfd5c8000 0x00 0x4000>; + phandle = <0x19f>; + }; + + syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d0000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x19e>; + + usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x00 0x10>; + interrupts = <0x00 0x189 0x04>; + resets = <0x02 0xc0047 0x02 0x488>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0x00>; + rockchip,usbctrl-grf = <0x75>; + status = "okay"; + phandle = <0x1a0>; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + rockchip,typec-vbus-det; + phandle = <0x67>; + }; + }; + }; + + syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d8000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x285>; + + usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0x00 0x187 0x04>; + resets = <0x02 0xc0049 0x02 0x48a>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x6a>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x6d>; + }; + }; + }; + + syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5dc000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x286>; + + usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0x00 0x188 0x04>; + resets = <0x02 0xc004a 0x02 0x48b>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x6e>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x70>; + }; + }; + }; + + syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x00 0xfd5e0000 0x00 0x100>; + phandle = <0x19d>; + }; + + syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5e8000 0x00 0x4000>; + phandle = <0x1a3>; + }; + + syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5ec000 0x00 0x4000>; + phandle = <0x1a4>; + }; + + syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc\0syscon"; + reg = <0x00 0xfd5f0000 0x00 0x10000>; + phandle = <0x1a9>; + }; + + clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <0x77>; + reg = <0x00 0xfd7c0000 0x00 0x5c000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x7b 0x02 0xec 0x02 0x114 0x02 0x208 0x02 0x20e 0x02 0x21f 0x02 0x77>; + assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00 0x5e69ec0 0x1312d00>; + phandle = <0x02>; + }; + + i2c@fd880000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfd880000 0x00 0x1000>; + clocks = <0x02 0x287 0x02 0x286>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13d 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x78>; + resets = <0x02 0xc0022 0x02 0xc0021>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x287>; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x19>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x1d>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + serial@fd890000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfd890000 0x00 0x100>; + interrupts = <0x00 0x14b 0x04>; + clocks = <0x02 0x2ae 0x02 0x2af>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x06 0x7a 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <0x7b>; + status = "disabled"; + phandle = <0x288>; + }; + + pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0000 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7c>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x289>; + }; + + pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0010 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7d>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1dc>; + }; + + pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0020 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7e>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x28a>; + }; + + pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0030 0x00 0x10>; + interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7f>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1f3>; + }; + + power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfd8d8000 0x00 0x400>; + phandle = <0xdc>; + + power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x06>; + + power-domain@8 { + reg = <0x08>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@9 { + reg = <0x09>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>; + pm_qos = <0x80 0x81 0x82>; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x83>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x84>; + }; + }; + }; + + power-domain@12 { + reg = <0x0c>; + clocks = <0x02 0x114 0x02 0x115 0x02 0x116>; + pm_qos = <0x85 0x86 0x87 0x88>; + }; + + power-domain@13 { + reg = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>; + pm_qos = <0x89>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>; + pm_qos = <0x8a>; + }; + + power-domain@16 { + reg = <0x10>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1c4 0x02 0x1c5>; + pm_qos = <0x8b 0x8c 0x8d>; + + power-domain@17 { + reg = <0x11>; + clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>; + pm_qos = <0x8e 0x8f 0x90>; + }; + }; + }; + + power-domain@21 { + reg = <0x15>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>; + pm_qos = <0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98>; + + power-domain@23 { + reg = <0x17>; + clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>; + pm_qos = <0x99>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>; + pm_qos = <0x89>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>; + pm_qos = <0x8a>; + }; + + power-domain@22 { + reg = <0x16>; + clocks = <0x02 0x1ba 0x02 0x1b9>; + pm_qos = <0x9a>; + }; + }; + + power-domain@24 { + reg = <0x18>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>; + pm_qos = <0x9b 0x9c>; + + power-domain@25 { + reg = <0x19>; + clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>; + pm_qos = <0x9d>; + }; + }; + + power-domain@26 { + reg = <0x1a>; + clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>; + pm_qos = <0x9e 0x9f>; + }; + + power-domain@27 { + reg = <0x1b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>; + pm_qos = <0xa0 0xa1 0xa2 0xa3>; + + power-domain@28 { + reg = <0x1c>; + clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>; + pm_qos = <0xa4 0xa5>; + }; + + power-domain@29 { + reg = <0x1d>; + clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>; + pm_qos = <0xa6 0xa7>; + }; + }; + + power-domain@30 { + reg = <0x1e>; + clocks = <0x02 0x189 0x02 0x18a>; + pm_qos = <0xa8>; + }; + + power-domain@31 { + reg = <0x1f>; + clocks = <0x02 0x166 0x02 0x1a1 0x02 0x1a4 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>; + pm_qos = <0xa9 0xaa 0xab 0xac>; + }; + + power-domain@33 { + reg = <0x21>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + }; + + power-domain@34 { + reg = <0x22>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + pm_qos = <0xad 0xae>; + }; + + power-domain@37 { + reg = <0x25>; + clocks = <0x02 0x199 0x02 0x140>; + pm_qos = <0xaf>; + }; + + power-domain@38 { + reg = <0x26>; + clocks = <0x02 0x3c 0x02 0x3d>; + }; + + power-domain@40 { + reg = <0x28>; + pm_qos = <0xb0>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x00 0xfda40000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@0 { + reg = <0x00>; + clocks = <0x02 0x2c6 0x02 0x15>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x00 0xfda50000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@1 { + reg = <0x01>; + clocks = <0x02 0x2c8 0x02 0x17>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x00 0xfda60000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@2 { + reg = <0x02>; + clocks = <0x02 0x2ca 0x02 0x1b>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x00 0xfdaf0000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@3 { + reg = <0x03>; + clocks = <0x02 0x12b 0x02 0x129>; + clock-names = "clk\0pclk"; + resets = <0x02 0x1de 0x02 0x1dc>; + reset-names = "rts\0rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x00 0xfdb30000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@4 { + reg = <0x04>; + clocks = <0x02 0x118>; + clock-names = "clk"; + resets = <0x02 0x430 0x02 0x42f>; + reset-names = "rts\0rst-p"; + }; + }; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>; + interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; + interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq"; + clocks = <0x0f 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>; + clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk"; + assigned-clocks = <0x0f 0x06>; + assigned-clock-rates = <0xbebc200>; + resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>; + reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2"; + power-domains = <0x06 0x09 0x06 0x0a 0x06 0x0b>; + power-domain-names = "npu0\0npu1\0npu2"; + operating-points-v2 = <0xb1>; + iommus = <0xb2>; + status = "disabled"; + rknpu-supply = <0xb3>; + mem-supply = <0xb3>; + phandle = <0x28b>; + }; + + npu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xb4 0xb5 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x31f 0x00 0x320 0x333 0x01 0x334 0x34c 0x02 0x34d 0x365 0x03 0x366 0x37e 0x04 0x37f 0x270f 0x05>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x2f3 0x00 0x2f4 0x307 0x01 0x308 0x31b 0x02 0x31c 0x32f 0x03 0x330 0x343 0x04 0x344 0x35c 0x05 0x35d 0x375 0x06 0x376 0x38e 0x07 0x38f 0x270f 0x08>; + rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = "\0\f5"; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + rockchip,opp-clocks = <0x02 0x12a 0x02 0x12f>; + rockchip,grf = <0xb6>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0x7a120>; + rockchip,init-freq = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = "\0\f5"; + phandle = <0xb1>; + + opp-300000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L1 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L6 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L6 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L7 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L8 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-b-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L8 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + }; + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-950000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L1 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L2 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L3 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L4 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L5 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + }; + }; + + iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>; + interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; + interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu"; + clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>; + clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2"; + #iommu-cells = <0x00>; + status = "disabled"; + phandle = <0xb2>; + }; + + vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x00 0xfdb50000 0x00 0x400>; + interrupts = <0x00 0x78 0x04>; + interrupt-names = "irq_vepu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x28c>; + }; + + vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x00 0xfdb50400 0x00 0x400>; + interrupts = <0x00 0x77 0x04>; + interrupt-names = "irq_vdpu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x28d>; + }; + + iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb50800 0x00 0x40>; + interrupts = <0x00 0x76 0x04>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xb7>; + }; + + avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x00 0xfdb51000 0x00 0x200>; + interrupts = <0x00 0x77 0x04>; + interrupt-names = "irq_avsd"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + power-domains = <0x06 0x15>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + status = "okay"; + phandle = <0x28e>; + }; + + rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x00 0xfdb60000 0x00 0x1000>; + interrupts = <0x00 0x72 0x04>; + interrupt-names = "rga3_core0_irq"; + clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>; + clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0"; + power-domains = <0x06 0x16>; + iommus = <0xb9>; + status = "okay"; + phandle = <0x28f>; + }; + + iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb60f00 0x00 0x100>; + interrupts = <0x00 0x72 0x04>; + interrupt-names = "rga3_0_mmu"; + clocks = <0x02 0x1ba 0x02 0x1b9>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x16>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xb9>; + }; + + rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x00 0xfdb70000 0x00 0x1000>; + interrupts = <0x00 0x73 0x04>; + interrupt-names = "rga3_core1_irq"; + clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>; + clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1"; + power-domains = <0x06 0x1e>; + iommus = <0xba>; + status = "okay"; + phandle = <0x290>; + }; + + iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb70f00 0x00 0x100>; + interrupts = <0x00 0x73 0x04>; + interrupt-names = "rga3_1_mmu"; + clocks = <0x02 0x18a 0x02 0x189>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1e>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xba>; + }; + + rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x00 0xfdb80000 0x00 0x1000>; + interrupts = <0x00 0x74 0x04>; + interrupt-names = "rga2_irq"; + clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>; + clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2"; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x291>; + }; + + jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x00 0xfdb90000 0x00 0x400>; + interrupts = <0x00 0x81 0x04>; + interrupt-names = "irq_jpegd"; + clocks = <0x02 0x1b4 0x02 0x1b5>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x23c34600 0x00>; + assigned-clocks = <0x02 0x1b4>; + assigned-clock-rates = <0x23c34600>; + resets = <0x02 0x2d2 0x02 0x2d3>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + iommus = <0xbb>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x01>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x292>; + }; + + iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb90480 0x00 0x40>; + interrupts = <0x00 0x82 0x04>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <0x02 0x1b4 0x02 0x1b5>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbb>; + }; + + jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba0000 0x00 0x400>; + interrupts = <0x00 0x7a 0x04>; + interrupt-names = "irq_jpege0"; + clocks = <0x02 0x1ac 0x02 0x1ad>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1ac>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2ca 0x02 0x2cb>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbc>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x293>; + }; + + iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba0800 0x00 0x40>; + interrupts = <0x00 0x79 0x04>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <0x02 0x1ac 0x02 0x1ad>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbc>; + }; + + jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba4000 0x00 0x400>; + interrupts = <0x00 0x7c 0x04>; + interrupt-names = "irq_jpege1"; + clocks = <0x02 0x1ae 0x02 0x1af>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1ae>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2cc 0x02 0x2cd>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbe>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x294>; + }; + + iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba4800 0x00 0x40>; + interrupts = <0x00 0x7b 0x04>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <0x02 0x1ae 0x02 0x1af>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbe>; + }; + + jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba8000 0x00 0x400>; + interrupts = <0x00 0x7e 0x04>; + interrupt-names = "irq_jpege2"; + clocks = <0x02 0x1b0 0x02 0x1b1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1b0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2ce 0x02 0x2cf>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbf>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x295>; + }; + + iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba8800 0x00 0x40>; + interrupts = <0x00 0x7d 0x04>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <0x02 0x1b0 0x02 0x1b1>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbf>; + }; + + jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdbac000 0x00 0x400>; + interrupts = <0x00 0x80 0x04>; + interrupt-names = "irq_jpege3"; + clocks = <0x02 0x1b2 0x02 0x1b3>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1b2>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2d0 0x02 0x2d1>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xc0>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x296>; + }; + + iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbac800 0x00 0x40>; + interrupts = <0x00 0x7f 0x04>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <0x02 0x1b2 0x02 0x1b3>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xc0>; + }; + + iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x00 0xfdbb0000 0x00 0x500>; + interrupts = <0x00 0x75 0x04>; + interrupt-names = "irq_iep"; + clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>; + clock-names = "aclk\0hclk\0sclk"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1aa>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>; + reset-names = "rst_a\0rst_h\0rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <0x06 0x15>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x06>; + iommus = <0xc1>; + status = "okay"; + phandle = <0x297>; + }; + + iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbb0800 0x00 0x100>; + interrupts = <0x00 0x75 0x04>; + interrupt-names = "irq_iep_mmu"; + clocks = <0x02 0x1aa 0x02 0x1a9>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0xc1>; + }; + + rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x00 0xfdbd0000 0x00 0x6000>; + interrupts = <0x00 0x65 0x04>; + interrupt-names = "irq_rkvenc0"; + clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x1dcd6500 0x00 0x2faf0800>; + assigned-clocks = <0x02 0x1c5 0x02 0x1c6>; + assigned-clock-rates = <0x1dcd6500 0x2faf0800>; + resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xc2>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xc3>; + rockchip,taskqueue-node = <0x07>; + rockchip,task-capacity = <0x08>; + power-domains = <0x06 0x10>; + operating-points-v2 = <0xc4>; + status = "okay"; + venc-supply = <0xc5>; + mem-supply = <0xc5>; + phandle = <0x298>; + }; + + iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>; + interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>; + interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1"; + clocks = <0x02 0x1c5 0x02 0x1c4>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x00>; + power-domains = <0x06 0x10>; + status = "okay"; + phandle = <0xc2>; + }; + + rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x00 0xfdbe0000 0x00 0x6000>; + interrupts = <0x00 0x68 0x04>; + interrupt-names = "irq_rkvenc1"; + clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x1dcd6500 0x00 0x2faf0800>; + assigned-clocks = <0x02 0x1ca 0x02 0x1cb>; + assigned-clock-rates = <0x1dcd6500 0x2faf0800>; + resets = <0x02 0x305 0x02 0x304 0x02 0x306>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xc6>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xc3>; + rockchip,taskqueue-node = <0x07>; + rockchip,task-capacity = <0x08>; + power-domains = <0x06 0x11>; + operating-points-v2 = <0xc4>; + status = "okay"; + venc-supply = <0xc5>; + mem-supply = <0xc5>; + phandle = <0x299>; + }; + + iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>; + interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>; + interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1"; + clocks = <0x02 0x1ca 0x02 0x1c9>; + lock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x00>; + power-domains = <0x06 0x11>; + status = "okay"; + phandle = <0xc6>; + }; + + venc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xc7 0xc8>; + nvmem-cell-names = "leakage\0opp-info"; + rockchip,leakage-voltage-sel = <0x01 0x0f 0x00 0x10 0x19 0x01 0x1a 0xfe 0x02>; + rockchip,grf = <0xc9>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + phandle = <0xc4>; + + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L0 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + }; + + rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x00 0xfdc30000 0x00 0x100>; + reg-names = "ccu"; + clocks = <0x02 0x18e>; + clock-names = "aclk_ccu"; + assigned-clocks = <0x02 0x18e>; + assigned-clock-rates = <0x23c34600>; + resets = <0x02 0x282>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + rockchip,ccu-mode = <0x01>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0xcb>; + }; + + rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>; + reg-names = "regs\0link"; + interrupts = <0x00 0x5f 0x04>; + interrupt-names = "irq_rkvdec0"; + clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xca>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xcb>; + rockchip,core-mask = <0x10001>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x09>; + rockchip,sram = <0xcc>; + rockchip,rcb-iova = <0xfff00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0x29a>; + }; + + iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>; + interrupts = <0x00 0x60 0x04>; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <0x02 0x190 0x02 0x18f>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x00>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0xca>; + }; + + rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>; + reg-names = "regs\0link"; + interrupts = <0x00 0x61 0x04>; + interrupt-names = "irq_rkvdec1"; + clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xcd>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xcb>; + rockchip,core-mask = <0x20002>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x09>; + rockchip,sram = <0xce>; + rockchip,rcb-iova = <0xffe00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x06 0x0f>; + status = "okay"; + phandle = <0x29b>; + }; + + iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>; + interrupts = <0x00 0x62 0x04>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <0x02 0x195 0x02 0x194>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x00>; + power-domains = <0x06 0x0f>; + status = "okay"; + phandle = <0xcd>; + }; + + av1d@fdc70000 { + compatible = "rockchip,av1-decoder"; + reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>; + reg-names = "vcd\0cache\0afbc"; + interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>; + interrupt-names = "irq_av1d\0irq_cache\0irq_afbc"; + clocks = <0x02 0x49 0x02 0x4b>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x17d78400 0x17d78400>; + assigned-clocks = <0x02 0x49 0x02 0x4b>; + assigned-clock-rates = <0x17d78400 0x17d78400>; + resets = <0x02 0x442 0x02 0x445>; + reset-names = "video_a\0video_h"; + iommus = <0xcf>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x0b>; + power-domains = <0x06 0x17>; + status = "okay"; + phandle = <0x29c>; + }; + + iommu@fdca0000 { + compatible = "rockchip,iommu-av1d"; + reg = <0x00 0xfdca0000 0x00 0x600>; + interrupts = <0x00 0x6d 0x04>; + interrupt-names = "irq_av1d_mmu"; + clocks = <0x02 0x49 0x02 0x4b>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + power-domains = <0x06 0x17>; + status = "okay"; + phandle = <0xcf>; + }; + + rkisp-unite@fdcb0000 { + compatible = "rockchip,rk3588-rkisp-unite"; + reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>; + interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; + clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1"; + power-domains = <0x06 0x1c>; + iommus = <0xd0>; + status = "disabled"; + phandle = <0x29d>; + }; + + rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x00 0xfdcb0000 0x00 0x7f00>; + interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x06 0x1b>; + iommus = <0xd1>; + status = "okay"; + phandle = <0x5a>; + }; + + rkisp-unite-mmu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>; + interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>; + interrupt-names = "isp0_mmu\0isp1_mmu"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>; + clock-names = "aclk0\0iface0\0aclk1\0iface1"; + power-domains = <0x06 0x1c>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd0>; + }; + + iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcb7f00 0x00 0x100>; + interrupts = <0x00 0x84 0x04>; + interrupt-names = "isp0_mmu"; + clocks = <0x02 0x1de 0x02 0x1df>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1b>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0xd1>; + }; + + rkisp@fdcc0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x00 0xfdcc0000 0x00 0x7f00>; + interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x06 0x1c>; + iommus = <0xd2>; + status = "disabled"; + phandle = <0x5c>; + }; + + iommu@fdcc7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcc7f00 0x00 0x100>; + interrupts = <0x00 0x88 0x04>; + interrupt-names = "isp1_mmu"; + clocks = <0x02 0x120 0x02 0x121>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1c>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd2>; + }; + + rkispp@fdcd0000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x00 0xfdcd0000 0x00 0xf00>; + interrupts = <0x00 0x8b 0x04>; + interrupt-names = "fec_irq"; + clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; + clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; + assigned-clocks = <0x02 0x1d6>; + assigned-clock-rates = <0x5f5e100>; + power-domains = <0x06 0x1d>; + iommus = <0xd3>; + status = "disabled"; + phandle = <0x5d>; + }; + + iommu@fdcd0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcd0f00 0x00 0x100>; + interrupts = <0x00 0x8c 0x04>; + interrupt-names = "fec0_mmu"; + clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; + clock-names = "aclk\0iface\0pclk"; + power-domains = <0x06 0x1d>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd3>; + }; + + rkispp@fdcd8000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x00 0xfdcd8000 0x00 0xf00>; + interrupts = <0x00 0x8d 0x04>; + interrupt-names = "fec_irq"; + clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; + clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; + assigned-clocks = <0x02 0x1d9>; + assigned-clock-rates = <0x5f5e100>; + power-domains = <0x06 0x1d>; + iommus = <0xd4>; + status = "disabled"; + phandle = <0x5e>; + }; + + iommu@fdcd8f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcd8f00 0x00 0x100>; + interrupts = <0x00 0x8e 0x04>; + interrupt-names = "fec1_mmu"; + clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; + clock-names = "aclk\0iface\0pclk"; + power-domains = <0x06 0x1d>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd4>; + }; + + rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x00 0xfdce0000 0x00 0x800>; + reg-names = "cif_regs"; + interrupts = <0x00 0x9b 0x04>; + interrupt-names = "cif-intr"; + clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3 0x02 0x1cd 0x02 0x1ce>; + clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_host0\0iclk_host1"; + resets = <0x02 0x317 0x02 0x318 0x02 0x316 0x02 0x334 0x02 0x335 0x02 0x336 0x02 0x337 0x02 0x338 0x02 0x339>; + reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_host0\0rst_cif_host1\0rst_cif_host2\0rst_cif_host3\0rst_cif_host4\0rst_cif_host5"; + assigned-clocks = <0x02 0x1e3>; + assigned-clock-rates = <0x23c34600>; + power-domains = <0x06 0x1b>; + rockchip,grf = <0xc9>; + iommus = <0xd5>; + nvmem-cells = <0x22 0xd6 0xd7>; + nvmem-cell-names = "specification\0package_low\0package_high"; + status = "okay"; + phandle = <0x50>; + }; + + iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>; + interrupts = <0x00 0x71 0x04>; + interrupt-names = "cif_mmu"; + clocks = <0x02 0x1e4 0x02 0x1e5>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1b>; + rockchip,disable-mmu-reset; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xd5>; + }; + + mipi0-csi2-hw@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd10000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1cf>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x324>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x48>; + }; + + mipi1-csi2-hw@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd20000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d0>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x325>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x49>; + }; + + mipi2-csi2-hw@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd30000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d1>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x326>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4a>; + }; + + mipi3-csi2-hw@fdd40000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd40000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d2>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x327>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4b>; + }; + + mipi4-csi2-hw@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd50000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x97 0x04 0x00 0x98 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d3>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x328>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4c>; + }; + + mipi5-csi2-hw@fdd60000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd60000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x99 0x04 0x00 0x9a 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d4>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x329>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4d>; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x00 0x9c 0x04>; + clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273 0x02 0x27d 0x02 0x27e 0x02 0x26b>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2\0aclk_dovi\0aclk_vop_div2_src\0aclk_vop_root"; + assigned-clocks = <0x02 0x270>; + assigned-clock-rates = <0x2cb41780>; + resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>; + reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3"; + rockchip,aclk-normal-mode-rates = <0x1dcd6500>; + rockchip,aclk-advanced-mode-rates = <0x2cb41780>; + operating-points-v2 = <0xd8>; + iommus = <0xd9>; + power-domains = <0x06 0x18>; + rockchip,grf = <0xc9>; + rockchip,vop-grf = <0xda>; + rockchip,vo1-grf = <0xdb>; + rockchip,pmu = <0xdc>; + status = "okay"; + vop-supply = <0x44>; + phandle = <0x29e>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x35>; + + port@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; + rockchip,plane-mask = <0x05>; + rockchip,primary-plane = <0x02>; + phandle = <0x29f>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xdd>; + phandle = <0x104>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xde>; + phandle = <0x10e>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xdf>; + phandle = <0x3d>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xe0>; + phandle = <0x1bb>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xe1>; + phandle = <0x1c4>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xe2>; + phandle = <0x1c1>; + }; + }; + + port@1 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; + rockchip,plane-mask = <0x0a>; + rockchip,primary-plane = <0x03>; + phandle = <0x2a0>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xe3>; + phandle = <0x39>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xe4>; + phandle = <0x10f>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xe5>; + phandle = <0x10b>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xe6>; + phandle = <0x3f>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xe7>; + phandle = <0x1c5>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xe8>; + phandle = <0x40>; + }; + }; + + port@2 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x02>; + assigned-clocks = <0x02 0x273>; + assigned-clock-parents = <0x02 0x04>; + rockchip,plane-mask = <0x140>; + rockchip,primary-plane = <0x08>; + phandle = <0x2a1>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xe9>; + phandle = <0x105>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xea>; + phandle = <0x3c>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xeb>; + phandle = <0x10c>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xec>; + phandle = <0xf6>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xed>; + phandle = <0xfe>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xee>; + phandle = <0x1bc>; + }; + + endpoint@6 { + reg = <0x06>; + remote-endpoint = <0xef>; + phandle = <0x1c6>; + }; + + endpoint@7 { + reg = <0x07>; + remote-endpoint = <0xf0>; + phandle = <0x1c2>; + }; + }; + + port@3 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x03>; + rockchip,plane-mask = <0x280>; + rockchip,primary-plane = <0x09>; + phandle = <0x2a2>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xf1>; + phandle = <0x3a>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xf2>; + phandle = <0x3b>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xf3>; + phandle = <0x3e>; + }; + }; + }; + }; + + vop-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x45>; + nvmem-cell-names = "leakage"; + rockchip,init-freq = <0xb71b0>; + rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>; + phandle = <0xd8>; + + opp-5000000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-7500000000 { + opp-hz = <0x00 0x2cb41780>; + opp-microvolt = <0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-8500000000 { + opp-hz = <0x00 0x32a9f880>; + opp-microvolt = "\0\f5\0\0\f5\0\0\f5"; + opp-microvolt-L1 = <0xbd358 0xbd358 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xc3500>; + }; + }; + + iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>; + interrupts = <0x00 0x9c 0x04>; + interrupt-names = "vop_mmu"; + clocks = <0x02 0x270 0x02 0x26f>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + phandle = <0xd9>; + }; + + spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfddb0000 0x00 0x1000>; + interrupts = <0x00 0xc3 0x04>; + dmas = <0xf4 0x06>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x209 0x02 0x204>; + assigned-clocks = <0x02 0x205>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1e5>; + }; + + i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddc0000 0x00 0x1000>; + interrupts = <0x00 0xb8 0x04>; + clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x1f9>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x00>; + dma-names = "tx"; + power-domains = <0x06 0x19>; + resets = <0x02 0x38d>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a3>; + }; + + spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfdde0000 0x00 0x1000>; + interrupts = <0x00 0xc4 0x04>; + dmas = <0xf4 0x07>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x257 0x02 0x253>; + assigned-clocks = <0x02 0x254>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x1a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a4>; + }; + + i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf0000 0x00 0x1000>; + interrupts = <0x00 0xb9 0x04>; + clocks = <0x02 0x246 0x02 0x246 0x02 0x248>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x243>; + assigned-clock-parents = <0x02 0x07>; + dmas = <0xf5 0x02>; + dma-names = "tx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3e8>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1df>; + }; + + i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddfc000 0x00 0x1000>; + interrupts = <0x00 0xbd 0x04>; + clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x23f>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x17>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x413>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a5>; + }; + + spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde08000 0x00 0x1000>; + interrupts = <0x00 0xc7 0x04>; + clocks = <0x02 0x25e 0x02 0x25d>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x25e>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x15>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3fd>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a6>; + }; + + dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x00 0xfde20000 0x00 0x10000>; + interrupts = <0x00 0xa7 0x04>; + clocks = <0x02 0x278 0x02 0x27a>; + clock-names = "pclk\0sys_clk"; + resets = <0x02 0x354>; + reset-names = "apb"; + power-domains = <0x06 0x18>; + phys = <0x31>; + phy-names = "dcphy"; + rockchip,grf = <0xda>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2a7>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2a8>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xf6>; + status = "disabled"; + phandle = <0xec>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3a>; + status = "okay"; + phandle = <0xf1>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xf7>; + phandle = <0xfd>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xf8>; + reset-delay-ms = <0x0a>; + enable-delay-ms = <0x0a>; + prepare-delay-ms = <0x0a>; + init-delay-ms = <0x0a>; + unprepare-delay-ms = <0x0a>; + disable-delay-ms = <0x3c>; + width-mm = <0x44>; + height-mm = <0x79>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 00 01 29]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xf9>; + reset-gpios = <0xfa 0x1b 0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0xfb>; + phandle = <0x2a9>; + + display-timings { + native-mode = <0xfc>; + phandle = <0x2aa>; + + timing0 { + clock-frequency = <0x7de2900>; + hactive = <0x438>; + vactive = <0x780>; + hfront-porch = <0x0f>; + hsync-len = <0x04>; + hback-porch = <0x1e>; + vfront-porch = <0x0f>; + vsync-len = <0x02>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0xfc>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xfd>; + phandle = <0xf7>; + }; + }; + }; + }; + }; + + dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x00 0xfde30000 0x00 0x10000>; + interrupts = <0x00 0xa8 0x04>; + clocks = <0x02 0x279 0x02 0x27b>; + clock-names = "pclk\0sys_clk"; + resets = <0x02 0x355>; + reset-names = "apb"; + power-domains = <0x06 0x18>; + phys = <0x32>; + phy-names = "dcphy"; + rockchip,grf = <0xda>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2ab>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2ac>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xfe>; + status = "disabled"; + phandle = <0xed>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3b>; + status = "disabled"; + phandle = <0xf2>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xff>; + phandle = <0x101>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xf8>; + reset-delay-ms = <0x0a>; + enable-delay-ms = <0x0a>; + prepare-delay-ms = <0x0a>; + init-delay-ms = <0x0a>; + unprepare-delay-ms = <0x0a>; + disable-delay-ms = <0x0a>; + width-mm = <0x44>; + height-mm = <0x79>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 00 01 29]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xf9>; + phandle = <0x2ad>; + + display-timings { + native-mode = <0x100>; + phandle = <0x2ae>; + + timing0 { + clock-frequency = <0x7de2900>; + hactive = <0x438>; + vactive = <0x780>; + hfront-porch = <0x0f>; + hsync-len = <0x04>; + hback-porch = <0x1e>; + vfront-porch = <0x0f>; + vsync-len = <0x02>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0x100>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x101>; + phandle = <0xff>; + }; + }; + }; + }; + }; + + hdcp@fde40000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x00 0xfde40000 0x00 0x80>; + interrupts = <0x00 0x9f 0x04>; + clocks = <0x02 0x1ed 0x02 0x1ef 0x02 0x1ee 0x02 0x1ec 0x02 0x1f1 0x02 0x1f2>; + clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng"; + resets = <0x02 0x37f 0x02 0x37d 0x02 0x37c 0x02 0x37b 0x02 0x381>; + reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng"; + power-domains = <0x06 0x19>; + rockchip,vo-grf = <0x102>; + status = "disabled"; + phandle = <0x2af>; + }; + + dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x00 0xfde50000 0x00 0x4000>; + interrupts = <0x00 0xa1 0x04>; + clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04 0x02 0x1ea>; + clock-names = "apb\0aux\0i2s\0spdif\0hclk\0hdcp"; + assigned-clocks = <0x02 0x2cc>; + assigned-clock-rates = <0xf42400>; + resets = <0x02 0x388>; + phys = <0x103>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x01>; + status = "okay"; + phandle = <0x1e6>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x104>; + status = "disabled"; + phandle = <0xdd>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x39>; + status = "disabled"; + phandle = <0xe3>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x105>; + status = "okay"; + phandle = <0xe9>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x2b0>; + }; + }; + }; + }; + + hdcp@fde70000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x00 0xfde70000 0x00 0x80>; + interrupts = <0x00 0xa0 0x04>; + clocks = <0x02 0x217 0x02 0x219 0x02 0x218 0x02 0x216 0x02 0x228 0x02 0x229>; + clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng"; + resets = <0x02 0x3c8 0x02 0x3c6 0x02 0x3c5 0x02 0x3c4 0x02 0x3ca>; + reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng"; + power-domains = <0x06 0x1a>; + rockchip,vo-grf = <0xdb>; + status = "disabled"; + phandle = <0x2b1>; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfde80000 0x00 0x10000 0x00 0xfde90000 0x00 0x10000>; + interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>; + clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x36>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x02 0x3d0 0x02 0x49c>; + reset-names = "ref\0hdp"; + power-domains = <0x06 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0x106 0x107 0x108 0x109>; + reg-io-width = <0x04>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + phys = <0x36>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "disabled"; + enable-gpios = <0x10a 0x09 0x00>; + phandle = <0x1e3>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2b2>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x3d>; + status = "disabled"; + phandle = <0xdf>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x10b>; + status = "disabled"; + phandle = <0xe5>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x10c>; + status = "disabled"; + phandle = <0xeb>; + }; + }; + }; + }; + + edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x00 0xfdec0000 0x00 0x1000>; + interrupts = <0x00 0xa3 0x04>; + clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>; + clock-names = "dp\0pclk\0spdif\0hclk"; + resets = <0x02 0x3e1 0x02 0x3e0>; + reset-names = "dp\0apb"; + phys = <0x10d>; + phy-names = "dp"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xdb>; + #sound-dai-cells = <0x01>; + status = "disabled"; + phandle = <0x1e0>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x10e>; + status = "disabled"; + phandle = <0xde>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x10f>; + status = "disabled"; + phandle = <0xe4>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x3c>; + status = "disabled"; + phandle = <0xea>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x2b3>; + }; + }; + }; + }; + + qos@fdf35000 { + compatible = "syscon"; + reg = <0x00 0xfdf35000 0x00 0x20>; + phandle = <0x85>; + }; + + qos@fdf35200 { + compatible = "syscon"; + reg = <0x00 0xfdf35200 0x00 0x20>; + phandle = <0x86>; + }; + + qos@fdf35400 { + compatible = "syscon"; + reg = <0x00 0xfdf35400 0x00 0x20>; + phandle = <0x87>; + }; + + qos@fdf35600 { + compatible = "syscon"; + reg = <0x00 0xfdf35600 0x00 0x20>; + phandle = <0x88>; + }; + + qos@fdf36000 { + compatible = "syscon"; + reg = <0x00 0xfdf36000 0x00 0x20>; + phandle = <0xa8>; + }; + + qos@fdf39000 { + compatible = "syscon"; + reg = <0x00 0xfdf39000 0x00 0x20>; + phandle = <0xaf>; + }; + + qos@fdf3a000 { + compatible = "syscon"; + reg = <0x00 0xfdf3a000 0x00 0x20>; + phandle = <0xad>; + }; + + qos@fdf3a200 { + compatible = "syscon"; + reg = <0x00 0xfdf3a200 0x00 0x20>; + phandle = <0xae>; + }; + + qos@fdf3d800 { + compatible = "syscon"; + reg = <0x00 0xfdf3d800 0x00 0x20>; + phandle = <0xb0>; + }; + + qos@fdf3e000 { + compatible = "syscon"; + reg = <0x00 0xfdf3e000 0x00 0x20>; + phandle = <0xaa>; + }; + + qos@fdf3e200 { + compatible = "syscon"; + reg = <0x00 0xfdf3e200 0x00 0x20>; + phandle = <0xa9>; + }; + + qos@fdf3e400 { + compatible = "syscon"; + reg = <0x00 0xfdf3e400 0x00 0x20>; + phandle = <0xab>; + }; + + qos@fdf3e600 { + compatible = "syscon"; + reg = <0x00 0xfdf3e600 0x00 0x20>; + phandle = <0xac>; + }; + + qos@fdf40000 { + compatible = "syscon"; + reg = <0x00 0xfdf40000 0x00 0x20>; + phandle = <0xa6>; + }; + + qos@fdf40200 { + compatible = "syscon"; + reg = <0x00 0xfdf40200 0x00 0x20>; + phandle = <0xa7>; + }; + + qos@fdf40400 { + compatible = "syscon"; + reg = <0x00 0xfdf40400 0x00 0x20>; + phandle = <0xa0>; + }; + + qos@fdf40500 { + compatible = "syscon"; + reg = <0x00 0xfdf40500 0x00 0x20>; + phandle = <0xa1>; + }; + + qos@fdf40600 { + compatible = "syscon"; + reg = <0x00 0xfdf40600 0x00 0x20>; + phandle = <0xa2>; + }; + + qos@fdf40800 { + compatible = "syscon"; + reg = <0x00 0xfdf40800 0x00 0x20>; + phandle = <0xa3>; + }; + + qos@fdf41000 { + compatible = "syscon"; + reg = <0x00 0xfdf41000 0x00 0x20>; + phandle = <0xa4>; + }; + + qos@fdf41100 { + compatible = "syscon"; + reg = <0x00 0xfdf41100 0x00 0x20>; + phandle = <0xa5>; + }; + + qos@fdf60000 { + compatible = "syscon"; + reg = <0x00 0xfdf60000 0x00 0x20>; + phandle = <0x8b>; + }; + + qos@fdf60200 { + compatible = "syscon"; + reg = <0x00 0xfdf60200 0x00 0x20>; + phandle = <0x8c>; + }; + + qos@fdf60400 { + compatible = "syscon"; + reg = <0x00 0xfdf60400 0x00 0x20>; + phandle = <0x8d>; + }; + + qos@fdf61000 { + compatible = "syscon"; + reg = <0x00 0xfdf61000 0x00 0x20>; + phandle = <0x8e>; + }; + + qos@fdf61200 { + compatible = "syscon"; + reg = <0x00 0xfdf61200 0x00 0x20>; + phandle = <0x8f>; + }; + + qos@fdf61400 { + compatible = "syscon"; + reg = <0x00 0xfdf61400 0x00 0x20>; + phandle = <0x90>; + }; + + qos@fdf62000 { + compatible = "syscon"; + reg = <0x00 0xfdf62000 0x00 0x20>; + phandle = <0x89>; + }; + + qos@fdf63000 { + compatible = "syscon"; + reg = <0x00 0xfdf63000 0x00 0x20>; + phandle = <0x8a>; + }; + + qos@fdf64000 { + compatible = "syscon"; + reg = <0x00 0xfdf64000 0x00 0x20>; + phandle = <0x99>; + }; + + qos@fdf66000 { + compatible = "syscon"; + reg = <0x00 0xfdf66000 0x00 0x20>; + phandle = <0x91>; + }; + + qos@fdf66200 { + compatible = "syscon"; + reg = <0x00 0xfdf66200 0x00 0x20>; + phandle = <0x92>; + }; + + qos@fdf66400 { + compatible = "syscon"; + reg = <0x00 0xfdf66400 0x00 0x20>; + phandle = <0x93>; + }; + + qos@fdf66600 { + compatible = "syscon"; + reg = <0x00 0xfdf66600 0x00 0x20>; + phandle = <0x94>; + }; + + qos@fdf66800 { + compatible = "syscon"; + reg = <0x00 0xfdf66800 0x00 0x20>; + phandle = <0x95>; + }; + + qos@fdf66a00 { + compatible = "syscon"; + reg = <0x00 0xfdf66a00 0x00 0x20>; + phandle = <0x96>; + }; + + qos@fdf66c00 { + compatible = "syscon"; + reg = <0x00 0xfdf66c00 0x00 0x20>; + phandle = <0x97>; + }; + + qos@fdf66e00 { + compatible = "syscon"; + reg = <0x00 0xfdf66e00 0x00 0x20>; + phandle = <0x98>; + }; + + qos@fdf67000 { + compatible = "syscon"; + reg = <0x00 0xfdf67000 0x00 0x20>; + phandle = <0x9a>; + }; + + qos@fdf67200 { + compatible = "syscon"; + reg = <0x00 0xfdf67200 0x00 0x20>; + phandle = <0x2b4>; + }; + + qos@fdf70000 { + compatible = "syscon"; + reg = <0x00 0xfdf70000 0x00 0x20>; + phandle = <0x83>; + }; + + qos@fdf71000 { + compatible = "syscon"; + reg = <0x00 0xfdf71000 0x00 0x20>; + phandle = <0x84>; + }; + + qos@fdf72000 { + compatible = "syscon"; + reg = <0x00 0xfdf72000 0x00 0x20>; + phandle = <0x80>; + }; + + qos@fdf72200 { + compatible = "syscon"; + reg = <0x00 0xfdf72200 0x00 0x20>; + phandle = <0x81>; + }; + + qos@fdf72400 { + compatible = "syscon"; + reg = <0x00 0xfdf72400 0x00 0x20>; + phandle = <0x82>; + }; + + qos@fdf80000 { + compatible = "syscon"; + reg = <0x00 0xfdf80000 0x00 0x20>; + phandle = <0x9d>; + }; + + qos@fdf81000 { + compatible = "syscon"; + reg = <0x00 0xfdf81000 0x00 0x20>; + phandle = <0x9e>; + }; + + qos@fdf81200 { + compatible = "syscon"; + reg = <0x00 0xfdf81200 0x00 0x20>; + phandle = <0x9f>; + }; + + qos@fdf82000 { + compatible = "syscon"; + reg = <0x00 0xfdf82000 0x00 0x20>; + phandle = <0x9b>; + }; + + qos@fdf82200 { + compatible = "syscon"; + reg = <0x00 0xfdf82200 0x00 0x20>; + phandle = <0x9c>; + }; + + dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + rockchip,pmu_grf = <0x110>; + clocks = <0x02 0x2d2 0x02 0x2d3 0x02 0x2d4 0x02 0x2d5>; + clock-names = "pclk_ddr_mon_ch0\0pclk_ddr_mon_ch1\0pclk_ddr_mon_ch2\0pclk_ddr_mon_ch3"; + status = "okay"; + phandle = <0x41>; + }; + + pcie@fe180000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x30 0x3f>; + clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x111 0x00 0x00 0x00 0x00 0x02 0x111 0x01 0x00 0x00 0x00 0x03 0x111 0x02 0x00 0x00 0x00 0x04 0x111 0x03>; + linux,pci-domain = <0x03>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x3000 0x112 0x3000 0x1000>; + num-lanes = <0x01>; + phys = <0x71 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>; + reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000 0x00 0xf3000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x210 0x02 0x21f>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x2b5>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xf5 0x01>; + phandle = <0x111>; + }; + }; + + pcie@fe190000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x40 0x4f>; + clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x113 0x00 0x00 0x00 0x00 0x02 0x113 0x01 0x00 0x00 0x00 0x03 0x113 0x02 0x00 0x00 0x00 0x04 0x113 0x03>; + linux,pci-domain = <0x04>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x4000 0x112 0x4000 0x1000>; + num-lanes = <0x01>; + phys = <0x114 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>; + reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000 0x00 0xf4000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x211 0x02 0x220>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x2b6>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xfa 0x01>; + phandle = <0x113>; + }; + }; + + uio@fe1c0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe1c0000 0x00 0x10000>; + rockchip,ethernet = <0x115>; + status = "disabled"; + phandle = <0x2b7>; + }; + + ethernet@fe1c0000 { + local-mac-address = [46 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe1c0000 0x00 0x10000>; + interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xc9>; + rockchip,php_grf = <0x77>; + clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x02 0x20b>; + reset-names = "stmmaceth"; + power-domains = <0x06 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x116>; + snps,mtl-rx-config = <0x117>; + snps,mtl-tx-config = <0x118>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0x119 0x0f 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x11a 0x11b 0x11c 0x11d 0x11e>; + tx_delay = <0x43>; + phy-handle = <0x11f>; + phandle = <0x115>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2b8>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + phandle = <0x11f>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + snps,rd_osr_lmt = <0x08>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + phandle = <0x116>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x117>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x118>; + + queue0 { + }; + }; + }; + + sata@fe210000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe210000 0x00 0x1000>; + clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x111 0x04>; + interrupt-names = "hostc"; + phys = <0x114 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "okay"; + phandle = <0x2b9>; + }; + + sata@fe230000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe230000 0x00 0x1000>; + clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x113 0x04>; + interrupt-names = "hostc"; + phys = <0x71 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "disabled"; + phandle = <0x2ba>; + }; + + spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x00 0xfe2b0000 0x00 0x4000>; + interrupts = <0x00 0xce 0x04>; + clocks = <0x02 0x13d 0x02 0x13e>; + clock-names = "clk_sfc\0hclk_sfc"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2bb>; + }; + + mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2c0000 0x00 0x4000>; + interrupts = <0x00 0xcb 0x04>; + clocks = <0x0f 0x17 0x0f 0x09 0x02 0x2c2 0x02 0x2c3>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x120 0x121 0x122 0x123>; + power-domains = <0x06 0x28>; + status = "okay"; + no-sdio; + no-mmc; + bus-width = <0x04>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <0x124>; + vmmc-supply = <0x125>; + phandle = <0x2bc>; + }; + + mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <0x00 0xcc 0x04>; + clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x126>; + power-domains = <0x06 0x25>; + status = "okay"; + no-sd; + no-mmc; + bus-width = <0x04>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <0x127>; + non-removable; + sd-uhs-sdr104; + phandle = <0x2bd>; + }; + + mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x00 0xfe2e0000 0x00 0x10000>; + interrupts = <0x00 0xcd 0x04>; + assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>; + reset-names = "core\0bus\0axi\0block\0timer"; + max-frequency = <0xbebc200>; + supports-cqe; + status = "okay"; + bus-width = <0x08>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + phandle = <0x2be>; + }; + + crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x00 0xfe370000 0x00 0x2000>; + interrupts = <0x00 0xd1 0x04>; + clocks = <0x0f 0x0b 0x0f 0x0c 0x0f 0x14 0x0f 0x15>; + clock-names = "aclk\0hclk\0sclk\0pka"; + resets = <0x128 0x0f>; + reset-names = "crypto-rst"; + status = "disabled"; + phandle = <0x2bf>; + }; + + rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x00 0xfe378000 0x00 0x200>; + interrupts = <0x00 0x190 0x04>; + clocks = <0x0f 0x0c>; + clock-names = "hclk_trng"; + resets = <0x128 0x30>; + reset-names = "reset"; + status = "okay"; + phandle = <0x2c0>; + }; + + i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfe470000 0x00 0x1000>; + interrupts = <0x00 0xb4 0x04>; + clocks = <0x02 0x33 0x02 0x37 0x02 0x30>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x31 0x02 0x35>; + assigned-clock-parents = <0x02 0x05 0x02 0x05>; + dmas = <0x7a 0x00 0x7a 0x01>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + resets = <0x02 0x77 0x02 0x7a>; + reset-names = "tx-m\0rx-m"; + rockchip,trcm-sync-tx-only; + i2s-lrck-gpio = <0x129 0x15 0x00>; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x12a 0x12b 0x12c 0x12d>; + pinctrl-1 = <0x12e>; + pinctrl-2 = <0x12a 0x12b>; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1f0>; + }; + + i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfe480000 0x00 0x1000>; + interrupts = <0x00 0xb5 0x04>; + clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0x7a 0x02 0x7a 0x03>; + dma-names = "tx\0rx"; + resets = <0x02 0xc002a 0x02 0xc002d>; + reset-names = "tx-m\0rx-m"; + rockchip,trcm-sync-tx-only; + i2s-lrck-gpio = <0x10a 0x02 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c1>; + }; + + i2s@fe490000 { + compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; + reg = <0x00 0xfe490000 0x00 0x1000>; + interrupts = <0x00 0xb6 0x04>; + clocks = <0x02 0x27 0x02 0x22>; + clock-names = "i2s_clk\0i2s_hclk"; + assigned-clocks = <0x02 0x24>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x00 0xf4 0x01>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x139 0x13a 0x13b 0x13c>; + pinctrl-1 = <0x13d>; + pinctrl-2 = <0x139 0x13a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + rockchip,bclk-fs = <0x20>; + phandle = <0x1dd>; + }; + + i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; + reg = <0x00 0xfe4a0000 0x00 0x1000>; + interrupts = <0x00 0xb7 0x04>; + clocks = <0x02 0x2d 0x02 0x23>; + clock-names = "i2s_clk\0i2s_hclk"; + assigned-clocks = <0x02 0x2a>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x02 0xf4 0x03>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x13e 0x13f>; + pinctrl-1 = <0x140>; + pinctrl-2 = <0x141 0x142>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c2>; + }; + + pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x00 0xfe4b0000 0x00 0x1000>; + clocks = <0x02 0x29f 0x02 0x29e>; + clock-names = "pdm_clk\0pdm_hclk"; + dmas = <0x7a 0x04>; + dma-names = "rx"; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x143 0x144 0x145 0x146>; + pinctrl-1 = <0x147>; + pinctrl-2 = <0x148 0x149>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c3>; + }; + + pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x00 0xfe4c0000 0x00 0x1000>; + clocks = <0x02 0x3b 0x02 0x3a>; + clock-names = "pdm_clk\0pdm_hclk"; + assigned-clocks = <0x02 0x3b>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x04>; + dma-names = "rx"; + power-domains = <0x06 0x26>; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x14a 0x14b 0x14c 0x14d>; + pinctrl-1 = <0x14e>; + pinctrl-2 = <0x14f 0x150>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c4>; + }; + + vad@fe4d0000 { + compatible = "rockchip,rk3588-vad"; + reg = <0x00 0xfe4d0000 0x00 0x1000>; + reg-names = "vad"; + clocks = <0x02 0x2a0>; + clock-names = "hclk"; + interrupts = <0x00 0xca 0x04>; + rockchip,audio-src = <0x00>; + rockchip,det-channel = <0x00>; + rockchip,mode = <0x00>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c5>; + }; + + spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfe4e0000 0x00 0x1000>; + interrupts = <0x00 0xc1 0x04>; + dmas = <0x7a 0x05>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x41 0x02 0x3e>; + assigned-clocks = <0x02 0x3f>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x26>; + pinctrl-names = "default"; + pinctrl-0 = <0x151>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1ea>; + }; + + spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfe4f0000 0x00 0x1000>; + interrupts = <0x00 0xc2 0x04>; + dmas = <0xf4 0x05>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x47 0x02 0x44>; + assigned-clocks = <0x02 0x45>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x26>; + pinctrl-names = "default"; + pinctrl-0 = <0x152>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1ec>; + }; + + codec-digital@fe500000 { + compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1"; + reg = <0x00 0xfe500000 0x00 0x1000>; + clocks = <0x02 0x29 0x02 0x2f>; + clock-names = "dac\0pclk"; + power-domains = <0x06 0x26>; + resets = <0x02 0x84>; + reset-names = "reset"; + rockchip,grf = <0xc9>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <0x153>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c6>; + }; + + hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x00 0xfe5a0000 0x00 0x100>; + #hwlock-cells = <0x01>; + phandle = <0x2c7>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + + // msi-controller@fe640000 { + // compatible = "arm,gic-v3-its"; + // msi-controller; + // #msi-cells = <0x01>; + // reg = <0x00 0xfe640000 0x00 0x20000>; + // phandle = <0x112>; + // }; + + // msi-controller@fe660000 { + // compatible = "arm,gic-v3-its"; + // msi-controller; + // #msi-cells = <0x01>; + // reg = <0x00 0xfe660000 0x00 0x20000>; + // phandle = <0x1ca>; + // }; + }; + + dma-controller@fea10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfea10000 0x00 0x4000>; + interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>; + clocks = <0x02 0x78>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0x7a>; + }; + + dma-controller@fea30000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfea30000 0x00 0x4000>; + interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>; + clocks = <0x02 0x79>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0xf4>; + }; + + can@fea50000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea50000 0x00 0x1000>; + interrupts = <0x00 0x155 0x04>; + clocks = <0x02 0x70 0x02 0x6f>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xb9 0x02 0xb8>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x154>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2c8>; + }; + + can@fea60000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea60000 0x00 0x1000>; + interrupts = <0x00 0x156 0x04>; + clocks = <0x02 0x72 0x02 0x71>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xbb 0x02 0xba>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x155>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2c9>; + }; + + can@fea70000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea70000 0x00 0x1000>; + interrupts = <0x00 0x157 0x04>; + clocks = <0x02 0x74 0x02 0x73>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xbd 0x02 0xbc>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x156>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2ca>; + }; + + decompress@fea80000 { + compatible = "rockchip,hw-decompress"; + reg = <0x00 0xfea80000 0x00 0x1000>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x02 0x75 0x02 0x77 0x02 0x76>; + clock-names = "aclk\0dclk\0pclk"; + resets = <0x02 0x118>; + reset-names = "dresetn"; + status = "disabled"; + phandle = <0x2cb>; + }; + + i2c@fea90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfea90000 0x00 0x1000>; + clocks = <0x02 0x8d 0x02 0x85>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13e 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x157>; + resets = <0x02 0xb0 0x02 0xa8>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2cc>; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0xb3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeaa0000 0x00 0x1000>; + clocks = <0x02 0x8e 0x02 0x86>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13f 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x158>; + resets = <0x02 0xb1 0x02 0xa9>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2cd>; + }; + + i2c@feab0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeab0000 0x00 0x1000>; + clocks = <0x02 0x8f 0x02 0x87>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x140 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x159>; + resets = <0x02 0xb2 0x02 0xaa>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2ce>; + + imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <0x02 0x102>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x15a>; + power-domains = <0x06 0x1b>; + pwdn-gpios = <0x129 0x07 0x00>; + avdd-supply = <0x15b>; + rockchip,camera-module-index = <0x00>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + phandle = <0x2cf>; + + port { + + endpoint { + remote-endpoint = <0x15c>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0x33>; + }; + }; + }; + }; + + i2c@feac0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeac0000 0x00 0x1000>; + clocks = <0x02 0x90 0x02 0x88>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x141 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x15d>; + resets = <0x02 0xb3 0x02 0xab>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2d0>; + + light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = <0x05>; + irq_enable = <0x00>; + als_threshold_high = <0x64>; + als_threshold_low = <0x0a>; + als_ctrl_gain = <0x02>; + poll_delay_ms = <0x64>; + phandle = <0x2d1>; + }; + + proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = <0x06>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <0x03>; + ps_led_current = <0x04>; + poll_delay_ms = <0x64>; + phandle = <0x2d2>; + }; + + icm_acc@68 { + status = "okay"; + compatible = "icm42607_acc"; + reg = <0x68>; + irq-gpio = <0x10a 0x12 0x01>; + irq_enable = <0x00>; + poll_delay_ms = <0x1e>; + type = <0x02>; + layout = <0x00>; + phandle = <0x2d3>; + }; + + icm_gyro@68 { + status = "okay"; + compatible = "icm42607_gyro"; + reg = <0x68>; + poll_delay_ms = <0x1e>; + type = <0x04>; + layout = <0x00>; + phandle = <0x2d4>; + }; + }; + + i2c@fead0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfead0000 0x00 0x1000>; + clocks = <0x02 0x91 0x02 0x89>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x142 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x15e>; + resets = <0x02 0xb4 0x02 0xac>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2d5>; + + gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0x15f>; + goodix,rst-gpio = <0x119 0x11 0x00>; + goodix,irq-gpio = <0x119 0x10 0x08>; + power-supply = <0xf9>; + phandle = <0x2d6>; + }; + + hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + pinctrl-names = "ts_active\0ts_suspend"; + pinctrl-0 = <0x160 0x161>; + pinctrl-1 = <0x162 0x163>; + reset-gpios = <0x119 0x11 0x00>; + irq-gpios = <0x119 0x10 0x01>; + max-touch-number = <0x05>; + display-coords = <0x00 0x00 0x438 0x780>; + pos-swap = <0x00>; + posx-reverse = <0x00>; + posy-reverse = <0x00>; + phandle = <0x2d7>; + }; + }; + + timer@feae0000 { + compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer"; + reg = <0x00 0xfeae0000 0x00 0x20>; + interrupts = <0x00 0x121 0x04>; + clocks = <0x02 0x5c 0x02 0x5f>; + clock-names = "pclk\0timer"; + phandle = <0x2d8>; + }; + + watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0xfeaf0000 0x00 0x100>; + clocks = <0x02 0x6c 0x02 0x6b>; + clock-names = "tclk\0pclk"; + interrupts = <0x00 0x13b 0x04>; + status = "disabled"; + phandle = <0x2d9>; + }; + + spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb00000 0x00 0x1000>; + interrupts = <0x00 0x146 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa3 0x02 0x9e>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x7a 0x0e 0x7a 0x0f>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x164 0x165 0x166>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2da>; + }; + + spi@feb10000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb10000 0x00 0x1000>; + interrupts = <0x00 0x147 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa4 0x02 0x9f>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x7a 0x10 0x7a 0x11>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x167 0x168 0x169>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2db>; + }; + + spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb20000 0x00 0x1000>; + interrupts = <0x00 0x148 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa5 0x02 0xa0>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf4 0x0f 0xf4 0x10>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x16a 0x16b>; + num-cs = <0x01>; + status = "okay"; + assigned-clocks = <0x02 0xa5>; + assigned-clock-rates = <0xbebc200>; + phandle = <0x2dc>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <0xf4240>; + reg = <0x00>; + interrupt-parent = <0xfa>; + interrupts = <0x07 0x08>; + pinctrl-names = "default\0pmic-power-off"; + pinctrl-0 = <0x16c 0x16d 0x16e 0x16f>; + pinctrl-1 = <0x170>; + low_voltage_threshold = <0xbb8>; + shutdown_voltage_threshold = <0xa8c>; + shutdown_temperture_threshold = <0xa0>; + hotdie_temperture_threshold = <0x73>; + pmic-reset-func = <0x01>; + vcc1-supply = <0x79>; + vcc2-supply = <0x79>; + vcc3-supply = <0x79>; + vcc4-supply = <0x79>; + vcc5-supply = <0x79>; + vcc6-supply = <0x79>; + vcc7-supply = <0x79>; + vcc8-supply = <0x79>; + vcc9-supply = <0x79>; + vcc10-supply = <0x79>; + vcc11-supply = <0x171>; + vcc12-supply = <0x79>; + vcc13-supply = <0x172>; + vcc14-supply = <0x172>; + vcca-supply = <0x79>; + phandle = <0x2dd>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806 { + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x2de>; + + rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x16d>; + }; + + rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + phandle = <0x2df>; + }; + + rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + phandle = <0x170>; + }; + + rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + phandle = <0x2e0>; + }; + + rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x16e>; + }; + + rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + phandle = <0x2e1>; + }; + + rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + phandle = <0x2e2>; + }; + + rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + phandle = <0x2e3>; + }; + + rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + phandle = <0x2e4>; + }; + + rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + phandle = <0x2e5>; + }; + + rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + phandle = <0x16f>; + }; + + rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + phandle = <0x2e6>; + }; + + rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + phandle = <0x2e7>; + }; + + rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + phandle = <0x2e8>; + }; + + rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + phandle = <0x2e9>; + }; + + rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + phandle = <0x2ea>; + }; + }; + + regulators { + + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <0x190>; + phandle = <0x63>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = "\0\f5"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_cpu_lit_s0"; + phandle = <0x13>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = "\0\f5"; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_log_s0"; + phandle = <0x44>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-init-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_vdenc_s0"; + phandle = <0xc5>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_ddr_s0"; + phandle = <0x43>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + phandle = <0x2eb>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1e8480>; + regulator-max-microvolt = <0x1e8480>; + regulator-name = "vdd_2v0_pldo_s3"; + phandle = <0x171>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1e8480>; + }; + }; + + DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s3"; + phandle = <0x2ec>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + phandle = <0x2ed>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s3"; + phandle = <0x2ee>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "avcc_1v8_s0"; + phandle = <0x1f7>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s0"; + phandle = <0x18e>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-name = "avdd_1v2_s0"; + phandle = <0x2ef>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s0"; + phandle = <0x2f0>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd_s0"; + phandle = <0x124>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "pldo6_s3"; + phandle = <0x2f1>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s3"; + phandle = <0x2f2>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_ddr_pll_s0"; + phandle = <0x2f3>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcc77c>; + regulator-max-microvolt = <0xcc77c>; + regulator-name = "avdd_0v75_s0"; + phandle = <0x1f8>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_0v85_s0"; + phandle = <0x1f6>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s0"; + phandle = <0x2f4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; + + spi@feb30000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb30000 0x00 0x1000>; + interrupts = <0x00 0x149 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa6 0x02 0xa1>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf4 0x11 0xf4 0x12>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x173 0x174 0x175>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2f5>; + }; + + serial@feb40000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb40000 0x00 0x100>; + interrupts = <0x00 0x14c 0x04>; + clocks = <0x02 0xb7 0x02 0xab>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x08 0x7a 0x09>; + pinctrl-names = "default"; + pinctrl-0 = <0x176>; + status = "disabled"; + phandle = <0x2f6>; + }; + + serial@feb50000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb50000 0x00 0x100>; + interrupts = <0x00 0x14d 0x04>; + clocks = <0x02 0xbb 0x02 0xac>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x0a 0x7a 0x0b>; + pinctrl-names = "default"; + pinctrl-0 = <0x177>; + status = "disabled"; + phandle = <0x2f7>; + }; + + serial@feb60000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb60000 0x00 0x100>; + interrupts = <0x00 0x14e 0x04>; + clocks = <0x02 0xbf 0x02 0xad>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x0c 0x7a 0x0d>; + pinctrl-names = "default"; + pinctrl-0 = <0x178>; + status = "disabled"; + phandle = <0x2f8>; + }; + + serial@feb70000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb70000 0x00 0x100>; + interrupts = <0x00 0x14f 0x04>; + clocks = <0x02 0xc3 0x02 0xae>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x09 0xf4 0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <0x179>; + status = "disabled"; + phandle = <0x2f9>; + }; + + serial@feb80000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb80000 0x00 0x100>; + interrupts = <0x00 0x150 0x04>; + clocks = <0x02 0xc7 0x02 0xaf>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x0b 0xf4 0x0c>; + pinctrl-names = "default"; + pinctrl-0 = <0x17a>; + status = "disabled"; + phandle = <0x2fa>; + }; + + serial@feb90000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb90000 0x00 0x100>; + interrupts = <0x00 0x151 0x04>; + clocks = <0x02 0xcb 0x02 0xb0>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x0d 0xf4 0x0e>; + pinctrl-names = "default"; + pinctrl-0 = <0x17b>; + status = "disabled"; + phandle = <0x2fb>; + }; + + serial@feba0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeba0000 0x00 0x100>; + interrupts = <0x00 0x152 0x04>; + clocks = <0x02 0xcf 0x02 0xb1>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x07 0xf5 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x17c>; + status = "disabled"; + phandle = <0x2fc>; + }; + + serial@febb0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfebb0000 0x00 0x100>; + interrupts = <0x00 0x153 0x04>; + clocks = <0x02 0xd3 0x02 0xb2>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x09 0xf5 0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <0x17d>; + status = "disabled"; + phandle = <0x2fd>; + }; + + serial@febc0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfebc0000 0x00 0x100>; + interrupts = <0x00 0x154 0x04>; + clocks = <0x02 0xd7 0x02 0xb3>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x0b 0xf5 0x0c>; + pinctrl-names = "default"; + pinctrl-0 = <0x17e 0x17f>; + status = "okay"; + phandle = <0x2fe>; + }; + + pwm@febd0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0000 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x180>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x2ff>; + }; + + pwm@febd0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0010 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x181>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x300>; + }; + + pwm@febd0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0020 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x182>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x301>; + }; + + pwm@febd0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0030 0x00 0x10>; + interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x183>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x302>; + }; + + pwm@febe0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0000 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x184>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x303>; + }; + + pwm@febe0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0010 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x185>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x304>; + }; + + pwm@febe0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0020 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x186>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x305>; + }; + + pwm@febe0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0030 0x00 0x10>; + interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x187>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x306>; + }; + + pwm@febf0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0000 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x188>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x307>; + }; + + pwm@febf0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0010 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x189>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x308>; + }; + + pwm@febf0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0020 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x18a>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x309>; + }; + + pwm@febf0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0030 0x00 0x10>; + interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x18b>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x30a>; + }; + + tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x00 0xfec00000 0x00 0x400>; + interrupts = <0x00 0x18d 0x04>; + clocks = <0x02 0xaa 0x02 0xa9>; + clock-names = "tsadc\0apb_pclk"; + assigned-clocks = <0x02 0xaa>; + assigned-clock-rates = <0x1e8480>; + resets = <0x02 0xc1 0x02 0xc0>; + reset-names = "tsadc\0tsadc-apb"; + #thermal-sensor-cells = <0x01>; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x00>; + rockchip,hw-tshut-polarity = <0x00>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x18c>; + pinctrl-1 = <0x18d>; + status = "okay"; + phandle = <0x5f>; + }; + + saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x00 0xfec10000 0x00 0x10000>; + interrupts = <0x00 0x18e 0x04>; + #io-channel-cells = <0x01>; + clocks = <0x02 0x9d 0x02 0x9c>; + clock-names = "saradc\0apb_pclk"; + resets = <0x02 0xbe>; + reset-names = "saradc-apb"; + status = "okay"; + vref-supply = <0x18e>; + phandle = <0x1db>; + }; + + mailbox@fec60000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfec60000 0x00 0x200>; + interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>; + clocks = <0x02 0x4c>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x30b>; + }; + + mailbox@fec70000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfec70000 0x00 0x200>; + interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>; + clocks = <0x02 0x4d>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x30c>; + }; + + i2c@fec80000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfec80000 0x00 0x1000>; + clocks = <0x02 0x92 0x02 0x8a>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x143 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x18f>; + resets = <0x02 0xb5 0x02 0xad>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x30d>; + + husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <0x119>; + interrupts = <0x0e 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x190>; + vbus-supply = <0x191>; + status = "okay"; + phandle = <0x30e>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0x192>; + phandle = <0x69>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <0xf4240>; + sink-pdos = <0x4019064>; + source-pdos = <0x401912c>; + phandle = <0x30f>; + + altmodes { + #address-cells = <0x01>; + #size-cells = <0x00>; + + altmode@0 { + reg = <0x00>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x193>; + phandle = <0x1a1>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x194>; + phandle = <0x1a2>; + }; + }; + }; + }; + }; + + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <0x195>; + interrupt-parent = <0xfa>; + interrupts = <0x08 0x08>; + wakeup-source; + phandle = <0x1f9>; + }; + }; + + i2c@fec90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfec90000 0x00 0x1000>; + clocks = <0x02 0x93 0x02 0x8b>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x144 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x196>; + resets = <0x02 0xb6 0x02 0xae>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x310>; + + es8388@11 { + status = "okay"; + #sound-dai-cells = <0x00>; + compatible = "everest,es8388\0everest,es8323"; + reg = <0x11>; + clocks = <0x197>; + clock-names = "mclk"; + assigned-clocks = <0x197>; + assigned-clock-rates = <0xbb8000>; + pinctrl-names = "default"; + pinctrl-0 = <0x198>; + phandle = <0x1f1>; + }; + }; + + i2c@feca0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeca0000 0x00 0x1000>; + clocks = <0x02 0x94 0x02 0x8c>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x145 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x199>; + resets = <0x02 0xb7 0x02 0xaf>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x311>; + }; + + spi@fecb0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfecb0000 0x00 0x1000>; + interrupts = <0x00 0x14a 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa7 0x02 0xa2>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf5 0x0d 0xf5 0x0e>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x19a 0x19b 0x19c>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x312>; + }; + + otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x00 0xfecc0000 0x00 0x400>; + #address-cells = <0x01>; + #size-cells = <0x01>; + clocks = <0x02 0x96 0x02 0x95 0x02 0x99>; + clock-names = "otpc\0apb\0phy"; + resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>; + reset-names = "otpc\0apb\0arb"; + phandle = <0x313>; + + cpu-code@2 { + reg = <0x02 0x02>; + phandle = <0x2e>; + }; + + package-serial-number-high@5 { + reg = <0x05 0x01>; + bits = <0x00 0x01>; + phandle = <0xd7>; + }; + + package-serial-number-low@6 { + reg = <0x06 0x01>; + bits = <0x05 0x03>; + phandle = <0xd6>; + }; + + specification-serial-number@6 { + reg = <0x06 0x01>; + bits = <0x00 0x05>; + phandle = <0x22>; + }; + + id@7 { + reg = <0x07 0x10>; + phandle = <0x2c>; + }; + + cpu-version@1c { + reg = <0x1c 0x01>; + bits = <0x03 0x03>; + phandle = <0x2d>; + }; + + cpub0-leakage@17 { + reg = <0x17 0x01>; + phandle = <0x26>; + }; + + cpub1-leakage@18 { + reg = <0x18 0x01>; + phandle = <0x29>; + }; + + cpul-leakage@19 { + reg = <0x19 0x01>; + phandle = <0x20>; + }; + + log-leakage@1a { + reg = <0x1a 0x01>; + phandle = <0x45>; + }; + + gpu-leakage@1b { + reg = <0x1b 0x01>; + phandle = <0x64>; + }; + + customer-demand@22 { + reg = <0x22 0x01>; + bits = <0x04 0x04>; + phandle = <0x23>; + }; + + npu-leakage@28 { + reg = <0x28 0x01>; + phandle = <0xb4>; + }; + + codec-leakage@29 { + reg = <0x29 0x01>; + phandle = <0xc7>; + }; + + cpul-opp-info@3d { + reg = <0x3d 0x06>; + phandle = <0x21>; + }; + + cpub01-opp-info@43 { + reg = <0x43 0x06>; + phandle = <0x27>; + }; + + cpub23-opp-info@49 { + reg = <0x49 0x06>; + phandle = <0x2a>; + }; + + gpu-opp-info@4f { + reg = <0x4f 0x06>; + phandle = <0x65>; + }; + + npu-opp-info@55 { + reg = <0x55 0x06>; + phandle = <0xb5>; + }; + + dmc-opp-info@5b { + reg = <0x5b 0x06>; + phandle = <0x46>; + }; + + vop-opp-info@61 { + reg = <0x61 0x06>; + phandle = <0x314>; + }; + + venc-opp-info@67 { + reg = <0x67 0x06>; + phandle = <0xc8>; + }; + }; + + mailbox@fece0000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfece0000 0x00 0x200>; + interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>; + clocks = <0x02 0x4e>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x315>; + }; + + dma-controller@fed10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfed10000 0x00 0x4000>; + interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>; + clocks = <0x02 0x7a>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0xf5>; + }; + + phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x267>; + clock-names = "ref\0apb"; + resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>; + reset-names = "apb\0init\0cmn\0lane"; + rockchip,grf = <0x19d>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x10d>; + }; + + hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x267>; + clock-names = "ref\0apb"; + clock-output-names = "clk_hdmiphy_pixel0"; + #clock-cells = <0x00>; + resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x19d>; + #phy-cells = <0x00>; + /* + * Keep DISABLED: the phy is passed through to zone2 (fed60000), + * whose phy driver probes it and registers clk_hdmiphy_pixel0 + * locally. If this node were enabled, root's phy driver would + * hold these 7 resets EXCLUSIVELY and zone2's SCMI reset requests + * for the same lines would fail (reset core WARN -EBUSY). + */ + status = "disabled"; + phandle = <0x36>; + }; + + phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x00 0xfed80000 0x00 0x10000>; + rockchip,u2phy-grf = <0x19e>; + rockchip,usb-grf = <0x75>; + rockchip,usbdpphy-grf = <0x19f>; + rockchip,vo-grf = <0x102>; + clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x1a0>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <0x10a 0x00 0x00>; + sbu2-dc-gpios = <0x10a 0x01 0x00>; + phandle = <0x316>; + + dp-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x103>; + }; + + u3-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x68>; + }; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1a1>; + phandle = <0x193>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x1a2>; + phandle = <0x194>; + }; + }; + }; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfeda0000 0x00 0x10000>; + rockchip,grf = <0x1a3>; + clocks = <0x02 0x108 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x31>; + }; + + phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfedb0000 0x00 0x10000>; + rockchip,grf = <0x1a4>; + clocks = <0x02 0x109 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x32>; + }; + + csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x00 0xfedc0000 0x00 0x8000>; + clocks = <0x02 0x10c>; + clock-names = "pclk"; + resets = <0x02 0x17 0x02 0x16>; + reset-names = "srst_csiphy0\0srst_p_csiphy0"; + rockchip,grf = <0x1a5>; + rockchip,sys_grf = <0xc9>; + status = "okay"; + phandle = <0x2f>; + }; + + csi2-dphy1-hw@fedc8000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x00 0xfedc8000 0x00 0x8000>; + clocks = <0x02 0x10d>; + clock-names = "pclk"; + resets = <0x02 0x19 0x02 0x18>; + reset-names = "srst_csiphy1\0srst_p_csiphy1"; + rockchip,grf = <0x1a6>; + rockchip,sys_grf = <0xc9>; + status = "okay"; + phandle = <0x30>; + }; + + phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee00000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2bd>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20005 0x02 0x4d6>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1a7>; + status = "okay"; + phandle = <0x114>; + }; + + phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee20000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2bf>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20007 0x02 0x4d8>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1a8>; + rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>; + status = "okay"; + phandle = <0x71>; + }; + + sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x00 0xff001000 0x00 0xef000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0xff001000 0xef000>; + phandle = <0x317>; + + rkvdec-sram@0 { + reg = <0x00 0x78000>; + phandle = <0xcc>; + }; + + rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + phandle = <0xce>; + }; + }; + + pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <0x1a9>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x1aa>; + + gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfd8a0000 0x00 0x100>; + interrupts = <0x00 0x115 0x04>; + clocks = <0x02 0x284 0x02 0x285>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x00 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xfa>; + }; + + gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec20000 0x00 0x100>; + interrupts = <0x00 0x116 0x04>; + clocks = <0x02 0x7d 0x02 0x7e>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x20 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x129>; + }; + + gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec30000 0x00 0x100>; + interrupts = <0x00 0x117 0x04>; + clocks = <0x02 0x7f 0x02 0x80>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x40 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x1fd>; + }; + + gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec40000 0x00 0x100>; + interrupts = <0x00 0x118 0x04>; + clocks = <0x02 0x81 0x02 0x82>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x60 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x119>; + }; + + gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec50000 0x00 0x100>; + interrupts = <0x00 0x119 0x04>; + clocks = <0x02 0x83 0x02 0x84>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x80 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x10a>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x1b1>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x1b5>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x1ab>; + }; + + pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0x00>; + phandle = <0x318>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x319>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x1b4>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x31a>; + }; + + pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <0x04>; + phandle = <0x31b>; + }; + + pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <0x05>; + phandle = <0x31c>; + }; + + pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <0x06>; + phandle = <0x31d>; + }; + + pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0x00>; + phandle = <0x31e>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x1b3>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x1ac>; + }; + + pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <0x03>; + phandle = <0x31f>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x320>; + }; + + pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <0x05>; + phandle = <0x321>; + }; + + pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <0x06>; + phandle = <0x1b2>; + }; + + pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0x00>; + phandle = <0x322>; + }; + + pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <0x01>; + phandle = <0x323>; + }; + + pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <0x02>; + phandle = <0x324>; + }; + + pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <0x03>; + phandle = <0x325>; + }; + + pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <0x04>; + phandle = <0x326>; + }; + + pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <0x05>; + phandle = <0x327>; + }; + + pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <0x06>; + phandle = <0x328>; + }; + + pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + phandle = <0x329>; + }; + + pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + phandle = <0x32a>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x1af>; + }; + + pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0x00>; + input-schmitt-enable; + phandle = <0x32b>; + }; + + pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <0x01>; + input-schmitt-enable; + phandle = <0x1ae>; + }; + + pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <0x02>; + input-schmitt-enable; + phandle = <0x32c>; + }; + + pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <0x03>; + input-schmitt-enable; + phandle = <0x1b0>; + }; + + pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <0x04>; + input-schmitt-enable; + phandle = <0x32d>; + }; + + pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <0x05>; + input-schmitt-enable; + phandle = <0x1ad>; + }; + + pcfg-pull-none-drv-level-6-smt { + bias-disable; + drive-strength = <0x06>; + input-schmitt-enable; + phandle = <0x32e>; + }; + + pcfg-output-high { + output-high; + phandle = <0x32f>; + }; + + pcfg-output-high-pull-up { + output-high; + bias-pull-up; + phandle = <0x330>; + }; + + pcfg-output-high-pull-down { + output-high; + bias-pull-down; + phandle = <0x331>; + }; + + pcfg-output-high-pull-none { + output-high; + bias-disable; + phandle = <0x332>; + }; + + pcfg-output-low { + output-low; + phandle = <0x1b6>; + }; + + pcfg-output-low-pull-up { + output-low; + bias-pull-up; + phandle = <0x333>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x334>; + }; + + pcfg-output-low-pull-none { + output-low; + bias-disable; + phandle = <0x335>; + }; + + auddsm { + + auddsm-pins { + rockchip,pins = <0x03 0x01 0x04 0x1ab 0x03 0x02 0x04 0x1ab 0x03 0x03 0x04 0x1ab 0x03 0x04 0x04 0x1ab>; + phandle = <0x153>; + }; + }; + + bt1120 { + + bt1120-pins { + rockchip,pins = <0x04 0x08 0x02 0x1ab 0x04 0x00 0x02 0x1ab 0x04 0x01 0x02 0x1ab 0x04 0x02 0x02 0x1ab 0x04 0x03 0x02 0x1ab 0x04 0x04 0x02 0x1ab 0x04 0x05 0x02 0x1ab 0x04 0x06 0x02 0x1ab 0x04 0x07 0x02 0x1ab 0x04 0x0a 0x02 0x1ab 0x04 0x0b 0x02 0x1ab 0x04 0x0c 0x02 0x1ab 0x04 0x0d 0x02 0x1ab 0x04 0x0e 0x02 0x1ab 0x04 0x0f 0x02 0x1ab 0x04 0x10 0x02 0x1ab 0x04 0x11 0x02 0x1ab>; + phandle = <0x72>; + }; + }; + + can0 { + + can0m0-pins { + rockchip,pins = <0x00 0x10 0x0b 0x1ab 0x00 0x0f 0x0b 0x1ab>; + phandle = <0x154>; + }; + + can0m1-pins { + rockchip,pins = <0x04 0x1d 0x09 0x1ab 0x04 0x1c 0x09 0x1ab>; + phandle = <0x336>; + }; + }; + + can1 { + + can1m0-pins { + rockchip,pins = <0x03 0x0d 0x09 0x1ab 0x03 0x0e 0x09 0x1ab>; + phandle = <0x155>; + }; + + can1m1-pins { + rockchip,pins = <0x04 0x0a 0x0c 0x1ab 0x04 0x0b 0x0c 0x1ab>; + phandle = <0x337>; + }; + }; + + can2 { + + can2m0-pins { + rockchip,pins = <0x03 0x14 0x09 0x1ab 0x03 0x15 0x09 0x1ab>; + phandle = <0x156>; + }; + + can2m1-pins { + rockchip,pins = <0x00 0x1c 0x0a 0x1ab 0x00 0x1d 0x0a 0x1ab>; + phandle = <0x338>; + }; + }; + + cif { + + cif-clk { + rockchip,pins = <0x04 0x0c 0x01 0x1ab>; + phandle = <0x339>; + }; + + cif-dvp-clk { + rockchip,pins = <0x04 0x08 0x01 0x1ab 0x04 0x0a 0x01 0x1ab 0x04 0x0b 0x01 0x1ab>; + phandle = <0x33a>; + }; + + cif-dvp-bus16 { + rockchip,pins = <0x03 0x14 0x01 0x1ab 0x03 0x15 0x01 0x1ab 0x03 0x16 0x01 0x1ab 0x03 0x17 0x01 0x1ab 0x03 0x18 0x01 0x1ab 0x03 0x19 0x01 0x1ab 0x03 0x1a 0x01 0x1ab 0x03 0x1b 0x01 0x1ab>; + phandle = <0x33b>; + }; + + cif-dvp-bus8 { + rockchip,pins = <0x04 0x00 0x01 0x1ab 0x04 0x01 0x01 0x1ab 0x04 0x02 0x01 0x1ab 0x04 0x03 0x01 0x1ab 0x04 0x04 0x01 0x1ab 0x04 0x05 0x01 0x1ab 0x04 0x06 0x01 0x1ab 0x04 0x07 0x01 0x1ab>; + phandle = <0x33c>; + }; + }; + + clk32k { + + clk32k-in { + rockchip,pins = <0x00 0x0a 0x01 0x1ab>; + phandle = <0x33d>; + }; + + clk32k-out0 { + rockchip,pins = <0x00 0x0a 0x02 0x1ab>; + phandle = <0x33e>; + }; + + clk32k-out1 { + rockchip,pins = <0x02 0x15 0x01 0x1ab>; + phandle = <0x33f>; + }; + }; + + cpu { + + cpu-pins { + rockchip,pins = <0x00 0x19 0x02 0x1ab 0x00 0x1d 0x02 0x1ab>; + phandle = <0x340>; + }; + }; + + ddrphych0 { + + ddrphych0-pins { + rockchip,pins = <0x04 0x00 0x07 0x1ab 0x04 0x01 0x07 0x1ab 0x04 0x02 0x07 0x1ab 0x04 0x03 0x07 0x1ab>; + phandle = <0x341>; + }; + }; + + ddrphych1 { + + ddrphych1-pins { + rockchip,pins = <0x04 0x04 0x07 0x1ab 0x04 0x05 0x07 0x1ab 0x04 0x06 0x07 0x1ab 0x04 0x07 0x07 0x1ab>; + phandle = <0x342>; + }; + }; + + ddrphych2 { + + ddrphych2-pins { + rockchip,pins = <0x04 0x08 0x07 0x1ab 0x04 0x09 0x07 0x1ab 0x04 0x0a 0x07 0x1ab 0x04 0x0b 0x07 0x1ab>; + phandle = <0x343>; + }; + }; + + ddrphych3 { + + ddrphych3-pins { + rockchip,pins = <0x04 0x0c 0x07 0x1ab 0x04 0x0d 0x07 0x1ab 0x04 0x0e 0x07 0x1ab 0x04 0x0f 0x07 0x1ab>; + phandle = <0x344>; + }; + }; + + dp0 { + + dp0m0-pins { + rockchip,pins = <0x04 0x0c 0x05 0x1ab>; + phandle = <0x345>; + }; + + dp0m1-pins { + rockchip,pins = <0x00 0x14 0x0a 0x1ab>; + phandle = <0x346>; + }; + + dp0m2-pins { + rockchip,pins = <0x01 0x00 0x05 0x1ab>; + phandle = <0x347>; + }; + }; + + dp1 { + + dp1m0-pins { + rockchip,pins = <0x03 0x1d 0x05 0x1ab>; + phandle = <0x1ba>; + }; + + dp1m1-pins { + rockchip,pins = <0x00 0x15 0x0a 0x1ab>; + phandle = <0x348>; + }; + + dp1m2-pins { + rockchip,pins = <0x01 0x01 0x05 0x1ab>; + phandle = <0x349>; + }; + }; + + emmc { + + emmc-rstnout { + rockchip,pins = <0x02 0x03 0x01 0x1ab>; + phandle = <0x34a>; + }; + + emmc-bus8 { + rockchip,pins = <0x02 0x18 0x01 0x1ac 0x02 0x19 0x01 0x1ac 0x02 0x1a 0x01 0x1ac 0x02 0x1b 0x01 0x1ac 0x02 0x1c 0x01 0x1ac 0x02 0x1d 0x01 0x1ac 0x02 0x1e 0x01 0x1ac 0x02 0x1f 0x01 0x1ac>; + phandle = <0x34b>; + }; + + emmc-clk { + rockchip,pins = <0x02 0x01 0x01 0x1ac>; + phandle = <0x34c>; + }; + + emmc-cmd { + rockchip,pins = <0x02 0x00 0x01 0x1ac>; + phandle = <0x34d>; + }; + + emmc-data-strobe { + rockchip,pins = <0x02 0x02 0x01 0x1ab>; + phandle = <0x34e>; + }; + }; + + eth1 { + + eth1-pins { + rockchip,pins = <0x03 0x06 0x01 0x1ab>; + phandle = <0x34f>; + }; + }; + + fspi { + + fspim0-pins { + rockchip,pins = <0x02 0x00 0x02 0x1ac 0x02 0x1e 0x02 0x1ac 0x02 0x18 0x02 0x1ac 0x02 0x19 0x02 0x1ac 0x02 0x1a 0x02 0x1ac 0x02 0x1b 0x02 0x1ac>; + phandle = <0x350>; + }; + + fspim0-cs1 { + rockchip,pins = <0x02 0x1f 0x02 0x1ac>; + phandle = <0x351>; + }; + + fspim2-pins { + rockchip,pins = <0x03 0x05 0x05 0x1ac 0x03 0x14 0x02 0x1ac 0x03 0x00 0x05 0x1ac 0x03 0x01 0x05 0x1ac 0x03 0x02 0x05 0x1ac 0x03 0x03 0x05 0x1ac>; + phandle = <0x352>; + }; + + fspim2-cs1 { + rockchip,pins = <0x03 0x15 0x02 0x1ac>; + phandle = <0x353>; + }; + + fspim1-pins { + rockchip,pins = <0x02 0x0b 0x03 0x1ac 0x02 0x0c 0x03 0x1ac 0x02 0x06 0x03 0x1ac 0x02 0x07 0x03 0x1ac 0x02 0x08 0x03 0x1ac 0x02 0x09 0x03 0x1ac>; + phandle = <0x354>; + }; + + fspim1-cs1 { + rockchip,pins = <0x02 0x0d 0x03 0x1ac>; + phandle = <0x355>; + }; + }; + + gmac1 { + + gmac1-miim { + rockchip,pins = <0x03 0x12 0x01 0x1ab 0x03 0x13 0x01 0x1ab>; + phandle = <0x11a>; + }; + + gmac1-clkinout { + rockchip,pins = <0x03 0x0e 0x01 0x1ab>; + phandle = <0x356>; + }; + + gmac1-rx-bus2 { + rockchip,pins = <0x03 0x07 0x01 0x1ab 0x03 0x08 0x01 0x1ab 0x03 0x09 0x01 0x1ab>; + phandle = <0x11c>; + }; + + gmac1-tx-bus2 { + rockchip,pins = <0x03 0x0b 0x01 0x1ab 0x03 0x0c 0x01 0x1ab 0x03 0x0d 0x01 0x1ab>; + phandle = <0x11b>; + }; + + gmac1-rgmii-clk { + rockchip,pins = <0x03 0x05 0x01 0x1ab 0x03 0x04 0x01 0x1ab>; + phandle = <0x11d>; + }; + + gmac1-rgmii-bus { + rockchip,pins = <0x03 0x02 0x01 0x1ab 0x03 0x03 0x01 0x1ab 0x03 0x00 0x01 0x1ab 0x03 0x01 0x01 0x1ab>; + phandle = <0x11e>; + }; + + gmac1-ppsclk { + rockchip,pins = <0x03 0x11 0x01 0x1ab>; + phandle = <0x357>; + }; + + gmac1-ppstrig { + rockchip,pins = <0x03 0x10 0x01 0x1ab>; + phandle = <0x358>; + }; + + gmac1-ptp-ref-clk { + rockchip,pins = <0x03 0x0f 0x01 0x1ab>; + phandle = <0x359>; + }; + + gmac1-txer { + rockchip,pins = <0x03 0x0a 0x01 0x1ab>; + phandle = <0x35a>; + }; + }; + + gpu { + + gpu-pins { + rockchip,pins = <0x00 0x15 0x02 0x1ab>; + phandle = <0x35b>; + }; + }; + + hdmi { + + hdmim0-rx-cec { + rockchip,pins = <0x04 0x0d 0x05 0x1ab>; + phandle = <0x35c>; + }; + + hdmim0-rx-hpdin { + rockchip,pins = <0x04 0x0e 0x05 0x1ab>; + phandle = <0x35d>; + }; + + hdmim0-rx-scl { + rockchip,pins = <0x00 0x1a 0x0b 0x1ab>; + phandle = <0x35e>; + }; + + hdmim0-rx-sda { + rockchip,pins = <0x00 0x19 0x0b 0x1ab>; + phandle = <0x35f>; + }; + + hdmim0-tx0-cec { + rockchip,pins = <0x04 0x11 0x05 0x1ab>; + phandle = <0x106>; + }; + + hdmim0-tx0-hpd { + rockchip,pins = <0x01 0x05 0x05 0x1ab>; + phandle = <0x107>; + }; + + hdmim0-tx0-scl { + rockchip,pins = <0x04 0x0f 0x05 0x1ad>; + phandle = <0x108>; + }; + + hdmim0-tx0-sda { + rockchip,pins = <0x04 0x10 0x05 0x1ae>; + phandle = <0x109>; + }; + + hdmim0-tx1-hpd { + rockchip,pins = <0x01 0x06 0x05 0x1ab>; + phandle = <0x1be>; + }; + + hdmim1-rx { + rockchip,pins = <0x03 0x19 0x05 0x1ab 0x03 0x1a 0x05 0x1af 0x03 0x1b 0x05 0x1af 0x03 0x1c 0x05 0x1ab>; + phandle = <0x1c7>; + }; + + hdmim1-rx-cec { + rockchip,pins = <0x03 0x19 0x05 0x1ab>; + phandle = <0x360>; + }; + + hdmim1-rx-hpdin { + rockchip,pins = <0x03 0x1c 0x05 0x1ab>; + phandle = <0x361>; + }; + + hdmim1-rx-scl { + rockchip,pins = <0x03 0x1a 0x05 0x1af>; + phandle = <0x362>; + }; + + hdmim1-rx-sda { + rockchip,pins = <0x03 0x1b 0x05 0x1af>; + phandle = <0x363>; + }; + + hdmim1-tx0-cec { + rockchip,pins = <0x00 0x19 0x0d 0x1ab>; + phandle = <0x364>; + }; + + hdmim1-tx0-hpd { + rockchip,pins = <0x03 0x1c 0x03 0x1ab>; + phandle = <0x365>; + }; + + hdmim1-tx0-scl { + rockchip,pins = <0x00 0x1d 0x0b 0x1ad>; + phandle = <0x366>; + }; + + hdmim1-tx0-sda { + rockchip,pins = <0x00 0x1c 0x0b 0x1ae>; + phandle = <0x367>; + }; + + hdmim1-tx1-cec { + rockchip,pins = <0x00 0x1a 0x0d 0x1ab>; + phandle = <0x368>; + }; + + hdmim1-tx1-hpd { + rockchip,pins = <0x03 0x0f 0x05 0x1ab>; + phandle = <0x369>; + }; + + hdmim1-tx1-scl { + rockchip,pins = <0x03 0x16 0x05 0x1ad>; + phandle = <0x1bf>; + }; + + hdmim1-tx1-sda { + rockchip,pins = <0x03 0x15 0x05 0x1ae>; + phandle = <0x1c0>; + }; + + hdmim2-rx-cec { + rockchip,pins = <0x01 0x0f 0x05 0x1ab>; + phandle = <0x36a>; + }; + + hdmim2-rx-hpdin { + rockchip,pins = <0x01 0x0e 0x05 0x1ab>; + phandle = <0x36b>; + }; + + hdmim2-rx-scl { + rockchip,pins = <0x01 0x1e 0x05 0x1ab>; + phandle = <0x36c>; + }; + + hdmim2-rx-sda { + rockchip,pins = <0x01 0x1f 0x05 0x1ab>; + phandle = <0x36d>; + }; + + hdmim2-tx0-scl { + rockchip,pins = <0x03 0x17 0x05 0x1ad>; + phandle = <0x36e>; + }; + + hdmim2-tx0-sda { + rockchip,pins = <0x03 0x18 0x05 0x1ae>; + phandle = <0x36f>; + }; + + hdmim2-tx1-cec { + rockchip,pins = <0x03 0x14 0x05 0x1ab>; + phandle = <0x1bd>; + }; + + hdmim2-tx1-scl { + rockchip,pins = <0x01 0x04 0x05 0x1ad>; + phandle = <0x370>; + }; + + hdmim2-tx1-sda { + rockchip,pins = <0x01 0x03 0x05 0x1ae>; + phandle = <0x371>; + }; + + hdmi-debug0 { + rockchip,pins = <0x01 0x07 0x07 0x1ab>; + phandle = <0x372>; + }; + + hdmi-debug1 { + rockchip,pins = <0x01 0x08 0x07 0x1ab>; + phandle = <0x373>; + }; + + hdmi-debug2 { + rockchip,pins = <0x01 0x09 0x07 0x1ab>; + phandle = <0x374>; + }; + + hdmi-debug3 { + rockchip,pins = <0x01 0x0a 0x07 0x1ab>; + phandle = <0x375>; + }; + + hdmi-debug4 { + rockchip,pins = <0x01 0x0b 0x07 0x1ab>; + phandle = <0x376>; + }; + + hdmi-debug5 { + rockchip,pins = <0x01 0x0c 0x07 0x1ab>; + phandle = <0x377>; + }; + + hdmi-debug6 { + rockchip,pins = <0x01 0x00 0x07 0x1ab>; + phandle = <0x378>; + }; + + hdmim0-tx1-cec { + rockchip,pins = <0x02 0x14 0x04 0x1ab>; + phandle = <0x379>; + }; + + hdmim0-tx1-scl { + rockchip,pins = <0x02 0x0d 0x04 0x1b0>; + phandle = <0x37a>; + }; + + hdmim0-tx1-sda { + rockchip,pins = <0x02 0x0c 0x04 0x1ae>; + phandle = <0x37b>; + }; + + hdmirx-det { + rockchip,pins = <0x01 0x1d 0x00 0x1b1>; + phandle = <0x1c8>; + }; + }; + + i2c0 { + + i2c0m0-xfer { + rockchip,pins = <0x00 0x0b 0x02 0x1af 0x00 0x06 0x02 0x1af>; + phandle = <0x37c>; + }; + + i2c0m2-xfer { + rockchip,pins = <0x00 0x19 0x03 0x1af 0x00 0x1a 0x03 0x1af>; + phandle = <0x78>; + }; + + i2c0m1-xfer { + rockchip,pins = <0x04 0x15 0x09 0x1af 0x04 0x16 0x09 0x1af>; + phandle = <0x37d>; + }; + }; + + i2c1 { + + i2c1m0-xfer { + rockchip,pins = <0x00 0x0d 0x09 0x1af 0x00 0x0e 0x09 0x1af>; + phandle = <0x37e>; + }; + + i2c1m1-xfer { + rockchip,pins = <0x00 0x08 0x02 0x1af 0x00 0x09 0x02 0x1af>; + phandle = <0x37f>; + }; + + i2c1m2-xfer { + rockchip,pins = <0x00 0x1c 0x09 0x1af 0x00 0x1d 0x09 0x1af>; + phandle = <0x157>; + }; + + i2c1m3-xfer { + rockchip,pins = <0x02 0x1c 0x09 0x1af 0x02 0x1d 0x09 0x1af>; + phandle = <0x380>; + }; + + i2c1m4-xfer { + rockchip,pins = <0x01 0x1a 0x09 0x1af 0x01 0x1b 0x09 0x1af>; + phandle = <0x381>; + }; + }; + + i2c2 { + + i2c2m0-xfer { + rockchip,pins = <0x00 0x0f 0x09 0x1af 0x00 0x10 0x09 0x1af>; + phandle = <0x158>; + }; + + i2c2m2-xfer { + rockchip,pins = <0x02 0x03 0x09 0x1af 0x02 0x02 0x09 0x1af>; + phandle = <0x382>; + }; + + i2c2m3-xfer { + rockchip,pins = <0x01 0x15 0x09 0x1af 0x01 0x14 0x09 0x1af>; + phandle = <0x383>; + }; + + i2c2m4-xfer { + rockchip,pins = <0x01 0x01 0x09 0x1af 0x01 0x00 0x09 0x1af>; + phandle = <0x384>; + }; + + i2c2m1-xfer { + rockchip,pins = <0x02 0x11 0x09 0x1af 0x02 0x10 0x09 0x1af>; + phandle = <0x385>; + }; + }; + + i2c3 { + + i2c3m0-xfer { + rockchip,pins = <0x01 0x11 0x09 0x1af 0x01 0x10 0x09 0x1af>; + phandle = <0x159>; + }; + + i2c3m1-xfer { + rockchip,pins = <0x03 0x0f 0x09 0x1af 0x03 0x10 0x09 0x1af>; + phandle = <0x386>; + }; + + i2c3m2-xfer { + rockchip,pins = <0x04 0x04 0x09 0x1af 0x04 0x05 0x09 0x1af>; + phandle = <0x387>; + }; + + i2c3m4-xfer { + rockchip,pins = <0x04 0x18 0x09 0x1af 0x04 0x19 0x09 0x1af>; + phandle = <0x388>; + }; + + i2c3m3-xfer { + rockchip,pins = <0x02 0x0a 0x09 0x1af 0x02 0x0b 0x09 0x1af>; + phandle = <0x389>; + }; + }; + + i2c4 { + + i2c4m0-xfer { + rockchip,pins = <0x03 0x06 0x09 0x1af 0x03 0x05 0x09 0x1af>; + phandle = <0x38a>; + }; + + i2c4m2-xfer { + rockchip,pins = <0x00 0x15 0x09 0x1af 0x00 0x14 0x09 0x1af>; + phandle = <0x38b>; + }; + + i2c4m3-xfer { + rockchip,pins = <0x01 0x03 0x09 0x1af 0x01 0x02 0x09 0x1af>; + phandle = <0x38c>; + }; + + i2c4m4-xfer { + rockchip,pins = <0x01 0x17 0x09 0x1af 0x01 0x16 0x09 0x1af>; + phandle = <0x38d>; + }; + + i2c4m1-xfer { + rockchip,pins = <0x02 0x0d 0x09 0x1af 0x02 0x0c 0x09 0x1af>; + phandle = <0x15d>; + }; + }; + + i2c5 { + + i2c5m0-xfer { + rockchip,pins = <0x03 0x17 0x09 0x1af 0x03 0x18 0x09 0x1af>; + phandle = <0x15e>; + }; + + i2c5m1-xfer { + rockchip,pins = <0x04 0x0e 0x09 0x1af 0x04 0x0f 0x09 0x1af>; + phandle = <0x38e>; + }; + + i2c5m2-xfer { + rockchip,pins = <0x04 0x06 0x09 0x1af 0x04 0x07 0x09 0x1af>; + phandle = <0x38f>; + }; + + i2c5m3-xfer { + rockchip,pins = <0x01 0x0e 0x09 0x1af 0x01 0x0f 0x09 0x1af>; + phandle = <0x390>; + }; + + i2c5m4-xfer { + rockchip,pins = <0x02 0x0e 0x09 0x1af 0x02 0x0f 0x09 0x1af>; + phandle = <0x391>; + }; + }; + + i2c6 { + + i2c6m0-xfer { + rockchip,pins = <0x00 0x18 0x09 0x1af 0x00 0x17 0x09 0x1af>; + phandle = <0x18f>; + }; + + i2c6m1-xfer { + rockchip,pins = <0x01 0x13 0x09 0x1af 0x01 0x12 0x09 0x1af>; + phandle = <0x392>; + }; + + i2c6m3-xfer { + rockchip,pins = <0x04 0x09 0x09 0x1af 0x04 0x08 0x09 0x1af>; + phandle = <0x393>; + }; + + i2c6m4-xfer { + rockchip,pins = <0x03 0x01 0x09 0x1af 0x03 0x00 0x09 0x1af>; + phandle = <0x394>; + }; + + i2c6m2-xfer { + rockchip,pins = <0x02 0x13 0x09 0x1af 0x02 0x12 0x09 0x1af>; + phandle = <0x395>; + }; + }; + + i2c7 { + + i2c7m0-xfer { + rockchip,pins = <0x01 0x18 0x09 0x1af 0x01 0x19 0x09 0x1af>; + phandle = <0x196>; + }; + + i2c7m2-xfer { + rockchip,pins = <0x03 0x1a 0x09 0x1af 0x03 0x1b 0x09 0x1af>; + phandle = <0x396>; + }; + + i2c7m3-xfer { + rockchip,pins = <0x04 0x0a 0x09 0x1af 0x04 0x0b 0x09 0x1af>; + phandle = <0x397>; + }; + + i2c7m1-xfer { + rockchip,pins = <0x04 0x13 0x09 0x1af 0x04 0x14 0x09 0x1af>; + phandle = <0x398>; + }; + }; + + i2c8 { + + i2c8m0-xfer { + rockchip,pins = <0x04 0x1a 0x09 0x1af 0x04 0x1b 0x09 0x1af>; + phandle = <0x199>; + }; + + i2c8m2-xfer { + rockchip,pins = <0x01 0x1e 0x09 0x1af 0x01 0x1f 0x09 0x1af>; + phandle = <0x399>; + }; + + i2c8m3-xfer { + rockchip,pins = <0x04 0x10 0x09 0x1af 0x04 0x11 0x09 0x1af>; + phandle = <0x39a>; + }; + + i2c8m4-xfer { + rockchip,pins = <0x03 0x12 0x09 0x1af 0x03 0x13 0x09 0x1af>; + phandle = <0x39b>; + }; + + i2c8m1-xfer { + rockchip,pins = <0x02 0x08 0x09 0x1af 0x02 0x09 0x09 0x1af>; + phandle = <0x39c>; + }; + }; + + i2s0 { + + i2s0-idle { + rockchip,pins = <0x01 0x15 0x00 0x1ab 0x01 0x13 0x00 0x1ab>; + phandle = <0x12e>; + }; + + i2s0-lrck { + rockchip,pins = <0x01 0x15 0x01 0x1af>; + phandle = <0x12a>; + }; + + i2s0-mclk { + rockchip,pins = <0x01 0x12 0x01 0x1af>; + phandle = <0x198>; + }; + + i2s0-sclk { + rockchip,pins = <0x01 0x13 0x01 0x1af>; + phandle = <0x12b>; + }; + + i2s0-sdi0 { + rockchip,pins = <0x01 0x1c 0x02 0x1ab>; + phandle = <0x12c>; + }; + + i2s0-sdi1 { + rockchip,pins = <0x01 0x1b 0x02 0x1ab>; + phandle = <0x39d>; + }; + + i2s0-sdi2 { + rockchip,pins = <0x01 0x1a 0x02 0x1ab>; + phandle = <0x39e>; + }; + + i2s0-sdi3 { + rockchip,pins = <0x01 0x19 0x02 0x1ab>; + phandle = <0x39f>; + }; + + i2s0-sdo0 { + rockchip,pins = <0x01 0x17 0x01 0x1ab>; + phandle = <0x12d>; + }; + + i2s0-sdo1 { + rockchip,pins = <0x01 0x18 0x01 0x1ab>; + phandle = <0x3a0>; + }; + + i2s0-sdo2 { + rockchip,pins = <0x01 0x19 0x01 0x1ab>; + phandle = <0x3a1>; + }; + + i2s0-sdo3 { + rockchip,pins = <0x01 0x1a 0x01 0x1ab>; + phandle = <0x3a2>; + }; + }; + + i2s1 { + + i2s1m0-lrck { + rockchip,pins = <0x04 0x02 0x03 0x1af>; + phandle = <0x12f>; + }; + + i2s1m0-mclk { + rockchip,pins = <0x04 0x00 0x03 0x1af>; + phandle = <0x3a3>; + }; + + i2s1m0-sclk { + rockchip,pins = <0x04 0x01 0x03 0x1af>; + phandle = <0x130>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x04 0x05 0x03 0x1ab>; + phandle = <0x131>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x04 0x06 0x03 0x1ab>; + phandle = <0x132>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x04 0x07 0x03 0x1ab>; + phandle = <0x133>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x04 0x08 0x03 0x1ab>; + phandle = <0x134>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x04 0x09 0x03 0x1ab>; + phandle = <0x135>; + }; + + i2s1m0-sdo1 { + rockchip,pins = <0x04 0x0a 0x03 0x1ab>; + phandle = <0x136>; + }; + + i2s1m0-sdo2 { + rockchip,pins = <0x04 0x0b 0x03 0x1ab>; + phandle = <0x137>; + }; + + i2s1m0-sdo3 { + rockchip,pins = <0x04 0x0c 0x03 0x1ab>; + phandle = <0x138>; + }; + + i2s1m1-lrck { + rockchip,pins = <0x00 0x0f 0x01 0x1af>; + phandle = <0x3a4>; + }; + + i2s1m1-mclk { + rockchip,pins = <0x00 0x0d 0x01 0x1af>; + phandle = <0x3a5>; + }; + + i2s1m1-sclk { + rockchip,pins = <0x00 0x0e 0x01 0x1af>; + phandle = <0x3a6>; + }; + + i2s1m1-sdi0 { + rockchip,pins = <0x00 0x15 0x01 0x1ab>; + phandle = <0x3a7>; + }; + + i2s1m1-sdi1 { + rockchip,pins = <0x00 0x16 0x01 0x1ab>; + phandle = <0x3a8>; + }; + + i2s1m1-sdi2 { + rockchip,pins = <0x00 0x17 0x01 0x1ab>; + phandle = <0x3a9>; + }; + + i2s1m1-sdi3 { + rockchip,pins = <0x00 0x18 0x01 0x1ab>; + phandle = <0x3aa>; + }; + + i2s1m1-sdo0 { + rockchip,pins = <0x00 0x19 0x01 0x1ab>; + phandle = <0x3ab>; + }; + + i2s1m1-sdo1 { + rockchip,pins = <0x00 0x1a 0x01 0x1ab>; + phandle = <0x3ac>; + }; + + i2s1m1-sdo2 { + rockchip,pins = <0x00 0x1c 0x01 0x1ab>; + phandle = <0x3ad>; + }; + + i2s1m1-sdo3 { + rockchip,pins = <0x00 0x1d 0x01 0x1ab>; + phandle = <0x3ae>; + }; + }; + + i2s2 { + + i2s2m1-idle { + rockchip,pins = <0x03 0x0e 0x00 0x1ab 0x03 0x0d 0x00 0x1ab>; + phandle = <0x13d>; + }; + + i2s2m1-lrck { + rockchip,pins = <0x03 0x0e 0x03 0x1af>; + phandle = <0x139>; + }; + + i2s2m1-mclk { + rockchip,pins = <0x03 0x0c 0x03 0x1af>; + phandle = <0x3af>; + }; + + i2s2m1-sclk { + rockchip,pins = <0x03 0x0d 0x03 0x1af>; + phandle = <0x13a>; + }; + + i2s2m1-sdi { + rockchip,pins = <0x03 0x0a 0x03 0x1ab>; + phandle = <0x13b>; + }; + + i2s2m1-sdo { + rockchip,pins = <0x03 0x0b 0x03 0x1ab>; + phandle = <0x13c>; + }; + + i2s2m0-idle { + rockchip,pins = <0x02 0x10 0x00 0x1ab 0x02 0x0f 0x00 0x1ab>; + phandle = <0x3b0>; + }; + + i2s2m0-lrck { + rockchip,pins = <0x02 0x10 0x02 0x1af>; + phandle = <0x3b1>; + }; + + i2s2m0-mclk { + rockchip,pins = <0x02 0x0e 0x02 0x1af>; + phandle = <0x3b2>; + }; + + i2s2m0-sclk { + rockchip,pins = <0x02 0x0f 0x02 0x1af>; + phandle = <0x3b3>; + }; + + i2s2m0-sdi { + rockchip,pins = <0x02 0x13 0x02 0x1ab>; + phandle = <0x3b4>; + }; + + i2s2m0-sdo { + rockchip,pins = <0x04 0x13 0x02 0x1ab>; + phandle = <0x3b5>; + }; + }; + + i2s3 { + + i2s3-idle { + rockchip,pins = <0x03 0x02 0x00 0x1ab 0x03 0x01 0x00 0x1ab>; + phandle = <0x140>; + }; + + i2s3-lrck { + rockchip,pins = <0x03 0x02 0x03 0x1af>; + phandle = <0x141>; + }; + + i2s3-mclk { + rockchip,pins = <0x03 0x00 0x03 0x1af>; + phandle = <0x3b6>; + }; + + i2s3-sclk { + rockchip,pins = <0x03 0x01 0x03 0x1af>; + phandle = <0x142>; + }; + + i2s3-sdi { + rockchip,pins = <0x03 0x04 0x03 0x1ab>; + phandle = <0x13e>; + }; + + i2s3-sdo { + rockchip,pins = <0x03 0x03 0x03 0x1ab>; + phandle = <0x13f>; + }; + }; + + jtag { + + jtagm0-pins { + rockchip,pins = <0x04 0x1a 0x05 0x1ab 0x04 0x1b 0x05 0x1ab>; + phandle = <0x3b7>; + }; + + jtagm1-pins { + rockchip,pins = <0x04 0x18 0x05 0x1ab 0x04 0x19 0x05 0x1ab>; + phandle = <0x3b8>; + }; + + jtagm2-pins { + rockchip,pins = <0x00 0x0d 0x02 0x1ab 0x00 0x0e 0x02 0x1ab>; + phandle = <0x3b9>; + }; + }; + + litcpu { + + litcpu-pins { + rockchip,pins = <0x00 0x1b 0x01 0x1ab>; + phandle = <0x3ba>; + }; + }; + + mcu { + + mcum0-pins { + rockchip,pins = <0x04 0x1c 0x05 0x1ab 0x04 0x1d 0x05 0x1ab>; + phandle = <0x3bb>; + }; + + mcum1-pins { + rockchip,pins = <0x03 0x1c 0x06 0x1ab 0x03 0x1d 0x06 0x1ab>; + phandle = <0x3bc>; + }; + }; + + mipi { + + mipim0-camera0-clk { + rockchip,pins = <0x04 0x09 0x01 0x1ab>; + phandle = <0x3bd>; + }; + + mipim0-camera1-clk { + rockchip,pins = <0x01 0x0e 0x02 0x1ab>; + phandle = <0x3be>; + }; + + mipim0-camera2-clk { + rockchip,pins = <0x01 0x0f 0x02 0x1ab>; + phandle = <0x3bf>; + }; + + mipim0-camera3-clk { + rockchip,pins = <0x01 0x1e 0x02 0x1ab>; + phandle = <0x15a>; + }; + + mipim0-camera4-clk { + rockchip,pins = <0x01 0x1f 0x02 0x1ab>; + phandle = <0x3c0>; + }; + + mipim1-camera0-clk { + rockchip,pins = <0x03 0x05 0x04 0x1ab>; + phandle = <0x3c1>; + }; + + mipim1-camera1-clk { + rockchip,pins = <0x03 0x06 0x04 0x1ab>; + phandle = <0x3c2>; + }; + + mipim1-camera2-clk { + rockchip,pins = <0x03 0x07 0x04 0x1ab>; + phandle = <0x3c3>; + }; + + mipim1-camera3-clk { + rockchip,pins = <0x03 0x08 0x04 0x1ab>; + phandle = <0x3c4>; + }; + + mipim1-camera4-clk { + rockchip,pins = <0x03 0x09 0x04 0x1ab>; + phandle = <0x3c5>; + }; + + mipi-te0 { + rockchip,pins = <0x03 0x12 0x02 0x1ab>; + phandle = <0x3c6>; + }; + + mipi-te1 { + rockchip,pins = <0x03 0x13 0x02 0x1ab>; + phandle = <0x3c7>; + }; + }; + + npu { + + npu-pins { + rockchip,pins = <0x00 0x16 0x02 0x1ab>; + phandle = <0x3c8>; + }; + }; + + pcie20x1 { + + pcie20x1m0-pins { + rockchip,pins = <0x03 0x17 0x04 0x1ab 0x03 0x19 0x04 0x1ab 0x03 0x18 0x04 0x1ab>; + phandle = <0x3c9>; + }; + + pcie20x1m1-pins { + rockchip,pins = <0x04 0x0f 0x04 0x1ab 0x04 0x11 0x04 0x1ab 0x04 0x10 0x04 0x1ab>; + phandle = <0x3ca>; + }; + + pcie20x1-2-button-rstn { + rockchip,pins = <0x04 0x0b 0x04 0x1ab>; + phandle = <0x3cb>; + }; + }; + + pcie30phy { + + pcie30phy-pins { + rockchip,pins = <0x01 0x14 0x04 0x1ab 0x01 0x19 0x04 0x1ab>; + phandle = <0x3cc>; + }; + }; + + pcie30x1 { + + pcie30x1m0-pins { + rockchip,pins = <0x00 0x10 0x0c 0x1ab 0x00 0x15 0x0c 0x1ab 0x00 0x14 0x0c 0x1ab 0x00 0x0d 0x0c 0x1ab 0x00 0x0f 0x0c 0x1ab 0x00 0x0e 0x0c 0x1ab>; + phandle = <0x3cd>; + }; + + pcie30x1m1-pins { + rockchip,pins = <0x04 0x03 0x04 0x1ab 0x04 0x05 0x04 0x1ab 0x04 0x04 0x04 0x1ab 0x04 0x00 0x04 0x1ab 0x04 0x02 0x04 0x1ab 0x04 0x01 0x04 0x1ab>; + phandle = <0x3ce>; + }; + + pcie30x1m2-pins { + rockchip,pins = <0x01 0x0d 0x04 0x1ab 0x01 0x0c 0x04 0x1ab 0x01 0x0b 0x04 0x1ab 0x01 0x00 0x04 0x1ab 0x01 0x07 0x04 0x1ab 0x01 0x01 0x04 0x1ab>; + phandle = <0x3cf>; + }; + + pcie30x1-0-button-rstn { + rockchip,pins = <0x04 0x09 0x04 0x1ab>; + phandle = <0x3d0>; + }; + + pcie30x1-1-button-rstn { + rockchip,pins = <0x04 0x0a 0x04 0x1ab>; + phandle = <0x3d1>; + }; + }; + + pcie30x2 { + + pcie30x2m0-pins { + rockchip,pins = <0x00 0x19 0x0c 0x1ab 0x00 0x1c 0x0c 0x1ab 0x00 0x1a 0x0c 0x1ab>; + phandle = <0x3d2>; + }; + + pcie30x2m1-pins { + rockchip,pins = <0x04 0x06 0x04 0x1ab 0x04 0x08 0x04 0x1ab 0x04 0x07 0x04 0x1ab>; + phandle = <0x3d3>; + }; + + pcie30x2m2-pins { + rockchip,pins = <0x03 0x1a 0x04 0x1ab 0x03 0x1c 0x04 0x1ab 0x03 0x1b 0x04 0x1ab>; + phandle = <0x3d4>; + }; + + pcie30x2m3-pins { + rockchip,pins = <0x01 0x1f 0x04 0x1ab 0x01 0x0f 0x04 0x1ab 0x01 0x0e 0x04 0x1ab>; + phandle = <0x3d5>; + }; + + pcie30x2-button-rstn { + rockchip,pins = <0x03 0x11 0x04 0x1ab>; + phandle = <0x3d6>; + }; + }; + + pcie30x4 { + + pcie30x4m0-pins { + rockchip,pins = <0x00 0x16 0x0c 0x1ab 0x00 0x18 0x0c 0x1ab 0x00 0x17 0x0c 0x1ab>; + phandle = <0x3d7>; + }; + + pcie30x4m1-pins { + rockchip,pins = <0x04 0x0c 0x04 0x1ab 0x04 0x0e 0x04 0x1ab 0x04 0x0d 0x04 0x1ab>; + phandle = <0x3d8>; + }; + + pcie30x4m2-pins { + rockchip,pins = <0x03 0x14 0x04 0x1ab 0x03 0x16 0x04 0x1ab 0x03 0x15 0x04 0x1ab>; + phandle = <0x3d9>; + }; + + pcie30x4m3-pins { + rockchip,pins = <0x01 0x08 0x04 0x1ab 0x01 0x0a 0x04 0x1ab 0x01 0x09 0x04 0x1ab>; + phandle = <0x3da>; + }; + + pcie30x4-button-rstn { + rockchip,pins = <0x03 0x1d 0x04 0x1ab>; + phandle = <0x3db>; + }; + }; + + pdm0 { + + pdm0m0-clk { + rockchip,pins = <0x01 0x16 0x03 0x1ab>; + phandle = <0x148>; + }; + + pdm0m0-clk1 { + rockchip,pins = <0x01 0x14 0x03 0x1ab>; + phandle = <0x149>; + }; + + pdm0m0-idle { + rockchip,pins = <0x01 0x16 0x00 0x1ab 0x01 0x14 0x00 0x1ab>; + phandle = <0x147>; + }; + + pdm0m0-sdi0 { + rockchip,pins = <0x01 0x1d 0x03 0x1ab>; + phandle = <0x143>; + }; + + pdm0m0-sdi1 { + rockchip,pins = <0x01 0x19 0x03 0x1ab>; + phandle = <0x144>; + }; + + pdm0m0-sdi2 { + rockchip,pins = <0x01 0x1a 0x03 0x1ab>; + phandle = <0x145>; + }; + + pdm0m0-sdi3 { + rockchip,pins = <0x01 0x1b 0x03 0x1ab>; + phandle = <0x146>; + }; + + pdm0m1-clk { + rockchip,pins = <0x00 0x10 0x02 0x1ab>; + phandle = <0x3dc>; + }; + + pdm0m1-clk1 { + rockchip,pins = <0x00 0x14 0x02 0x1ab>; + phandle = <0x3dd>; + }; + + pdm0m1-idle { + rockchip,pins = <0x00 0x10 0x00 0x1ab 0x00 0x14 0x00 0x1ab>; + phandle = <0x3de>; + }; + + pdm0m1-sdi0 { + rockchip,pins = <0x00 0x17 0x02 0x1ab>; + phandle = <0x3df>; + }; + + pdm0m1-sdi1 { + rockchip,pins = <0x00 0x18 0x02 0x1ab>; + phandle = <0x3e0>; + }; + + pdm0m1-sdi2 { + rockchip,pins = <0x00 0x1c 0x02 0x1ab>; + phandle = <0x3e1>; + }; + + pdm0m1-sdi3 { + rockchip,pins = <0x00 0x1e 0x02 0x1ab>; + phandle = <0x3e2>; + }; + }; + + pdm1 { + + pdm1m0-clk { + rockchip,pins = <0x04 0x1d 0x02 0x1ab>; + phandle = <0x14f>; + }; + + pdm1m0-clk1 { + rockchip,pins = <0x04 0x1c 0x02 0x1ab>; + phandle = <0x150>; + }; + + pdm1m0-idle { + rockchip,pins = <0x04 0x1d 0x00 0x1ab 0x04 0x1c 0x00 0x1ab>; + phandle = <0x14e>; + }; + + pdm1m0-sdi0 { + rockchip,pins = <0x04 0x1b 0x02 0x1ab>; + phandle = <0x14a>; + }; + + pdm1m0-sdi1 { + rockchip,pins = <0x04 0x1a 0x02 0x1ab>; + phandle = <0x14b>; + }; + + pdm1m0-sdi2 { + rockchip,pins = <0x04 0x19 0x02 0x1ab>; + phandle = <0x14c>; + }; + + pdm1m0-sdi3 { + rockchip,pins = <0x04 0x18 0x02 0x1ab>; + phandle = <0x14d>; + }; + + pdm1m1-clk { + rockchip,pins = <0x01 0x0c 0x02 0x1ab>; + phandle = <0x3e3>; + }; + + pdm1m1-clk1 { + rockchip,pins = <0x01 0x0b 0x02 0x1ab>; + phandle = <0x3e4>; + }; + + pdm1m1-idle { + rockchip,pins = <0x01 0x0c 0x00 0x1ab 0x01 0x0b 0x00 0x1ab>; + phandle = <0x3e5>; + }; + + pdm1m1-sdi0 { + rockchip,pins = <0x01 0x07 0x02 0x1ab>; + phandle = <0x3e6>; + }; + + pdm1m1-sdi1 { + rockchip,pins = <0x01 0x08 0x02 0x1ab>; + phandle = <0x3e7>; + }; + + pdm1m1-sdi2 { + rockchip,pins = <0x01 0x09 0x02 0x1ab>; + phandle = <0x3e8>; + }; + + pdm1m1-sdi3 { + rockchip,pins = <0x01 0x0a 0x02 0x1ab>; + phandle = <0x3e9>; + }; + }; + + pmic { + + pmic-pins { + rockchip,pins = <0x00 0x07 0x00 0x1b1 0x00 0x02 0x01 0x1ab 0x00 0x03 0x01 0x1ab 0x00 0x11 0x01 0x1ab 0x00 0x12 0x01 0x1ab 0x00 0x13 0x01 0x1ab 0x00 0x1e 0x01 0x1ab>; + phandle = <0x16c>; + }; + }; + + pmu { + + pmu-pins { + rockchip,pins = <0x00 0x05 0x03 0x1ab>; + phandle = <0x3ea>; + }; + }; + + pwm0 { + + pwm0m0-pins { + rockchip,pins = <0x00 0x0f 0x03 0x1ab>; + phandle = <0x7c>; + }; + + pwm0m1-pins { + rockchip,pins = <0x01 0x1a 0x0b 0x1ab>; + phandle = <0x3eb>; + }; + + pwm0m2-pins { + rockchip,pins = <0x01 0x02 0x0b 0x1ab>; + phandle = <0x3ec>; + }; + }; + + pwm1 { + + pwm1m0-pins { + rockchip,pins = <0x00 0x10 0x03 0x1ab>; + phandle = <0x7d>; + }; + + pwm1m1-pins { + rockchip,pins = <0x01 0x1b 0x0b 0x1ab>; + phandle = <0x3ed>; + }; + + pwm1m2-pins { + rockchip,pins = <0x01 0x03 0x0b 0x1ab>; + phandle = <0x3ee>; + }; + }; + + pwm2 { + + pwm2m0-pins { + rockchip,pins = <0x00 0x14 0x03 0x1ab>; + phandle = <0x7e>; + }; + + pwm2m1-pins { + rockchip,pins = <0x03 0x09 0x0b 0x1ab>; + phandle = <0x3ef>; + }; + + pwm2m2-pins { + rockchip,pins = <0x04 0x12 0x0b 0x1ab>; + phandle = <0x3f0>; + }; + }; + + pwm3 { + + pwm3m0-pins { + rockchip,pins = <0x00 0x1c 0x03 0x1ab>; + phandle = <0x3f1>; + }; + + pwm3m1-pins { + rockchip,pins = <0x03 0x0a 0x0b 0x1ab>; + phandle = <0x7f>; + }; + + pwm3m2-pins { + rockchip,pins = <0x01 0x12 0x0b 0x1ab>; + phandle = <0x3f2>; + }; + + pwm3m3-pins { + rockchip,pins = <0x01 0x07 0x0b 0x1ab>; + phandle = <0x3f3>; + }; + }; + + pwm4 { + + pwm4m0-pins { + rockchip,pins = <0x00 0x15 0x0b 0x1ab>; + phandle = <0x180>; + }; + + pwm4m1-pins { + rockchip,pins = <0x04 0x13 0x0b 0x1ab>; + phandle = <0x3f4>; + }; + }; + + pwm5 { + + pwm5m0-pins { + rockchip,pins = <0x00 0x09 0x03 0x1ab>; + phandle = <0x181>; + }; + + pwm5m1-pins { + rockchip,pins = <0x00 0x16 0x0b 0x1ab>; + phandle = <0x3f5>; + }; + + pwm5m2-pins { + rockchip,pins = <0x04 0x14 0x0b 0x1ab>; + phandle = <0x3f6>; + }; + }; + + pwm6 { + + pwm6m0-pins { + rockchip,pins = <0x00 0x17 0x0b 0x1ab>; + phandle = <0x182>; + }; + + pwm6m1-pins { + rockchip,pins = <0x04 0x11 0x0b 0x1ab>; + phandle = <0x3f7>; + }; + + pwm6m2-pins { + rockchip,pins = <0x04 0x15 0x0b 0x1ab>; + phandle = <0x3f8>; + }; + }; + + pwm7 { + + pwm7m0-pins { + rockchip,pins = <0x00 0x18 0x0b 0x1ab>; + phandle = <0x183>; + }; + + pwm7m1-pins { + rockchip,pins = <0x04 0x1c 0x0b 0x1ab>; + phandle = <0x3f9>; + }; + + pwm7m2-pins { + rockchip,pins = <0x01 0x13 0x0b 0x1ab>; + phandle = <0x3fa>; + }; + + pwm7m3-pins { + rockchip,pins = <0x04 0x16 0x0b 0x1ab>; + phandle = <0x3fb>; + }; + }; + + pwm8 { + + pwm8m0-pins { + rockchip,pins = <0x03 0x07 0x0b 0x1ab>; + phandle = <0x184>; + }; + + pwm8m1-pins { + rockchip,pins = <0x04 0x18 0x0b 0x1ab>; + phandle = <0x3fc>; + }; + + pwm8m2-pins { + rockchip,pins = <0x03 0x18 0x0b 0x1ab>; + phandle = <0x3fd>; + }; + }; + + pwm9 { + + pwm9m0-pins { + rockchip,pins = <0x03 0x08 0x0b 0x1ab>; + phandle = <0x185>; + }; + + pwm9m1-pins { + rockchip,pins = <0x04 0x19 0x0b 0x1ab>; + phandle = <0x3fe>; + }; + + pwm9m2-pins { + rockchip,pins = <0x03 0x19 0x0b 0x1ab>; + phandle = <0x3ff>; + }; + }; + + pwm10 { + + pwm10m0-pins { + rockchip,pins = <0x03 0x00 0x0b 0x1ab>; + phandle = <0x186>; + }; + + pwm10m1-pins { + rockchip,pins = <0x04 0x1b 0x0b 0x1ab>; + phandle = <0x400>; + }; + + pwm10m2-pins { + rockchip,pins = <0x03 0x1b 0x0b 0x1ab>; + phandle = <0x401>; + }; + }; + + pwm11 { + + pwm11m0-pins { + rockchip,pins = <0x03 0x01 0x0b 0x1ab>; + phandle = <0x187>; + }; + + pwm11m1-pins { + rockchip,pins = <0x04 0x0c 0x0b 0x1ab>; + phandle = <0x402>; + }; + + pwm11m2-pins { + rockchip,pins = <0x01 0x14 0x0b 0x1ab>; + phandle = <0x403>; + }; + + pwm11m3-pins { + rockchip,pins = <0x03 0x1d 0x0b 0x1ab>; + phandle = <0x404>; + }; + }; + + pwm12 { + + pwm12m0-pins { + rockchip,pins = <0x03 0x0d 0x0b 0x1ab>; + phandle = <0x188>; + }; + + pwm12m1-pins { + rockchip,pins = <0x04 0x0d 0x0b 0x1ab>; + phandle = <0x405>; + }; + }; + + pwm13 { + + pwm13m0-pins { + rockchip,pins = <0x03 0x0e 0x0b 0x1ab>; + phandle = <0x189>; + }; + + pwm13m1-pins { + rockchip,pins = <0x04 0x0e 0x0b 0x1ab>; + phandle = <0x406>; + }; + + pwm13m2-pins { + rockchip,pins = <0x01 0x0f 0x0b 0x1ab>; + phandle = <0x407>; + }; + }; + + pwm14 { + + pwm14m0-pins { + rockchip,pins = <0x03 0x12 0x0b 0x1ab>; + phandle = <0x18a>; + }; + + pwm14m1-pins { + rockchip,pins = <0x04 0x0a 0x0b 0x1ab>; + phandle = <0x408>; + }; + + pwm14m2-pins { + rockchip,pins = <0x01 0x1e 0x0b 0x1ab>; + phandle = <0x409>; + }; + }; + + pwm15 { + + pwm15m0-pins { + rockchip,pins = <0x03 0x13 0x0b 0x1ab>; + phandle = <0x18b>; + }; + + pwm15m1-pins { + rockchip,pins = <0x04 0x0b 0x0b 0x1ab>; + phandle = <0x40a>; + }; + + pwm15m2-pins { + rockchip,pins = <0x01 0x16 0x0b 0x1ab>; + phandle = <0x40b>; + }; + + pwm15m3-pins { + rockchip,pins = <0x01 0x1f 0x0b 0x1ab>; + phandle = <0x40c>; + }; + }; + + refclk { + + refclk-pins { + rockchip,pins = <0x00 0x00 0x01 0x1ab>; + phandle = <0x40d>; + }; + }; + + sata { + + sata-pins { + rockchip,pins = <0x00 0x16 0x0d 0x1ab 0x00 0x1c 0x0d 0x1ab 0x00 0x1d 0x0d 0x1ab>; + phandle = <0x40e>; + }; + }; + + sata0 { + + sata0m0-pins { + rockchip,pins = <0x04 0x0e 0x06 0x1ab>; + phandle = <0x40f>; + }; + + sata0m1-pins { + rockchip,pins = <0x01 0x0b 0x06 0x1ab>; + phandle = <0x410>; + }; + }; + + sata1 { + + sata1m0-pins { + rockchip,pins = <0x04 0x0d 0x06 0x1ab>; + phandle = <0x411>; + }; + + sata1m1-pins { + rockchip,pins = <0x01 0x01 0x06 0x1ab>; + phandle = <0x412>; + }; + }; + + sata2 { + + sata2m0-pins { + rockchip,pins = <0x04 0x09 0x06 0x1ab>; + phandle = <0x413>; + }; + + sata2m1-pins { + rockchip,pins = <0x01 0x0f 0x06 0x1ab>; + phandle = <0x414>; + }; + }; + + sdio { + + sdiom1-pins { + rockchip,pins = <0x03 0x05 0x02 0x1ab 0x03 0x04 0x02 0x1b1 0x03 0x00 0x02 0x1b1 0x03 0x01 0x02 0x1b1 0x03 0x02 0x02 0x1b1 0x03 0x03 0x02 0x1b1>; + phandle = <0x415>; + }; + + sdiom0-pins { + rockchip,pins = <0x02 0x0b 0x02 0x1ab 0x02 0x0a 0x02 0x1b1 0x02 0x06 0x02 0x1b1 0x02 0x07 0x02 0x1b1 0x02 0x08 0x02 0x1b1 0x02 0x09 0x02 0x1b1>; + phandle = <0x126>; + }; + }; + + sdmmc { + + sdmmc-bus4 { + rockchip,pins = <0x04 0x18 0x01 0x1ac 0x04 0x19 0x01 0x1ac 0x04 0x1a 0x01 0x1ac 0x04 0x1b 0x01 0x1ac>; + phandle = <0x123>; + }; + + sdmmc-clk { + rockchip,pins = <0x04 0x1d 0x01 0x1ac>; + phandle = <0x120>; + }; + + sdmmc-cmd { + rockchip,pins = <0x04 0x1c 0x01 0x1ac>; + phandle = <0x121>; + }; + + sdmmc-det { + rockchip,pins = <0x00 0x04 0x01 0x1b1>; + phandle = <0x122>; + }; + + sdmmc-pwren { + rockchip,pins = <0x00 0x05 0x02 0x1ab>; + phandle = <0x416>; + }; + + sd-s0-pwr { + rockchip,pins = <0x00 0x0f 0x00 0x1b1>; + phandle = <0x202>; + }; + }; + + spdif0 { + + spdif0m0-tx { + rockchip,pins = <0x01 0x0e 0x03 0x1ab>; + phandle = <0x151>; + }; + + spdif0m1-tx { + rockchip,pins = <0x04 0x0c 0x06 0x1ab>; + phandle = <0x417>; + }; + }; + + spdif1 { + + spdif1m0-tx { + rockchip,pins = <0x01 0x0f 0x03 0x1ab>; + phandle = <0x152>; + }; + + spdif1m1-tx { + rockchip,pins = <0x04 0x09 0x02 0x1ab>; + phandle = <0x418>; + }; + + spdif1m2-tx { + rockchip,pins = <0x04 0x11 0x03 0x1ab>; + phandle = <0x419>; + }; + }; + + spi0 { + + spi0m0-pins { + rockchip,pins = <0x00 0x16 0x08 0x1b2 0x00 0x17 0x08 0x1b2 0x00 0x10 0x08 0x1b2>; + phandle = <0x166>; + }; + + spi0m0-cs0 { + rockchip,pins = <0x00 0x19 0x08 0x1b2>; + phandle = <0x164>; + }; + + spi0m0-cs1 { + rockchip,pins = <0x00 0x0f 0x08 0x1b2>; + phandle = <0x165>; + }; + + spi0m1-pins { + rockchip,pins = <0x04 0x02 0x08 0x1b2 0x04 0x00 0x08 0x1b2 0x04 0x01 0x08 0x1b2>; + phandle = <0x41a>; + }; + + spi0m1-cs0 { + rockchip,pins = <0x04 0x0a 0x08 0x1b2>; + phandle = <0x41b>; + }; + + spi0m1-cs1 { + rockchip,pins = <0x04 0x09 0x08 0x1b2>; + phandle = <0x41c>; + }; + + spi0m2-pins { + rockchip,pins = <0x01 0x0b 0x08 0x1b2 0x01 0x09 0x08 0x1b2 0x01 0x0a 0x08 0x1b2>; + phandle = <0x41d>; + }; + + spi0m2-cs0 { + rockchip,pins = <0x01 0x0c 0x08 0x1b2>; + phandle = <0x41e>; + }; + + spi0m2-cs1 { + rockchip,pins = <0x01 0x0d 0x08 0x1b2>; + phandle = <0x41f>; + }; + + spi0m3-pins { + rockchip,pins = <0x03 0x1b 0x08 0x1b2 0x03 0x19 0x08 0x1b2 0x03 0x1a 0x08 0x1b2>; + phandle = <0x420>; + }; + + spi0m3-cs0 { + rockchip,pins = <0x03 0x1c 0x08 0x1b2>; + phandle = <0x421>; + }; + + spi0m3-cs1 { + rockchip,pins = <0x03 0x1d 0x08 0x1b2>; + phandle = <0x422>; + }; + }; + + spi1 { + + spi1m1-pins { + rockchip,pins = <0x03 0x11 0x08 0x1b2 0x03 0x10 0x08 0x1b2 0x03 0x0f 0x08 0x1b2>; + phandle = <0x169>; + }; + + spi1m1-cs0 { + rockchip,pins = <0x03 0x12 0x08 0x1b2>; + phandle = <0x167>; + }; + + spi1m1-cs1 { + rockchip,pins = <0x03 0x13 0x08 0x1b2>; + phandle = <0x168>; + }; + + spi1m2-pins { + rockchip,pins = <0x01 0x1a 0x08 0x1b2 0x01 0x18 0x08 0x1b2 0x01 0x19 0x08 0x1b2>; + phandle = <0x423>; + }; + + spi1m2-cs0 { + rockchip,pins = <0x01 0x1b 0x08 0x1b2>; + phandle = <0x424>; + }; + + spi1m2-cs1 { + rockchip,pins = <0x01 0x1d 0x08 0x1b2>; + phandle = <0x425>; + }; + + spi1m0-pins { + rockchip,pins = <0x02 0x10 0x08 0x1b3 0x02 0x11 0x08 0x1b3 0x02 0x12 0x08 0x1b3>; + phandle = <0x426>; + }; + + spi1m0-cs0 { + rockchip,pins = <0x02 0x13 0x08 0x1b3>; + phandle = <0x427>; + }; + + spi1m0-cs1 { + rockchip,pins = <0x02 0x14 0x08 0x1b3>; + phandle = <0x428>; + }; + }; + + spi2 { + + spi2m0-pins { + rockchip,pins = <0x01 0x06 0x08 0x1b2 0x01 0x04 0x08 0x1b2 0x01 0x05 0x08 0x1b2>; + phandle = <0x429>; + }; + + spi2m0-cs0 { + rockchip,pins = <0x01 0x07 0x08 0x1b2>; + phandle = <0x42a>; + }; + + spi2m0-cs1 { + rockchip,pins = <0x01 0x08 0x08 0x1b2>; + phandle = <0x42b>; + }; + + spi2m1-pins { + rockchip,pins = <0x04 0x06 0x08 0x1b2 0x04 0x04 0x08 0x1b2 0x04 0x05 0x08 0x1b2>; + phandle = <0x42c>; + }; + + spi2m1-cs0 { + rockchip,pins = <0x04 0x07 0x08 0x1b2>; + phandle = <0x42d>; + }; + + spi2m1-cs1 { + rockchip,pins = <0x04 0x08 0x08 0x1b2>; + phandle = <0x42e>; + }; + + spi2m2-pins { + rockchip,pins = <0x00 0x05 0x01 0x1b3 0x00 0x0b 0x01 0x1b3 0x00 0x06 0x01 0x1b3>; + phandle = <0x16b>; + }; + + spi2m2-cs0 { + rockchip,pins = <0x00 0x09 0x01 0x1b3>; + phandle = <0x16a>; + }; + + spi2m2-cs1 { + rockchip,pins = <0x00 0x08 0x01 0x1b3>; + phandle = <0x42f>; + }; + }; + + spi3 { + + spi3m1-pins { + rockchip,pins = <0x04 0x0f 0x08 0x1b2 0x04 0x0d 0x08 0x1b2 0x04 0x0e 0x08 0x1b2>; + phandle = <0x175>; + }; + + spi3m1-cs0 { + rockchip,pins = <0x04 0x10 0x08 0x1b2>; + phandle = <0x173>; + }; + + spi3m1-cs1 { + rockchip,pins = <0x04 0x11 0x08 0x1b2>; + phandle = <0x174>; + }; + + spi3m2-pins { + rockchip,pins = <0x00 0x1b 0x08 0x1b2 0x00 0x18 0x08 0x1b2 0x00 0x1a 0x08 0x1b2>; + phandle = <0x430>; + }; + + spi3m2-cs0 { + rockchip,pins = <0x00 0x1c 0x08 0x1b2>; + phandle = <0x431>; + }; + + spi3m2-cs1 { + rockchip,pins = <0x00 0x1d 0x08 0x1b2>; + phandle = <0x432>; + }; + + spi3m3-pins { + rockchip,pins = <0x03 0x18 0x08 0x1b2 0x03 0x16 0x08 0x1b2 0x03 0x17 0x08 0x1b2>; + phandle = <0x433>; + }; + + spi3m3-cs0 { + rockchip,pins = <0x03 0x14 0x08 0x1b2>; + phandle = <0x434>; + }; + + spi3m3-cs1 { + rockchip,pins = <0x03 0x15 0x08 0x1b2>; + phandle = <0x435>; + }; + + spi3m0-pins { + rockchip,pins = <0x04 0x16 0x08 0x1b3 0x04 0x14 0x08 0x1b3 0x04 0x15 0x08 0x1b3>; + phandle = <0x436>; + }; + + spi3m0-cs0 { + rockchip,pins = <0x04 0x12 0x08 0x1b3>; + phandle = <0x437>; + }; + + spi3m0-cs1 { + rockchip,pins = <0x04 0x13 0x08 0x1b3>; + phandle = <0x438>; + }; + }; + + spi4 { + + spi4m0-pins { + rockchip,pins = <0x01 0x12 0x08 0x1b2 0x01 0x10 0x08 0x1b2 0x01 0x11 0x08 0x1b2>; + phandle = <0x19c>; + }; + + spi4m0-cs0 { + rockchip,pins = <0x01 0x13 0x08 0x1b2>; + phandle = <0x19a>; + }; + + spi4m0-cs1 { + rockchip,pins = <0x01 0x14 0x08 0x1b2>; + phandle = <0x19b>; + }; + + spi4m1-pins { + rockchip,pins = <0x03 0x02 0x08 0x1b2 0x03 0x00 0x08 0x1b2 0x03 0x01 0x08 0x1b2>; + phandle = <0x439>; + }; + + spi4m1-cs0 { + rockchip,pins = <0x03 0x03 0x08 0x1b2>; + phandle = <0x43a>; + }; + + spi4m1-cs1 { + rockchip,pins = <0x03 0x04 0x08 0x1b2>; + phandle = <0x43b>; + }; + + spi4m2-pins { + rockchip,pins = <0x01 0x02 0x08 0x1b2 0x01 0x00 0x08 0x1b2 0x01 0x01 0x08 0x1b2>; + phandle = <0x43c>; + }; + + spi4m2-cs0 { + rockchip,pins = <0x01 0x03 0x08 0x1b2>; + phandle = <0x43d>; + }; + }; + + tsadc { + + tsadcm1-shut { + rockchip,pins = <0x00 0x02 0x02 0x1ab>; + phandle = <0x43e>; + }; + + tsadc-shut { + rockchip,pins = <0x00 0x01 0x02 0x1ab>; + phandle = <0x18d>; + }; + + tsadc-shut-org { + rockchip,pins = <0x00 0x01 0x01 0x1ab>; + phandle = <0x43f>; + }; + }; + + uart0 { + + uart0m0-xfer { + rockchip,pins = <0x00 0x14 0x04 0x1b1 0x00 0x15 0x04 0x1b1>; + phandle = <0x440>; + }; + + uart0m1-xfer { + rockchip,pins = <0x00 0x08 0x04 0x1b1 0x00 0x09 0x04 0x1b1>; + phandle = <0x7b>; + }; + + uart0m2-xfer { + rockchip,pins = <0x04 0x04 0x0a 0x1b1 0x04 0x03 0x0a 0x1b1>; + phandle = <0x441>; + }; + + uart0-ctsn { + rockchip,pins = <0x00 0x19 0x04 0x1ab>; + phandle = <0x442>; + }; + + uart0-rtsn { + rockchip,pins = <0x00 0x16 0x04 0x1ab>; + phandle = <0x443>; + }; + }; + + uart1 { + + uart1m1-xfer { + rockchip,pins = <0x01 0x0f 0x0a 0x1b1 0x01 0x0e 0x0a 0x1b1>; + phandle = <0x176>; + }; + + uart1m1-ctsn { + rockchip,pins = <0x01 0x1f 0x0a 0x1ab>; + phandle = <0x444>; + }; + + uart1m1-rtsn { + rockchip,pins = <0x01 0x1e 0x0a 0x1ab>; + phandle = <0x445>; + }; + + uart1m2-xfer { + rockchip,pins = <0x00 0x1a 0x0a 0x1b1 0x00 0x19 0x0a 0x1b1>; + phandle = <0x446>; + }; + + uart1m2-ctsn { + rockchip,pins = <0x00 0x18 0x0a 0x1ab>; + phandle = <0x447>; + }; + + uart1m2-rtsn { + rockchip,pins = <0x00 0x17 0x0a 0x1ab>; + phandle = <0x448>; + }; + + uart1m0-xfer { + rockchip,pins = <0x02 0x0e 0x0a 0x1b1 0x02 0x0f 0x0a 0x1b1>; + phandle = <0x449>; + }; + + uart1m0-ctsn { + rockchip,pins = <0x02 0x11 0x0a 0x1ab>; + phandle = <0x44a>; + }; + + uart1m0-rtsn { + rockchip,pins = <0x02 0x10 0x0a 0x1ab>; + phandle = <0x44b>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x0e 0x0a 0x1b1 0x00 0x0d 0x0a 0x1b1>; + phandle = <0x209>; + }; + + uart2m1-xfer { + rockchip,pins = <0x04 0x19 0x0a 0x1b1 0x04 0x18 0x0a 0x1b1>; + phandle = <0x177>; + }; + + uart2m2-xfer { + rockchip,pins = <0x03 0x0a 0x0a 0x1b1 0x03 0x09 0x0a 0x1b1>; + phandle = <0x44c>; + }; + + uart2-ctsn { + rockchip,pins = <0x03 0x0c 0x0a 0x1ab>; + phandle = <0x44d>; + }; + + uart2-rtsn { + rockchip,pins = <0x03 0x0b 0x0a 0x1ab>; + phandle = <0x44e>; + }; + }; + + uart3 { + + uart3m0-xfer { + rockchip,pins = <0x01 0x10 0x0a 0x1b1 0x01 0x11 0x0a 0x1b1>; + phandle = <0x44f>; + }; + + uart3m1-xfer { + rockchip,pins = <0x03 0x0e 0x0a 0x1b1 0x03 0x0d 0x0a 0x1b1>; + phandle = <0x178>; + }; + + uart3m2-xfer { + rockchip,pins = <0x04 0x06 0x0a 0x1b1 0x04 0x05 0x0a 0x1b1>; + phandle = <0x450>; + }; + + uart3-ctsn { + rockchip,pins = <0x01 0x13 0x0a 0x1ab>; + phandle = <0x451>; + }; + + uart3-rtsn { + rockchip,pins = <0x01 0x12 0x0a 0x1ab>; + phandle = <0x452>; + }; + }; + + uart4 { + + uart4m0-xfer { + rockchip,pins = <0x01 0x1b 0x0a 0x1b1 0x01 0x1a 0x0a 0x1b1>; + phandle = <0x453>; + }; + + uart4m1-xfer { + rockchip,pins = <0x03 0x18 0x0a 0x1b1 0x03 0x19 0x0a 0x1b1>; + phandle = <0x179>; + }; + + uart4m2-xfer { + rockchip,pins = <0x01 0x0a 0x0a 0x1b1 0x01 0x0b 0x0a 0x1b1>; + phandle = <0x454>; + }; + + uart4-ctsn { + rockchip,pins = <0x01 0x17 0x0a 0x1ab>; + phandle = <0x455>; + }; + + uart4-rtsn { + rockchip,pins = <0x01 0x15 0x0a 0x1ab>; + phandle = <0x456>; + }; + }; + + uart5 { + + uart5m0-xfer { + rockchip,pins = <0x04 0x1c 0x0a 0x1b1 0x04 0x1d 0x0a 0x1b1>; + phandle = <0x457>; + }; + + uart5m0-ctsn { + rockchip,pins = <0x04 0x1a 0x0a 0x1ab>; + phandle = <0x458>; + }; + + uart5m0-rtsn { + rockchip,pins = <0x04 0x1b 0x0a 0x1ab>; + phandle = <0x459>; + }; + + uart5m1-xfer { + rockchip,pins = <0x03 0x15 0x0a 0x1b1 0x03 0x14 0x0a 0x1b1>; + phandle = <0x17a>; + }; + + uart5m1-ctsn { + rockchip,pins = <0x02 0x02 0x0a 0x1ab>; + phandle = <0x45a>; + }; + + uart5m1-rtsn { + rockchip,pins = <0x02 0x03 0x0a 0x1ab>; + phandle = <0x45b>; + }; + + uart5m2-xfer { + rockchip,pins = <0x02 0x1c 0x0a 0x1b1 0x02 0x1d 0x0a 0x1b1>; + phandle = <0x45c>; + }; + }; + + uart6 { + + uart6m1-xfer { + rockchip,pins = <0x01 0x00 0x0a 0x1b1 0x01 0x01 0x0a 0x1b1>; + phandle = <0x17b>; + }; + + uart6m1-ctsn { + rockchip,pins = <0x01 0x03 0x0a 0x1ab>; + phandle = <0x45d>; + }; + + uart6m1-rtsn { + rockchip,pins = <0x01 0x02 0x0a 0x1ab>; + phandle = <0x45e>; + }; + + uart6m2-xfer { + rockchip,pins = <0x01 0x19 0x0a 0x1b1 0x01 0x18 0x0a 0x1b1>; + phandle = <0x45f>; + }; + + uart6m0-xfer { + rockchip,pins = <0x02 0x06 0x0a 0x1b1 0x02 0x07 0x0a 0x1b1>; + phandle = <0x460>; + }; + + uart6m0-ctsn { + rockchip,pins = <0x02 0x09 0x0a 0x1ab>; + phandle = <0x461>; + }; + + uart6m0-rtsn { + rockchip,pins = <0x02 0x08 0x0a 0x1ab>; + phandle = <0x462>; + }; + }; + + uart7 { + + uart7m1-xfer { + rockchip,pins = <0x03 0x11 0x0a 0x1b1 0x03 0x10 0x0a 0x1b1>; + phandle = <0x17c>; + }; + + uart7m1-ctsn { + rockchip,pins = <0x03 0x13 0x0a 0x1ab>; + phandle = <0x463>; + }; + + uart7m1-rtsn { + rockchip,pins = <0x03 0x12 0x0a 0x1ab>; + phandle = <0x464>; + }; + + uart7m2-xfer { + rockchip,pins = <0x01 0x0c 0x0a 0x1b1 0x01 0x0d 0x0a 0x1b1>; + phandle = <0x465>; + }; + + uart7m0-xfer { + rockchip,pins = <0x02 0x0c 0x0a 0x1b1 0x02 0x0d 0x0a 0x1b1>; + phandle = <0x466>; + }; + + uart7m0-ctsn { + rockchip,pins = <0x04 0x16 0x0a 0x1ab>; + phandle = <0x467>; + }; + + uart7m0-rtsn { + rockchip,pins = <0x04 0x12 0x0a 0x1ab>; + phandle = <0x468>; + }; + }; + + uart8 { + + uart8m0-xfer { + rockchip,pins = <0x04 0x09 0x0a 0x1b1 0x04 0x08 0x0a 0x1b1>; + phandle = <0x469>; + }; + + uart8m0-ctsn { + rockchip,pins = <0x04 0x0b 0x0a 0x1ab>; + phandle = <0x46a>; + }; + + uart8m0-rtsn { + rockchip,pins = <0x04 0x0a 0x0a 0x1ab>; + phandle = <0x46b>; + }; + + uart8m1-xfer { + rockchip,pins = <0x03 0x03 0x0a 0x1b1 0x03 0x02 0x0a 0x1b1>; + phandle = <0x17d>; + }; + + uart8m1-ctsn { + rockchip,pins = <0x03 0x05 0x0a 0x1ab>; + phandle = <0x46c>; + }; + + uart8m1-rtsn { + rockchip,pins = <0x03 0x04 0x0a 0x1ab>; + phandle = <0x46d>; + }; + + uart8-xfer { + rockchip,pins = <0x04 0x09 0x0a 0x1b1>; + phandle = <0x46e>; + }; + }; + + uart9 { + + uart9m1-xfer { + rockchip,pins = <0x04 0x0d 0x0a 0x1b1 0x04 0x0c 0x0a 0x1b1>; + phandle = <0x46f>; + }; + + uart9m1-ctsn { + rockchip,pins = <0x04 0x01 0x0a 0x1ab>; + phandle = <0x470>; + }; + + uart9m1-rtsn { + rockchip,pins = <0x04 0x00 0x0a 0x1ab>; + phandle = <0x471>; + }; + + uart9m2-xfer { + rockchip,pins = <0x03 0x1c 0x0a 0x1b1 0x03 0x1d 0x0a 0x1b1>; + phandle = <0x472>; + }; + + uart9m2-ctsn { + rockchip,pins = <0x03 0x1b 0x0a 0x1ab>; + phandle = <0x473>; + }; + + uart9m2-rtsn { + rockchip,pins = <0x03 0x1a 0x0a 0x1ab>; + phandle = <0x474>; + }; + + uart9m0-xfer { + rockchip,pins = <0x02 0x14 0x0a 0x1b1 0x02 0x12 0x0a 0x1b1>; + phandle = <0x17e>; + }; + + uart9m0-ctsn { + rockchip,pins = <0x04 0x15 0x0a 0x1ab>; + phandle = <0x17f>; + }; + + uart9m0-rtsn { + rockchip,pins = <0x04 0x14 0x0a 0x1ab>; + phandle = <0x203>; + }; + }; + + vop { + + vop-pins { + rockchip,pins = <0x01 0x02 0x01 0x1ab>; + phandle = <0x475>; + }; + }; + + bt656 { + + bt656-pins { + rockchip,pins = <0x04 0x08 0x02 0x1b4 0x04 0x00 0x02 0x1b4 0x04 0x01 0x02 0x1b4 0x04 0x02 0x02 0x1b4 0x04 0x03 0x02 0x1b4 0x04 0x04 0x02 0x1b4 0x04 0x05 0x02 0x1b4 0x04 0x06 0x02 0x1b4 0x04 0x07 0x02 0x1b4>; + phandle = <0x476>; + }; + }; + + gpio-func { + + tsadc-gpio-func { + rockchip,pins = <0x00 0x01 0x00 0x1ab>; + phandle = <0x18c>; + }; + }; + + pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <0x07>; + phandle = <0x477>; + }; + + pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <0x08>; + phandle = <0x478>; + }; + + pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <0x09>; + phandle = <0x479>; + }; + + pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <0x0a>; + phandle = <0x47a>; + }; + + pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <0x0b>; + phandle = <0x47b>; + }; + + pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <0x0c>; + phandle = <0x47c>; + }; + + pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <0x0d>; + phandle = <0x47d>; + }; + + pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <0x0e>; + phandle = <0x47e>; + }; + + pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <0x0f>; + phandle = <0x47f>; + }; + + pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <0x07>; + phandle = <0x480>; + }; + + pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <0x08>; + phandle = <0x481>; + }; + + pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <0x09>; + phandle = <0x482>; + }; + + pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <0x0a>; + phandle = <0x483>; + }; + + pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <0x0b>; + phandle = <0x484>; + }; + + pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <0x0c>; + phandle = <0x485>; + }; + + pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <0x0d>; + phandle = <0x486>; + }; + + pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <0x0e>; + phandle = <0x487>; + }; + + pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <0x0f>; + phandle = <0x488>; + }; + + pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <0x07>; + phandle = <0x489>; + }; + + pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <0x08>; + phandle = <0x48a>; + }; + + pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <0x09>; + phandle = <0x48b>; + }; + + pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <0x0a>; + phandle = <0x48c>; + }; + + pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <0x0b>; + phandle = <0x48d>; + }; + + pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <0x0c>; + phandle = <0x48e>; + }; + + pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <0x0d>; + phandle = <0x48f>; + }; + + pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <0x0e>; + phandle = <0x490>; + }; + + pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <0x0f>; + phandle = <0x491>; + }; + + eth0 { + + eth0-pins { + rockchip,pins = <0x02 0x13 0x01 0x1ab>; + phandle = <0x492>; + }; + }; + + gmac0 { + + gmac0-miim { + rockchip,pins = <0x04 0x14 0x01 0x1ab 0x04 0x15 0x01 0x1ab>; + phandle = <0x493>; + }; + + gmac0-clkinout { + rockchip,pins = <0x04 0x13 0x01 0x1ab>; + phandle = <0x494>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x02 0x11 0x01 0x1ab 0x02 0x12 0x01 0x1ab 0x04 0x12 0x01 0x1ab>; + phandle = <0x495>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x02 0x0e 0x01 0x1ab 0x02 0x0f 0x01 0x1ab 0x02 0x10 0x01 0x1ab>; + phandle = <0x496>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x02 0x08 0x01 0x1ab 0x02 0x0b 0x01 0x1ab>; + phandle = <0x497>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x02 0x06 0x01 0x1ab 0x02 0x07 0x01 0x1ab 0x02 0x09 0x01 0x1ab 0x02 0x0a 0x01 0x1ab>; + phandle = <0x498>; + }; + + gmac0-ppsclk { + rockchip,pins = <0x02 0x14 0x01 0x1ab>; + phandle = <0x499>; + }; + + gmac0-ppstring { + rockchip,pins = <0x02 0x0d 0x01 0x1ab>; + phandle = <0x49a>; + }; + + gmac0-ptp-refclk { + rockchip,pins = <0x02 0x0c 0x01 0x1ab>; + phandle = <0x49b>; + }; + + gmac0-txer { + rockchip,pins = <0x04 0x16 0x01 0x1ab>; + phandle = <0x49c>; + }; + }; + + cam { + + mipicsi0-pwr { + rockchip,pins = <0x01 0x1a 0x00 0x1ab>; + phandle = <0x1ff>; + }; + + mipicsi1-pwr { + rockchip,pins = <0x01 0x1b 0x00 0x1ab>; + phandle = <0x200>; + }; + + mipidcphy0-pwr { + rockchip,pins = <0x02 0x14 0x00 0x1ab>; + phandle = <0x49d>; + }; + + mipidphy0-pwr { + rockchip,pins = <0x01 0x0a 0x00 0x1ab>; + phandle = <0x201>; + }; + }; + + headphone { + + hp-det { + rockchip,pins = <0x01 0x14 0x00 0x1ab>; + phandle = <0x1f2>; + }; + }; + + hym8563 { + + hym8563-int { + rockchip,pins = <0x00 0x08 0x00 0x1b1>; + phandle = <0x195>; + }; + }; + + lcd { + + lcd-rst-gpio { + rockchip,pins = <0x00 0x1b 0x00 0x1ab>; + phandle = <0xfb>; + }; + }; + + leds { + + work-leds-gpio { + rockchip,pins = <0x01 0x16 0x00 0x1b5>; + phandle = <0x1e9>; + }; + }; + + sdio-pwrseq { + + wifi-enable-h { + rockchip,pins = <0x00 0x14 0x00 0x1b1>; + phandle = <0x1fa>; + }; + }; + + touch { + + touch-gpio { + rockchip,pins = <0x03 0x11 0x00 0x1b5 0x03 0x10 0x00 0x1b1>; + phandle = <0x15f>; + }; + + ts_int_active { + rockchip,pins = <0x03 0x10 0x00 0x1b1>; + phandle = <0x160>; + }; + + ts_reset_active { + rockchip,pins = <0x03 0x11 0x00 0x1b1>; + phandle = <0x161>; + }; + + ts_int_suspend { + rockchip,pins = <0x03 0x10 0x00 0x1b5>; + phandle = <0x162>; + }; + + ts_reset_suspend { + rockchip,pins = <0x03 0x11 0x00 0x1b5>; + phandle = <0x163>; + }; + }; + + usb { + + vcc5v0-host-en { + rockchip,pins = <0x04 0x08 0x00 0x1ab>; + phandle = <0x1fe>; + }; + }; + + usb-typec { + + usbc0-int { + rockchip,pins = <0x03 0x0e 0x00 0x1b1>; + phandle = <0x190>; + }; + + typec5v-pwren { + rockchip,pins = <0x03 0x06 0x00 0x1ab>; + phandle = <0x1fc>; + }; + }; + + wireless-bluetooth { + + uart9-gpios { + rockchip,pins = <0x04 0x14 0x00 0x1ab>; + phandle = <0x207>; + }; + + bt-reset-gpio { + rockchip,pins = <0x00 0x16 0x00 0x1ab>; + phandle = <0x204>; + }; + + bt-wake-gpio { + rockchip,pins = <0x00 0x15 0x00 0x1ab>; + phandle = <0x205>; + }; + + bt-irq-gpio { + rockchip,pins = <0x00 0x00 0x00 0x1ab>; + phandle = <0x206>; + }; + }; + + wireless-wlan { + + wifi-host-wake-irq { + rockchip,pins = <0x00 0x0a 0x00 0x1b5>; + phandle = <0x208>; + }; + }; + + pcie { + + pcie20x1-0-clkreqn-m1 { + rockchip,pins = <0x04 0x0c 0x00 0x1b6>; + phandle = <0x1cd>; + }; + }; + }; + + usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x1a6 0x02 0x1a5 0x02 0x1a4>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x49e>; + + usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfc400000 0x00 0x400000>; + interrupts = <0x00 0xdd 0x04>; + power-domains = <0x06 0x1f>; + resets = <0x02 0x2a7>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <0x1b7 0x1b8>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + phandle = <0x49f>; + }; + }; + + syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf\0syscon"; + reg = <0x00 0xfd5b8000 0x00 0x10000>; + phandle = <0x1da>; + }; + + syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5c0000 0x00 0x100>; + phandle = <0x1d9>; + }; + + syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x00 0xfd5cc000 0x00 0x4000>; + phandle = <0x1d7>; + }; + + syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d4000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x1d6>; + + usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <0x00 0x18a 0x04>; + resets = <0x02 0xc0048 0x02 0x489>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0x00>; + rockchip,usbctrl-grf = <0x75>; + status = "okay"; + phandle = <0x1d8>; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x1b7>; + }; + }; + }; + + syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x00 0xfd5e4000 0x00 0x100>; + phandle = <0x1d5>; + }; + + spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfddb8000 0x00 0x1000>; + interrupts = <0x00 0xc6 0x04>; + dmas = <0xf4 0x16>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x20f 0x02 0x20a>; + assigned-clocks = <0x02 0x20b>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1e7>; + }; + + i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddc8000 0x00 0x1000>; + interrupts = <0x00 0xbc 0x04>; + clocks = <0x02 0x201 0x02 0x1fe>; + clock-names = "mclk_tx\0hclk"; + assigned-clocks = <0x02 0x1ff>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x16>; + dma-names = "tx"; + power-domains = <0x06 0x19>; + resets = <0x02 0x391>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a0>; + }; + + spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfdde8000 0x00 0x1000>; + interrupts = <0x00 0xc5 0x04>; + dmas = <0xf4 0x08>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x25c 0x02 0x258>; + assigned-clocks = <0x02 0x259>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x1a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a1>; + }; + + i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf4000 0x00 0x1000>; + interrupts = <0x00 0xba 0x04>; + clocks = <0x02 0x24c 0x02 0x24c 0x02 0x252>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x249>; + assigned-clock-parents = <0x02 0x07>; + dmas = <0xf5 0x04>; + dma-names = "tx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3ef>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1e1>; + }; + + i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf8000 0x00 0x1000>; + interrupts = <0x00 0xbb 0x04>; + clocks = <0x02 0x23c 0x02 0x23c 0x02 0x238>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x239>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x15>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3c3>; + reset-names = "rx-m"; + rockchip,capture-only; + rockchip,i2s-rx-wait-time-ms = <0x32>; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1f5>; + }; + + i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfde00000 0x00 0x1000>; + interrupts = <0x00 0xbe 0x04>; + clocks = <0x02 0x237 0x02 0x237 0x02 0x233>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x234>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x18>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x417>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a2>; + }; + + spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde10000 0x00 0x1000>; + interrupts = <0x00 0xc8 0x04>; + clocks = <0x02 0x260 0x02 0x25f>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x260>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x16>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3ff>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a3>; + }; + + spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde18000 0x00 0x1000>; + interrupts = <0x00 0xc9 0x04>; + clocks = <0x02 0x262 0x02 0x261>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x262>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x17>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x401>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a4>; + }; + + dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x00 0xfde60000 0x00 0x4000>; + interrupts = <0x00 0xa2 0x04>; + clocks = <0x02 0x1e7 0x02 0x2cd 0x02 0x201 0x02 0x20d 0x04 0x02 0x1eb>; + clock-names = "apb\0aux\0i2s\0spdif\0hclk\0hdcp"; + assigned-clocks = <0x02 0x2cd>; + assigned-clock-rates = <0xf42400>; + resets = <0x02 0x389>; + phys = <0x1b9>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x01>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x1ba>; + phandle = <0x1e8>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1bb>; + status = "disabled"; + phandle = <0xe0>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3f>; + status = "disabled"; + phandle = <0xe6>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1bc>; + status = "okay"; + phandle = <0xee>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x4a5>; + }; + }; + }; + }; + + hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfdea0000 0x00 0x10000 0x00 0xfdeb0000 0x00 0x10000>; + interrupts = <0x00 0xad 0x04 0x00 0xae 0x04 0x00 0xaf 0x04 0x00 0xb0 0x04 0x00 0x169 0x04>; + clocks = <0x02 0x224 0x02 0x266 0x02 0x225 0x02 0x226 0x02 0x24c 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x37>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x02 0x3d7 0x02 0x49d>; + reset-names = "ref\0hdp"; + power-domains = <0x06 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0x1bd 0x1be 0x1bf 0x1c0>; + reg-io-width = <0x04>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + phys = <0x37>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "disabled"; + enable-gpios = <0x10a 0x0a 0x00>; + phandle = <0x1e4>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x4a6>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1c1>; + status = "disabled"; + phandle = <0xe2>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x40>; + status = "okay"; + phandle = <0xe8>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1c2>; + status = "disabled"; + phandle = <0xf0>; + }; + }; + }; + }; + + edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x00 0xfded0000 0x00 0x1000>; + interrupts = <0x00 0xa4 0x04>; + clocks = <0x02 0x214 0x02 0x213 0x02 0x215 0x05>; + clock-names = "dp\0pclk\0spdif\0hclk"; + resets = <0x02 0x3e4 0x02 0x3e3>; + reset-names = "dp\0apb"; + phys = <0x1c3>; + phy-names = "dp"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xdb>; + #sound-dai-cells = <0x01>; + status = "disabled"; + phandle = <0x1e2>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1c4>; + status = "disabled"; + phandle = <0xe1>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x1c5>; + status = "disabled"; + phandle = <0xe7>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1c6>; + status = "disabled"; + phandle = <0xef>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x4a7>; + }; + }; + }; + }; + + hdmirx-controller@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler\0rockchip,hdmirx-ctrler"; + reg = <0x00 0xfdee0000 0x00 0x6000>; + reg-names = "hdmirx_regs"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + interrupts = <0x00 0xb1 0x04 0x00 0x1b4 0x04 0x00 0xb3 0x04>; + interrupt-names = "cec\0hdmi\0dma"; + clocks = <0x02 0x21a 0x02 0x21f 0x02 0x2b2 0x02 0x21b 0x02 0x21c 0x02 0x232 0x05>; + clock-names = "aclk\0audio\0cr_para\0pclk\0ref\0hclk_s_hdmirx\0hclk_vo1"; + resets = <0x02 0x3d9 0x02 0x3da 0x02 0x3db 0x02 0x3b7>; + reset-names = "rst_a\0rst_p\0rst_ref\0rst_biu"; + pinctrl-0 = <0x1c7 0x1c8>; + pinctrl-names = "default"; + status = "okay"; + #sound-dai-cells = <0x01>; + hpd-trigger-level = <0x01>; + hdmirx-det-gpios = <0x129 0x1d 0x01>; + phandle = <0x1f4>; + }; + + pcie@fe150000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x00 0x0f>; + clocks = <0x02 0x14e 0x02 0x153 0x02 0x149 0x02 0x158 0x02 0x15e 0x02 0x183>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0x107 0x04 0x00 0x106 0x04 0x00 0x105 0x04 0x00 0x104 0x04 0x00 0x103 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1c9 0x00 0x00 0x00 0x00 0x02 0x1c9 0x01 0x00 0x00 0x00 0x03 0x1c9 0x02 0x00 0x00 0x00 0x04 0x1c9 0x03>; + linux,pci-domain = <0x00>; + num-ib-windows = <0x10>; + num-ob-windows = <0x10>; + num-viewport = <0x08>; + max-link-speed = <0x03>; + msi-map = <0x00 0x1ca 0x00 0x1000>; + num-lanes = <0x04>; + phys = <0x1cb>; + phy-names = "pcie-phy"; + power-domains = <0x06 0x22>; + ranges = <0x81000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x82000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0xe00000 0xc3000000 0x09 0x00 0x09 0x00 0x00 0x40000000>; + reg = <0x00 0xfe150000 0x00 0x10000 0x0a 0x40000000 0x00 0x400000 0x00 0xf0000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20d 0x02 0x21c>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "okay"; + reset-gpios = <0x10a 0x0e 0x00>; + vpcie3v3-supply = <0x1cc>; + pinctrl-names = "default"; + pinctrl-0 = <0x1cd>; + phandle = <0x4a8>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x104 0x01>; + phandle = <0x1c9>; + }; + }; + + pcie@fe160000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x10 0x1f>; + clocks = <0x02 0x14f 0x02 0x154 0x02 0x14a 0x02 0x159 0x02 0x15f 0x02 0x184>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0x102 0x04 0x00 0x101 0x04 0x00 0x100 0x04 0x00 0xff 0x04 0x00 0xfe 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1ce 0x00 0x00 0x00 0x00 0x02 0x1ce 0x01 0x00 0x00 0x00 0x03 0x1ce 0x02 0x00 0x00 0x00 0x04 0x1ce 0x03>; + linux,pci-domain = <0x01>; + num-ib-windows = <0x10>; + num-ob-windows = <0x10>; + num-viewport = <0x08>; + max-link-speed = <0x03>; + msi-map = <0x1000 0x1ca 0x1000 0x1000>; + num-lanes = <0x02>; + phys = <0x1cb>; + phy-names = "pcie-phy"; + power-domains = <0x06 0x22>; + ranges = <0x81000000 0x00 0xf1100000 0x00 0xf1100000 0x00 0x100000 0x82000000 0x00 0xf1200000 0x00 0xf1200000 0x00 0xe00000 0xc3000000 0x09 0x40000000 0x09 0x40000000 0x00 0x40000000>; + reg = <0x00 0xfe160000 0x00 0x10000 0x0a 0x40400000 0x00 0x400000 0x00 0xf1000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20e 0x02 0x21d>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x4a9>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xff 0x01>; + phandle = <0x1ce>; + }; + }; + + pcie@fe170000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x20 0x2f>; + clocks = <0x02 0x150 0x02 0x155 0x02 0x14b 0x02 0x15b 0x02 0x160 0x02 0x2c4>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xf3 0x04 0x00 0xf2 0x04 0x00 0xf1 0x04 0x00 0xf0 0x04 0x00 0xef 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1cf 0x00 0x00 0x00 0x00 0x02 0x1cf 0x01 0x00 0x00 0x00 0x03 0x1cf 0x02 0x00 0x00 0x00 0x04 0x1cf 0x03>; + linux,pci-domain = <0x02>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x2000 0x112 0x2000 0x1000>; + num-lanes = <0x01>; + phys = <0x1d0 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf2100000 0x00 0xf2100000 0x00 0x100000 0x82000000 0x00 0xf2200000 0x00 0xf2200000 0x00 0xe00000 0xc3000000 0x09 0x80000000 0x09 0x80000000 0x00 0x40000000>; + reg = <0x00 0xfe170000 0x00 0x10000 0x0a 0x40800000 0x00 0x400000 0x00 0xf2000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20f 0x02 0x21e>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "okay"; + reset-gpios = <0x129 0x0c 0x00>; + phandle = <0x4aa>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xf0 0x01>; + phandle = <0x1cf>; + }; + }; + + uio@fe1b0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe1b0000 0x00 0x10000>; + rockchip,ethernet = <0x1d1>; + status = "disabled"; + phandle = <0x4ab>; + }; + + ethernet@fe1b0000 { + local-mac-address = [42 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe1b0000 0x00 0x10000>; + interrupts = <0x00 0xe3 0x04 0x00 0xe2 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xc9>; + rockchip,php_grf = <0x77>; + clocks = <0x02 0x144 0x02 0x145 0x02 0x167 0x02 0x16c 0x02 0x142>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x02 0x20a>; + reset-names = "stmmaceth"; + power-domains = <0x06 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x1d2>; + snps,mtl-rx-config = <0x1d3>; + snps,mtl-tx-config = <0x1d4>; + status = "disabled"; + phandle = <0x1d1>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x4ac>; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + snps,rd_osr_lmt = <0x08>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + phandle = <0x1d2>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x1d3>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x1d4>; + + queue0 { + }; + }; + }; + + sata@fe220000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe220000 0x00 0x1000>; + clocks = <0x02 0x172 0x02 0x16f 0x02 0x175 0x02 0x164 0x02 0x17f>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x112 0x04>; + interrupt-names = "hostc"; + phys = <0x1d0 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "disabled"; + phandle = <0x4ad>; + }; + + phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x00 0xfed70000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x268>; + clock-names = "ref\0apb"; + resets = <0x02 0x486 0x02 0xc003f 0x02 0xc0040 0x02 0xc0041>; + reset-names = "apb\0init\0cmn\0lane"; + rockchip,grf = <0x1d5>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x1c3>; + }; + + hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed70000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x268>; + clock-names = "ref\0apb"; + clock-output-names = "clk_hdmiphy_pixel1"; + #clock-cells = <0x00>; + resets = <0x02 0x491 0x02 0x486 0x02 0xc003f 0x02 0xc0040 0x02 0xc0041 0x02 0x48f 0x02 0x490>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x1d5>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x37>; + }; + + phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x00 0xfed90000 0x00 0x10000>; + rockchip,u2phy-grf = <0x1d6>; + rockchip,usb-grf = <0x75>; + rockchip,usbdpphy-grf = <0x1d7>; + rockchip,vo-grf = <0x102>; + clocks = <0x02 0x2b6 0x02 0x280 0x02 0x26a 0x1d8>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x02 0x2f 0x02 0x30 0x02 0x31 0x02 0x32 0x02 0x484>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + rockchip,dp-lane-mux = <0x00 0x01 0x02 0x03>; + phandle = <0x4ae>; + + dp-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x1b9>; + }; + + u3-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x1b8>; + }; + }; + + phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee10000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2be 0x02 0x186 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2be>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20006 0x02 0x4d7>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1d9>; + rockchip,pcie1ln-sel-bits = <0x100 0x00 0x00 0x00>; + status = "okay"; + phandle = <0x1d0>; + }; + + phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x00 0xfee80000 0x00 0x20000>; + #phy-cells = <0x00>; + clocks = <0x02 0x188 0x02 0x166>; + clock-names = "pclk\0phpclk"; + resets = <0x02 0x2000a>; + reset-names = "phy"; + rockchip,pipe-grf = <0x77>; + rockchip,phy-grf = <0x1da>; + status = "okay"; + rockchip,pcie30-phymode = <0x04>; + phandle = <0x1cb>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <0x1db 0x01>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + phandle = <0x4af>; + + vol-up-key { + label = "volume up"; + linux,code = <0x73>; + press-threshold-microvolt = <0x4268>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <0x72>; + press-threshold-microvolt = <0x65ce8>; + }; + + menu-key { + label = "menu"; + linux,code = <0x8b>; + press-threshold-microvolt = <0xd9490>; + }; + + back-key { + label = "back"; + linux,code = <0x9e>; + press-threshold-microvolt = <0x12d838>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + pwms = <0x1dc 0x00 0x61a8 0x00>; + status = "okay"; + phandle = <0xf8>; + }; + + bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0x01>; + phandle = <0x1de>; + }; + + bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,name = "rockchip,bt"; + phandle = <0x4b0>; + + simple-audio-card,cpu { + sound-dai = <0x1dd>; + }; + + simple-audio-card,codec { + sound-dai = <0x1de 0x01>; + }; + }; + + edp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-edp0"; + rockchip,cpu = <0x1df>; + rockchip,codec = <0x1e0 0x00>; + phandle = <0x4b1>; + }; + + edp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-edp1"; + rockchip,cpu = <0x1e1>; + rockchip,codec = <0x1e2 0x00>; + phandle = <0x4b2>; + }; + + hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <0x1df>; + rockchip,codec = <0x1e3>; + rockchip,jack-det; + phandle = <0x4b3>; + }; + + hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <0x1e1>; + rockchip,codec = <0x1e4>; + rockchip,jack-det; + phandle = <0x4b4>; + }; + + dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <0x200>; + rockchip,cpu = <0x1e5>; + rockchip,codec = <0x1e6 0x01>; + rockchip,jack-det; + phandle = <0x4b5>; + }; + + dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp1"; + rockchip,mclk-fs = <0x200>; + rockchip,cpu = <0x1e7>; + rockchip,codec = <0x1e8 0x01>; + rockchip,jack-det; + phandle = <0x4b6>; + }; + + leds { + compatible = "gpio-leds"; + phandle = <0x4b7>; + + work { + gpios = <0x129 0x16 0x00>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <0x1e9>; + phandle = <0x4b8>; + }; + }; + + spdif-tx0-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00>; + phandle = <0x1eb>; + }; + + spdif-tx0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x80>; + simple-audio-card,name = "rockchip,spdif-tx0"; + phandle = <0x4b9>; + + simple-audio-card,cpu { + sound-dai = <0x1ea>; + }; + + simple-audio-card,codec { + sound-dai = <0x1eb>; + }; + }; + + spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00>; + phandle = <0x1ed>; + }; + + spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x80>; + simple-audio-card,name = "rockchip,spdif-tx1"; + phandle = <0x4ba>; + + simple-audio-card,cpu { + sound-dai = <0x1ec>; + }; + + simple-audio-card,codec { + sound-dai = <0x1ed>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b00>; + regulator-max-microvolt = <0xb71b00>; + phandle = <0x1ee>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ee>; + phandle = <0x79>; + }; + + vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ee>; + phandle = <0x1ef>; + }; + + vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ef>; + phandle = <0x1fb>; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x00 0x10000000 0x00 0x10000000>; + linux,cma-default; + size = <0x00 0x800000>; + }; + + drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x00 0xede00000 0x00 0x2e0000>; + phandle = <0x38>; + status = "disabled"; + }; + + drm-cubic-lut@0 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x4bb>; + status = "disabled"; + }; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x00 0x110000 0x00 0xe0000>; + boot-log-size = <0x8000>; + boot-log-count = <0x01>; + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00>; + record-size = <0x14000>; + phandle = <0x4bc>; + }; + + minidump-smem@1f0000 { + reg = <0x00 0x1f0000 0x00 0x100>; + no-map; + status = "disabled"; + phandle = <0x20a>; + }; + + minidump-mem@c000000 { + reg = <0x00 0xc000000 0x00 0x2000000>; + no-map; + status = "disabled"; + phandle = <0x20b>; + }; + }; + + es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <0x129 0x14 0x01>; + io-channels = <0x1db 0x03>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + spk-con-gpio = <0x10a 0x02 0x00>; + hp-con-gpio = <0x10a 0x07 0x00>; + rockchip,pre-power-on-delay-ms = <0x1e>; + rockchip,post-power-down-delay-ms = <0x28>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <0x100>; + rockchip,cpu = <0x1f0>; + rockchip,codec = <0x1f1>; + rockchip,audio-routing = "Headphone\0LOUT1\0Headphone\0ROUT1\0Speaker\0LOUT2\0Speaker\0ROUT2\0Headphone\0Headphone Power\0Headphone\0Headphone Power\0Speaker\0Speaker Power\0Speaker\0Speaker Power\0LINPUT1\0Main Mic\0LINPUT2\0Main Mic\0RINPUT1\0Headset Mic\0RINPUT2\0Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <0x1f2>; + phandle = <0x4bd>; + + play-pause-key { + label = "playpause"; + linux,code = <0xa4>; + press-threshold-microvolt = <0x7d0>; + }; + }; + + pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <0x02>; + pwms = <0x1f3 0x00 0xc350 0x00>; + cooling-levels = <0x00 0x32 0x64 0x96 0xc8 0xff>; + rockchip,temp-trips = <0xc350 0x01 0xd6d8 0x02 0xea60 0x03 0xfde8 0x04 0x11170 0x05>; + phandle = <0x4be>; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <0x1f4>; + rockchip,frame-master = <0x1f4>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <0x1f5>; + rockchip,codec = <0x1f4 0x00>; + rockchip,jack-det; + }; + + pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + vin-supply = <0x1f6>; + phandle = <0x4bf>; + }; + + pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + vin-supply = <0x1f7>; + phandle = <0x4c0>; + }; + + pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + vin-supply = <0x1f8>; + phandle = <0x4c1>; + }; + + pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + vin-supply = <0x1f7>; + phandle = <0x4c2>; + }; + + sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <0x1f9>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <0x1fa>; + post-power-on-delay-ms = <0xc8>; + reset-gpios = <0xfa 0x14 0x01>; + phandle = <0x127>; + }; + + rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <0x129 0x1d 0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0x1f2>; + io-channels = <0x1db 0x03>; + phandle = <0x4c3>; + }; + + vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x10c8e0>; + regulator-max-microvolt = <0x10c8e0>; + vin-supply = <0x79>; + phandle = <0x172>; + }; + + vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0x119 0x06 0x00>; + vin-supply = <0x1fb>; + pinctrl-names = "default"; + pinctrl-0 = <0x1fc>; + phandle = <0x191>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <0x1fd 0x11 0x00>; + vin-supply = <0x18e>; + phandle = <0xf9>; + }; + + vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + enable-active-high; + gpios = <0x1fd 0x15 0x00>; + startup-delay-us = <0x1388>; + vin-supply = <0x1ee>; + phandle = <0x1cc>; + }; + + vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0x10a 0x08 0x00>; + vin-supply = <0x1fb>; + pinctrl-names = "default"; + pinctrl-0 = <0x1fe>; + phandle = <0x76>; + }; + + vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x1a 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x1ff>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + phandle = <0x4c4>; + }; + + vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x1b 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x200>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + phandle = <0x4c5>; + }; + + vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x0a 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x201>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + phandle = <0x15b>; + }; + + vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <0xfa 0x0f 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x202>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + phandle = <0x125>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <0x1f9>; + clock-names = "ext_clock"; + uart_rts_gpios = <0x10a 0x14 0x01>; + pinctrl-names = "default\0rts_gpio"; + pinctrl-0 = <0x203 0x204 0x205 0x206>; + pinctrl-1 = <0x207>; + BT,reset_gpio = <0xfa 0x16 0x00>; + BT,wake_gpio = <0xfa 0x15 0x00>; + BT,wake_host_irq = <0xfa 0x00 0x00>; + status = "okay"; + phandle = <0x4c6>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <0x208>; + WIFI,host_wake_irq = <0xfa 0x0a 0x00>; + WIFI,poweren_gpio = <0xfa 0x14 0x00>; + status = "okay"; + phandle = <0x4c7>; + }; + + chosen { + bootargs = "storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal dsi-0=1 androidboot.verifiedbootstate=orange ro rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 rcupdate.rcu_expedited=1 rcu_nocbs=all net.ifnames=0 fastboot=n comm-04/19/2026 androidboot.fwver=ddr-v1.19-ff1a08bde6,spl-v1.13,bl31-v1.51,bl32-v1.20,uboot--boot rockchip_pm_domains.always_on=1"; + phandle = <0x4c8>; + }; + + cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>; + phandle = <0x4c9>; + }; + + debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>; + phandle = <0x4ca>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x00 0x1a7 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x209>; + status = "okay"; + phandle = <0x4cb>; + }; + + minidump { + compatible = "rockchip,minidump"; + smem-region = <0x20a>; + minidump-region = <0x20b>; + status = "disabled"; + phandle = <0x4cc>; + }; + + __symbols__ { + spll = "/clocks/spll"; + xin32k = "/clocks/xin32k"; + xin24m = "/clocks/xin24m"; + hclk_vo1 = "/clocks/hclk_vo1@fd7c08ec"; + aclk_vdpu_low_pre = "/clocks/aclk_vdpu_low_pre@fd7c08b0"; + hclk_vo0 = "/clocks/hclk_vo0@fd7c08dc"; + hclk_usb = "/clocks/hclk_usb@fd7c08a8"; + hclk_nvm = "/clocks/hclk_nvm@fd7c087c"; + aclk_usb = "/clocks/aclk_usb@fd7c08a8"; + hclk_isp1_pre = "/clocks/hclk_isp1_pre@fd7c0868"; + aclk_isp1_pre = "/clocks/aclk_isp1_pre@fd7c0868"; + aclk_rkvdec0_pre = "/clocks/aclk_rkvdec0_pre@fd7c08a0"; + hclk_rkvdec0_pre = "/clocks/hclk_rkvdec0_pre@fd7c08a0"; + aclk_rkvdec1_pre = "/clocks/aclk_rkvdec1_pre@fd7c08a4"; + hclk_rkvdec1_pre = "/clocks/hclk_rkvdec1_pre@fd7c08a4"; + aclk_jpeg_decoder_pre = "/clocks/aclk_jpeg_decoder_pre@fd7c08b0"; + aclk_rkvenc1_pre = "/clocks/aclk_rkvenc1_pre@fd7c08c0"; + hclk_rkvenc1_pre = "/clocks/hclk_rkvenc1_pre@fd7c08c0"; + aclk_hdcp0_pre = "/clocks/aclk_hdcp0_pre@fd7c08dc"; + aclk_hdcp1_pre = "/clocks/aclk_hdcp1_pre@fd7c08ec"; + pclk_av1_pre = "/clocks/pclk_av1_pre@fd7c0910"; + aclk_av1_pre = "/clocks/aclk_av1_pre@fd7c0910"; + hclk_sdio_pre = "/clocks/hclk_sdio_pre@fd7c092c"; + pclk_vo0_grf = "/clocks/pclk_vo0_grf@fd7c08dc"; + pclk_vo1_grf = "/clocks/pclk_vo1_grf@fd7c08ec"; + mclkin_i2s0 = "/clocks/mclkin-i2s0"; + mclkin_i2s1 = "/clocks/mclkin-i2s1"; + mclkin_i2s2 = "/clocks/mclkin-i2s2"; + mclkin_i2s3 = "/clocks/mclkin-i2s3"; + mclkout_i2s0 = "/clocks/mclkout-i2s0@fd58c318"; + mclkout_i2s1 = "/clocks/mclkout-i2s1@fd58c318"; + mclkout_i2s1m1 = "/clocks/mclkout-i2s1@fd58a000"; + mclkout_i2s2 = "/clocks/mclkout-i2s2@fd58c318"; + mclkout_i2s3 = "/clocks/mclkout-i2s3@fd58c318"; + cpu_l0 = "/cpus/cpu@0"; + cpu_l1 = "/cpus/cpu@100"; + cpu_l2 = "/cpus/cpu@200"; + cpu_l3 = "/cpus/cpu@300"; + cpu_b0 = "/cpus/cpu@400"; + cpu_b1 = "/cpus/cpu@500"; + cpu_b2 = "/cpus/cpu@600"; + cpu_b3 = "/cpus/cpu@700"; + CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; + l2_cache_l0 = "/cpus/l2-cache-l0"; + l2_cache_l1 = "/cpus/l2-cache-l1"; + l2_cache_l2 = "/cpus/l2-cache-l2"; + l2_cache_l3 = "/cpus/l2-cache-l3"; + l2_cache_b0 = "/cpus/l2-cache-b0"; + l2_cache_b1 = "/cpus/l2-cache-b1"; + l2_cache_b2 = "/cpus/l2-cache-b2"; + l2_cache_b3 = "/cpus/l2-cache-b3"; + l3_cache = "/cpus/l3-cache"; + cluster0_opp_table = "/cluster0-opp-table"; + cluster1_opp_table = "/cluster1-opp-table"; + cluster2_opp_table = "/cluster2-opp-table"; + arm_pmu = "/arm-pmu"; + csi2_dcphy0 = "/csi2-dcphy0"; + csi2_dcphy1 = "/csi2-dcphy1"; + csi2_dphy0 = "/csi2-dphy0"; + mipidphy0_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1"; + csidphy0_out = "/csi2-dphy0/ports/port@1/endpoint@0"; + csi2_dphy1 = "/csi2-dphy1"; + csi2_dphy2 = "/csi2-dphy2"; + csi2_dphy3 = "/csi2-dphy3"; + csi2_dphy4 = "/csi2-dphy4"; + csi2_dphy5 = "/csi2-dphy5"; + display_subsystem = "/display-subsystem"; + route_dp0 = "/display-subsystem/route/route-dp0"; + route_dsi0 = "/display-subsystem/route/route-dsi0"; + route_dsi1 = "/display-subsystem/route/route-dsi1"; + route_edp0 = "/display-subsystem/route/route-edp0"; + route_edp1 = "/display-subsystem/route/route-edp1"; + route_hdmi0 = "/display-subsystem/route/route-hdmi0"; + route_rgb = "/display-subsystem/route/route-rgb"; + route_dp1 = "/display-subsystem/route/route-dp1"; + route_hdmi1 = "/display-subsystem/route/route-hdmi1"; + dmc = "/dmc"; + dmc_opp_table = "/dmc-opp-table"; + dmcdbg = "/dmcdbg"; + scmi = "/firmware/scmi"; + scmi_clk = "/firmware/scmi/protocol@14"; + scmi_reset = "/firmware/scmi/protocol@16"; + sdei = "/firmware/sdei"; + optee = "/firmware/optee"; + jpege_ccu = "/jpege-ccu"; + mipi_dcphy1 = "/mipi-dcphy-dummy"; + mipi_dcphy0 = "/mipi-dcphy-dummy"; + mipi0_csi2 = "/mipi0-csi2"; + mipi1_csi2 = "/mipi1-csi2"; + mipi2_csi2 = "/mipi2-csi2"; + mipi2_csi2_input = "/mipi2-csi2/ports/port@0/endpoint@1"; + mipi2_csi2_output = "/mipi2-csi2/ports/port@1/endpoint@0"; + mipi3_csi2 = "/mipi3-csi2"; + mipi4_csi2 = "/mipi4-csi2"; + mipi5_csi2 = "/mipi5-csi2"; + mpp_srv = "/mpp-srv"; + rkcif_dvp = "/rkcif-dvp"; + rkcif_dvp_sditf = "/rkcif-dvp-sditf"; + rkcif_mipi_lvds = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds_sditf = "/rkcif-mipi-lvds-sditf"; + rkcif_mipi_lvds_sditf_vir1 = "/rkcif-mipi-lvds-sditf-vir1"; + rkcif_mipi_lvds_sditf_vir2 = "/rkcif-mipi-lvds-sditf-vir2"; + rkcif_mipi_lvds_sditf_vir3 = "/rkcif-mipi-lvds-sditf-vir3"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds1_sditf = "/rkcif-mipi-lvds1-sditf"; + rkcif_mipi_lvds1_sditf_vir1 = "/rkcif-mipi-lvds1-sditf-vir1"; + rkcif_mipi_lvds1_sditf_vir2 = "/rkcif-mipi-lvds1-sditf-vir2"; + rkcif_mipi_lvds1_sditf_vir3 = "/rkcif-mipi-lvds1-sditf-vir3"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + cif_mipi2_in0 = "/rkcif-mipi-lvds2/port/endpoint"; + rkcif_mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf"; + mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf/port/endpoint"; + rkcif_mipi_lvds2_sditf_vir1 = "/rkcif-mipi-lvds2-sditf-vir1"; + rkcif_mipi_lvds2_sditf_vir2 = "/rkcif-mipi-lvds2-sditf-vir2"; + rkcif_mipi_lvds2_sditf_vir3 = "/rkcif-mipi-lvds2-sditf-vir3"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkcif_mipi_lvds3_sditf = "/rkcif-mipi-lvds3-sditf"; + rkcif_mipi_lvds3_sditf_vir1 = "/rkcif-mipi-lvds3-sditf-vir1"; + rkcif_mipi_lvds3_sditf_vir2 = "/rkcif-mipi-lvds3-sditf-vir2"; + rkcif_mipi_lvds3_sditf_vir3 = "/rkcif-mipi-lvds3-sditf-vir3"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds4_sditf = "/rkcif-mipi-lvds4-sditf"; + rkcif_mipi_lvds4_sditf_vir1 = "/rkcif-mipi-lvds4-sditf-vir1"; + rkcif_mipi_lvds4_sditf_vir2 = "/rkcif-mipi-lvds4-sditf-vir2"; + rkcif_mipi_lvds4_sditf_vir3 = "/rkcif-mipi-lvds4-sditf-vir3"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + rkcif_mipi_lvds5_sditf = "/rkcif-mipi-lvds5-sditf"; + rkcif_mipi_lvds5_sditf_vir1 = "/rkcif-mipi-lvds5-sditf-vir1"; + rkisp0_vir0 = "/rkisp0-vir0"; + isp0_vir0 = "/rkisp0-vir0/port/endpoint@0"; + rkisp0_vir1 = "/rkisp0-vir1"; + rkisp0_vir2 = "/rkisp0-vir2"; + rkisp0_vir3 = "/rkisp0-vir3"; + rkisp1_vir0 = "/rkisp1-vir0"; + rkisp1_vir1 = "/rkisp1-vir1"; + rkisp1_vir2 = "/rkisp1-vir2"; + rkisp1_vir3 = "/rkisp1-vir3"; + rkispp0_vir0 = "/rkispp0-vir0"; + rkispp1_vir0 = "/rkispp1-vir0"; + rkvenc_ccu = "/rkvenc-ccu"; + rkvtunnel = "/rkvtunnel"; + rockchip_suspend = "/rockchip-suspend"; + rockchip_system_monitor = "/rockchip-system-monitor"; + thermal_zones = "/thermal-zones"; + soc_thermal = "/thermal-zones/soc-thermal"; + threshold = "/thermal-zones/soc-thermal/trips/trip-point-0"; + target = "/thermal-zones/soc-thermal/trips/trip-point-1"; + soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit"; + bigcore0_thermal = "/thermal-zones/bigcore0-thermal"; + bigcore0_crit = "/thermal-zones/bigcore0-thermal/trips/bigcore0-crit"; + bigcore1_thermal = "/thermal-zones/bigcore1-thermal"; + bigcore1_crit = "/thermal-zones/bigcore1-thermal/trips/bigcore1-crit"; + little_core_thermal = "/thermal-zones/littlecore-thermal"; + litcore_crit = "/thermal-zones/littlecore-thermal/trips/litcore-crit"; + center_thermal = "/thermal-zones/center-thermal"; + center_crit = "/thermal-zones/center-thermal/trips/center-crit"; + gpu_thermal = "/thermal-zones/gpu-thermal"; + gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu-crit"; + npu_thermal = "/thermal-zones/npu-thermal"; + npu_crit = "/thermal-zones/npu-thermal/trips/npu-crit"; + scmi_shmem = "/sram@10f000/sram@0"; + gpu = "/gpu@fb000000"; + gpu_opp_table = "/gpu-opp-table"; + usbdrd3_0 = "/usbdrd3_0"; + usbdrd_dwc3_0 = "/usbdrd3_0/usb@fc000000"; + dwc3_0_role_switch = "/usbdrd3_0/usb@fc000000/port/endpoint@0"; + usb_host0_ehci = "/usb@fc800000"; + usb_host0_ohci = "/usb@fc840000"; + usb_host1_ehci = "/usb@fc880000"; + usb_host1_ohci = "/usb@fc8c0000"; + mmu600_pcie = "/iommu@fc900000"; + mmu600_php = "/iommu@fcb00000"; + usbhost3_0 = "/usbhost3_0"; + usbhost_dwc3_0 = "/usbhost3_0/usb@fcd00000"; + pmu0_grf = "/syscon@fd588000"; + reboot_mode = "/syscon@fd588000/reboot-mode"; + pmu1_grf = "/syscon@fd58a000"; + sys_grf = "/syscon@fd58c000"; + rgb = "/syscon@fd58c000/rgb"; + rgb_in_vp3 = "/syscon@fd58c000/rgb/ports/port@0/endpoint@2"; + bigcore0_grf = "/syscon@fd590000"; + bigcore1_grf = "/syscon@fd592000"; + litcore_grf = "/syscon@fd594000"; + dsu_grf = "/syscon@fd598000"; + gpu_grf = "/syscon@fd5a0000"; + npu_grf = "/syscon@fd5a2000"; + vop_grf = "/syscon@fd5a4000"; + vo0_grf = "/syscon@fd5a6000"; + vo1_grf = "/syscon@fd5a8000"; + usb_grf = "/syscon@fd5ac000"; + php_grf = "/syscon@fd5b0000"; + mipidphy0_grf = "/syscon@fd5b4000"; + mipidphy1_grf = "/syscon@fd5b5000"; + pipe_phy0_grf = "/syscon@fd5bc000"; + pipe_phy2_grf = "/syscon@fd5c4000"; + usbdpphy0_grf = "/syscon@fd5c8000"; + usb2phy0_grf = "/syscon@fd5d0000"; + u2phy0 = "/syscon@fd5d0000/usb2-phy@0"; + u2phy0_otg = "/syscon@fd5d0000/usb2-phy@0/otg-port"; + usb2phy2_grf = "/syscon@fd5d8000"; + u2phy2 = "/syscon@fd5d8000/usb2-phy@8000"; + u2phy2_host = "/syscon@fd5d8000/usb2-phy@8000/host-port"; + usb2phy3_grf = "/syscon@fd5dc000"; + u2phy3 = "/syscon@fd5dc000/usb2-phy@c000"; + u2phy3_host = "/syscon@fd5dc000/usb2-phy@c000/host-port"; + hdptxphy0_grf = "/syscon@fd5e0000"; + mipidcphy0_grf = "/syscon@fd5e8000"; + mipidcphy1_grf = "/syscon@fd5ec000"; + ioc = "/syscon@fd5f0000"; + cru = "/clock-controller@fd7c0000"; + i2c0 = "/i2c@fd880000"; + vdd_cpu_big0_s0 = "/i2c@fd880000/rk8602@42"; + vdd_cpu_big0_mem_s0 = "/i2c@fd880000/rk8602@42"; + vdd_cpu_big1_s0 = "/i2c@fd880000/rk8603@43"; + vdd_cpu_big1_mem_s0 = "/i2c@fd880000/rk8603@43"; + uart0 = "/serial@fd890000"; + pwm0 = "/pwm@fd8b0000"; + pwm1 = "/pwm@fd8b0010"; + pwm2 = "/pwm@fd8b0020"; + pwm3 = "/pwm@fd8b0030"; + pmu = "/power-management@fd8d8000"; + power = "/power-management@fd8d8000/power-controller"; + rknpu = "/npu@fdab0000"; + npu_opp_table = "/npu-opp-table"; + rknpu_mmu = "/iommu@fdab9000"; + vepu = "/vepu@fdb50000"; + vdpu = "/vdpu@fdb50400"; + vdpu_mmu = "/iommu@fdb50800"; + avsd = "/avsd-plus@fdb51000"; + rga3_core0 = "/rga@fdb60000"; + rga3_0_mmu = "/iommu@fdb60f00"; + rga3_core1 = "/rga@fdb70000"; + rga3_1_mmu = "/iommu@fdb70f00"; + rga2 = "/rga@fdb80000"; + jpegd = "/jpegd@fdb90000"; + jpegd_mmu = "/iommu@fdb90480"; + jpege0 = "/jpege-core@fdba0000"; + jpege0_mmu = "/iommu@fdba0800"; + jpege1 = "/jpege-core@fdba4000"; + jpege1_mmu = "/iommu@fdba4800"; + jpege2 = "/jpege-core@fdba8000"; + jpege2_mmu = "/iommu@fdba8800"; + jpege3 = "/jpege-core@fdbac000"; + jpege3_mmu = "/iommu@fdbac800"; + iep = "/iep@fdbb0000"; + iep_mmu = "/iommu@fdbb0800"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc0_mmu = "/iommu@fdbdf000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + rkvenc1_mmu = "/iommu@fdbef000"; + venc_opp_table = "/venc-opp-table"; + rkvdec_ccu = "/rkvdec-ccu@fdc30000"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec0_mmu = "/iommu@fdc38700"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvdec1_mmu = "/iommu@fdc48700"; + av1d = "/av1d@fdc70000"; + av1d_mmu = "/iommu@fdca0000"; + rkisp_unite = "/rkisp-unite@fdcb0000"; + rkisp0 = "/rkisp@fdcb0000"; + rkisp_unite_mmu = "/rkisp-unite-mmu@fdcb7f00"; + isp0_mmu = "/iommu@fdcb7f00"; + rkisp1 = "/rkisp@fdcc0000"; + isp1_mmu = "/iommu@fdcc7f00"; + rkispp0 = "/rkispp@fdcd0000"; + fec0_mmu = "/iommu@fdcd0f00"; + rkispp1 = "/rkispp@fdcd8000"; + fec1_mmu = "/iommu@fdcd8f00"; + rkcif = "/rkcif@fdce0000"; + rkcif_mmu = "/iommu@fdce0800"; + mipi0_csi2_hw = "/mipi0-csi2-hw@fdd10000"; + mipi1_csi2_hw = "/mipi1-csi2-hw@fdd20000"; + mipi2_csi2_hw = "/mipi2-csi2-hw@fdd30000"; + mipi3_csi2_hw = "/mipi3-csi2-hw@fdd40000"; + mipi4_csi2_hw = "/mipi4-csi2-hw@fdd50000"; + mipi5_csi2_hw = "/mipi5-csi2-hw@fdd60000"; + vop = "/vop@fdd90000"; + vop_out = "/vop@fdd90000/ports"; + vp0 = "/vop@fdd90000/ports/port@0"; + vp0_out_dp0 = "/vop@fdd90000/ports/port@0/endpoint@0"; + vp0_out_edp0 = "/vop@fdd90000/ports/port@0/endpoint@1"; + vp0_out_hdmi0 = "/vop@fdd90000/ports/port@0/endpoint@2"; + vp0_out_dp1 = "/vop@fdd90000/ports/port@0/endpoint@3"; + vp0_out_edp1 = "/vop@fdd90000/ports/port@0/endpoint@4"; + vp0_out_hdmi1 = "/vop@fdd90000/ports/port@0/endpoint@5"; + vp1 = "/vop@fdd90000/ports/port@1"; + vp1_out_dp0 = "/vop@fdd90000/ports/port@1/endpoint@0"; + vp1_out_edp0 = "/vop@fdd90000/ports/port@1/endpoint@1"; + vp1_out_hdmi0 = "/vop@fdd90000/ports/port@1/endpoint@2"; + vp1_out_dp1 = "/vop@fdd90000/ports/port@1/endpoint@3"; + vp1_out_edp1 = "/vop@fdd90000/ports/port@1/endpoint@4"; + vp1_out_hdmi1 = "/vop@fdd90000/ports/port@1/endpoint@5"; + vp2 = "/vop@fdd90000/ports/port@2"; + vp2_out_dp0 = "/vop@fdd90000/ports/port@2/endpoint@0"; + vp2_out_edp0 = "/vop@fdd90000/ports/port@2/endpoint@1"; + vp2_out_hdmi0 = "/vop@fdd90000/ports/port@2/endpoint@2"; + vp2_out_dsi0 = "/vop@fdd90000/ports/port@2/endpoint@3"; + vp2_out_dsi1 = "/vop@fdd90000/ports/port@2/endpoint@4"; + vp2_out_dp1 = "/vop@fdd90000/ports/port@2/endpoint@5"; + vp2_out_edp1 = "/vop@fdd90000/ports/port@2/endpoint@6"; + vp2_out_hdmi1 = "/vop@fdd90000/ports/port@2/endpoint@7"; + vp3 = "/vop@fdd90000/ports/port@3"; + vp3_out_dsi0 = "/vop@fdd90000/ports/port@3/endpoint@0"; + vp3_out_dsi1 = "/vop@fdd90000/ports/port@3/endpoint@1"; + vp3_out_rgb = "/vop@fdd90000/ports/port@3/endpoint@2"; + vop_opp_table = "/vop-opp-table"; + vop_mmu = "/iommu@fdd97e00"; + spdif_tx2 = "/spdif-tx@fddb0000"; + i2s4_8ch = "/i2s@fddc0000"; + spdif_tx3 = "/spdif-tx@fdde0000"; + i2s5_8ch = "/i2s@fddf0000"; + i2s9_8ch = "/i2s@fddfc000"; + spdif_rx0 = "/spdif-rx@fde08000"; + dsi0 = "/dsi@fde20000"; + dsi0_in = "/dsi@fde20000/ports/port@0"; + dsi0_in_vp2 = "/dsi@fde20000/ports/port@0/endpoint@0"; + dsi0_in_vp3 = "/dsi@fde20000/ports/port@0/endpoint@1"; + dsi_out_panel = "/dsi@fde20000/ports/port@1/endpoint"; + dsi0_panel = "/dsi@fde20000/panel@0"; + disp_timings0 = "/dsi@fde20000/panel@0/display-timings"; + dsi0_timing0 = "/dsi@fde20000/panel@0/display-timings/timing0"; + panel_in_dsi = "/dsi@fde20000/panel@0/ports/port@0/endpoint"; + dsi1 = "/dsi@fde30000"; + dsi1_in = "/dsi@fde30000/ports/port@0"; + dsi1_in_vp2 = "/dsi@fde30000/ports/port@0/endpoint@0"; + dsi1_in_vp3 = "/dsi@fde30000/ports/port@0/endpoint@1"; + dsi1_out_panel = "/dsi@fde30000/ports/port@1/endpoint"; + dsi1_panel = "/dsi@fde30000/panel@0"; + disp_timings1 = "/dsi@fde30000/panel@0/display-timings"; + dsi1_timing0 = "/dsi@fde30000/panel@0/display-timings/timing0"; + panel_in_dsi1 = "/dsi@fde30000/panel@0/ports/port@0/endpoint"; + hdcp0 = "/hdcp@fde40000"; + dp0 = "/dp@fde50000"; + dp0_in_vp0 = "/dp@fde50000/ports/port@0/endpoint@0"; + dp0_in_vp1 = "/dp@fde50000/ports/port@0/endpoint@1"; + dp0_in_vp2 = "/dp@fde50000/ports/port@0/endpoint@2"; + dp0_out = "/dp@fde50000/ports/port@1/endpoint"; + hdcp1 = "/hdcp@fde70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi0_in = "/hdmi@fde80000/ports/port@0"; + hdmi0_in_vp0 = "/hdmi@fde80000/ports/port@0/endpoint@0"; + hdmi0_in_vp1 = "/hdmi@fde80000/ports/port@0/endpoint@1"; + hdmi0_in_vp2 = "/hdmi@fde80000/ports/port@0/endpoint@2"; + edp0 = "/edp@fdec0000"; + edp0_in_vp0 = "/edp@fdec0000/ports/port@0/endpoint@0"; + edp0_in_vp1 = "/edp@fdec0000/ports/port@0/endpoint@1"; + edp0_in_vp2 = "/edp@fdec0000/ports/port@0/endpoint@2"; + edp0_out = "/edp@fdec0000/ports/port@1/endpoint"; + qos_gpu_m0 = "/qos@fdf35000"; + qos_gpu_m1 = "/qos@fdf35200"; + qos_gpu_m2 = "/qos@fdf35400"; + qos_gpu_m3 = "/qos@fdf35600"; + qos_rga3_1 = "/qos@fdf36000"; + qos_sdio = "/qos@fdf39000"; + qos_gic600_m0 = "/qos@fdf3a000"; + qos_gic600_m1 = "/qos@fdf3a200"; + qos_sdmmc = "/qos@fdf3d800"; + qos_usb3_1 = "/qos@fdf3e000"; + qos_usb3_0 = "/qos@fdf3e200"; + qos_usb2host_0 = "/qos@fdf3e400"; + qos_usb2host_1 = "/qos@fdf3e600"; + qos_fisheye0 = "/qos@fdf40000"; + qos_fisheye1 = "/qos@fdf40200"; + qos_isp0_mro = "/qos@fdf40400"; + qos_isp0_mwo = "/qos@fdf40500"; + qos_vicap_m0 = "/qos@fdf40600"; + qos_vicap_m1 = "/qos@fdf40800"; + qos_isp1_mwo = "/qos@fdf41000"; + qos_isp1_mro = "/qos@fdf41100"; + qos_rkvenc0_m0ro = "/qos@fdf60000"; + qos_rkvenc0_m1ro = "/qos@fdf60200"; + qos_rkvenc0_m2wo = "/qos@fdf60400"; + qos_rkvenc1_m0ro = "/qos@fdf61000"; + qos_rkvenc1_m1ro = "/qos@fdf61200"; + qos_rkvenc1_m2wo = "/qos@fdf61400"; + qos_rkvdec0 = "/qos@fdf62000"; + qos_rkvdec1 = "/qos@fdf63000"; + qos_av1 = "/qos@fdf64000"; + qos_iep = "/qos@fdf66000"; + qos_jpeg_dec = "/qos@fdf66200"; + qos_jpeg_enc0 = "/qos@fdf66400"; + qos_jpeg_enc1 = "/qos@fdf66600"; + qos_jpeg_enc2 = "/qos@fdf66800"; + qos_jpeg_enc3 = "/qos@fdf66a00"; + qos_rga2_mro = "/qos@fdf66c00"; + qos_rga2_mwo = "/qos@fdf66e00"; + qos_rga3_0 = "/qos@fdf67000"; + qos_vdpu = "/qos@fdf67200"; + qos_npu1 = "/qos@fdf70000"; + qos_npu2 = "/qos@fdf71000"; + qos_npu0_mwr = "/qos@fdf72000"; + qos_npu0_mro = "/qos@fdf72200"; + qos_mcu_npu = "/qos@fdf72400"; + qos_hdcp0 = "/qos@fdf80000"; + qos_hdcp1 = "/qos@fdf81000"; + qos_hdmirx = "/qos@fdf81200"; + qos_vop_m0 = "/qos@fdf82000"; + qos_vop_m1 = "/qos@fdf82200"; + dfi = "/dfi@fe060000"; + pcie2x1l1 = "/pcie@fe180000"; + pcie2x1l1_intc = "/pcie@fe180000/legacy-interrupt-controller"; + pcie2x1l2 = "/pcie@fe190000"; + pcie2x1l2_intc = "/pcie@fe190000/legacy-interrupt-controller"; + gmac_uio1 = "/uio@fe1c0000"; + gmac1 = "/ethernet@fe1c0000"; + mdio1 = "/ethernet@fe1c0000/mdio"; + rgmii_phy = "/ethernet@fe1c0000/mdio/phy@1"; + gmac1_stmmac_axi_setup = "/ethernet@fe1c0000/stmmac-axi-config"; + gmac1_mtl_rx_setup = "/ethernet@fe1c0000/rx-queues-config"; + gmac1_mtl_tx_setup = "/ethernet@fe1c0000/tx-queues-config"; + sata0 = "/sata@fe210000"; + sata2 = "/sata@fe230000"; + sfc = "/spi@fe2b0000"; + sdmmc = "/mmc@fe2c0000"; + sdio = "/mmc@fe2d0000"; + sdhci = "/mmc@fe2e0000"; + crypto = "/crypto@fe370000"; + rng = "/rng@fe378000"; + i2s0_8ch = "/i2s@fe470000"; + i2s1_8ch = "/i2s@fe480000"; + i2s2_2ch = "/i2s@fe490000"; + i2s3_2ch = "/i2s@fe4a0000"; + pdm0 = "/pdm@fe4b0000"; + pdm1 = "/pdm@fe4c0000"; + vad = "/vad@fe4d0000"; + spdif_tx0 = "/spdif-tx@fe4e0000"; + spdif_tx1 = "/spdif-tx@fe4f0000"; + acdcdig_dsm = "/codec-digital@fe500000"; + hwlock = "/hwspinlock@fe5a0000"; + gic = "/interrupt-controller@fe600000"; + its0 = "/interrupt-controller@fe600000/msi-controller@fe640000"; + its1 = "/interrupt-controller@fe600000/msi-controller@fe660000"; + dmac0 = "/dma-controller@fea10000"; + dmac1 = "/dma-controller@fea30000"; + can0 = "/can@fea50000"; + can1 = "/can@fea60000"; + can2 = "/can@fea70000"; + hw_decompress = "/decompress@fea80000"; + i2c1 = "/i2c@fea90000"; + vdd_npu_s0 = "/i2c@fea90000/rk8602@42"; + vdd_npu_mem_s0 = "/i2c@fea90000/rk8602@42"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + imx415 = "/i2c@feab0000/imx415@1a"; + imx415_out0 = "/i2c@feab0000/imx415@1a/port/endpoint"; + i2c4 = "/i2c@feac0000"; + ls_stk3332 = "/i2c@feac0000/light@47"; + ps_stk3332 = "/i2c@feac0000/proximity@47"; + icm42607_acc = "/i2c@feac0000/icm_acc@68"; + icm42607_gyro = "/i2c@feac0000/icm_gyro@68"; + i2c5 = "/i2c@fead0000"; + gt1x = "/i2c@fead0000/gt1x@14"; + hynitron = "/i2c@fead0000/hynitron@5a"; + rktimer = "/timer@feae0000"; + wdt = "/watchdog@feaf0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + rk806single = "/spi@feb20000/rk806single@0"; + pinctrl_rk806 = "/spi@feb20000/rk806single@0/pinctrl_rk806"; + rk806_dvs1_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_null"; + rk806_dvs1_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_slp"; + rk806_dvs1_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_pwrdn"; + rk806_dvs1_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_rst"; + rk806_dvs2_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_null"; + rk806_dvs2_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_slp"; + rk806_dvs2_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_pwrdn"; + rk806_dvs2_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_rst"; + rk806_dvs2_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_dvs"; + rk806_dvs2_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_gpio"; + rk806_dvs3_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_null"; + rk806_dvs3_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_slp"; + rk806_dvs3_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_pwrdn"; + rk806_dvs3_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_rst"; + rk806_dvs3_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_dvs"; + rk806_dvs3_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_gpio"; + vdd_gpu_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1"; + vdd_gpu_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1"; + vdd_cpu_lit_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2"; + vdd_cpu_lit_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2"; + vdd_log_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG3"; + vdd_vdenc_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4"; + vdd_vdenc_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4"; + vdd_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG5"; + vdd2_ddr_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG6"; + vcc_2v0_pldo_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG7"; + vcc_3v3_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG8"; + vddq_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG9"; + vcc_1v8_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG10"; + avcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG1"; + vcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG2"; + avdd_1v2_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG3"; + vcc_3v3_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG4"; + vccio_sd_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG5"; + pldo6_s3 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG6"; + vdd_0v75_s3 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG1"; + vdd_ddr_pll_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG2"; + avdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG3"; + vdd_0v85_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG4"; + vdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG5"; + spi3 = "/spi@feb30000"; + uart1 = "/serial@feb40000"; + uart2 = "/serial@feb50000"; + uart3 = "/serial@feb60000"; + uart4 = "/serial@feb70000"; + uart5 = "/serial@feb80000"; + uart6 = "/serial@feb90000"; + uart7 = "/serial@feba0000"; + uart8 = "/serial@febb0000"; + uart9 = "/serial@febc0000"; + pwm4 = "/pwm@febd0000"; + pwm5 = "/pwm@febd0010"; + pwm6 = "/pwm@febd0020"; + pwm7 = "/pwm@febd0030"; + pwm8 = "/pwm@febe0000"; + pwm9 = "/pwm@febe0010"; + pwm10 = "/pwm@febe0020"; + pwm11 = "/pwm@febe0030"; + pwm12 = "/pwm@febf0000"; + pwm13 = "/pwm@febf0010"; + pwm14 = "/pwm@febf0020"; + pwm15 = "/pwm@febf0030"; + tsadc = "/tsadc@fec00000"; + saradc = "/saradc@fec10000"; + mailbox0 = "/mailbox@fec60000"; + mailbox1 = "/mailbox@fec70000"; + i2c6 = "/i2c@fec80000"; + usbc0 = "/i2c@fec80000/husb311@4e"; + usbc0_role_sw = "/i2c@fec80000/husb311@4e/ports/port@0/endpoint@0"; + usb_con = "/i2c@fec80000/husb311@4e/connector"; + usbc0_orien_sw = "/i2c@fec80000/husb311@4e/connector/ports/port@0/endpoint"; + dp_altmode_mux = "/i2c@fec80000/husb311@4e/connector/ports/port@1/endpoint"; + hym8563 = "/i2c@fec80000/hym8563@51"; + i2c7 = "/i2c@fec90000"; + es8388 = "/i2c@fec90000/es8388@11"; + i2c8 = "/i2c@feca0000"; + spi4 = "/spi@fecb0000"; + otp = "/otp@fecc0000"; + cpu_code = "/otp@fecc0000/cpu-code@2"; + package_serial_number_high = "/otp@fecc0000/package-serial-number-high@5"; + package_serial_number_low = "/otp@fecc0000/package-serial-number-low@6"; + specification_serial_number = "/otp@fecc0000/specification-serial-number@6"; + otp_id = "/otp@fecc0000/id@7"; + otp_cpu_version = "/otp@fecc0000/cpu-version@1c"; + cpub0_leakage = "/otp@fecc0000/cpub0-leakage@17"; + cpub1_leakage = "/otp@fecc0000/cpub1-leakage@18"; + cpul_leakage = "/otp@fecc0000/cpul-leakage@19"; + log_leakage = "/otp@fecc0000/log-leakage@1a"; + gpu_leakage = "/otp@fecc0000/gpu-leakage@1b"; + customer_demand = "/otp@fecc0000/customer-demand@22"; + npu_leakage = "/otp@fecc0000/npu-leakage@28"; + codec_leakage = "/otp@fecc0000/codec-leakage@29"; + cpul_opp_info = "/otp@fecc0000/cpul-opp-info@3d"; + cpub01_opp_info = "/otp@fecc0000/cpub01-opp-info@43"; + cpub23_opp_info = "/otp@fecc0000/cpub23-opp-info@49"; + gpu_opp_info = "/otp@fecc0000/gpu-opp-info@4f"; + npu_opp_info = "/otp@fecc0000/npu-opp-info@55"; + dmc_opp_info = "/otp@fecc0000/dmc-opp-info@5b"; + vop_opp_info = "/otp@fecc0000/vop-opp-info@61"; + venc_opp_info = "/otp@fecc0000/venc-opp-info@67"; + mailbox2 = "/mailbox@fece0000"; + dmac2 = "/dma-controller@fed10000"; + hdptxphy0 = "/phy@fed60000"; + hdptxphy_hdmi0 = "/hdmiphy@fed60000"; + usbdp_phy0 = "/phy@fed80000"; + usbdp_phy0_dp = "/phy@fed80000/dp-port"; + usbdp_phy0_u3 = "/phy@fed80000/u3-port"; + usbdp_phy0_orientation_switch = "/phy@fed80000/port/endpoint@0"; + usbdp_phy0_dp_altmode_mux = "/phy@fed80000/port/endpoint@1"; + mipidcphy0 = "/phy@feda0000"; + mipidcphy1 = "/phy@fedb0000"; + csi2_dphy0_hw = "/csi2-dphy0-hw@fedc0000"; + csi2_dphy1_hw = "/csi2-dphy1-hw@fedc8000"; + combphy0_ps = "/phy@fee00000"; + combphy2_psu = "/phy@fee20000"; + syssram = "/sram@ff001000"; + rkvdec0_sram = "/sram@ff001000/rkvdec-sram@0"; + rkvdec1_sram = "/sram@ff001000/rkvdec-sram@78000"; + pinctrl = "/pinctrl"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + pcfg_pull_up = "/pinctrl/pcfg-pull-up"; + pcfg_pull_down = "/pinctrl/pcfg-pull-down"; + pcfg_pull_none = "/pinctrl/pcfg-pull-none"; + pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0"; + pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1"; + pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2"; + pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3"; + pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4"; + pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5"; + pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6"; + pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0"; + pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1"; + pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2"; + pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3"; + pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4"; + pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5"; + pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6"; + pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0"; + pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1"; + pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2"; + pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3"; + pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4"; + pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5"; + pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6"; + pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt"; + pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt"; + pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt"; + pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt"; + pcfg_pull_none_drv_level_1_smt = "/pinctrl/pcfg-pull-none-drv-level-1-smt"; + pcfg_pull_none_drv_level_2_smt = "/pinctrl/pcfg-pull-none-drv-level-2-smt"; + pcfg_pull_none_drv_level_3_smt = "/pinctrl/pcfg-pull-none-drv-level-3-smt"; + pcfg_pull_none_drv_level_4_smt = "/pinctrl/pcfg-pull-none-drv-level-4-smt"; + pcfg_pull_none_drv_level_5_smt = "/pinctrl/pcfg-pull-none-drv-level-5-smt"; + pcfg_pull_none_drv_level_6_smt = "/pinctrl/pcfg-pull-none-drv-level-6-smt"; + pcfg_output_high = "/pinctrl/pcfg-output-high"; + pcfg_output_high_pull_up = "/pinctrl/pcfg-output-high-pull-up"; + pcfg_output_high_pull_down = "/pinctrl/pcfg-output-high-pull-down"; + pcfg_output_high_pull_none = "/pinctrl/pcfg-output-high-pull-none"; + pcfg_output_low = "/pinctrl/pcfg-output-low"; + pcfg_output_low_pull_up = "/pinctrl/pcfg-output-low-pull-up"; + pcfg_output_low_pull_down = "/pinctrl/pcfg-output-low-pull-down"; + pcfg_output_low_pull_none = "/pinctrl/pcfg-output-low-pull-none"; + auddsm_pins = "/pinctrl/auddsm/auddsm-pins"; + bt1120_pins = "/pinctrl/bt1120/bt1120-pins"; + can0m0_pins = "/pinctrl/can0/can0m0-pins"; + can0m1_pins = "/pinctrl/can0/can0m1-pins"; + can1m0_pins = "/pinctrl/can1/can1m0-pins"; + can1m1_pins = "/pinctrl/can1/can1m1-pins"; + can2m0_pins = "/pinctrl/can2/can2m0-pins"; + can2m1_pins = "/pinctrl/can2/can2m1-pins"; + cif_clk = "/pinctrl/cif/cif-clk"; + cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk"; + cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16"; + cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8"; + clk32k_in = "/pinctrl/clk32k/clk32k-in"; + clk32k_out0 = "/pinctrl/clk32k/clk32k-out0"; + clk32k_out1 = "/pinctrl/clk32k/clk32k-out1"; + cpu_pins = "/pinctrl/cpu/cpu-pins"; + ddrphych0_pins = "/pinctrl/ddrphych0/ddrphych0-pins"; + ddrphych1_pins = "/pinctrl/ddrphych1/ddrphych1-pins"; + ddrphych2_pins = "/pinctrl/ddrphych2/ddrphych2-pins"; + ddrphych3_pins = "/pinctrl/ddrphych3/ddrphych3-pins"; + dp0m0_pins = "/pinctrl/dp0/dp0m0-pins"; + dp0m1_pins = "/pinctrl/dp0/dp0m1-pins"; + dp0m2_pins = "/pinctrl/dp0/dp0m2-pins"; + dp1m0_pins = "/pinctrl/dp1/dp1m0-pins"; + dp1m1_pins = "/pinctrl/dp1/dp1m1-pins"; + dp1m2_pins = "/pinctrl/dp1/dp1m2-pins"; + emmc_rstnout = "/pinctrl/emmc/emmc-rstnout"; + emmc_bus8 = "/pinctrl/emmc/emmc-bus8"; + emmc_clk = "/pinctrl/emmc/emmc-clk"; + emmc_cmd = "/pinctrl/emmc/emmc-cmd"; + emmc_data_strobe = "/pinctrl/emmc/emmc-data-strobe"; + eth1_pins = "/pinctrl/eth1/eth1-pins"; + fspim0_pins = "/pinctrl/fspi/fspim0-pins"; + fspim0_cs1 = "/pinctrl/fspi/fspim0-cs1"; + fspim2_pins = "/pinctrl/fspi/fspim2-pins"; + fspim2_cs1 = "/pinctrl/fspi/fspim2-cs1"; + fspim1_pins = "/pinctrl/fspi/fspim1-pins"; + fspim1_cs1 = "/pinctrl/fspi/fspim1-cs1"; + gmac1_miim = "/pinctrl/gmac1/gmac1-miim"; + gmac1_clkinout = "/pinctrl/gmac1/gmac1-clkinout"; + gmac1_rx_bus2 = "/pinctrl/gmac1/gmac1-rx-bus2"; + gmac1_tx_bus2 = "/pinctrl/gmac1/gmac1-tx-bus2"; + gmac1_rgmii_clk = "/pinctrl/gmac1/gmac1-rgmii-clk"; + gmac1_rgmii_bus = "/pinctrl/gmac1/gmac1-rgmii-bus"; + gmac1_ppsclk = "/pinctrl/gmac1/gmac1-ppsclk"; + gmac1_ppstrig = "/pinctrl/gmac1/gmac1-ppstrig"; + gmac1_ptp_ref_clk = "/pinctrl/gmac1/gmac1-ptp-ref-clk"; + gmac1_txer = "/pinctrl/gmac1/gmac1-txer"; + gpu_pins = "/pinctrl/gpu/gpu-pins"; + hdmim0_rx_cec = "/pinctrl/hdmi/hdmim0-rx-cec"; + hdmim0_rx_hpdin = "/pinctrl/hdmi/hdmim0-rx-hpdin"; + hdmim0_rx_scl = "/pinctrl/hdmi/hdmim0-rx-scl"; + hdmim0_rx_sda = "/pinctrl/hdmi/hdmim0-rx-sda"; + hdmim0_tx0_cec = "/pinctrl/hdmi/hdmim0-tx0-cec"; + hdmim0_tx0_hpd = "/pinctrl/hdmi/hdmim0-tx0-hpd"; + hdmim0_tx0_scl = "/pinctrl/hdmi/hdmim0-tx0-scl"; + hdmim0_tx0_sda = "/pinctrl/hdmi/hdmim0-tx0-sda"; + hdmim0_tx1_hpd = "/pinctrl/hdmi/hdmim0-tx1-hpd"; + hdmim1_rx = "/pinctrl/hdmi/hdmim1-rx"; + hdmim1_rx_cec = "/pinctrl/hdmi/hdmim1-rx-cec"; + hdmim1_rx_hpdin = "/pinctrl/hdmi/hdmim1-rx-hpdin"; + hdmim1_rx_scl = "/pinctrl/hdmi/hdmim1-rx-scl"; + hdmim1_rx_sda = "/pinctrl/hdmi/hdmim1-rx-sda"; + hdmim1_tx0_cec = "/pinctrl/hdmi/hdmim1-tx0-cec"; + hdmim1_tx0_hpd = "/pinctrl/hdmi/hdmim1-tx0-hpd"; + hdmim1_tx0_scl = "/pinctrl/hdmi/hdmim1-tx0-scl"; + hdmim1_tx0_sda = "/pinctrl/hdmi/hdmim1-tx0-sda"; + hdmim1_tx1_cec = "/pinctrl/hdmi/hdmim1-tx1-cec"; + hdmim1_tx1_hpd = "/pinctrl/hdmi/hdmim1-tx1-hpd"; + hdmim1_tx1_scl = "/pinctrl/hdmi/hdmim1-tx1-scl"; + hdmim1_tx1_sda = "/pinctrl/hdmi/hdmim1-tx1-sda"; + hdmim2_rx_cec = "/pinctrl/hdmi/hdmim2-rx-cec"; + hdmim2_rx_hpdin = "/pinctrl/hdmi/hdmim2-rx-hpdin"; + hdmim2_rx_scl = "/pinctrl/hdmi/hdmim2-rx-scl"; + hdmim2_rx_sda = "/pinctrl/hdmi/hdmim2-rx-sda"; + hdmim2_tx0_scl = "/pinctrl/hdmi/hdmim2-tx0-scl"; + hdmim2_tx0_sda = "/pinctrl/hdmi/hdmim2-tx0-sda"; + hdmim2_tx1_cec = "/pinctrl/hdmi/hdmim2-tx1-cec"; + hdmim2_tx1_scl = "/pinctrl/hdmi/hdmim2-tx1-scl"; + hdmim2_tx1_sda = "/pinctrl/hdmi/hdmim2-tx1-sda"; + hdmi_debug0 = "/pinctrl/hdmi/hdmi-debug0"; + hdmi_debug1 = "/pinctrl/hdmi/hdmi-debug1"; + hdmi_debug2 = "/pinctrl/hdmi/hdmi-debug2"; + hdmi_debug3 = "/pinctrl/hdmi/hdmi-debug3"; + hdmi_debug4 = "/pinctrl/hdmi/hdmi-debug4"; + hdmi_debug5 = "/pinctrl/hdmi/hdmi-debug5"; + hdmi_debug6 = "/pinctrl/hdmi/hdmi-debug6"; + hdmim0_tx1_cec = "/pinctrl/hdmi/hdmim0-tx1-cec"; + hdmim0_tx1_scl = "/pinctrl/hdmi/hdmim0-tx1-scl"; + hdmim0_tx1_sda = "/pinctrl/hdmi/hdmim0-tx1-sda"; + hdmirx_det = "/pinctrl/hdmi/hdmirx-det"; + i2c0m0_xfer = "/pinctrl/i2c0/i2c0m0-xfer"; + i2c0m2_xfer = "/pinctrl/i2c0/i2c0m2-xfer"; + i2c0m1_xfer = "/pinctrl/i2c0/i2c0m1-xfer"; + i2c1m0_xfer = "/pinctrl/i2c1/i2c1m0-xfer"; + i2c1m1_xfer = "/pinctrl/i2c1/i2c1m1-xfer"; + i2c1m2_xfer = "/pinctrl/i2c1/i2c1m2-xfer"; + i2c1m3_xfer = "/pinctrl/i2c1/i2c1m3-xfer"; + i2c1m4_xfer = "/pinctrl/i2c1/i2c1m4-xfer"; + i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer"; + i2c2m2_xfer = "/pinctrl/i2c2/i2c2m2-xfer"; + i2c2m3_xfer = "/pinctrl/i2c2/i2c2m3-xfer"; + i2c2m4_xfer = "/pinctrl/i2c2/i2c2m4-xfer"; + i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer"; + i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer"; + i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer"; + i2c3m2_xfer = "/pinctrl/i2c3/i2c3m2-xfer"; + i2c3m4_xfer = "/pinctrl/i2c3/i2c3m4-xfer"; + i2c3m3_xfer = "/pinctrl/i2c3/i2c3m3-xfer"; + i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer"; + i2c4m2_xfer = "/pinctrl/i2c4/i2c4m2-xfer"; + i2c4m3_xfer = "/pinctrl/i2c4/i2c4m3-xfer"; + i2c4m4_xfer = "/pinctrl/i2c4/i2c4m4-xfer"; + i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer"; + i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer"; + i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer"; + i2c5m2_xfer = "/pinctrl/i2c5/i2c5m2-xfer"; + i2c5m3_xfer = "/pinctrl/i2c5/i2c5m3-xfer"; + i2c5m4_xfer = "/pinctrl/i2c5/i2c5m4-xfer"; + i2c6m0_xfer = "/pinctrl/i2c6/i2c6m0-xfer"; + i2c6m1_xfer = "/pinctrl/i2c6/i2c6m1-xfer"; + i2c6m3_xfer = "/pinctrl/i2c6/i2c6m3-xfer"; + i2c6m4_xfer = "/pinctrl/i2c6/i2c6m4-xfer"; + i2c6m2_xfer = "/pinctrl/i2c6/i2c6m2-xfer"; + i2c7m0_xfer = "/pinctrl/i2c7/i2c7m0-xfer"; + i2c7m2_xfer = "/pinctrl/i2c7/i2c7m2-xfer"; + i2c7m3_xfer = "/pinctrl/i2c7/i2c7m3-xfer"; + i2c7m1_xfer = "/pinctrl/i2c7/i2c7m1-xfer"; + i2c8m0_xfer = "/pinctrl/i2c8/i2c8m0-xfer"; + i2c8m2_xfer = "/pinctrl/i2c8/i2c8m2-xfer"; + i2c8m3_xfer = "/pinctrl/i2c8/i2c8m3-xfer"; + i2c8m4_xfer = "/pinctrl/i2c8/i2c8m4-xfer"; + i2c8m1_xfer = "/pinctrl/i2c8/i2c8m1-xfer"; + i2s0_idle = "/pinctrl/i2s0/i2s0-idle"; + i2s0_lrck = "/pinctrl/i2s0/i2s0-lrck"; + i2s0_mclk = "/pinctrl/i2s0/i2s0-mclk"; + i2s0_sclk = "/pinctrl/i2s0/i2s0-sclk"; + i2s0_sdi0 = "/pinctrl/i2s0/i2s0-sdi0"; + i2s0_sdi1 = "/pinctrl/i2s0/i2s0-sdi1"; + i2s0_sdi2 = "/pinctrl/i2s0/i2s0-sdi2"; + i2s0_sdi3 = "/pinctrl/i2s0/i2s0-sdi3"; + i2s0_sdo0 = "/pinctrl/i2s0/i2s0-sdo0"; + i2s0_sdo1 = "/pinctrl/i2s0/i2s0-sdo1"; + i2s0_sdo2 = "/pinctrl/i2s0/i2s0-sdo2"; + i2s0_sdo3 = "/pinctrl/i2s0/i2s0-sdo3"; + i2s1m0_lrck = "/pinctrl/i2s1/i2s1m0-lrck"; + i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk"; + i2s1m0_sclk = "/pinctrl/i2s1/i2s1m0-sclk"; + i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0"; + i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1"; + i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2"; + i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3"; + i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0"; + i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1"; + i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2"; + i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3"; + i2s1m1_lrck = "/pinctrl/i2s1/i2s1m1-lrck"; + i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk"; + i2s1m1_sclk = "/pinctrl/i2s1/i2s1m1-sclk"; + i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0"; + i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1"; + i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2"; + i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3"; + i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0"; + i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1"; + i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2"; + i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3"; + i2s2m1_idle = "/pinctrl/i2s2/i2s2m1-idle"; + i2s2m1_lrck = "/pinctrl/i2s2/i2s2m1-lrck"; + i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk"; + i2s2m1_sclk = "/pinctrl/i2s2/i2s2m1-sclk"; + i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi"; + i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo"; + i2s2m0_idle = "/pinctrl/i2s2/i2s2m0-idle"; + i2s2m0_lrck = "/pinctrl/i2s2/i2s2m0-lrck"; + i2s2m0_mclk = "/pinctrl/i2s2/i2s2m0-mclk"; + i2s2m0_sclk = "/pinctrl/i2s2/i2s2m0-sclk"; + i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi"; + i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo"; + i2s3_idle = "/pinctrl/i2s3/i2s3-idle"; + i2s3_lrck = "/pinctrl/i2s3/i2s3-lrck"; + i2s3_mclk = "/pinctrl/i2s3/i2s3-mclk"; + i2s3_sclk = "/pinctrl/i2s3/i2s3-sclk"; + i2s3_sdi = "/pinctrl/i2s3/i2s3-sdi"; + i2s3_sdo = "/pinctrl/i2s3/i2s3-sdo"; + jtagm0_pins = "/pinctrl/jtag/jtagm0-pins"; + jtagm1_pins = "/pinctrl/jtag/jtagm1-pins"; + jtagm2_pins = "/pinctrl/jtag/jtagm2-pins"; + litcpu_pins = "/pinctrl/litcpu/litcpu-pins"; + mcum0_pins = "/pinctrl/mcu/mcum0-pins"; + mcum1_pins = "/pinctrl/mcu/mcum1-pins"; + mipim0_camera0_clk = "/pinctrl/mipi/mipim0-camera0-clk"; + mipim0_camera1_clk = "/pinctrl/mipi/mipim0-camera1-clk"; + mipim0_camera2_clk = "/pinctrl/mipi/mipim0-camera2-clk"; + mipim0_camera3_clk = "/pinctrl/mipi/mipim0-camera3-clk"; + mipim0_camera4_clk = "/pinctrl/mipi/mipim0-camera4-clk"; + mipim1_camera0_clk = "/pinctrl/mipi/mipim1-camera0-clk"; + mipim1_camera1_clk = "/pinctrl/mipi/mipim1-camera1-clk"; + mipim1_camera2_clk = "/pinctrl/mipi/mipim1-camera2-clk"; + mipim1_camera3_clk = "/pinctrl/mipi/mipim1-camera3-clk"; + mipim1_camera4_clk = "/pinctrl/mipi/mipim1-camera4-clk"; + mipi_te0 = "/pinctrl/mipi/mipi-te0"; + mipi_te1 = "/pinctrl/mipi/mipi-te1"; + npu_pins = "/pinctrl/npu/npu-pins"; + pcie20x1m0_pins = "/pinctrl/pcie20x1/pcie20x1m0-pins"; + pcie20x1m1_pins = "/pinctrl/pcie20x1/pcie20x1m1-pins"; + pcie20x1_2_button_rstn = "/pinctrl/pcie20x1/pcie20x1-2-button-rstn"; + pcie30phy_pins = "/pinctrl/pcie30phy/pcie30phy-pins"; + pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins"; + pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins"; + pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins"; + pcie30x1_0_button_rstn = "/pinctrl/pcie30x1/pcie30x1-0-button-rstn"; + pcie30x1_1_button_rstn = "/pinctrl/pcie30x1/pcie30x1-1-button-rstn"; + pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins"; + pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins"; + pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins"; + pcie30x2m3_pins = "/pinctrl/pcie30x2/pcie30x2m3-pins"; + pcie30x2_button_rstn = "/pinctrl/pcie30x2/pcie30x2-button-rstn"; + pcie30x4m0_pins = "/pinctrl/pcie30x4/pcie30x4m0-pins"; + pcie30x4m1_pins = "/pinctrl/pcie30x4/pcie30x4m1-pins"; + pcie30x4m2_pins = "/pinctrl/pcie30x4/pcie30x4m2-pins"; + pcie30x4m3_pins = "/pinctrl/pcie30x4/pcie30x4m3-pins"; + pcie30x4_button_rstn = "/pinctrl/pcie30x4/pcie30x4-button-rstn"; + pdm0m0_clk = "/pinctrl/pdm0/pdm0m0-clk"; + pdm0m0_clk1 = "/pinctrl/pdm0/pdm0m0-clk1"; + pdm0m0_idle = "/pinctrl/pdm0/pdm0m0-idle"; + pdm0m0_sdi0 = "/pinctrl/pdm0/pdm0m0-sdi0"; + pdm0m0_sdi1 = "/pinctrl/pdm0/pdm0m0-sdi1"; + pdm0m0_sdi2 = "/pinctrl/pdm0/pdm0m0-sdi2"; + pdm0m0_sdi3 = "/pinctrl/pdm0/pdm0m0-sdi3"; + pdm0m1_clk = "/pinctrl/pdm0/pdm0m1-clk"; + pdm0m1_clk1 = "/pinctrl/pdm0/pdm0m1-clk1"; + pdm0m1_idle = "/pinctrl/pdm0/pdm0m1-idle"; + pdm0m1_sdi0 = "/pinctrl/pdm0/pdm0m1-sdi0"; + pdm0m1_sdi1 = "/pinctrl/pdm0/pdm0m1-sdi1"; + pdm0m1_sdi2 = "/pinctrl/pdm0/pdm0m1-sdi2"; + pdm0m1_sdi3 = "/pinctrl/pdm0/pdm0m1-sdi3"; + pdm1m0_clk = "/pinctrl/pdm1/pdm1m0-clk"; + pdm1m0_clk1 = "/pinctrl/pdm1/pdm1m0-clk1"; + pdm1m0_idle = "/pinctrl/pdm1/pdm1m0-idle"; + pdm1m0_sdi0 = "/pinctrl/pdm1/pdm1m0-sdi0"; + pdm1m0_sdi1 = "/pinctrl/pdm1/pdm1m0-sdi1"; + pdm1m0_sdi2 = "/pinctrl/pdm1/pdm1m0-sdi2"; + pdm1m0_sdi3 = "/pinctrl/pdm1/pdm1m0-sdi3"; + pdm1m1_clk = "/pinctrl/pdm1/pdm1m1-clk"; + pdm1m1_clk1 = "/pinctrl/pdm1/pdm1m1-clk1"; + pdm1m1_idle = "/pinctrl/pdm1/pdm1m1-idle"; + pdm1m1_sdi0 = "/pinctrl/pdm1/pdm1m1-sdi0"; + pdm1m1_sdi1 = "/pinctrl/pdm1/pdm1m1-sdi1"; + pdm1m1_sdi2 = "/pinctrl/pdm1/pdm1m1-sdi2"; + pdm1m1_sdi3 = "/pinctrl/pdm1/pdm1m1-sdi3"; + pmic_pins = "/pinctrl/pmic/pmic-pins"; + pmu_pins = "/pinctrl/pmu/pmu-pins"; + pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins"; + pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins"; + pwm0m2_pins = "/pinctrl/pwm0/pwm0m2-pins"; + pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins"; + pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins"; + pwm1m2_pins = "/pinctrl/pwm1/pwm1m2-pins"; + pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins"; + pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins"; + pwm2m2_pins = "/pinctrl/pwm2/pwm2m2-pins"; + pwm3m0_pins = "/pinctrl/pwm3/pwm3m0-pins"; + pwm3m1_pins = "/pinctrl/pwm3/pwm3m1-pins"; + pwm3m2_pins = "/pinctrl/pwm3/pwm3m2-pins"; + pwm3m3_pins = "/pinctrl/pwm3/pwm3m3-pins"; + pwm4m0_pins = "/pinctrl/pwm4/pwm4m0-pins"; + pwm4m1_pins = "/pinctrl/pwm4/pwm4m1-pins"; + pwm5m0_pins = "/pinctrl/pwm5/pwm5m0-pins"; + pwm5m1_pins = "/pinctrl/pwm5/pwm5m1-pins"; + pwm5m2_pins = "/pinctrl/pwm5/pwm5m2-pins"; + pwm6m0_pins = "/pinctrl/pwm6/pwm6m0-pins"; + pwm6m1_pins = "/pinctrl/pwm6/pwm6m1-pins"; + pwm6m2_pins = "/pinctrl/pwm6/pwm6m2-pins"; + pwm7m0_pins = "/pinctrl/pwm7/pwm7m0-pins"; + pwm7m1_pins = "/pinctrl/pwm7/pwm7m1-pins"; + pwm7m2_pins = "/pinctrl/pwm7/pwm7m2-pins"; + pwm7m3_pins = "/pinctrl/pwm7/pwm7m3-pins"; + pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins"; + pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins"; + pwm8m2_pins = "/pinctrl/pwm8/pwm8m2-pins"; + pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins"; + pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins"; + pwm9m2_pins = "/pinctrl/pwm9/pwm9m2-pins"; + pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins"; + pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins"; + pwm10m2_pins = "/pinctrl/pwm10/pwm10m2-pins"; + pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins"; + pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins"; + pwm11m2_pins = "/pinctrl/pwm11/pwm11m2-pins"; + pwm11m3_pins = "/pinctrl/pwm11/pwm11m3-pins"; + pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins"; + pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins"; + pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins"; + pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins"; + pwm13m2_pins = "/pinctrl/pwm13/pwm13m2-pins"; + pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins"; + pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins"; + pwm14m2_pins = "/pinctrl/pwm14/pwm14m2-pins"; + pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins"; + pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins"; + pwm15m2_pins = "/pinctrl/pwm15/pwm15m2-pins"; + pwm15m3_pins = "/pinctrl/pwm15/pwm15m3-pins"; + refclk_pins = "/pinctrl/refclk/refclk-pins"; + sata_pins = "/pinctrl/sata/sata-pins"; + sata0m0_pins = "/pinctrl/sata0/sata0m0-pins"; + sata0m1_pins = "/pinctrl/sata0/sata0m1-pins"; + sata1m0_pins = "/pinctrl/sata1/sata1m0-pins"; + sata1m1_pins = "/pinctrl/sata1/sata1m1-pins"; + sata2m0_pins = "/pinctrl/sata2/sata2m0-pins"; + sata2m1_pins = "/pinctrl/sata2/sata2m1-pins"; + sdiom1_pins = "/pinctrl/sdio/sdiom1-pins"; + sdiom0_pins = "/pinctrl/sdio/sdiom0-pins"; + sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4"; + sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk"; + sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd"; + sdmmc_det = "/pinctrl/sdmmc/sdmmc-det"; + sdmmc_pwren = "/pinctrl/sdmmc/sdmmc-pwren"; + sd_s0_pwr = "/pinctrl/sdmmc/sd-s0-pwr"; + spdif0m0_tx = "/pinctrl/spdif0/spdif0m0-tx"; + spdif0m1_tx = "/pinctrl/spdif0/spdif0m1-tx"; + spdif1m0_tx = "/pinctrl/spdif1/spdif1m0-tx"; + spdif1m1_tx = "/pinctrl/spdif1/spdif1m1-tx"; + spdif1m2_tx = "/pinctrl/spdif1/spdif1m2-tx"; + spi0m0_pins = "/pinctrl/spi0/spi0m0-pins"; + spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0"; + spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1"; + spi0m1_pins = "/pinctrl/spi0/spi0m1-pins"; + spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0"; + spi0m1_cs1 = "/pinctrl/spi0/spi0m1-cs1"; + spi0m2_pins = "/pinctrl/spi0/spi0m2-pins"; + spi0m2_cs0 = "/pinctrl/spi0/spi0m2-cs0"; + spi0m2_cs1 = "/pinctrl/spi0/spi0m2-cs1"; + spi0m3_pins = "/pinctrl/spi0/spi0m3-pins"; + spi0m3_cs0 = "/pinctrl/spi0/spi0m3-cs0"; + spi0m3_cs1 = "/pinctrl/spi0/spi0m3-cs1"; + spi1m1_pins = "/pinctrl/spi1/spi1m1-pins"; + spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0"; + spi1m1_cs1 = "/pinctrl/spi1/spi1m1-cs1"; + spi1m2_pins = "/pinctrl/spi1/spi1m2-pins"; + spi1m2_cs0 = "/pinctrl/spi1/spi1m2-cs0"; + spi1m2_cs1 = "/pinctrl/spi1/spi1m2-cs1"; + spi1m0_pins = "/pinctrl/spi1/spi1m0-pins"; + spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0"; + spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1"; + spi2m0_pins = "/pinctrl/spi2/spi2m0-pins"; + spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0"; + spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1"; + spi2m1_pins = "/pinctrl/spi2/spi2m1-pins"; + spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0"; + spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1"; + spi2m2_pins = "/pinctrl/spi2/spi2m2-pins"; + spi2m2_cs0 = "/pinctrl/spi2/spi2m2-cs0"; + spi2m2_cs1 = "/pinctrl/spi2/spi2m2-cs1"; + spi3m1_pins = "/pinctrl/spi3/spi3m1-pins"; + spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0"; + spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1"; + spi3m2_pins = "/pinctrl/spi3/spi3m2-pins"; + spi3m2_cs0 = "/pinctrl/spi3/spi3m2-cs0"; + spi3m2_cs1 = "/pinctrl/spi3/spi3m2-cs1"; + spi3m3_pins = "/pinctrl/spi3/spi3m3-pins"; + spi3m3_cs0 = "/pinctrl/spi3/spi3m3-cs0"; + spi3m3_cs1 = "/pinctrl/spi3/spi3m3-cs1"; + spi3m0_pins = "/pinctrl/spi3/spi3m0-pins"; + spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0"; + spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1"; + spi4m0_pins = "/pinctrl/spi4/spi4m0-pins"; + spi4m0_cs0 = "/pinctrl/spi4/spi4m0-cs0"; + spi4m0_cs1 = "/pinctrl/spi4/spi4m0-cs1"; + spi4m1_pins = "/pinctrl/spi4/spi4m1-pins"; + spi4m1_cs0 = "/pinctrl/spi4/spi4m1-cs0"; + spi4m1_cs1 = "/pinctrl/spi4/spi4m1-cs1"; + spi4m2_pins = "/pinctrl/spi4/spi4m2-pins"; + spi4m2_cs0 = "/pinctrl/spi4/spi4m2-cs0"; + tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut"; + tsadc_shut = "/pinctrl/tsadc/tsadc-shut"; + tsadc_shut_org = "/pinctrl/tsadc/tsadc-shut-org"; + uart0m0_xfer = "/pinctrl/uart0/uart0m0-xfer"; + uart0m1_xfer = "/pinctrl/uart0/uart0m1-xfer"; + uart0m2_xfer = "/pinctrl/uart0/uart0m2-xfer"; + uart0_ctsn = "/pinctrl/uart0/uart0-ctsn"; + uart0_rtsn = "/pinctrl/uart0/uart0-rtsn"; + uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer"; + uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn"; + uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn"; + uart1m2_xfer = "/pinctrl/uart1/uart1m2-xfer"; + uart1m2_ctsn = "/pinctrl/uart1/uart1m2-ctsn"; + uart1m2_rtsn = "/pinctrl/uart1/uart1m2-rtsn"; + uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; + uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn"; + uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn"; + uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer"; + uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer"; + uart2m2_xfer = "/pinctrl/uart2/uart2m2-xfer"; + uart2_ctsn = "/pinctrl/uart2/uart2-ctsn"; + uart2_rtsn = "/pinctrl/uart2/uart2-rtsn"; + uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer"; + uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer"; + uart3m2_xfer = "/pinctrl/uart3/uart3m2-xfer"; + uart3_ctsn = "/pinctrl/uart3/uart3-ctsn"; + uart3_rtsn = "/pinctrl/uart3/uart3-rtsn"; + uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer"; + uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer"; + uart4m2_xfer = "/pinctrl/uart4/uart4m2-xfer"; + uart4_ctsn = "/pinctrl/uart4/uart4-ctsn"; + uart4_rtsn = "/pinctrl/uart4/uart4-rtsn"; + uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; + uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn"; + uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn"; + uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer"; + uart5m1_ctsn = "/pinctrl/uart5/uart5m1-ctsn"; + uart5m1_rtsn = "/pinctrl/uart5/uart5m1-rtsn"; + uart5m2_xfer = "/pinctrl/uart5/uart5m2-xfer"; + uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer"; + uart6m1_ctsn = "/pinctrl/uart6/uart6m1-ctsn"; + uart6m1_rtsn = "/pinctrl/uart6/uart6m1-rtsn"; + uart6m2_xfer = "/pinctrl/uart6/uart6m2-xfer"; + uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer"; + uart6m0_ctsn = "/pinctrl/uart6/uart6m0-ctsn"; + uart6m0_rtsn = "/pinctrl/uart6/uart6m0-rtsn"; + uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer"; + uart7m1_ctsn = "/pinctrl/uart7/uart7m1-ctsn"; + uart7m1_rtsn = "/pinctrl/uart7/uart7m1-rtsn"; + uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer"; + uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer"; + uart7m0_ctsn = "/pinctrl/uart7/uart7m0-ctsn"; + uart7m0_rtsn = "/pinctrl/uart7/uart7m0-rtsn"; + uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer"; + uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn"; + uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn"; + uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer"; + uart8m1_ctsn = "/pinctrl/uart8/uart8m1-ctsn"; + uart8m1_rtsn = "/pinctrl/uart8/uart8m1-rtsn"; + uart8_xfer = "/pinctrl/uart8/uart8-xfer"; + uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer"; + uart9m1_ctsn = "/pinctrl/uart9/uart9m1-ctsn"; + uart9m1_rtsn = "/pinctrl/uart9/uart9m1-rtsn"; + uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer"; + uart9m2_ctsn = "/pinctrl/uart9/uart9m2-ctsn"; + uart9m2_rtsn = "/pinctrl/uart9/uart9m2-rtsn"; + uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer"; + uart9m0_ctsn = "/pinctrl/uart9/uart9m0-ctsn"; + uart9m0_rtsn = "/pinctrl/uart9/uart9m0-rtsn"; + vop_pins = "/pinctrl/vop/vop-pins"; + bt656_pins = "/pinctrl/bt656/bt656-pins"; + tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func"; + pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7"; + pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8"; + pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9"; + pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10"; + pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11"; + pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12"; + pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13"; + pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14"; + pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15"; + pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7"; + pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8"; + pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9"; + pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10"; + pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11"; + pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12"; + pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13"; + pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14"; + pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15"; + pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7"; + pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8"; + pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9"; + pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10"; + pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11"; + pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12"; + pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13"; + pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14"; + pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15"; + eth0_pins = "/pinctrl/eth0/eth0-pins"; + gmac0_miim = "/pinctrl/gmac0/gmac0-miim"; + gmac0_clkinout = "/pinctrl/gmac0/gmac0-clkinout"; + gmac0_rx_bus2 = "/pinctrl/gmac0/gmac0-rx-bus2"; + gmac0_tx_bus2 = "/pinctrl/gmac0/gmac0-tx-bus2"; + gmac0_rgmii_clk = "/pinctrl/gmac0/gmac0-rgmii-clk"; + gmac0_rgmii_bus = "/pinctrl/gmac0/gmac0-rgmii-bus"; + gmac0_ppsclk = "/pinctrl/gmac0/gmac0-ppsclk"; + gmac0_ppstring = "/pinctrl/gmac0/gmac0-ppstring"; + gmac0_ptp_refclk = "/pinctrl/gmac0/gmac0-ptp-refclk"; + gmac0_txer = "/pinctrl/gmac0/gmac0-txer"; + mipicsi0_pwr = "/pinctrl/cam/mipicsi0-pwr"; + mipicsi1_pwr = "/pinctrl/cam/mipicsi1-pwr"; + mipidcphy0_pwr = "/pinctrl/cam/mipidcphy0-pwr"; + mipidphy0_pwr = "/pinctrl/cam/mipidphy0-pwr"; + hp_det = "/pinctrl/headphone/hp-det"; + hym8563_int = "/pinctrl/hym8563/hym8563-int"; + lcd_rst_gpio = "/pinctrl/lcd/lcd-rst-gpio"; + work_leds_gpio = "/pinctrl/leds/work-leds-gpio"; + wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h"; + touch_gpio = "/pinctrl/touch/touch-gpio"; + ts_int_active = "/pinctrl/touch/ts_int_active"; + ts_reset_active = "/pinctrl/touch/ts_reset_active"; + ts_int_suspend = "/pinctrl/touch/ts_int_suspend"; + ts_reset_suspend = "/pinctrl/touch/ts_reset_suspend"; + vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en"; + usbc0_int = "/pinctrl/usb-typec/usbc0-int"; + typec5v_pwren = "/pinctrl/usb-typec/typec5v-pwren"; + uart9_gpios = "/pinctrl/wireless-bluetooth/uart9-gpios"; + bt_reset_gpio = "/pinctrl/wireless-bluetooth/bt-reset-gpio"; + bt_wake_gpio = "/pinctrl/wireless-bluetooth/bt-wake-gpio"; + bt_irq_gpio = "/pinctrl/wireless-bluetooth/bt-irq-gpio"; + wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq"; + pcie20x1_0_clkreqn_m1 = "/pinctrl/pcie/pcie20x1-0-clkreqn-m1"; + usbdrd3_1 = "/usbdrd3_1"; + usbdrd_dwc3_1 = "/usbdrd3_1/usb@fc400000"; + pcie30_phy_grf = "/syscon@fd5b8000"; + pipe_phy1_grf = "/syscon@fd5c0000"; + usbdpphy1_grf = "/syscon@fd5cc000"; + usb2phy1_grf = "/syscon@fd5d4000"; + u2phy1 = "/syscon@fd5d4000/usb2-phy@4000"; + u2phy1_otg = "/syscon@fd5d4000/usb2-phy@4000/otg-port"; + hdptxphy1_grf = "/syscon@fd5e4000"; + spdif_tx5 = "/spdif-tx@fddb8000"; + i2s8_8ch = "/i2s@fddc8000"; + spdif_tx4 = "/spdif-tx@fdde8000"; + i2s6_8ch = "/i2s@fddf4000"; + i2s7_8ch = "/i2s@fddf8000"; + i2s10_8ch = "/i2s@fde00000"; + spdif_rx1 = "/spdif-rx@fde10000"; + spdif_rx2 = "/spdif-rx@fde18000"; + dp1 = "/dp@fde60000"; + dp1_in_vp0 = "/dp@fde60000/ports/port@0/endpoint@0"; + dp1_in_vp1 = "/dp@fde60000/ports/port@0/endpoint@1"; + dp1_in_vp2 = "/dp@fde60000/ports/port@0/endpoint@2"; + dp1_out = "/dp@fde60000/ports/port@1/endpoint"; + hdmi1 = "/hdmi@fdea0000"; + hdmi1_in = "/hdmi@fdea0000/ports/port@0"; + hdmi1_in_vp0 = "/hdmi@fdea0000/ports/port@0/endpoint@0"; + hdmi1_in_vp1 = "/hdmi@fdea0000/ports/port@0/endpoint@1"; + hdmi1_in_vp2 = "/hdmi@fdea0000/ports/port@0/endpoint@2"; + edp1 = "/edp@fded0000"; + edp1_in_vp0 = "/edp@fded0000/ports/port@0/endpoint@0"; + edp1_in_vp1 = "/edp@fded0000/ports/port@0/endpoint@1"; + edp1_in_vp2 = "/edp@fded0000/ports/port@0/endpoint@2"; + edp1_out = "/edp@fded0000/ports/port@1/endpoint"; + hdmirx_ctrler = "/hdmirx-controller@fdee0000"; + pcie3x4 = "/pcie@fe150000"; + pcie3x4_intc = "/pcie@fe150000/legacy-interrupt-controller"; + pcie3x2 = "/pcie@fe160000"; + pcie3x2_intc = "/pcie@fe160000/legacy-interrupt-controller"; + pcie2x1l0 = "/pcie@fe170000"; + pcie2x1l0_intc = "/pcie@fe170000/legacy-interrupt-controller"; + gmac_uio0 = "/uio@fe1b0000"; + gmac0 = "/ethernet@fe1b0000"; + mdio0 = "/ethernet@fe1b0000/mdio"; + gmac0_stmmac_axi_setup = "/ethernet@fe1b0000/stmmac-axi-config"; + gmac0_mtl_rx_setup = "/ethernet@fe1b0000/rx-queues-config"; + gmac0_mtl_tx_setup = "/ethernet@fe1b0000/tx-queues-config"; + sata1 = "/sata@fe220000"; + hdptxphy1 = "/phy@fed70000"; + hdptxphy_hdmi1 = "/hdmiphy@fed70000"; + usbdp_phy1 = "/phy@fed90000"; + usbdp_phy1_dp = "/phy@fed90000/dp-port"; + usbdp_phy1_u3 = "/phy@fed90000/u3-port"; + combphy1_ps = "/phy@fee10000"; + pcie30phy = "/phy@fee80000"; + adc_keys = "/adc-keys"; + backlight = "/backlight"; + bt_sco = "/bt-sco"; + bt_sound = "/bt-sound"; + edp0_sound = "/edp0-sound"; + edp1_sound = "/edp1-sound"; + hdmi0_sound = "/hdmi0-sound"; + hdmi1_sound = "/hdmi1-sound"; + dp0_sound = "/dp0-sound"; + dp1_sound = "/dp1-sound"; + leds = "/leds"; + work_led = "/leds/work"; + spdif_tx0_dc = "/spdif-tx0-dc"; + spdif_tx0_sound = "/spdif-tx0-sound"; + spdif_tx1_dc = "/spdif-tx1-dc"; + spdif_tx1_sound = "/spdif-tx1-sound"; + vcc12v_dcin = "/vcc12v-dcin"; + vcc5v0_sys = "/vcc5v0-sys"; + vcc5v0_usbdcin = "/vcc5v0-usbdcin"; + vcc5v0_usb = "/vcc5v0-usb"; + drm_logo = "/reserved-memory/drm-logo@0"; + drm_cubic_lut = "/reserved-memory/drm-cubic-lut@0"; + ramoops = "/reserved-memory/ramoops@110000"; + minidump_smem = "/reserved-memory/minidump-smem@1f0000"; + minidump_mem = "/reserved-memory/minidump-mem@c000000"; + es8388_sound = "/es8388-sound"; + fan = "/pwm-fan"; + pcie20_avdd0v85 = "/pcie20-avdd0v85"; + pcie20_avdd1v8 = "/pcie20-avdd1v8"; + pcie30_avdd0v75 = "/pcie30-avdd0v75"; + pcie30_avdd1v8 = "/pcie30-avdd1v8"; + sdio_pwrseq = "/sdio-pwrseq"; + rk_headset = "/rk-headset"; + vcc_1v1_nldo_s3 = "/vcc-1v1-nldo-s3"; + vbus5v0_typec = "/vbus5v0-typec"; + vcc3v3_lcd_n = "/vcc3v3-lcd0-n"; + vcc3v3_pcie30 = "/vcc3v3-pcie30"; + vcc5v0_host = "/vcc5v0-host"; + vcc_mipicsi0 = "/vcc-mipicsi0-regulator"; + vcc_mipicsi1 = "/vcc-mipicsi1-regulator"; + vcc_mipidphy0 = "/vcc-mipidcphy0-regulator"; + vcc_mipidcphy0 = "/vcc-mipidcphy0-regulator"; + vcc_3v3_sd_s0 = "/vcc-3v3-sd-s0-regulator"; + wireless_bluetooth = "/wireless-bluetooth"; + wireless_wlan = "/wireless-wlan"; + chosen = "/chosen"; + cspmu = "/cspmu@fd10c000"; + debug = "/debug@fd104000"; + fiq_debugger = "/fiq-debugger"; + minidump = "/minidump"; + }; +}; + +/ { + hvisor_virtio_device { + compatible = "hvisor"; + interrupt-parent = <0x1>; + interrupts = <0x00 0x20 0x01>; + power-domains = <0x06 0x09>, <0x06 0x0a>, <0x06 0x0b>, + <0x06 0x0c>, + <0x06 0x18>, <0x06 0x1a>; + clocks = <0x0f 0x06>, <0x02 0x12d>, <0x02 0x122>, <0x02 0x124>, + <0x02 0x12e>, <0x02 0x123>, <0x02 0x125>, <0x02 0x131>, + <0x0f 0x05>, <0x02 0x115>, <0x02 0x116>, <0x02 0x114>, + <0x02 0x270>, /* VOP: aclk_vop */ + <0x02 0x26f>, /* VOP: hclk_vop */ + <0x02 0x274>, /* VOP+DISP: dclk_vp0 */ + <0x02 0x275>, /* VOP+DISP: dclk_vp1 */ + <0x02 0x276>, /* VOP+DISP: dclk_vp2 */ + <0x02 0x277>, /* VOP+DISP: dclk_vp3 */ + <0x02 0x26e>, /* VOP: pclk_vop */ + <0x02 0x271>, /* VOP: dclk_src_vp0 */ + <0x02 0x272>, /* VOP: dclk_src_vp1 */ + <0x02 0x273>, /* VOP: dclk_src_vp2 */ + <0x02 0x27d>, /* VOP: aclk_dovi */ + <0x02 0x27e>, /* VOP: aclk_vop_div2 */ + <0x02 0x26b>, /* VOP: aclk_vop_root */ + <0x02 0x221>, /* HDMI0: pclk */ + <0x02 0x265>, /* HDMI0: hpd */ + <0x02 0x222>, /* HDMI0: earc */ + <0x02 0x223>, /* HDMI0: hdmitx_ref */ + <0x02 0x246>, /* HDMI0: aud */ + <0x02 0x224>, /* HDMI1: pclk */ + <0x02 0x266>, /* HDMI1: hpd */ + <0x02 0x225>, /* HDMI1: earc */ + <0x02 0x226>, /* HDMI1: hdmitx_ref */ + <0x02 0x24c>, /* HDMI1: aud */ + <0x02 0x2b5>, /* HDPHY0+1: ref */ + <0x02 0x267>, /* HDPHY0: apb */ + <0x02 0x268>; /* HDPHY1: apb */ + clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", + "hclk0", "hclk1", "hclk2", "pclk", + "clk_gpu", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_mali", + "aclk_vop", "hclk_vop", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "pclk_vop", "dclk_src_vp0", + "dclk_src_vp1", "dclk_src_vp2", + "aclk_dovi", "aclk_vop_div2", + "aclk_vop_root", + "hdmi0_pclk", "hdmi0_hpd", + "hdmi0_earc", "hdmi0_hdmitx_ref", + "hdmi0_aud", + "hdmi1_pclk", "hdmi1_hpd", + "hdmi1_earc", "hdmi1_hdmitx_ref", + "hdmi1_aud", + "hdphy_ref", "hdphy0_apb", + "hdphy1_apb"; + resets = <0x02 0x1e6>, <0x02 0x1b0>, <0x02 0x1c0>, + <0x02 0x1e8>, <0x02 0x1b2>, <0x02 0x1c2>, + <0x02 0x349>, /* VOP: axi */ + <0x02 0x348>, /* VOP: ahb */ + <0x02 0x34d>, /* VOP: dclk_vp0 */ + <0x02 0x350>, /* VOP: dclk_vp1 */ + <0x02 0x351>, /* VOP: dclk_vp2 */ + <0x02 0x352>, /* VOP: dclk_vp3 */ + <0x02 0x3d0>, /* HDMI0: ref */ + <0x02 0x49c>, /* HDMI0: hdp */ + <0x02 0x3d7>, /* HDMI1: ref */ + <0x02 0x49d>, /* HDMI1: hdp */ + <0x02 0x48e>, <0x02 0x485>, <0x02 0xc003b>, + <0x02 0xc003c>, <0x02 0xc003d>, <0x02 0x48c>, + <0x02 0x48d>, + <0x02 0x491>, <0x02 0x486>, <0x02 0xc003f>, + <0x02 0xc0040>, <0x02 0xc0041>, <0x02 0x48f>, + <0x02 0x490>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2", + "vop_axi", "vop_ahb", "vop_dclk0", + "vop_dclk1", "vop_dclk2", "vop_dclk3", + "hdmi0_ref", "hdmi0_hdp", + "hdmi1_ref", "hdmi1_hdp", + "hdmiphy0_phy", "hdmiphy0_apb", + "hdmiphy0_init", "hdmiphy0_cmn", + "hdmiphy0_lane", "hdmiphy0_ropll", + "hdmiphy0_lcpll", + "hdmiphy1_phy", "hdmiphy1_apb", + "hdmiphy1_init", "hdmiphy1_cmn", + "hdmiphy1_lane", "hdmiphy1_ropll", + "hdmiphy1_lcpll"; + }; + + // reserve memory for hvisor and GuestOS + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + hvisor@500000 { + no-map; + reg = <0x00 0x00500000 0x00 0x04600000>; + }; + + linux-bootmisc@30000000 { + no-map; + reg = <0x00 0x30000000 0x00 0x10000000>; + // [0x3000_0000, 0x3040_0000), 4 MiB, device-tree-blob + // [0x3040_0000, 0x3340_0000), 48 MiB, kernel + // [0x3340_0000, 0x5000_0000), 204 MiB, free + }; + + linux-memory@100000000 { + no-map; + reg = <0x01 0x00000000 0x01 0xfc000000>; + }; + + zone2-gpu-memory@58000000 { + no-map; + reg = <0x00 0x58000000 0x00 0x80000000>; + }; + }; +}; + +&{/gpu@fb000000} { + status = "disabled"; +}; + +&{/vop@fdd90000} { + status = "disabled"; +}; + +&{/iommu@fdd97e00} { + status = "disabled"; +}; + +&{/syscon@fd5a4000} { + status = "disabled"; +}; + +&{/dmc} { + status = "disabled"; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts new file mode 100644 index 000000000..72781af39 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts @@ -0,0 +1,366 @@ +/dts-v1/; + +/ { + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 XIUOS Board (Zone1-Linux with NPU + VirtIO-SCMI)"; + + memory { + reg = <0x00 0x30000000 0x00 0x10000000>, + <0x01 0x00000000 0x01 0xfc000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + npu_reserved: npu-memory@38000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x38000000 0x00 0x04000000>; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x06>; + }; + + core1 { + cpu = <0x07>; + }; + }; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + phandle = <0x06>; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0x07>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x06 0x07>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + aliases { + }; + + // ========== VirtIO-SCMI (Clock, Reset & Power via VirtIO) ========== + firmware { + scmi { + compatible = "arm,scmi-virtio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1000>; + + scmi_clk: protocol@14 { // clock protocol + reg = <0x14>; + #clock-cells = <0x01>; + }; + + scmi_rst: protocol@16 { // reset protocol + reg = <0x16>; + #reset-cells = <0x01>; + }; + + scmi_pwr: protocol@11 { // power domain protocol + reg = <0x11>; + #power-domain-cells = <0x01>; + }; + }; + }; + + // virtio-mmio for SCMI + virtio_mmio@ff9c0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x24 0x1>; + reg = <0x0 0xff9c0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for blk + virtio_mmio@ff9d0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x21 0x1>; + reg = <0x0 0xff9d0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for serial/console + virtio_mmio@ff9e0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x22 0x1>; + reg = <0x0 0xff9e0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for net + virtio_mmio@ffa00000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x25 0x1>; + reg = <0x0 0xffa00000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // ========== NPU OPP Table ========== + + npu-opp-table { + compatible = "operating-points-v2"; + phandle = <0x70>; + + opp-300000000 { + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8>; + }; + + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8>; + }; + + opp-700000000 { + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60>; + }; + + opp-900000000 { + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500>; + }; + }; + + // ========== GPU OPP Table ========== + + + // ========== GPU ========== + + + // ========== Display Dependencies (GRF) ========== + + pmu0_grf: syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; + reg = <0x00 0xfd588000 0x00 0x1000>; + }; + + /* sys_grf (0xfd58c000) intentionally NOT exposed to this zone: + * system-wide GRF; zone1 has no consumer for it, and probing it as a + * syscon would generate unmapped MMIO accesses (hvisor shuts the zone + * down on unhandled MMIO faults). */ + + + + + + // ========== HDMIPHYs ========== + + + + // ========== VOP + VOP MMU ========== + + + + // ========== HDMI Fixed Clocks ========== + + hclk_vo1_fixed: hclk-vo1-fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + // ========== HDMI0 ========== + + + // ========== HDMI1 ========== + + + + // ========== NPU (no IOMMU mode) ========== + + rknpu: npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x00 0xfdab0000 0x00 0x10000>, + <0x00 0xfdac0000 0x00 0x10000>, + <0x00 0xfdad0000 0x00 0x10000>; + interrupts = <0x00 0x6e 0x04>, + <0x00 0x6f 0x04>, + <0x00 0x70 0x04>; + interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; + // All clocks via SCMI (virtual IDs 0-7, mapped by hvisor DT order) + clocks = <&scmi_clk 0>, + <&scmi_clk 1>, + <&scmi_clk 2>, + <&scmi_clk 3>, + <&scmi_clk 4>, + <&scmi_clk 5>, + <&scmi_clk 6>, + <&scmi_clk 7>; + clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", + "hclk0", "hclk1", "hclk2", "pclk"; + // All resets via SCMI (virtual IDs 0-5) + resets = <&scmi_rst 0>, + <&scmi_rst 1>, + <&scmi_rst 2>, + <&scmi_rst 3>, + <&scmi_rst 4>, + <&scmi_rst 5>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2"; + // Power domains via SCMI (virtual IDs 0-2) + power-domains = <&scmi_pwr 0>, + <&scmi_pwr 1>, + <&scmi_pwr 2>; + power-domain-names = "npu0", "npu1", "npu2"; + // Operating points (via SCMI clock) + operating-points-v2 = <0x70>; + // Reserved memory for DMA (non-IOMMU mode) + memory-region = <&npu_reserved>; + status = "okay"; + }; + + chosen { + bootargs = "earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw"; + stdout-path = "/virtio_mmio@0xff9e0000"; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts new file mode 100644 index 000000000..96a2f56fb --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts @@ -0,0 +1,549 @@ +/dts-v1/; + +/ { + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 XIUOS Board (Zone2-Linux with GPU + VirtIO-SCMI)"; + + memory { + reg = <0x00 0x58000000 0x00 0x80000000>; + device_type = "memory"; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x04>; + }; + core1 { + cpu = <0x05>; + }; + }; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + phandle = <0x04>; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0x05>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x04 0x05>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + aliases { + }; + + // ========== VirtIO-SCMI ========== + firmware { + scmi { + compatible = "arm,scmi-virtio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1000>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + }; + + scmi_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <0x01>; + }; + + scmi_pwr: protocol@11 { + reg = <0x11>; + #power-domain-cells = <0x01>; + }; + }; + }; + + // virtio-mmio for SCMI (zone2 IPA, mapped by hvisor) + virtio_mmio@ffa10000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x46 0x1>; + reg = <0x0 0xffa10000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for blk + virtio_mmio@ffa20000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x47 0x1>; + reg = <0x0 0xffa20000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for serial/console + virtio_mmio@ffa30000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x48 0x1>; + reg = <0x0 0xffa30000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for net + virtio_mmio@ffa50000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x49 0x1>; + reg = <0x0 0xffa50000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + + // ========== VOP/HDMI Dependencies ========== + // + // IMPORTANT: SYS_GRF (0xfd58c000) and PMU_GRF (0xfd588000) are + // intentionally NOT exposed to this zone. They are system-wide GRFs: + // GPIO0/GPIO1 IOMUX lives in PMU_GRF, and zone0's SPI2 (PMIC rk806) + // uses GPIO0 pins — passing these GRFs through let a guest driver + // clobber the SPI2 pinmux, breaking PMIC communication. + // + // VOP/HDMI drivers access "rockchip,grf" / "rockchip,pmu" / + // "rockchip,ioc-grf" regmaps unconditionally (vop2_grf_readl has no + // NULL guard), so instead of removing the properties we point them at + // VO1_GRF (0xfd5a8000), which IS passed through. VO1_GRF is + // display-only: its valid registers live at low offsets (0x0004-0x0024) + // while the drivers' sys-grf offsets (0x0304/0x0308/0x0384) land in + // undefined space inside the VO1_GRF block — reads return 0, writes + // are dropped by the hardware. GRF blocks are decoded at block + // granularity, so these accesses cannot hang the bus. + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x00 0xfd5a4000 0x00 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x00 0xfd5a8000 0x00 0x1000>; + }; + + hdptx_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x00 0xfd5e0000 0x00 0x1000>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x00 0xfd5f0000 0x00 0x10000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x00 0xfd58c000 0x00 0x1000>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <&ioc>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + hdmi { + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = <4 17 5 &pcfg_pull_none>; + }; + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = <1 5 5 &pcfg_pull_none>; + }; + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = <4 15 5 &pcfg_pull_none_drv_level_5_smt>; + }; + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = <4 16 5 &pcfg_pull_none_drv_level_1_smt>; + }; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + }; + + /* + * VOP IOMMU (rk_iommu, passthrough). Without it the VOP has no + * scatter-gather support: rockchip_gem_prime_import_sg_table then + * requires physically contiguous buffers, which the Mali GPU (own + * MMU) does not provide -> gbm front buffer import fails. With the + * IOMMU the DRM core uses the iommu map path instead. + */ + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdd97e00 0x00 0x100>, + <0x00 0xfdd97f00 0x00 0x100>; + interrupts = <0x00 0x9c 0x04>; + interrupt-names = "vop_mmu"; + clocks = <&scmi_clk 4>, <&scmi_clk 5>; + clock-names = "aclk", "iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + /* + * hdmi0_phy_pll = clk_hdmiphy_pixel0, the HDPTX PLL output + * clock registered LOCALLY by this zone's phy driver + * (fed60000 is passed through). NOT an SCMI virtual clock: + * the PLL registers live in this zone. vop2_extend_clk_init + * looks it up on the DRM master device (this node) by name, + * which lets mode_valid accept HDMI modes without the v0pll + * parent check. fw_devlink (clocks phandle) makes sure the + * phy probes before this master. + */ + clocks = <&hdmiphy0>; + clock-names = "hdmi0_phy_pll"; + status = "okay"; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x00 0xfdd90000 0x00 0x4200>, + <0x00 0xfdd95000 0x00 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = <0x00 0x9c 0x04>; + clocks = <&scmi_clk 4>, <&scmi_clk 5>, + <&scmi_clk 6>, <&scmi_clk 7>, + <&scmi_clk 8>, <&scmi_clk 9>, + <&scmi_clk 10>, <&scmi_clk 11>, + <&scmi_clk 12>, <&scmi_clk 13>, + <&scmi_clk 14>, <&scmi_clk 15>, + <&scmi_clk 16>; + clock-names = "aclk_vop", "hclk_vop", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "pclk_vop", "dclk_src_vp0", + "dclk_src_vp1", "dclk_src_vp2", + "aclk_dovi", "aclk_vop_div2_src", + "aclk_vop_root"; + resets = <&scmi_rst 0>, <&scmi_rst 1>, + <&scmi_rst 2>, <&scmi_rst 3>, + <&scmi_rst 4>, <&scmi_rst 5>; + reset-names = "axi", "ahb", "dclk_vp0", + "dclk_vp1", "dclk_vp2", "dclk_vp3"; + power-domains = <&scmi_pwr 1>; + iommus = <&vop_mmu>; + /* sys_grf/pmu/ioc redirected to vo1_grf — see note above */ + rockchip,grf = <&vo1_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&vo1_grf>; + rockchip,ioc-grf = <&vo1_grf>; + status = "okay"; + + vop_out: ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + /* + * Plane assignment strategy (rk3588 win phys ids: + * Cluster0=0 Cluster1=1 Esmart0=2 Esmart1=3 + * Cluster2=6 Cluster3=7 Esmart2=8 Esmart3=9). + * + * ALL windows are assigned to VP0 (0x3cf) - the only + * VP that has a connector and ever gets driven. + * VP1/VP2/VP3 are left with mask 0 and are never + * registered as CRTCs. + * + * The vop2 driver requires every window to be + * assigned to exactly one VP (the plane masks must + * sum to 0x3cf), otherwise it discards the DTS + * assignment and uses its default (VP0 = 0x145, + * which adds Cluster0/2 + Esmart2 to VP0). + * + * Why everything on VP0: u-boot leaves the VOP + * hardware in a dirty state - it drives the HDMI + * logo on VP0 and enables arbitrary windows (seen: + * Esmart1/Esmart3 with a stale DMA address + * 0xedeb8000). Those stale windows are only + * disabled by vop2_disable_all_planes_for_crtc(), + * which iterates vp->win_mask (= plane mask) and is + * only invoked when the new mode differs from the + * current hardware mode (vop2_crtc_mode_update). + * If a stale window is NOT in VP0's mask it can + * never be disabled: it keeps scanning the stale + * address through the IOMMU, faults, and shows a + * green screen. Putting every window on VP0 makes + * any mode switch clean all of them. + */ + vp0: port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x3cf>; /* all 12 windows */ + rockchip,primary-plane = <0x02>; /* Esmart0 */ + + vp0_out_hdmi0: endpoint@0 { + reg = <0x00>; + remote-endpoint = <&hdmi0_in>; + }; + }; + vp1: port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x00>; + }; + vp2: port@2 { + reg = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x00>; + }; + }; + }; + + hdmiphy0: hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <&scmi_clk 22>, <&scmi_clk 23>; + clock-names = "ref", "apb"; + clock-output-names = "clk_hdmiphy_pixel0"; + #clock-cells = <0x00>; + resets = <&scmi_rst 8>, <&scmi_rst 9>, <&scmi_rst 10>, + <&scmi_rst 11>, <&scmi_rst 12>, <&scmi_rst 13>, + <&scmi_rst 14>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptx_grf>; + #phy-cells = <0x00>; + status = "okay"; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfde80000 0x00 0x10000>, + <0x00 0xfde90000 0x00 0x10000>; + interrupts = <0x00 0xa9 0x04>, <0x00 0xaa 0x04>, + <0x00 0xab 0x04>, <0x00 0xac 0x04>, + <0x00 0x168 0x04>; + clocks = <&scmi_clk 17>, <&scmi_clk 18>, + <&scmi_clk 19>, <&scmi_clk 20>, + <&scmi_clk 21>, <&scmi_clk 7>, + <&scmi_clk 8>, <&scmi_clk 9>, + <&scmi_clk 10>, <&hdmiphy0>; + clock-names = "pclk", "hpd", "earc", + "hdmitx_ref", "aud", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "link_clk"; + resets = <&scmi_rst 6>, <&scmi_rst 7>; + reset-names = "ref", "hdp"; + power-domains = <&scmi_pwr 2>; + reg-io-width = <0x04>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdmiphy0>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + hdmi0_in: endpoint@0 { + reg = <0x00>; + remote-endpoint = <&vp0_out_hdmi0>; + }; + }; + }; + }; + + // ========== GPU Dependencies ========== + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x00 0xfd5a0000 0x00 0x100>; + phandle = <0x66>; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x00 0xfdb30000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + // ========== GPU OPP Table ========== + + gpu-opp-table { + compatible = "operating-points-v2"; + phandle = <0x71>; + + opp-300000000 { + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8>; + }; + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8>; + }; + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0>; + }; + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850>; + }; + }; + + // ========== GPU ========== + + gpu@fb000000 { + compatible = "arm,mali-valhall"; + reg = <0x00 0xfb000000 0x00 0x200000>; + interrupts = <0x00 0x5e 0x04>, + <0x00 0x5d 0x04>, + <0x00 0x5c 0x04>; + interrupt-names = "GPU", "MMU", "JOB"; + /* + * SCMI virtual IDs 0-3 mapped via clock_ids [8,9,10,11]: + * 0 → hvisor clock[8] = clk_gpu + * 1 → hvisor clock[9] = clk_gpu_coregroup + * 2 → hvisor clock[10] = clk_gpu_stacks + * 3 → hvisor clock[11] = clk_mali + */ + clocks = <&scmi_clk 0>, <&scmi_clk 1>, + <&scmi_clk 2>, <&scmi_clk 3>; + clock-names = "clk_mali", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_gpu"; + operating-points-v2 = <0x71>; + /* + * SCMI virtual ID 0 → power_ids[0] = 3 → hvisor power[3] = 0x0c + */ + power-domains = <&scmi_pwr 0>; + status = "okay"; + }; + + chosen { + bootargs = "earlycon=virtio,mmio,0xffa30000 console=hvc0 root=/dev/vda rootwait rw"; + stdout-path = "/virtio_mmio@0xffa30000"; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig b/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/sysoul_x3300-scmi/linker.ld b/platform/aarch64/sysoul_x3300-scmi/linker.ld new file mode 100644 index 000000000..b287362b6 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/linker.ld @@ -0,0 +1,68 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x500000; +CPU_NUM = 8; + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + .boot : { + *(.text.boot) + *(.data.boot) + } + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + _percpu_start = .; + _percpu_end = _percpu_start + SIZEOF(.percpu); + .percpu 0x0 (NOLOAD) : AT(_percpu_start) { + _percpu_load_start = .; + *(.percpu .percpu.*) + _percpu_load_end = .; + . = _percpu_load_start + ALIGN(64) * CPU_NUM; + } + . = _percpu_end; + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} + +__hv_end = __core_end + HV_EXTENDED_SIZE; diff --git a/platform/aarch64/sysoul_x3300-scmi/platform.mk b/platform/aarch64/sysoul_x3300-scmi/platform.mk new file mode 100644 index 000000000..e68880956 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/platform.mk @@ -0,0 +1,8 @@ +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt update && sudo apt install u-boot-tools; \ + fi && \ + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \ + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x00500000 \ + -e 0x00500000 -d $(hvisor_bin).tmp $(hvisor_bin) && \ + rm -rf $(hvisor_bin).tmp \ No newline at end of file