Execute accepted CVA6 custom-3 encodings through the standard tandem simulation flow

[metasmile]

Summary

Follow-up to #43. The CVA6 report currently verifies the custom-3 encoding space at the model level: the fixture is derived from the hardware decoder mask table (commit 6544a714c), and the Spike backend re-checks the constraint model and word assembly in C. What is not yet done is executing the accepted encodings on the actual CVA6 core through the standard verification flow.

Goal

Close the loop between encoding-space classification and actual execution: take the 196,608 decoder-accepted custom-3 encodings (or a representative subset) and run them through the CVA6 standard verification environment, confirming the core accepts them.

Standard flow to use

• CVA6 simulation driver: verif/sim/cva6.py
• Simulator modes: veri-testharness (Verilator with corev_apu testharness), vcs-testharness, vcs-uvm
• Tandem reference: DV_SIMULATORS=veri-testharness,spike with trace comparison summarized in iss_regr.log
• Regression suites: riscv-dv, riscv-arch-test, riscv-compliance, riscv-tests
• Tutorial reference: https://raw.githubusercontent.com/bsc-loca/cva6/refs/heads/master/tutorials/running_sim.md

Open engineering questions

1. Custom-3 opcodes are illegal in the base RISC-V ISA, so Spike cannot execute them as-is. The tandem trace comparison needs the coprocessor behavior represented in the reference model, or the comparison must be scoped to the non-custom portion while the custom encodings are validated on the RTL testharness alone (assert issue_ready/accept from the coprocessor).
2. How to batch 196,608 encodings into directed assembly tests (ev already packs valid rows into a single ELF for its own Spike backend; a similar generator can emit directed cva6.py tests).
3. The DV/decoder divergence finding from Structural enumeration correctness and verification claim accuracy #43 (the DV class generates CUS_U_ADD, CUS_S_ADD, CUS_ADD_MULTI at funct3=000 and CUS_EXC at funct3=010 that the reference decoder rejects) can be validated empirically in this flow.
4. Which target variant to run first (cv32a60x, cv64a6_imafdc_sv39) and whether the cvxif_example coprocessor must be enabled in the build.

Definition of done

• The decoder-accepted encoding set from the fixture is exercised on the RTL testharness and the coprocessor acceptance is confirmed.
• The tandem flow reports no unexpected divergence for the portions it can compare.
• Results are added to the CVA6 master report (docs/cva6.qmd) as an execution-validation section.