Issues

• [BUG] Sqrt/Div operation is processed without in_ready_o

  openhwfoundation/cvfpu#183 · Filter by author nguyen-vu-axiomise opened on Aug 21, 2026

• [BUG] Underflow flag incorrect on some edge cases when ADDMUL unit is set to MERGED

  openhwfoundation/cvfpu#182 · Filter by author Axionix77 opened on Aug 10, 2026
  1

• [Bug] DivSqrt units do not support rounding modes ROD and DYN.

  openhwfoundation/cvfpu#181 · Filter by author ashraf629 opened on Aug 5, 2026

• PULP DIVSQRT output handshake stability bug

  openhwfoundation/cvfpu#180 · Filter by author baselkelziye opened on Aug 2, 2026
  2

• DivSqrtSel=PULP gives wrong result vs DivSqrtSel=THMULTI for RUP/RDN/RMM

  openhwfoundation/cvfpu#178 · Filter by author hailinzeng opened on Jul 27, 2026

• [BUG] BFloat16: Special Underflow case in DIV

  openhwfoundation/cvfpu#169 · Filter by author Whitenix opened on May 19, 2026
  5

• Document 'vendorization' process for this repo

  Documentation
  openhwfoundation/cvfpu#159 · Filter by author MikeOpenHWGroup opened on Mar 5, 2026
  

• PULP divsqrt unit does not produce correct results and stalls the unit with busy signal high

  openhwfoundation/cvfpu#152 · Filter by author wedeha opened on Aug 14, 2025
  4

• Undefined width of reg_ena_i at fpnew_divsqrt_multi

  openhwfoundation/cvfpu#144 · Filter by author redpanda3 opened on Nov 14, 2024
  2

• Out of bound signals generated by yosys

  openhwfoundation/cvfpu#143 · Filter by author redpanda3 opened on Nov 6, 2024

• [BUG] NX flag not correctly triggered in specific cases

  openhwfoundation/cvfpu#139 · Filter by author fly-1011 opened on Aug 22, 2024
  8

• [BUG] Incorrectly set fflags: An underflow exception is triggered when the computed result is an exact subnormal number.

  openhwfoundation/cvfpu#121 · Filter by author fly-1011 opened on May 18, 2024
  3

• [BUG] Incorrect fflags Set When Using fdiv Instruction to Divide by Infinity

  openhwfoundation/cvfpu#120 · Filter by author fly-1011 opened on May 15, 2024
  3

• SQRT operation for FP16ALT only works when all op[n] lanes are assigned to the same input

  openhwfoundation/cvfpu#117 · Filter by author selimsandal opened on May 12, 2024
  1

• [BUG] Unexpected Rounding Behavior During fsqrt.d Execution

  openhwfoundation/cvfpu#112 · Filter by author youzi27 opened on Apr 22, 2024
  2

• [BUG] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity

  openhwfoundation/cvfpu#111 · Filter by author youzi27 opened on Apr 22, 2024
  2

• [BUG] Incorrect Result from 'fdiv' Operation Leading to Negative Infinity Instead of Smallest Negative Number

  openhwfoundation/cvfpu#110 · Filter by author youzi27 opened on Apr 22, 2024
  2

• how complicated would it be add FP8 E3M4 and E2M5 support to this IP?

  openhwfoundation/cvfpu#105 · Filter by author muzafferkal opened on Nov 2, 2023
  2

• Is it possible to do BF16*int8 + int8 using this IP ? #103

  openhwfoundation/cvfpu#104 · Filter by author muzafferkal opened on Nov 2, 2023

• Bug report: fdiv.s taking two NaN may return a valid number and is not always the consequence of a wrong rounding

  openhwfoundation/cvfpu#85 · Filter by author flaviens opened on Apr 17, 2023

• Bug report: FSQRT of non-canonical NaN gives valid large floats

  openhwfoundation/cvfpu#84 · Filter by author flaviens opened on Apr 17, 2023

• Bug report: Under some microarchitectural circumstances, NAN conversion from simple to double precision gives wrong result

  openhwfoundation/cvfpu#77 · Filter by author flaviens opened on Mar 6, 2023

• Bug report: Floating conversion from double to unsigned int may provide wrong result

  openhwfoundation/cvfpu#76 · Filter by author flaviens opened on Mar 5, 2023

• Bug report: Floating conversion from double to simple infinity sets a lot of ones in the mantissa

  openhwfoundation/cvfpu#75 · Filter by author flaviens opened on Mar 5, 2023

• Narrowing converting instruction mismatch issue for number infinity

  openhwfoundation/cvfpu#69 · Filter by author Shafi10x opened on Jan 23, 2023
  3