From 73cd8905ff7c949af4b7a20fe60208e5792022c8 Mon Sep 17 00:00:00 2001 From: pofa10 Date: Fri, 11 Sep 2026 13:54:10 +0330 Subject: [PATCH 1/2] Add XDC (Xilinx Design Constraints) UDL (Dark and Light themes) --- UDL-samples/XDC_example.xdc | 85 +++++++++++++++++++++++++++++++++++++ UDLs/XDC_DarkTheme.xml | 65 ++++++++++++++++++++++++++++ UDLs/XDC_LightTheme.xml | 65 ++++++++++++++++++++++++++++ udl-list.json | 20 +++++++++ udl-list.md | 2 + 5 files changed, 237 insertions(+) create mode 100644 UDL-samples/XDC_example.xdc create mode 100644 UDLs/XDC_DarkTheme.xml create mode 100644 UDLs/XDC_LightTheme.xml diff --git a/UDL-samples/XDC_example.xdc b/UDL-samples/XDC_example.xdc new file mode 100644 index 0000000..0f90f9d --- /dev/null +++ b/UDL-samples/XDC_example.xdc @@ -0,0 +1,85 @@ +############################################################################### +# Example XDC (Xilinx Design Constraints) File for Notepad++ UDL Testing +# Demonstrates syntax highlighting for clocks, I/O pins, timing, and Tcl script +############################################################################### + +# ----------------------------------------------------------------------------- +# 1. Device Configuration & Operating Voltage +# ----------------------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] + +# ----------------------------------------------------------------------------- +# 2. Primary Clocks & Generated Clocks +# ----------------------------------------------------------------------------- +# 100 MHz System Clock (Period = 10.000 ns, 50% Duty Cycle) +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} [get_ports sys_clk] + +# 200 MHz Differential Reference Clock +create_clock -period 5.000 -name ref_clk_200mhz [get_ports clk_200_p] + +# Generated Clock from MMCM / PLL output +create_generated_clock -name clk_core \ + -source [get_pins u_clk_wiz/inst/mmcm_adv_inst/CLKIN1] \ + -divide_by 2 \ + [get_pins u_clk_wiz/inst/mmcm_adv_inst/CLKOUT0] + +# ----------------------------------------------------------------------------- +# 3. Asynchronous Clock Groups +# ----------------------------------------------------------------------------- +set_clock_groups -asynchronous \ + -group [get_clocks sys_clk_pin] \ + -group [get_clocks -include_replicated_objects clk_core] + +# ----------------------------------------------------------------------------- +# 4. Pin Placement & I/O Standards (set_property -dict) +# ----------------------------------------------------------------------------- +# System Clock and Reset +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports sys_clk] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports rst_n] + +# LEDs (Active High, 3.3V LVCMOS, Slew Rate and Drive Strength) +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] + +# High-speed Differential I/O (TMDS / LVDS) +set_property -dict {PACKAGE_PIN D14 IOSTANDARD TMDS_33} [get_ports tmds_clk_p] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD TMDS_33} [get_ports tmds_clk_n] + +# ----------------------------------------------------------------------------- +# 5. Timing Constraints: Input/Output Delays & Exceptions +# ----------------------------------------------------------------------------- +# Setup & Hold constraints on external SPI bus +set_input_delay -clock [get_clocks sys_clk_pin] -max 3.500 [get_ports spi_miso] +set_input_delay -clock [get_clocks sys_clk_pin] -min 0.500 [get_ports spi_miso] +set_output_delay -clock [get_clocks sys_clk_pin] -max 2.000 [get_ports spi_mosi] + +# False paths for asynchronous reset & static user switches +set_false_path -from [get_ports rst_n] +set_false_path -to [get_ports {led[*]}] + +# Multicycle path for slow multi-cycle arithmetic logic +set_multicycle_path 2 -setup -from [get_cells {u_alu/reg_a_reg[*]}] -to [get_cells {u_alu/result_reg[*]}] +set_multicycle_path 1 -hold -from [get_cells {u_alu/reg_a_reg[*]}] -to [get_cells {u_alu/result_reg[*]}] + +# ----------------------------------------------------------------------------- +# 6. Vivado Synthesis / Implementation Properties +# ----------------------------------------------------------------------------- +set_property DONT_TOUCH true [get_cells u_core/u_crypto_core] +set_property ASYNC_REG true [get_cells -hier -filter {NAME =~ *sync_reg[0]* || NAME =~ *sync_reg[1]*}] +set_property RAM_STYLE block [get_cells u_fifo/u_ram/ram_reg] + +# ----------------------------------------------------------------------------- +# 7. Tcl Scripting Constructs inside XDC +# ----------------------------------------------------------------------------- +set board_rev "rev2" +puts "Applying constraints for board revision: $board_rev" + +if {$board_rev == "rev2"} { + set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports uart_rx] +} else { + set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports uart_rx] +} diff --git a/UDLs/XDC_DarkTheme.xml b/UDLs/XDC_DarkTheme.xml new file mode 100644 index 0000000..918d1f0 --- /dev/null +++ b/UDLs/XDC_DarkTheme.xml @@ -0,0 +1,65 @@ + + + + + + + + + 00# 01 02 03 04 + + + + + + + + [ ] { } + + + + + + + + + + + get_ports get_pins get_cells get_nets get_clocks get_sites get_bel_sites get_iobanks get_package_pins get_debug_cores get_debug_ports get_slrs get_pblocks get_nodes get_wires get_shapes get_files get_drc_violations all_inputs all_outputs all_clocks all_registers all_ffs all_latches all_rams current_design current_instance filter sizeof from_structure + -dict -filter -name -period -waveform -group -asynchronous -logically_exclusive -physically_exclusive -from -to -through -fall -rise -fall_from -rise_from -fall_to -rise_to -fall_through -rise_through -max -min -add_delay -clock -clock_fall -source -edges -edge_shift -divide_by -multiply_by -invert -hierarchical -include_replicated_objects -quiet -verbose -objects -setup -hold -start -end -combinational -datapath_only -cells -pins -nets -ports -clocks -match_style -case -regexp -nocase -of_objects + set unset puts expr if else elseif for foreach while break continue proc return string list lindex llength lappend lrange linsert lreplace lsearch lsort concat catch source info error eval global upvar incr format split join + false true FALSE TRUE yes no YES NO none NONE high low HIGH LOW unconstrained UNCONSTRAINED rise fall min max setup hold FAST SLOW fixed FIXED unplaced UNPLACED + set_property get_property reset_property create_clock create_generated_clock set_clock_groups set_clock_uncertainty set_clock_latency set_clock_sense set_input_delay set_output_delay set_false_path set_max_delay set_min_delay set_multicycle_path set_case_analysis set_disable_timing set_input_jitter set_system_jitter set_external_delay group_path set_operating_conditions set_data_check set_param create_pblock add_cells_to_pblock resize_pblock create_debug_core create_debug_port connect_debug_port set_units set_hierarchy_separator set_max_fanout set_max_area + PACKAGE_PIN IOSTANDARD DIFF_TERM DIFF_TERM_ADV SLEW DRIVE PULLUP PULLDOWN KEEPER IN_TERM OFFCHIP_TERM LOC BEL DONT_TOUCH MARK_DEBUG ASYNC_REG RAM_STYLE ROM_STYLE CLOCK_DEDICATED_ROUTE CONFIG_VOLTAGE CFGBVS CONFIG_MODE PROHIBIT LUTNM HLUTNM EQUIVALENT_IO POST_CRC DCI_CASCADE VCCAUX_IO IOB SHREG_EXTRACT OPT_MODIFIED + LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL SSTL15 SSTL15_R SSTL135 SSTL135_R SSTL18_I SSTL18_II DIFF_SSTL15 DIFF_SSTL15_R DIFF_SSTL135 DIFF_SSTL135_R DIFF_SSTL18_I DIFF_SSTL18_II TMDS_33 LVDS LVDS_25 SUB_LVDS SLVS_400_18 SLVS_400_25 HSTL_I HSTL_II DIFF_HSTL_I DIFF_HSTL_II PCI33_3 MOBILE_DDR + + 00" 01\ 02" 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/UDLs/XDC_LightTheme.xml b/UDLs/XDC_LightTheme.xml new file mode 100644 index 0000000..424b525 --- /dev/null +++ b/UDLs/XDC_LightTheme.xml @@ -0,0 +1,65 @@ + + + + + + + + + 00# 01 02 03 04 + + + + + + + + [ ] { } + + + + + + + + + + + get_ports get_pins get_cells get_nets get_clocks get_sites get_bel_sites get_iobanks get_package_pins get_debug_cores get_debug_ports get_slrs get_pblocks get_nodes get_wires get_shapes get_files get_drc_violations all_inputs all_outputs all_clocks all_registers all_ffs all_latches all_rams current_design current_instance filter sizeof from_structure + -dict -filter -name -period -waveform -group -asynchronous -logically_exclusive -physically_exclusive -from -to -through -fall -rise -fall_from -rise_from -fall_to -rise_to -fall_through -rise_through -max -min -add_delay -clock -clock_fall -source -edges -edge_shift -divide_by -multiply_by -invert -hierarchical -include_replicated_objects -quiet -verbose -objects -setup -hold -start -end -combinational -datapath_only -cells -pins -nets -ports -clocks -match_style -case -regexp -nocase -of_objects + set unset puts expr if else elseif for foreach while break continue proc return string list lindex llength lappend lrange linsert lreplace lsearch lsort concat catch source info error eval global upvar incr format split join + false true FALSE TRUE yes no YES NO none NONE high low HIGH LOW unconstrained UNCONSTRAINED rise fall min max setup hold FAST SLOW fixed FIXED unplaced UNPLACED + set_property get_property reset_property create_clock create_generated_clock set_clock_groups set_clock_uncertainty set_clock_latency set_clock_sense set_input_delay set_output_delay set_false_path set_max_delay set_min_delay set_multicycle_path set_case_analysis set_disable_timing set_input_jitter set_system_jitter set_external_delay group_path set_operating_conditions set_data_check set_param create_pblock add_cells_to_pblock resize_pblock create_debug_core create_debug_port connect_debug_port set_units set_hierarchy_separator set_max_fanout set_max_area + PACKAGE_PIN IOSTANDARD DIFF_TERM DIFF_TERM_ADV SLEW DRIVE PULLUP PULLDOWN KEEPER IN_TERM OFFCHIP_TERM LOC BEL DONT_TOUCH MARK_DEBUG ASYNC_REG RAM_STYLE ROM_STYLE CLOCK_DEDICATED_ROUTE CONFIG_VOLTAGE CFGBVS CONFIG_MODE PROHIBIT LUTNM HLUTNM EQUIVALENT_IO POST_CRC DCI_CASCADE VCCAUX_IO IOB SHREG_EXTRACT OPT_MODIFIED + LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL SSTL15 SSTL15_R SSTL135 SSTL135_R SSTL18_I SSTL18_II DIFF_SSTL15 DIFF_SSTL15_R DIFF_SSTL135 DIFF_SSTL135_R DIFF_SSTL18_I DIFF_SSTL18_II TMDS_33 LVDS LVDS_25 SUB_LVDS SLVS_400_18 SLVS_400_25 HSTL_I HSTL_II DIFF_HSTL_I DIFF_HSTL_II PCI33_3 MOBILE_DDR + + 00" 01\ 02" 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/udl-list.json b/udl-list.json index c8cdee8..fac5351 100644 --- a/udl-list.json +++ b/udl-list.json @@ -3980,6 +3980,26 @@ "autoCompletion": "XC", "autoCompletionAuthor": "generate_ac.py" }, + { + "id-name": "XDC_DarkTheme", + "display-name": "XDC_DarkTheme", + "version": "v1.0", + "sample": "XDC_sample.xdc", + "repository": "https://raw.githubusercontent.com/pofa10/XDC_for_NotepadPP/master/UDLs/XDC_DarkTheme.xml", + "description": "Xilinx Design Constraints (XDC) syntax highlighting for Dark Theme", + "author": "Pourya Farrokhi ", + "homepage": "https://github.com/pofa10/XDC_for_NotepadPP" + }, + { + "id-name": "XDC_LightTheme", + "display-name": "XDC_LightTheme", + "version": "v1.0", + "sample": "XDC_sample.xdc", + "repository": "https://raw.githubusercontent.com/pofa10/XDC_for_NotepadPP/master/UDLs/XDC_LightTheme.xml", + "description": "Xilinx Design Constraints (XDC) syntax highlighting for Light Theme", + "author": "Pourya Farrokhi ", + "homepage": "https://github.com/pofa10/XDC_for_NotepadPP" + }, { "id-name": "yang_by-gribok", "display-name": "YANG", diff --git a/udl-list.md b/udl-list.md index bdd317c..1ec66c2 100644 --- a/udl-list.md +++ b/udl-list.md @@ -395,6 +395,8 @@ | [WSH Panel Mod](./UDLs/JScript-WSH-PanelMod_byLSI-N.xml) | [LSI N](mailto:p774lsi@gmail.com) | WSH Panel Mod | | [X3D](./UDLs/X3D_ClassicEncoding_byJordiRCardona.xml) | [Jordi R Cardona ](http://sourceforge.net/projects/nppx3d) | X3D | | [XC=BASIC 3](./UDLs/xcbasic3_byAlanBourke.xml) | Alan Bourke | XC=BASIC 3 syntax highlighting | +| [XDC_DarkTheme](https://raw.githubusercontent.com/pofa10/XDC_for_NotepadPP/master/UDLs/XDC_DarkTheme.xml) | [Pourya Farrokhi](https://github.com/pofa10/XDC_for_NotepadPP) | Xilinx Design Constraints (XDC) syntax highlighting for Dark Theme | +| [XDC_LightTheme](https://raw.githubusercontent.com/pofa10/XDC_for_NotepadPP/master/UDLs/XDC_LightTheme.xml) | [Pourya Farrokhi](https://github.com/pofa10/XDC_for_NotepadPP) | Xilinx Design Constraints (XDC) syntax highlighting for Light Theme | | [XMOS xCORE XC Programming Language](./UDLs/XMOS-xCORE-XC_by-johned02.xml) | [johned02](mailto:johned02@users.sourceforge.net) | XMOS xCORE XC Programming Language | | [YANG](https://raw.githubusercontent.com/gribok/notepad-plus-plus-yang-language/master/yang_by-gribok.xml) | [gribok](https://github.com/gribok/notepad-plus-plus-yang-language) | YANG Data Modeling Language | | [YARA](./UDLs/YARA_byM0N4.xml) | [m0n4](https://github.com/m0n4) | YARA syntax highlighting for Notepad++. | From c74d9ed087129c1f1f312558f41c868e31eb0ef7 Mon Sep 17 00:00:00 2001 From: pofa10 Date: Fri, 11 Sep 2026 14:05:16 +0330 Subject: [PATCH 2/2] Fix sample filename to match udl-list.json --- UDL-samples/{XDC_example.xdc => XDC_sample.xdc} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename UDL-samples/{XDC_example.xdc => XDC_sample.xdc} (100%) diff --git a/UDL-samples/XDC_example.xdc b/UDL-samples/XDC_sample.xdc similarity index 100% rename from UDL-samples/XDC_example.xdc rename to UDL-samples/XDC_sample.xdc