diff --git a/board/drivers/interrupts.h b/board/drivers/interrupts.h
index c404e43d22f..e458e44856a 100644
--- a/board/drivers/interrupts.h
+++ b/board/drivers/interrupts.h
@@ -74,6 +74,7 @@ void init_interrupts(bool check_rate_limit){
 
   for(uint16_t i=0U; i<NUM_INTERRUPTS; i++){
     interrupts[i].handler = unused_interrupt_handler;
+    NVIC_SetPriority((IRQn_Type)i, 1U);
   }
 
   // Init interrupt timer for a 1s interval
diff --git a/board/drivers/spi.h b/board/drivers/spi.h
index 2e992d907f2..49319c35871 100644
--- a/board/drivers/spi.h
+++ b/board/drivers/spi.h
@@ -225,9 +225,10 @@ void spi_rx_done(void) {
     spi_state = SPI_STATE_HEADER_NACK;
     response_len = 1U;
   }
-  llspi_miso_dma(spi_buf_tx, response_len);
-
+  __disable_irq();
   spi_state = next_rx_state;
+  llspi_miso_dma(spi_buf_tx, response_len);
+  __enable_irq();
   if (!checksum_valid) {
     spi_error_count += 1U;
   }
diff --git a/board/stm32h7/llspi.h b/board/stm32h7/llspi.h
index 25a7c76e06d..b817a693c67 100644
--- a/board/stm32h7/llspi.h
+++ b/board/stm32h7/llspi.h
@@ -85,6 +85,9 @@ void llspi_init(void) {
   REGISTER_INTERRUPT(DMA2_Stream2_IRQn, DMA2_Stream2_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
   REGISTER_INTERRUPT(DMA2_Stream3_IRQn, DMA2_Stream3_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
 
+  NVIC_SetPriority(SPI4_IRQn, 0U);
+  NVIC_SetPriority(DMA2_Stream3_IRQn, 0U);
+
   // Setup MOSI DMA
   register_set(&(DMAMUX1_Channel10->CCR), 83U, 0xFFFFFFFFU);
   register_set(&(DMA2_Stream2->CR), (DMA_SxCR_MINC | DMA_SxCR_TCIE), 0x1E077EFEU);
diff --git a/board/sys/critical.h b/board/sys/critical.h
index 70c143f7012..8088c6e88de 100644
--- a/board/sys/critical.h
+++ b/board/sys/critical.h
@@ -7,6 +7,7 @@ static volatile bool interrupts_enabled = false;
 
 void enable_interrupts(void) {
   interrupts_enabled = true;
+  __set_BASEPRI(0U);
   __enable_irq();
 }
 
diff --git a/board/sys/sys.h b/board/sys/sys.h
index fe5527a0c72..a32dddfb0cf 100644
--- a/board/sys/sys.h
+++ b/board/sys/sys.h
@@ -9,7 +9,7 @@ extern uint8_t global_critical_depth;
 
 #ifndef ENTER_CRITICAL
 #define ENTER_CRITICAL()                                      \
-  __disable_irq();                                            \
+  __set_BASEPRI(1U << (8U - __NVIC_PRIO_BITS));               \
   global_critical_depth += 1U;
 #endif
 
@@ -17,7 +17,7 @@ extern uint8_t global_critical_depth;
 #define EXIT_CRITICAL()                                       \
   global_critical_depth -= 1U;                                \
   if ((global_critical_depth == 0U) && interrupts_enabled) {  \
-    __enable_irq();                                           \
+    __set_BASEPRI(0U);                                        \
   }
 #endif