aarch64: Disable csdb emission by default (#12932)

* aarch64: Disable csdb emission by default

This has a massive performance penalty on macOS, for example, and peer
compilers are not emitting this as part of on-by-default mitigations.
This commit preserves the option to emit it with an aarch64-specific
`use_csdb` flag, but the default is now `false` meaning that this is not
emitted by default.

Closes #12789

* Fix tests

* Fix tests & review comments

* Use ISLE rule introduced

Author: alexcrichton

cranelift/codegen/meta/src/isa/arm64.rs

@@ -54,6 +54,12 @@ pub(crate) fn define() -> TargetIsa {
         "",
         false,
     );
+    settings.add_bool(
+        "use_csdb",
+        "Use the `csdb` instruction when spectre mitigations are enabled",
+        "",
+        false,
+    );
 
     TargetIsa::new("arm64", settings.build())
 }

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -1822,6 +1822,9 @@
 (decl pure use_fp16 () bool)
 (extern constructor use_fp16 use_fp16)
 
+(decl pure use_csdb () bool)
+(extern constructor use_csdb use_csdb)
+
 ;; Extractor helpers for various immediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl pure partial move_wide_const_from_u64 (Type u64) MoveWideConst)

cranelift/codegen/src/isa/aarch64/inst/emit.rs

@@ -3,6 +3,7 @@
 use cranelift_control::ControlPlane;
 
 use crate::ir::{self, types::*};
+use crate::isa::aarch64;
 use crate::isa::aarch64::inst::*;
 use crate::trace;
 
@@ -711,12 +712,15 @@ impl EmitState {
 }
 
 /// Constant state used during function compilation.
-pub struct EmitInfo(settings::Flags);
+pub struct EmitInfo {
+    flags: settings::Flags,
+    isa_flags: aarch64::settings::Flags,
+}
 
 impl EmitInfo {
     /// Create a constant state for emission of instructions.
-    pub fn new(flags: settings::Flags) -> Self {
-        Self(flags)
+    pub fn new(flags: settings::Flags, isa_flags: aarch64::settings::Flags) -> Self {
+        Self { flags, isa_flags }
     }
 }
 
@@ -3188,7 +3192,9 @@ impl MachInstEmit for Inst {
                 inst.emit(sink, emit_info, state);
                 // Prevent any data value speculation if spectre mitigations are
                 // enabled.
-                if emit_info.0.enable_table_access_spectre_mitigation() {
+                if emit_info.flags.enable_table_access_spectre_mitigation()
+                    && emit_info.isa_flags.use_csdb()
+                {
                     Inst::Csdb.emit(sink, emit_info, state);
                 }
 
@@ -3560,7 +3566,7 @@ impl MachInstEmit for Inst {
             }
 
             &Inst::StackProbeLoop { start, end, step } => {
-                assert!(emit_info.0.enable_probestack());
+                assert!(emit_info.flags.enable_probestack());
 
                 // The loop generated here uses `start` as a counter register to
                 // count backwards until negating it exceeds `end`. In other
@@ -3647,9 +3653,11 @@ fn emit_return_call_common_sequence<T>(
     state: &mut EmitState,
     info: &ReturnCallInfo<T>,
 ) {
-    for inst in
-        AArch64MachineDeps::gen_clobber_restore(CallConv::Tail, &emit_info.0, state.frame_layout())
-    {
+    for inst in AArch64MachineDeps::gen_clobber_restore(
+        CallConv::Tail,
+        &emit_info.flags,
+        state.frame_layout(),
+    ) {
         inst.emit(sink, emit_info, state);
     }
 

cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs

@@ -1,5 +1,6 @@
 use crate::ir::types::*;
 use crate::ir::{ExternalName, TrapCode};
+use crate::isa::aarch64;
 use crate::isa::aarch64::inst::*;
 
 use alloc::boxed::Box;
@@ -7929,7 +7930,8 @@ fn test_aarch64_binemit() {
     insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
 
     let flags = settings::Flags::new(settings::builder());
-    let emit_info = EmitInfo::new(flags);
+    let isa_flags = aarch64::settings::Flags::new(&flags, &aarch64::settings::builder());
+    let emit_info = EmitInfo::new(flags, isa_flags);
     for (insn, expected_encoding, expected_printing) in insns {
         println!("AArch64: {insn:?}, {expected_encoding}, {expected_printing}");
 

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -2266,6 +2266,14 @@
 
 ;;;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+(decl maybe_csdb_after_select (ValueRegs) ValueRegs)
+(rule (maybe_csdb_after_select dst)
+  (if-let true (use_csdb))
+  (let ((_ InstOutput (side_effect (csdb)))) dst))
+(rule (maybe_csdb_after_select dst)
+  (if-let false (use_csdb))
+  dst)
+
 (rule (lower (has_type ty
                        (select_spectre_guard _ (maybe_uextend (icmp _ cc x @ (value_type in_ty) y))
                                              if_true
@@ -2276,9 +2284,8 @@
                             (cond_code (flags_and_cc_cc comparison))
                             ty
                             if_true
-                            if_false))
-            (_ InstOutput (side_effect (csdb))))
-       dst))
+                            if_false)))
+       (maybe_csdb_after_select dst)))
 
 (rule -1 (lower (has_type ty (select_spectre_guard _ rcond @ (value_type (fits_in_64 _)) rn rm)))
       (let ((rcond Reg (put_in_reg_zext64 rcond)))

cranelift/codegen/src/isa/aarch64/lower/isle.rs

@@ -181,6 +181,10 @@ impl Context for IsleContext<'_, '_, MInst, AArch64Backend> {
         self.backend.isa_flags.has_fp16()
     }
 
+    fn use_csdb(&mut self) -> bool {
+        self.backend.isa_flags.use_csdb()
+    }
+
     fn move_wide_const_from_u64(&mut self, ty: Type, n: u64) -> Option<MoveWideConst> {
         let bits = ty.bits();
         let n = if bits < 64 {

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -59,7 +59,7 @@ impl AArch64Backend {
         domtree: &DominatorTree,
         ctrl_plane: &mut ControlPlane,
     ) -> CodegenResult<(VCode<inst::Inst>, regalloc2::Output)> {
-        let emit_info = EmitInfo::new(self.flags.clone());
+        let emit_info = EmitInfo::new(self.flags.clone(), self.isa_flags.clone());
         let sigs = SigSet::new::<abi::AArch64MachineDeps>(func, &self.flags)?;
         let abi = abi::AArch64Callee::new(func, self, &self.isa_flags, &sigs)?;
         compile::compile::<AArch64Backend>(func, domtree, self, abi, emit_info, sigs, ctrl_plane)

cranelift/codegen/src/machinst/buffer.rs

@@ -2518,6 +2518,7 @@ mod test {
 
     use super::*;
     use crate::ir::UserExternalNameRef;
+    use crate::isa::aarch64;
     use crate::isa::aarch64::inst::{BranchTarget, CondBrKind, EmitInfo, Inst};
     use crate::isa::aarch64::inst::{OperandSize, xreg};
     use crate::machinst::{MachInstEmit, MachInstEmitState};
@@ -2530,9 +2531,15 @@ mod test {
         BranchTarget::Label(label(n))
     }
 
+    fn emit_info() -> EmitInfo {
+        let flags = settings::Flags::new(settings::builder());
+        let isa_flags = aarch64::settings::Flags::new(&flags, &aarch64::settings::builder());
+        EmitInfo::new(flags, isa_flags)
+    }
+
     #[test]
     fn test_elide_jump_to_next() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2548,7 +2555,7 @@ mod test {
 
     #[test]
     fn test_elide_trivial_jump_blocks() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2579,7 +2586,7 @@ mod test {
 
     #[test]
     fn test_flip_cond() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2625,7 +2632,7 @@ mod test {
 
     #[test]
     fn test_island() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2694,7 +2701,7 @@ mod test {
 
     #[test]
     fn test_island_backward() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2780,7 +2787,7 @@ mod test {
         // label7:
         //   ret
 
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();
@@ -2857,7 +2864,7 @@ mod test {
         //
         // label0, label1, ..., label4:
         //   b label0
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
+        let info = emit_info();
         let mut buf = MachBuffer::new();
         let mut state = <Inst as MachInstEmit>::State::default();
         let constants = Default::default();

cranelift/filetests/filetests/isa/aarch64/bti.clif

@@ -57,31 +57,30 @@ block5(v5: i32):
 ;   hint #0x22
 ; block1: ; offset 0x4
 ;   cmp w0, #3
-;   b.hs #0x54
+;   b.hs #0x50
 ;   csel x11, xzr, x0, hs
-;   csdb
-;   adr x10, #0x24
+;   adr x10, #0x20
 ;   ldrsw x11, [x10, w11, uxtw #2]
 ;   add x10, x10, x11
 ;   br x10
 ;   .byte 0x24, 0x00, 0x00, 0x00
 ;   .byte 0x18, 0x00, 0x00, 0x00
 ;   .byte 0x0c, 0x00, 0x00, 0x00
-; block2: ; offset 0x30
+; block2: ; offset 0x2c
 ;   hint #0x24
 ;   mov w5, #3
-;   b #0x58
-; block3: ; offset 0x3c
+;   b #0x54
+; block3: ; offset 0x38
 ;   hint #0x24
 ;   mov w5, #2
-;   b #0x58
-; block4: ; offset 0x48
+;   b #0x54
+; block4: ; offset 0x44
 ;   hint #0x24
 ;   mov w5, #1
-;   b #0x58
-; block5: ; offset 0x54
+;   b #0x54
+; block5: ; offset 0x50
 ;   mov w5, #4
-; block6: ; offset 0x58
+; block6: ; offset 0x54
 ;   add w0, w0, w5
 ;   ret
 
@@ -124,20 +123,19 @@ block2:
 ;   ldr x5, [x0]
 ;   mov x8, x5
 ;   cmp w0, #1
-;   b.hs #0x40
+;   b.hs #0x3c
 ;   csel x7, xzr, x0, hs
-;   csdb
-;   adr x6, #0x2c
+;   adr x6, #0x28
 ;   ldrsw x7, [x6, w7, uxtw #2]
 ;   add x6, x6, x7
 ;   br x6
 ;   .byte 0x04, 0x00, 0x00, 0x00
-; block2: ; offset 0x30
+; block2: ; offset 0x2c
 ;   hint #0x24
 ;   mov x0, x8
 ;   add x0, x0, #0x2a
 ;   ret
-; block3: ; offset 0x40
+; block3: ; offset 0x3c
 ;   mov x0, x8
 ;   ret