Cranelift: riscv64: fix zero-extension in trapif + icmp folding. (#12952)

* Add bad test.

* Fix lowering to properly zero-extend compared values.

Author: cfallin

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -2126,7 +2126,10 @@
 
 ; fold icmp + trapz
 (rule 2 (lower (trapz (icmp _ cc x @ (value_type (fits_in_64 _)) y) code))
-  (gen_trapif (intcc_complement cc) x y code))
+  (gen_trapif (intcc_complement cc)
+    (put_value_in_reg_for_icmp cc x)
+    (put_value_in_reg_for_icmp cc y)
+    code))
 
 ;;;;;  Rules for `trapnz`;;;;;;;;;
 (rule
@@ -2139,7 +2142,10 @@
 
 ; fold icmp + trapnz
 (rule 2 (lower (trapnz (icmp _ cc x @ (value_type (fits_in_64 _)) y) code))
-  (gen_trapif cc x y code))
+  (gen_trapif cc
+    (put_value_in_reg_for_icmp cc x)
+    (put_value_in_reg_for_icmp cc y)
+    code))
 
 ;;;;;  Rules for `uload8`;;;;;;;;;
 (rule (lower (uload8 _ (little_or_native_endian flags) addr offset))

cranelift/filetests/filetests/isa/riscv64/trapz-sign-extend-load32.clif

@@ -0,0 +1,33 @@
+test compile precise-output
+target riscv64
+
+function %f(i64, i64) {
+block0(v0: i64, v1: i64):
+    v2 = load.i32 notrap aligned readonly v0
+    v3 = ireduce.i32 v1
+    v4 = icmp ult v2, v3
+    trapz v4, user15
+    return
+}
+
+; VCode:
+; block0:
+;   lw a0,0(a0)
+;   slli a0,a0,32
+;   srli a0,a0,32
+;   slli a1,a1,32
+;   srli a1,a1,32
+;   trap_if user15##(a0 uge a1)
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   lw a0, 0(a0)
+;   slli a0, a0, 0x20
+;   srli a0, a0, 0x20
+;   slli a1, a1, 0x20
+;   srli a1, a1, 0x20
+;   bltu a0, a1, 8
+;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user15
+;   ret
+