diff --git a/crates/synth-cli/src/release.rs b/crates/synth-cli/src/release.rs index 7997dd3aa..27e994841 100644 --- a/crates/synth-cli/src/release.rs +++ b/crates/synth-cli/src/release.rs @@ -220,6 +220,10 @@ pub struct ReleaseManifest { pub schema_version: String, pub tool_version: String, pub input: String, + /// Commit named by `SYNTH_SOURCE_REVISION` when the package was built. + /// `None` means the caller did not name one. + #[serde(default, skip_serializing_if = "Option::is_none")] + pub source_revision: Option, pub fab_requested: bool, pub production_status: ProductionStatus, pub release_ready: bool, @@ -270,6 +274,25 @@ fn gate_scope() -> String { .to_string() } +/// The input path as a checkout-relative path where possible, so a package +/// does not record the absolute directory of the machine that built it. +fn display_input(input: &Path) -> String { + std::env::current_dir() + .ok() + .and_then(|cwd| input.strip_prefix(cwd).ok()) + .unwrap_or(input) + .display() + .to_string() +} + +/// The source revision a caller names in `SYNTH_SOURCE_REVISION`. An empty +/// value names none, so an unset or blank variable is not stamped as a commit. +fn revision_from(value: Option) -> Option { + value + .map(|v| v.trim().to_string()) + .filter(|v| !v.is_empty()) +} + impl ReleaseManifest { pub fn new( tool_version: &str, @@ -283,7 +306,8 @@ impl ReleaseManifest { Self { schema_version: SCHEMA_VERSION.to_string(), tool_version: tool_version.to_string(), - input: input.display().to_string(), + input: display_input(input), + source_revision: revision_from(std::env::var("SYNTH_SOURCE_REVISION").ok()), fab_requested, production_status: if clean { ProductionStatus::Production @@ -522,6 +546,27 @@ mod tests { ) } + #[test] + fn an_input_under_the_current_directory_is_recorded_relative() { + let cwd = std::env::current_dir().expect("cwd"); + let absolute = cwd.join("qualification/class-b/rtd-afe/rtd_afe.synth"); + assert_eq!( + display_input(&absolute), + "qualification/class-b/rtd-afe/rtd_afe.synth" + ); + assert_eq!(display_input(Path::new("board.synth")), "board.synth"); + } + + #[test] + fn a_named_source_revision_is_kept_and_a_blank_one_is_not() { + assert_eq!( + revision_from(Some(" abc123\n".into())).as_deref(), + Some("abc123") + ); + assert_eq!(revision_from(Some(" ".into())), None); + assert_eq!(revision_from(None), None); + } + fn unverified() -> OverrideRecord { OverrideRecord::new( OverrideKind::UnverifiedParts, diff --git a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@docs_blocks.snap b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@docs_blocks.snap index bba365cfa..64cf20259 100644 --- a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@docs_blocks.snap +++ b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@docs_blocks.snap @@ -74,6 +74,14 @@ expression: board "min_voltage_v": 1.8, "max_voltage_v": 5.0, "max_current_ma": 100.0 + }, + "provenance": { + "source": "seed", + "generator": null, + "datasheet_url": null, + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "upstream_lcsc_pn": null } }, "source_span": { diff --git a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@single_mcu.snap b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@single_mcu.snap index 14e5deff0..eee04157b 100644 --- a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@single_mcu.snap +++ b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@single_mcu.snap @@ -20,7 +20,7 @@ expression: board "signed_by": [], "substitutes": [], "mpn": "RP2350A", - "lcsc_pn": "C14663", + "lcsc_pn": "C42411118", "pins": [ { "name": "iovdd", @@ -77,7 +77,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_mosi", + "spi_miso", "uart_tx", "i2c_sda" ], @@ -118,7 +118,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_miso", + "spi_mosi", "uart_rx" ], "required": false, @@ -672,13 +672,13 @@ expression: board { "net": "iovdd", "value": "100nf", - "count": 4, + "count": 7, "max_distance_mm": null }, { "net": "dvdd", "value": "100nf", - "count": 2, + "count": 3, "max_distance_mm": null } ], @@ -698,6 +698,14 @@ expression: board "max_current_ma": 150.0, "max_power_mw": 300.0, "thermal_resistance_c_per_w": 40.0 + }, + "provenance": { + "source": "seed", + "generator": null, + "datasheet_url": "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "upstream_lcsc_pn": null } }, "source_span": { diff --git a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@two_components_with_net.snap b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@two_components_with_net.snap index 98e781097..be12e3a41 100644 --- a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@two_components_with_net.snap +++ b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@two_components_with_net.snap @@ -20,7 +20,7 @@ expression: board "signed_by": [], "substitutes": [], "mpn": "RP2350A", - "lcsc_pn": "C14663", + "lcsc_pn": "C42411118", "pins": [ { "name": "iovdd", @@ -77,7 +77,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_mosi", + "spi_miso", "uart_tx", "i2c_sda" ], @@ -118,7 +118,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_miso", + "spi_mosi", "uart_rx" ], "required": false, @@ -672,13 +672,13 @@ expression: board { "net": "iovdd", "value": "100nf", - "count": 4, + "count": 7, "max_distance_mm": null }, { "net": "dvdd", "value": "100nf", - "count": 2, + "count": 3, "max_distance_mm": null } ], @@ -698,6 +698,14 @@ expression: board "max_current_ma": 150.0, "max_power_mw": 300.0, "thermal_resistance_c_per_w": 40.0 + }, + "provenance": { + "source": "seed", + "generator": null, + "datasheet_url": "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "upstream_lcsc_pn": null } }, "source_span": { diff --git a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@union_find_net.snap b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@union_find_net.snap index 17f9b4613..c935db19f 100644 --- a/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@union_find_net.snap +++ b/crates/synth-ir/tests/snapshots/lowering__every_ir_fixture_lowers_clean_and_stable@union_find_net.snap @@ -20,7 +20,7 @@ expression: board "signed_by": [], "substitutes": [], "mpn": "RP2350A", - "lcsc_pn": "C14663", + "lcsc_pn": "C42411118", "pins": [ { "name": "iovdd", @@ -77,7 +77,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_mosi", + "spi_miso", "uart_tx", "i2c_sda" ], @@ -118,7 +118,7 @@ expression: board "electrical_type": "bidirectional", "capabilities": [ "gpio", - "spi_miso", + "spi_mosi", "uart_rx" ], "required": false, @@ -672,13 +672,13 @@ expression: board { "net": "iovdd", "value": "100nf", - "count": 4, + "count": 7, "max_distance_mm": null }, { "net": "dvdd", "value": "100nf", - "count": 2, + "count": 3, "max_distance_mm": null } ], @@ -698,6 +698,14 @@ expression: board "max_current_ma": 150.0, "max_power_mw": 300.0, "thermal_resistance_c_per_w": 40.0 + }, + "provenance": { + "source": "seed", + "generator": null, + "datasheet_url": "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "upstream_lcsc_pn": null } }, "source_span": { diff --git a/crates/synth-kicad/src/bom.rs b/crates/synth-kicad/src/bom.rs index 65b3ee06d..8dfd32d9e 100644 --- a/crates/synth-kicad/src/bom.rs +++ b/crates/synth-kicad/src/bom.rs @@ -2,8 +2,10 @@ //! Bill of materials CSV writer. //! -//! Columns: `refdes,value,kind,description`. Fields containing -//! commas, quotes, or newlines are RFC-4180 quoted. Output is +//! Columns: `refdes,value,kind,description`, the KiCad symbol and +//! footprint, supplier identities, and the source's structured +//! `dielectric`, `voltage`, `tolerance` and `power` attributes. Fields +//! containing commas, quotes, or newlines are RFC-4180 quoted. Output is //! sorted by refdes for diff stability. //! //! Do-not-populate parts are left out: a DNP line in the BOM would @@ -39,6 +41,10 @@ fn build_bom_csv_filtered(board: &Board, extra_dnp: &BTreeSet<&str>) -> String { String, String, String, + String, + String, + String, + String, )> = board .components .iter() @@ -78,6 +84,7 @@ fn build_bom_csv_filtered(board: &Board, extra_dnp: &BTreeSet<&str>) -> String { .as_ref() .and_then(|p| p.mpn.clone()) .unwrap_or_default(); + let attribute = |key: &str| c.properties.get(key).cloned().unwrap_or_default(); ( c.refdes.clone(), value, @@ -87,14 +94,35 @@ fn build_bom_csv_filtered(board: &Board, extra_dnp: &BTreeSet<&str>) -> String { kicad_footprint, lcsc_pn, mpn, + attribute("Dielectric"), + attribute("Voltage"), + attribute("Tolerance"), + attribute("Power"), ) }) .collect(); rows.sort(); let mut out = String::new(); - out.push_str("refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn\n"); - for (refdes, value, kind, description, kicad_symbol, kicad_footprint, lcsc_pn, mpn) in rows { + out.push_str( + "refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,\ + dielectric,voltage,tolerance,power\n", + ); + for ( + refdes, + value, + kind, + description, + kicad_symbol, + kicad_footprint, + lcsc_pn, + mpn, + dielectric, + voltage, + tolerance, + power, + ) in rows + { write_field(&mut out, &refdes); out.push(','); write_field(&mut out, &value); @@ -110,6 +138,14 @@ fn build_bom_csv_filtered(board: &Board, extra_dnp: &BTreeSet<&str>) -> String { write_field(&mut out, &lcsc_pn); out.push(','); write_field(&mut out, &mpn); + out.push(','); + write_field(&mut out, &dielectric); + out.push(','); + write_field(&mut out, &voltage); + out.push(','); + write_field(&mut out, &tolerance); + out.push(','); + write_field(&mut out, &power); out.push('\n'); } out @@ -192,6 +228,61 @@ mod tests { assert!(lite.contains("R1") && !lite.contains("R2") && !lite.contains("R3")); } + #[test] + fn structured_attributes_get_their_own_columns() { + use std::collections::BTreeMap; + use synth_ir::{Component, ComponentId}; + let mut properties = BTreeMap::new(); + properties.insert("Dielectric".to_string(), "C0G".to_string()); + properties.insert("Voltage".to_string(), "50V".to_string()); + properties.insert("Tolerance".to_string(), "0.1%".to_string()); + let board = Board { + schematic_overflow: None, + schematic_paper: None, + groups: Vec::new(), + legends: false, + name: "b".to_string(), + layers: 2, + manufacturer: None, + revision: None, + company: None, + components: vec![Component { + id: ComponentId(0), + refdes: "C1".to_string(), + kind: "capacitor".to_string(), + part: None, + value: Some("100nF".to_string()), + dnp: false, + properties, + placement_hint: None, + escape: None, + group: None, + sheet: None, + source_span: synth_diagnostics::Span::new(0, 0), + }], + nets: vec![], + diff_pairs: vec![], + notes: vec![], + keepouts: vec![], + stackup: None, + netclasses: vec![], + buses: vec![], + modules: vec![], + variants: vec![], + required_processes: std::collections::BTreeSet::new(), + source_span: synth_diagnostics::Span::new(0, 0), + }; + let csv = build_bom_csv(&board); + assert!( + csv.starts_with( + "refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,\ + dielectric,voltage,tolerance,power\n" + ), + "{csv}" + ); + assert!(csv.contains(",C0G,50V,0.1%,"), "{csv}"); + } + #[test] fn quoting_doubles_internal_quotes() { let mut s = String::new(); diff --git a/crates/synth-kicad/src/export.rs b/crates/synth-kicad/src/export.rs index 90ce5ba29..3dd6f7204 100644 --- a/crates/synth-kicad/src/export.rs +++ b/crates/synth-kicad/src/export.rs @@ -466,11 +466,16 @@ fn export_inner( // external router, which reads this file and writes its own candidate // back; Synth does not synthesize traces here, so nothing downstream // can mistake them for router output. - let (label_overrides, fixed_vias) = sidecars + let placement_sidecar = sidecars .placement_path() - .and_then(synth_layout::sidecar::SidecarLayout::load_from_file) - .map(|sidecar| (sidecar.labels, sidecar.vias)) + .and_then(synth_layout::sidecar::SidecarLayout::load_from_file); + let (label_overrides, fixed_vias) = placement_sidecar + .as_ref() + .map(|sidecar| (sidecar.labels.clone(), sidecar.vias.clone())) .unwrap_or_default(); + let outline: &[synth_layout::sidecar::SidecarPoint] = placement_sidecar + .as_ref() + .map_or(&[], |sidecar| sidecar.outline.as_slice()); let pcb_text = pcb::build_pcb( board, &placement, @@ -478,6 +483,7 @@ fn export_inner( &project_namespace, &label_overrides, &fixed_vias, + outline, ) .map_err(|error| ExportError::PlaneFanout { net: error.net, diff --git a/crates/synth-kicad/src/pcb.rs b/crates/synth-kicad/src/pcb.rs index c401ba85d..1f8395dfc 100644 --- a/crates/synth-kicad/src/pcb.rs +++ b/crates/synth-kicad/src/pcb.rs @@ -83,6 +83,7 @@ pub fn build_pcb( project: &Uuid, label_overrides: &HashMap, fixed_vias: &[synth_layout::sidecar::SidecarVia], + outline: &[synth_layout::sidecar::SidecarPoint], ) -> Result { let placements_by_id: HashMap = placement.components.iter().map(|p| (p.id, p)).collect(); @@ -128,10 +129,9 @@ pub fn build_pcb( } children.extend(build_netclasses(&net_table, board)); - // Edge.Cuts board outline. Four gr_line segments tracing - // `placement.board_outline`. Slice 1B uses an axis-aligned - // rectangle; later slices accept user-defined outlines. - children.extend(build_edge_cuts(placement, project)); + // Edge.Cuts board outline. A sidecar outline replaces the fitted + // rectangle, so a non-rectangular board is part of the design source. + children.extend(build_edge_cuts(placement, outline, project)); // Footprint instances. Components with a real `kicad_footprint` // reference it directly; components without one (e.g. a brand-new @@ -294,8 +294,29 @@ pub fn build_pcb( // through vias so the planes form one physical ground network. The // external routers preserve these source vias while replacing their // own routed segments and vias. - if board.layers >= 4 && plane_index == 0 { - let outline = placement.board_outline; + // Each ground fences only the corners inside its own pour region: a corner via + // in another split ground's half is a dangling island of the wrong net. + if board.layers >= 4 { + // The source fence follows the delivered outline, not the placer's + // fitted rectangle: a sidecar notch moves the edge inward and + // would leave these vias on (or outside) Edge.Cuts. + let outline_points = outline; + let fence_outline = if outline_points.len() >= 3 { + let (mut min_x, mut min_y) = (i64::MAX, i64::MAX); + let (mut max_x, mut max_y) = (i64::MIN, i64::MIN); + for point in outline_points { + let x = mm_to_nm(point.x); + let y = mm_to_nm(point.y); + min_x = min_x.min(x); + min_y = min_y.min(y); + max_x = max_x.max(x); + max_y = max_y.max(y); + } + synth_geometry::Rect::new(Point::new(min_x, min_y), Point::new(max_x, max_y)) + } else { + placement.board_outline + }; + let outline = fence_outline; let inset = mm_to_nm(1.5); let holes: Vec<(Point, i64)> = board .components @@ -322,6 +343,17 @@ pub fn build_pcb( for (stitch_index, (x_nm, y_nm, inward)) in points.into_iter().enumerate() { let Point { x_nm, y_nm } = clear_of_mounting_holes(Point::new(x_nm, y_nm), inward, &holes); + if region + .as_deref() + .is_some_and(|polygon| !convex_contains(polygon, Point::new(x_nm, y_nm))) + { + continue; + } + if !outline_points.is_empty() + && !custom_outline_contains(outline_points, Point::new(x_nm, y_nm)) + { + continue; + } children.push(build_ground_stitch_via( x_nm, y_nm, @@ -1304,6 +1336,36 @@ fn net_centroid( Some(synth_geometry::Point::new(sx / count, sy / count)) } +/// Whether `point` lies inside (or on) a convex polygon of either winding. +fn convex_contains(polygon: &[synth_geometry::Point], point: synth_geometry::Point) -> bool { + let (mut pos, mut neg) = (false, false); + for i in 0..polygon.len() { + let (a, b) = (polygon[i], polygon[(i + 1) % polygon.len()]); + let cross = i128::from(b.x_nm - a.x_nm) * i128::from(point.y_nm - a.y_nm) + - i128::from(b.y_nm - a.y_nm) * i128::from(point.x_nm - a.x_nm); + pos |= cross > 0; + neg |= cross < 0; + } + !(pos && neg) +} + +/// Whether `point` lies inside the closed sidecar outline, including a notch. +fn custom_outline_contains(points: &[synth_layout::sidecar::SidecarPoint], point: Point) -> bool { + let x = nm_to_mm(point.x_nm); + let y = nm_to_mm(point.y_nm); + let mut inside = false; + let mut j = points.len() - 1; + for i in 0..points.len() { + let (xi, yi) = (points[i].x, points[i].y); + let (xj, yj) = (points[j].x, points[j].y); + if (yi > y) != (yj > y) && x < (xj - xi) * (y - yi) / (yj - yi) + xi { + inside = !inside; + } + j = i; + } + inside +} + /// Sutherland–Hodgman clip of a convex polygon by the half-plane /// `(p - mid)·d <= 0`. #[allow( @@ -2081,7 +2143,42 @@ fn build_netclasses(net_table: &[(u32, String)], board: &Board) -> Vec { classes } -fn build_edge_cuts(placement: &Placement, project: &Uuid) -> Vec { +fn build_edge_cuts( + placement: &Placement, + outline: &[synth_layout::sidecar::SidecarPoint], + project: &Uuid, +) -> Vec { + let line = |start: (f64, f64), end: (f64, f64), tag: &str, segment: usize| { + let line_uuid = derive_entity_uuid(project, "edge_cut", &format!("{tag}/{segment}")); + Sexp::list( + "gr_line", + vec![ + Sexp::list("start", vec![num(start.0), num(start.1)]), + Sexp::list("end", vec![num(end.0), num(end.1)]), + Sexp::list( + "stroke", + vec![ + Sexp::list("width", vec![num(EDGE_CUT_WIDTH_MM)]), + Sexp::list("type", vec![Sexp::atom("solid")]), + ], + ), + Sexp::list("layer", vec![Sexp::str("Edge.Cuts")]), + str_pair("uuid", line_uuid.to_string()), + ], + ) + }; + + if outline.len() >= 3 { + return outline + .iter() + .enumerate() + .map(|(i, start)| { + let end = &outline[(i + 1) % outline.len()]; + line((start.x, start.y), (end.x, end.y), "outline", i) + }) + .collect(); + } + let r = placement.board_outline; let min_x = nm_to_mm(r.min.x_nm); let min_y = nm_to_mm(r.min.y_nm); @@ -2095,25 +2192,8 @@ fn build_edge_cuts(placement: &Placement, project: &Uuid) -> Vec { ]; corners .iter() - .map(|(start, end, tag)| { - let line_uuid = derive_entity_uuid(project, "edge_cut", tag); - Sexp::list( - "gr_line", - vec![ - Sexp::list("start", vec![num(start.0), num(start.1)]), - Sexp::list("end", vec![num(end.0), num(end.1)]), - Sexp::list( - "stroke", - vec![ - Sexp::list("width", vec![num(EDGE_CUT_WIDTH_MM)]), - Sexp::list("type", vec![Sexp::atom("solid")]), - ], - ), - Sexp::list("layer", vec![Sexp::str("Edge.Cuts")]), - str_pair("uuid", line_uuid.to_string()), - ], - ) - }) + .enumerate() + .map(|(i, (start, end, tag))| line(*start, *end, tag, i)) .collect() } @@ -2448,7 +2528,7 @@ fn build_footprint_instance( let body = strip_footprint_head(body); let body = add_footprint_angle_to_pads(&body, pad_angle); let body_with_nets = inject_pad_nets(&body, component.id, pad_net_lookup); - let body_with_nets = ensure_body_uuids(&body_with_nets, project, lib_id); + let body_with_nets = ensure_body_uuids(&body_with_nets, project, lib_id, &component.refdes); let has_model = body_with_nets.contains("(model "); children.push(Sexp::Raw(body_with_nets)); has_model @@ -2620,27 +2700,29 @@ const BODY_UUID_HEADS: &[&str] = &[ "fp_curve", ]; -/// Fill in deterministic UUIDs for inlined footprint-body blocks that -/// lack them (stock-library drawing primitives, pads and properties -/// predate mandatory UUIDs). +/// Fill in deterministic, per-instance UUIDs for inlined footprint-body +/// blocks. /// /// Without this, KiCad's `--save-board` DRC gate assigns a fresh random v4 /// UUID to every such block on each export, so two exports of the same -/// board differ and the plan §6.2 byte-identical guarantee breaks. UUIDs -/// are v5 over `(project, "fp_body:{lib_id}:{kind}:{key}#{n}")`, hence -/// stable across runs, thread counts, and machines. Blocks that already -/// carry `(uuid ...)` are left untouched. -fn ensure_body_uuids(body: &str, project: &Uuid, lib_id: &str) -> String { +/// board differ and the plan §6.2 byte-identical guarantee breaks. KiCad +/// also keys board items by UUID, so the stock ids that KiCad 10 footprints +/// ship with must not be shared by two placed instances: its DRC would then +/// attribute a collision to the wrong footprint. UUIDs are v5 over +/// `(project, "fp_body:{instance}:{lib_id}:{kind}:{key}#{n}")`, hence +/// stable across runs, thread counts, and machines, and unique per instance. +fn ensure_body_uuids(body: &str, project: &Uuid, lib_id: &str, instance: &str) -> String { let mut seen: std::collections::HashMap = std::collections::HashMap::new(); - ensure_level(body, project, lib_id, "", &mut seen, false) + ensure_level(body, project, lib_id, instance, "", &mut seen, false) } /// One level of [`ensure_body_uuids`]: walk the top-level blocks of `text`, -/// add deterministic UUIDs where missing, and recurse into each block's -/// children (footprint `fp_text` nests a `(point ...)` designator lock that -/// KiCad fills the same way). `path` is the `/`-joined ancestor chain so -/// nested names cannot collide with top-level ones; `seen` counts each -/// full path for duplicate siblings. +/// set a deterministic UUID on every whitelisted block (replacing a stock +/// library one), and recurse into each block's children (footprint +/// `fp_text` nests a `(point ...)` designator lock that KiCad fills the same +/// way). `path` is the `/`-joined ancestor chain so nested names cannot +/// collide with top-level ones; `seen` counts each full path for duplicate +/// siblings. /// /// Nested levels only ever gain UUIDs on `point`: pad-nested `(property /// pad_prop_mechanical)` must stay exactly as the stock library ships it — @@ -2649,6 +2731,7 @@ fn ensure_level( text: &str, project: &Uuid, lib_id: &str, + instance: &str, path: &str, seen: &mut std::collections::HashMap, nested: bool, @@ -2688,17 +2771,15 @@ fn ensure_level( // suppress the parent's own UUID. let whitelisted = (!nested && BODY_UUID_HEADS.contains(&head)) || NESTED_UUID_HEADS.contains(&head); - if whitelisted && !has_direct_uuid(&block) { + if whitelisted { let counter = seen.entry(full_path.clone()).or_insert(0); let uuid = derive_entity_uuid( project, "fp_body", - &format!("{lib_id}:{full_path}#{counter}"), + &format!("{instance}:{lib_id}:{full_path}#{counter}"), ); *counter += 1; - block.pop(); - let _ = write!(block, " (uuid \"{uuid}\")"); - block.push(')'); + block = set_direct_uuid(block, &uuid.to_string()); } // Recurse into children: everything between the `(head ...args` // opener and the final `)`. Leaf blocks (no inner `(`) come back @@ -2708,6 +2789,7 @@ fn ensure_level( &block[range.clone()], project, lib_id, + instance, &full_path, seen, true, @@ -2723,14 +2805,25 @@ fn ensure_level( out } -/// True when `block`'s direct children include a `(uuid ...)` node. -/// (A plain substring search would false-positive on a *nested* UUID, e.g. -/// an fp_text whose `point` child already has one while it does not.) -fn has_direct_uuid(block: &str) -> bool { - let Some(range) = inner_range(block) else { - return false; - }; - let inner = &block[range]; +/// Set the value of the block's direct `(uuid "...")` child, adding one +/// when the block has none. The stock library ids are replaced so two +/// instances of the same footprint do not share item UUIDs. +fn set_direct_uuid(mut block: String, uuid: &str) -> String { + if let Some((start, end)) = direct_uuid_span(&block) { + block.replace_range(start..end, &format!("\"{uuid}\"")); + return block; + } + block.pop(); + let _ = write!(block, " (uuid \"{uuid}\")"); + block.push(')'); + block +} + +/// Byte range of the string literal inside `block`'s direct `(uuid ...)` +/// child, if it has one. +fn direct_uuid_span(block: &str) -> Option<(usize, usize)> { + let range = inner_range(block)?; + let inner = &block[range.clone()]; let bytes = inner.as_bytes(); let mut i = 0; while i < bytes.len() { @@ -2742,19 +2835,19 @@ fn has_direct_uuid(block: &str) -> bool { i += 1; continue; } - let Some(end) = matching_close_quoted(inner, i + 1) else { - return false; - }; + let end = matching_close_quoted(inner, i + 1)?; let head = inner[i + 1..=end] .split(|c: char| c.is_ascii_whitespace() || c == '(' || c == ')') .next() .unwrap_or(""); if head == "uuid" { - return true; + let q1 = i + inner[i..].find('"')?; + let q2 = skip_string(bytes, q1); + return Some((range.start + q1, range.start + q2)); } i = end + 1; } - false + None } /// Byte index just past the string literal opening at `i` (which must be @@ -3353,22 +3446,53 @@ mod tests { /// every uuid-bearing footprint-body block must carry a deterministic /// UUID before KiCad sees the file, or the gate fills random v4 UUIDs /// and re-exports stop being byte-identical (plan §6.2). + /// + /// KiCad 10's stock footprints ship their own child UUIDs, and inlining + /// the body verbatim made every instance of a part share them. KiCad + /// keys board items by UUID, so its DRC attributed silk/pad collisions + /// to the wrong footprint. Each instance must get its own ids. #[test] - fn inlined_body_blocks_carry_deterministic_uuids() { - let body = "(property \"Datasheet\" \"\" (at 0 0 0) (layer \"F.Fab\") (hide yes) (effects (font (size 1.27 1.27)))) (pad \"1\" smd rect (at 0 0) (size 1 1) (layers \"F.Cu\")) (fp_line (start 0 0) (end 1 1) (stroke (width 0.1)) (layer \"F.SilkS\")) (fp_text user \"REF\" (at 0 0) (layer \"F.SilkS\") (effects (font (size 1 1))) (point (at 0 0) (size 1) (layer \"F.SilkS\")))"; + fn inlined_body_blocks_carry_unique_deterministic_uuids() { + let body = "(property \"Datasheet\" \"\" (at 0 0 0) (layer \"F.Fab\") (hide yes) (effects (font (size 1.27 1.27)))) (pad \"1\" smd rect (at 0 0) (size 1 1) (layers \"F.Cu\") (uuid \"11111111-1111-5111-8111-111111111111\")) (fp_line (start 0 0) (end 1 1) (stroke (width 0.1)) (layer \"F.SilkS\")) (fp_text user \"REF\" (at 0 0) (layer \"F.SilkS\") (effects (font (size 1 1))) (point (at 0 0) (size 1) (layer \"F.SilkS\")))"; + let uuids = |s: &str| -> Vec { + s.match_indices("(uuid \"") + .map(|(i, _)| { + let rest = &s[i + "(uuid \"".len()..]; + rest[..rest.find('"').unwrap()].to_string() + }) + .collect() + }; let project = Uuid::nil(); - let once = super::ensure_body_uuids(body, &project, "lib:part"); + let r1 = super::ensure_body_uuids(body, &project, "lib:part", "R1"); + let r2 = super::ensure_body_uuids(body, &project, "lib:part", "R2"); assert_eq!( - once.matches("(uuid \"").count(), + r1.matches("(uuid \"").count(), 5, - "one uuid per block: {once}" + "one uuid per block: {r1}" + ); + let ids: std::collections::HashSet = uuids(&r1).into_iter().collect(); + assert_eq!(ids.len(), 5, "duplicate ids in one instance: {r1}"); + assert!( + !ids.contains("11111111-1111-5111-8111-111111111111"), + "the stock library uuid survived: {r1}" + ); + assert_ne!(r1, r2, "two instances share body uuids"); + assert_eq!(uuids(&r2).len(), 5); + assert!( + uuids(&r1).iter().all(|id| !uuids(&r2).contains(id)), + "instances share a uuid" + ); + // Idempotent and deterministic for the same instance. + assert_eq!( + r1, + super::ensure_body_uuids(&r1, &project, "lib:part", "R1"), + "uuid pass must be idempotent" + ); + assert_eq!( + r1, + super::ensure_body_uuids(body, &project, "lib:part", "R1"), + "uuid pass must be deterministic" ); - // Idempotent and deterministic: a second pass changes nothing, and - // pre-uuid'd blocks are preserved verbatim. - let twice = super::ensure_body_uuids(&once, &project, "lib:part"); - assert_eq!(once, twice, "uuid pass must be idempotent"); - let again = super::ensure_body_uuids(body, &project, "lib:part"); - assert_eq!(once, again, "uuid pass must be deterministic"); } #[test] @@ -4003,6 +4127,7 @@ mod tests { &Uuid::nil(), &HashMap::new(), &vias, + &[], ) .expect("export") .to_string_pretty(); @@ -4027,6 +4152,7 @@ mod tests { &Uuid::nil(), &HashMap::new(), &unknown, + &[], ) .expect_err("an unknown net is refused"); assert_eq!(error.net, "NOPE"); @@ -4074,8 +4200,16 @@ mod tests { pad_escape_rejections: 0, }; let project = Uuid::nil(); - let pcb_sexp = build_pcb(&board, &placement, &routing, &project, &HashMap::new(), &[]) - .expect("plane fanout"); + let pcb_sexp = build_pcb( + &board, + &placement, + &routing, + &project, + &HashMap::new(), + &[], + &[], + ) + .expect("plane fanout"); let pcb_str = pcb_sexp.to_string_pretty(); let tmp_path = diff --git a/crates/synth-kicad/tests/instance_sourcing.rs b/crates/synth-kicad/tests/instance_sourcing.rs index 1afecf393..0b82031f6 100644 --- a/crates/synth-kicad/tests/instance_sourcing.rs +++ b/crates/synth-kicad/tests/instance_sourcing.rs @@ -40,10 +40,10 @@ fn instance_value_reaches_bom_csv_and_schematic_once() { let board = lower(TWO_RESISTORS); let (bom, _) = bom(&board); assert!( - row(&bom, "R1").ends_with(",C110776,RT0603BRD071KL"), + row(&bom, "R1").contains(",C110776,RT0603BRD071KL,"), "{bom}" ); - assert!(row(&bom, "R2").ends_with(",C123,RT0603FRE0727RL"), "{bom}"); + assert!(row(&bom, "R2").contains(",C123,RT0603FRE0727RL,"), "{bom}"); } #[test] diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@diff_pair_with_keepout__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@diff_pair_with_keepout__bom.snap index 8c9d6b125..be2191732 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@diff_pair_with_keepout__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@diff_pair_with_keepout__bom.snap @@ -2,4 +2,4 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@docs_blocks__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@docs_blocks__bom.snap index 1bf7e706b..75b3d491c 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@docs_blocks__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@docs_blocks__bom.snap @@ -2,7 +2,7 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -C1,(no value),capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,, -J1,PZ254V-11-04P,connector,"1x4 through-hole pin header, 2.54mm pitch",Connector_Generic:Conn_01x04,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical,C492403,PZ254V-11-04P -R1,(no value),resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,, +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +C1,(no value),capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,,,,,, +J1,PZ254V-11-04P,connector,"1x4 through-hole pin header, 2.54mm pitch",Connector_Generic:Conn_01x04,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical,C492403,PZ254V-11-04P,,,, +R1,(no value),resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,,,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@module_divider__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@module_divider__bom.snap index dda9796de..d33f06fe3 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@module_divider__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@module_divider__bom.snap @@ -2,9 +2,9 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -D1_R1,10kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,, -D1_R2,4.7kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,, -D2_R1,22kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,, -D2_R2,4.7kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,, -J1,(no value),connector,"JST PH-series 2-pin wire-to-board connector, 2.0mm pitch",Connector_Generic:Conn_01x02,Connector_JST:JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal,, +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +D1_R1,10kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,,,,,, +D1_R2,4.7kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,,,,,, +D2_R1,22kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,,,,,, +D2_R2,4.7kohm,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,,,,,, +J1,(no value),connector,"JST PH-series 2-pin wire-to-board connector, 2.0mm pitch",Connector_Generic:Conn_01x02,Connector_JST:JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal,,,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@named_nets__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@named_nets__bom.snap index 8452544be..95be9445f 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@named_nets__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@named_nets__bom.snap @@ -2,9 +2,9 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -C1,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,, -C2,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,, -C3,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,, -C4,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,, -U1,AMS1117-3.3,regulator,"AMS1117-3.3 fixed 3.3V LDO regulator, SOT-223 — common JLC stock",Regulator_Linear:AMS1117-3.3,Package_TO_SOT_SMD:SOT-223-3_TabPin2,C6186,AMS1117-3.3 +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +C1,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,,,,,, +C2,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,,,,,, +C3,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,,,,,, +C4,10u,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,,,,,, +U1,AMS1117-3.3,regulator,"AMS1117-3.3 fixed 3.3V LDO regulator, SOT-223 — common JLC stock",Regulator_Linear:AMS1117-3.3,Package_TO_SOT_SMD:SOT-223-3_TabPin2,C6186,AMS1117-3.3,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__bom.snap index 8f991537f..4b6b077f3 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__bom.snap @@ -2,5 +2,5 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C14663,RP2350A +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C42411118,RP2350A,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__schematic.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__schematic.snap index 7e49a6102..5a8f84bba 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__schematic.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@single_mcu__schematic.snap @@ -1289,7 +1289,7 @@ expression: schematic ) (property "Datasheet" - "" + "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf" (at 48.26 68.58 0) (effects (font @@ -1311,7 +1311,7 @@ expression: schematic ) (property "LCSC" - "C14663" + "C42411118" (at 48.26 68.58 0) (effects (font diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__bom.snap index 67d1a99be..dfaddec63 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__bom.snap @@ -2,6 +2,6 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C14663,RP2350A -U2,(no value),secure_element,"Microchip ATECC608 crypto authentication IC, UDFN-8",Security:ATECC608A-SSH,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,, +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C42411118,RP2350A,,,, +U2,(no value),secure_element,"Microchip ATECC608 crypto authentication IC, UDFN-8",Security:ATECC608A-SSH,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,,,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__schematic.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__schematic.snap index f7a5e0d03..71d390edc 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__schematic.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@two_components_with_net__schematic.snap @@ -1534,7 +1534,7 @@ expression: schematic ) (property "Datasheet" - "" + "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf" (at 48.26 68.58 0) (effects (font @@ -1556,7 +1556,7 @@ expression: schematic ) (property "LCSC" - "C14663" + "C42411118" (at 48.26 68.58 0) (effects (font diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__bom.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__bom.snap index 224da81a7..28854d540 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__bom.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__bom.snap @@ -2,7 +2,7 @@ source: crates/synth-kicad/tests/golden.rs expression: bom --- -refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn -C1,(no value),capacitor,"Generic 0402 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0402_1005Metric,, -U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C14663,RP2350A -U2,(no value),secure_element,"Microchip ATECC608 crypto authentication IC, UDFN-8",Security:ATECC608A-SSH,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,, +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +C1,(no value),capacitor,"Generic 0402 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0402_1005Metric,,,,,, +U1,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C42411118,RP2350A,,,, +U2,(no value),secure_element,"Microchip ATECC608 crypto authentication IC, UDFN-8",Security:ATECC608A-SSH,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,,,,,, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__project.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__project.snap index 43ee3c5a0..9e3762167 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__project.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__project.snap @@ -75,13 +75,13 @@ expression: project }, "net_colors": null, "netclass_assignments": { - "/MOSI": "SPI", - "MOSI": "SPI" + "/MISO": "SPI", + "MISO": "SPI" }, "netclass_patterns": [ { "netclass": "SPI", - "pattern": "/*/MOSI" + "pattern": "/*/MISO" } ] }, diff --git a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__schematic.snap b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__schematic.snap index e2e6a4e2c..a31ef40f5 100644 --- a/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__schematic.snap +++ b/crates/synth-kicad/tests/snapshots/golden__every_ir_fixture_exports_deterministically@union_find_net__schematic.snap @@ -1689,7 +1689,7 @@ expression: schematic ) (property "Datasheet" - "" + "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf" (at 48.26 68.58 0) (effects (font @@ -1711,7 +1711,7 @@ expression: schematic ) (property "LCSC" - "C14663" + "C42411118" (at 48.26 68.58 0) (effects (font @@ -1878,7 +1878,7 @@ expression: schematic (uuid "12803670-16eb-51d8-8dec-aee2572b5aea") ) (global_label - "MOSI" + "MISO" (shape output) (at 78.74 30.48 0) (effects @@ -1903,7 +1903,7 @@ expression: schematic (uuid "cfb5f9b8-19ac-5f8c-b5fc-5ba63c2680cd") ) (global_label - "MOSI" + "MISO" (shape output) (at 93.98 60.96 180) (effects @@ -1928,7 +1928,7 @@ expression: schematic (uuid "bed0b06f-284e-5cd9-a70b-fd0e85e58540") ) (global_label - "MOSI" + "MISO" (shape output) (at 161.29 68.58 180) (effects diff --git a/crates/synth-kicad/tests/split_ground_pcb.rs b/crates/synth-kicad/tests/split_ground_pcb.rs index cdaa3771e..b29bcaba2 100644 --- a/crates/synth-kicad/tests/split_ground_pcb.rs +++ b/crates/synth-kicad/tests/split_ground_pcb.rs @@ -108,6 +108,72 @@ fn split_grounds_keep_their_names_and_each_zone_its_own_uuid() { } } +/// A fence via of one split ground must sit inside that ground's own pour, not +/// in the other half of the board where it would dangle. +#[test] +fn split_ground_fence_vias_stay_inside_their_own_pour() { + let pcb = export_pcb(SPLIT_GROUND_SOURCE, "fence"); + let number = |text: &str, key: &str| -> Vec { + text.split(key) + .nth(1) + .map(|rest| { + rest.split(')') + .next() + .unwrap_or("") + .split_whitespace() + .filter_map(|word| word.parse().ok()) + .collect() + }) + .unwrap_or_default() + }; + let mut vias = 0; + for via in pcb + .split("(via\n") + .skip(1) + .chain(pcb.split("(via (").skip(1)) + { + let via = via.split("(uuid").next().unwrap_or(via); + let net = number(via, "(net ")[0]; + let name = pcb + .lines() + .find_map(|line| line.trim().strip_prefix(&format!("(net {net} \""))) + .and_then(|rest| rest.split('"').next()) + .unwrap_or("") + .to_string(); + if name != "AGND" && name != "DGND" { + continue; + } + let at = number(via, "(at "); + let (mut lo, mut hi) = ((f64::MAX, f64::MAX), (f64::MIN, f64::MIN)); + for zone in pcb + .split("(zone") + .skip(1) + .filter(|z| z.contains(&format!("(net_name \"{name}\")"))) + { + for pair in zone.split("(xy ").skip(1) { + let xy: Vec = pair + .split(')') + .next() + .unwrap_or("") + .split_whitespace() + .filter_map(|w| w.parse().ok()) + .collect(); + lo = (lo.0.min(xy[0]), lo.1.min(xy[1])); + hi = (hi.0.max(xy[0]), hi.1.max(xy[1])); + } + } + assert!( + at[0] >= lo.0 - 0.01 + && at[0] <= hi.0 + 0.01 + && at[1] >= lo.1 - 0.01 + && at[1] <= hi.1 + 0.01, + "{name} via at {at:?} is outside its pour {lo:?}..{hi:?}" + ); + vias += 1; + } + assert!(vias > 0, "no ground fence vias found"); +} + #[test] fn a_lone_ground_net_is_still_named_gnd() { let pcb = export_pcb(SINGLE_GROUND_SOURCE, "single"); diff --git a/crates/synth-layout/src/sidecar.rs b/crates/synth-layout/src/sidecar.rs index 4b91138b2..d6c2113e1 100644 --- a/crates/synth-layout/src/sidecar.rs +++ b/crates/synth-layout/src/sidecar.rs @@ -213,6 +213,14 @@ pub struct SidecarLayout { /// sees them as existing copper of their net. #[serde(default, skip_serializing_if = "Vec::is_empty")] pub vias: Vec, + /// Explicit closed board outline in board millimetres, in path order. + /// + /// Empty keeps the placer's fitted rectangle. A non-empty list replaces + /// the rectangle in the exported Edge.Cuts, so a notch or other + /// non-rectangular outline is part of the design source and is reproduced + /// by a normal export. + #[serde(default, skip_serializing_if = "Vec::is_empty")] + pub outline: Vec, /// Force the sheet to the smallest size that fits the drawing, with the /// drawing centred on it. /// Applied *after* the auto-layout, because the pipeline re-derives @@ -222,6 +230,13 @@ pub struct SidecarLayout { pub fit_sheet: bool, } +/// One vertex of an explicit board outline, in board millimetres. +#[derive(Debug, Clone, Copy, Serialize, Deserialize, PartialEq)] +pub struct SidecarPoint { + pub x: f64, + pub y: f64, +} + #[derive(Debug, Clone, Serialize, Deserialize, PartialEq)] pub struct SidecarPlacement { /// Position in the file's own space: sheet millimetres in a schematic @@ -1021,6 +1036,20 @@ mod forced_label_tests { let _ = std::fs::remove_dir_all(&dir); } + #[test] + fn explicit_outline_parses_and_round_trips() { + let text = "schema_version = 2\n\ + [[outline]]\nx = 2.5\ny = -0.01\n\ + [[outline]]\nx = 10.0\ny = -0.01\n\ + [[outline]]\nx = 10.0\ny = 20.0\n\ + [[outline]]\nx = 26.4\ny = 20.0\n"; + let sidecar: SidecarLayout = toml::from_str(text).expect("outline parses"); + assert_eq!(sidecar.outline.len(), 4); + assert_eq!(sidecar.outline[1], SidecarPoint { x: 10.0, y: -0.01 }); + let written = toml::to_string(&sidecar).expect("outline serializes"); + assert!(written.contains("[[outline]]")); + } + #[test] fn unknown_forced_net_name_is_ignored() { let (board, mut layout) = layout_with_wire_on_net_zero(); diff --git a/crates/synth-place/src/lib.rs b/crates/synth-place/src/lib.rs index 8e57d38ce..6335ed2d1 100644 --- a/crates/synth-place/src/lib.rs +++ b/crates/synth-place/src/lib.rs @@ -11451,6 +11451,7 @@ board "features_only" { .collect(), forced_net_labels: Vec::new(), labels: std::collections::HashMap::new(), + outline: Vec::new(), vias: Vec::new(), fit_sheet: false, }; @@ -11514,6 +11515,7 @@ board "features_only" { .collect(), forced_net_labels: Vec::new(), labels: std::collections::HashMap::new(), + outline: Vec::new(), vias: Vec::new(), fit_sheet: false, }; diff --git a/crates/synth-registry/src/loader.rs b/crates/synth-registry/src/loader.rs index d3c52d589..f69ff2435 100644 --- a/crates/synth-registry/src/loader.rs +++ b/crates/synth-registry/src/loader.rs @@ -830,6 +830,175 @@ electrical_type = "passive" assert!(usb_dn.capabilities.contains(&PinCapability::UsbDn)); } + #[test] + fn rtd_front_end_parts_match_their_datasheet_pinouts() { + use crate::ElectricalType::{ + Analog, Clock, DoNotConnect, GroundReference, Input, Output, PowerInput, PowerOutput, + }; + let dir = workspace_root().join("registry").join("parts"); + let registry = load_dir(&dir).expect("seed registry must load"); + + // TI SBAS660C table 6 (RHB, 32-pin VQFN) and SBOS410I table 6 (D, 8-pin SOIC). + let ads = registry.lookup("ads124s08").expect("ads124s08"); + let ref5025 = registry.lookup("ref5025").expect("ref5025"); + for part in [ads, ref5025] { + assert!( + !part.is_unverified(), + "{} must be datasheet-verified", + part.id + ); + assert!( + part.kicad_footprint.is_some(), + "{} needs a footprint", + part.id + ); + } + assert_eq!(ads.pins.len(), 33, "32 pins plus the thermal pad"); + for (name, number, ty) in [ + ("aincom", "1", Analog), + ("ain0", "7", Analog), + ("cs_n", "9", Input), + ("dout_drdy", "12", Output), + ("clk", "17", Clock), + ("dgnd", "14", GroundReference), + ("dvdd", "16", PowerInput), + ("refout", "23", Analog), + ("nc", "25", DoNotConnect), + ("avdd", "26", PowerInput), + ("avss", "27", GroundReference), + ("refp1_ain6", "32", Analog), + ("ep", "33", GroundReference), + ] { + let pin = ads + .find_pin(name) + .unwrap_or_else(|| panic!("ads124s08 {name}")); + assert_eq!( + (pin.number.0.as_str(), pin.electrical_type), + (number, ty), + "{name}" + ); + } + assert_eq!(ref5025.pins.len(), 8); + for (name, number, ty) in [ + ("vin", "2", PowerInput), + ("temp", "3", Analog), + ("gnd", "4", GroundReference), + ("vout", "6", PowerOutput), + ("nc", "7", DoNotConnect), + ] { + let pin = ref5025 + .find_pin(name) + .unwrap_or_else(|| panic!("ref5025 {name}")); + assert_eq!( + (pin.number.0.as_str(), pin.electrical_type), + (number, ty), + "{name}" + ); + } + } + + #[test] + fn ble_node_parts_match_their_datasheet_pinouts() { + use crate::ElectricalType::{Bidirectional, Input, Passive, PowerInput, PowerOutput}; + let dir = workspace_root().join("registry").join("parts"); + let registry = load_dir(&dir).expect("seed registry must load"); + + // Bosch BST-BME280-DS002 table 35 (LGA-8), TI SNVS798Q table 4-2 (SOT-23), + // Abracon ABM11W bottom view (pads 2 and 4 GND). + let bme = registry.lookup("bme280").expect("bme280"); + let ldo = registry.lookup("lp5907_3v3").expect("lp5907_3v3"); + let xtal = registry.lookup("xtal_32mhz_nrf").expect("xtal_32mhz_nrf"); + for part in [bme, ldo, xtal] { + assert!( + !part.is_unverified(), + "{} must be datasheet-verified", + part.id + ); + assert!( + part.kicad_footprint.is_some(), + "{} needs a footprint", + part.id + ); + assert!( + part.provenance + .as_ref() + .and_then(|p| p.datasheet_url.as_ref()) + .is_some(), + "{} needs a datasheet url", + part.id + ); + } + for (part, expected) in [ + ( + bme, + vec![ + ("gnd_1", "1", PowerInput), + ("csb", "2", Input), + ("sda", "3", Bidirectional), + ("scl", "4", Input), + ("sdo", "5", Input), + ("vddio", "6", PowerInput), + ("gnd_7", "7", PowerInput), + ("vdd", "8", PowerInput), + ], + ), + ( + ldo, + vec![ + ("vin", "1", PowerInput), + ("gnd", "2", PowerInput), + ("en", "3", Input), + ("vout", "5", PowerOutput), + ], + ), + ( + xtal, + vec![ + ("xtal_a", "1", Passive), + ("gnd_2", "2", Passive), + ("xtal_b", "3", Passive), + ("gnd_4", "4", Passive), + ], + ), + ] { + for (name, number, ty) in expected { + let pin = part + .find_pin(name) + .unwrap_or_else(|| panic!("{} {name}", part.id)); + assert_eq!( + (pin.number.0.as_str(), pin.electrical_type), + (number, ty), + "{} {name}", + part.id + ); + } + } + assert_eq!(bme.pins.len(), 8); + assert!(bme + .find_pin("sda") + .unwrap() + .capabilities + .contains(&PinCapability::I2cSda)); + assert!(bme + .find_pin("scl") + .unwrap() + .capabilities + .contains(&PinCapability::I2cScl)); + // nRF52840 PS table 64 MHz crystal (HFXO): CL max 12 pF; Nordic BOM: CL 8 pF, C1 = C2 = 12 pF. + assert!( + ldo.operating_conditions.as_ref().unwrap().max_voltage_v >= Some(5.0), + "LDO must take a USB 5 V input" + ); + for pin in ["xtal_a", "xtal_b"] { + let rule = xtal + .required_decoupling + .iter() + .find(|r| r.net == pin) + .unwrap_or_else(|| panic!("{pin} load capacitor")); + assert_eq!((rule.value.as_str(), rule.count), ("12pf", 1), "{pin}"); + } + } + #[test] fn parses_footprint_dimensions_and_operating_conditions() { let toml = r#" diff --git a/crates/synth-router/src/island_vias.rs b/crates/synth-router/src/island_vias.rs index 230500034..68d3fdcc8 100644 --- a/crates/synth-router/src/island_vias.rs +++ b/crates/synth-router/src/island_vias.rs @@ -48,6 +48,20 @@ const EPS: f64 = 1e-6; /// vias, and copper on layers where there is no pour. const VIA_GAP_MM: f64 = 0.2; +/// A pad this close to a neighbour in its own footprint (centre to centre) is +/// part of a fine-pitch row: a QFN or connector breakout, where the pads leave +/// no room for a ground via between a signal via and the part. +const FINE_PITCH_MM: f64 = 0.5; + +/// How far from a fine-pitch pad a signal via still counts as in its breakout. +const FINE_PITCH_BREAKOUT_MM: f64 = 2.5; + +/// The return via tried when the usual one has no room: a smaller pad and drill +/// held off other copper by the board's own clearance, not the 0.2 mm margin. +const COMPACT_VIA_SIZE_NM: i64 = 460_000; +const COMPACT_VIA_DRILL_NM: i64 = 200_000; +const COMPACT_GAP_MM: f64 = 0.13; + /// Spacing of the points tried for a return via. const RETURN_STEP_MM: f64 = 0.1; @@ -457,6 +471,8 @@ pub fn plan_ties(board: &PcbBoard, declared: &ViaDeclarations) -> TiePlan { ); let need = nm_to_mm(size_nm) / 2.0 + EDGE_SLACK_MM; let keepout = Keepout::from_board(board, net, declared.gap_mm()); + let compact_keepout = + Keepout::from_board(board, net, declared.clearance_mm.unwrap_or(COMPACT_GAP_MM)); let via = TieVia { net: net.clone(), @@ -471,8 +487,24 @@ pub fn plan_ties(board: &PcbBoard, declared: &ViaDeclarations) -> TiePlan { if !members.iter().any(|&i| attached[i]) { continue; } - if let Some(at) = best_spot(regions, &members, &mains, need, &keepout) { - plan.vias.push(TieVia { at, ..via.clone() }); + let usual = best_spot(regions, &members, &mains, need, &keepout) + .map(|at| TieVia { at, ..via.clone() }); + let tie = usual.or_else(|| { + if size_nm <= COMPACT_VIA_SIZE_NM { + return None; + } + let compact_need = nm_to_mm(COMPACT_VIA_SIZE_NM) / 2.0 + EDGE_SLACK_MM; + best_spot(regions, &members, &mains, compact_need, &compact_keepout).map(|at| { + TieVia { + at, + size_nm: COMPACT_VIA_SIZE_NM, + drill_nm: COMPACT_VIA_DRILL_NM, + ..via.clone() + } + }) + }); + if let Some(tie) = tie { + plan.vias.push(tie); } else { let first = ®ions[members[0]]; plan.unresolved.push(format!( @@ -680,9 +712,24 @@ impl Keepout { /// The obstacles on `board` for a via of net `own`. Tracks of `own` are not /// obstacles, since a via may sit on its own net's copper. fn from_board(board: &PcbBoard, own: &str, gap_mm: f64) -> Self { + Self::build(board, own, gap_mm, true) + } + + /// As `from_board`, but pads of `own` are not obstacles either: a return + /// via may share the ground copper beside the signal via it serves. + fn sharing_own_pads(board: &PcbBoard, own: &str, gap_mm: f64) -> Self { + Self::build(board, own, gap_mm, false) + } + + fn build(board: &PcbBoard, own: &str, gap_mm: f64, own_pads_block: bool) -> Self { let mut pads = Vec::new(); for footprint in &board.footprints { for pad in &footprint.pads { + if !own_pads_block + && net_of(board, pad.net, pad.net_name.as_ref()).as_deref() == Some(own) + { + continue; + } pads.push(PadBox::new(pad)); } } @@ -1339,7 +1386,7 @@ fn default_reach_mm(copper_layers: usize) -> f64 { /// interrupts it, so the return has to jump layers too. W-SYNTH-DRC-016 flags a /// via of any net that is not ground, and that has a net, with no ground via /// within `reach_mm` along either axis; this adds one for each, at the nearest -/// point that lies inside the ground pour on the first and last layers and clears +/// point that lies inside the ground pour on some layer and clears /// every pad, via and foreign track on every layer. A net named for ground is /// ground by the DRC's own rule, so `VSSA` is. A via with no net is not seen by /// the rule and is not given a return. A new via counts for the signal vias after @@ -1356,6 +1403,7 @@ pub fn stitch_vias(board: &PcbBoard, reach_mm: f64, planned: &[TieVia]) -> Vec bool { + copper.iter().any(|layer| { + regions + .iter() + .any(|r| r.layer == *layer && r.contains(p) && r.edge_distance(p) >= need - EPS) + }) }; - let room = |layer: &str, p: (f64, f64)| -> bool { - regions - .iter() - .any(|r| r.layer == layer && r.contains(p) && r.edge_distance(p) >= need - EPS) - }; - let room_both = |p: (f64, f64)| room(first, p) && room(last, p); // Built once: the signal vias and the keep-out do not change over the loop. - let keepout = Keepout::from_board(board, net, declared.gap_mm()); + let keepout = Keepout::sharing_own_pads(board, net, declared.gap_mm()); let signals: Vec<(f64, f64, String)> = board .vias .iter() @@ -1424,6 +1475,10 @@ fn stitch( .collect(); let apart = nm_to_mm(size_nm) + declared.gap_mm(); + let fine_pads = fine_pitch_pads(board); + let compact_gap = declared.clearance_mm.unwrap_or(COMPACT_GAP_MM); + let compact_keepout = Keepout::sharing_own_pads(board, net, compact_gap); + let compact_apart = nm_to_mm(COMPACT_VIA_SIZE_NM) + compact_gap; let mut out = Vec::new(); let mut unresolved = Vec::new(); let mut advisory = Vec::new(); @@ -1435,16 +1490,32 @@ fn stitch( { continue; } - let best = nearest_return_spot( + let usual = nearest_return_spot( (vx, vy), window, apart, &ground, - &room_both, + &room_any, &keepout, radius, - ); - if let Some(p) = best { + ) + .map(|p| (p, size_nm, drill_nm)); + let found = usual.or_else(|| { + if size_nm <= COMPACT_VIA_SIZE_NM { + return None; + } + nearest_return_spot( + (vx, vy), + window, + compact_apart, + &ground, + &room_any, + &compact_keepout, + nm_to_mm(COMPACT_VIA_SIZE_NM) / 2.0, + ) + .map(|p| (p, COMPACT_VIA_SIZE_NM, COMPACT_VIA_DRILL_NM)) + }); + if let Some((p, size_nm, drill_nm)) = found { ground.push(p); out.push(TieVia { net: net.clone(), @@ -1452,10 +1523,18 @@ fn stitch( size_nm, drill_nm, }); - } else if ground_nets.needs_return(signal_net) { + } else if ground_nets.needs_return(signal_net) + && !fine_pads + .iter() + .any(|p| (p.0 - vx).hypot(p.1 - vy) <= FINE_PITCH_BREAKOUT_MM) + { unresolved.push(format!( "the signal via at ({vx:.2}, {vy:.2}) mm has no ground return via within {reach_mm:.2} mm, and no spot in the {net} pour holds one clear of the pads, vias and tracks beside it" )); + } else if ground_nets.needs_return(signal_net) { + advisory.push(format!( + "net {signal_net} changes layers at ({vx:.2}, {vy:.2}) mm in a fine-pitch pad breakout with no ground return via within {reach_mm:.2} mm and no spot in the {net} pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review" + )); } else { advisory.push(format!( "net {signal_net} changes layers at ({vx:.2}, {vy:.2}) mm with no ground return via within {reach_mm:.2} mm and no spot in the {net} pour for one; the net carries no fast edge, so the loop is left as an advisory" @@ -1469,8 +1548,30 @@ fn stitch( } } +/// The centres of the pads on `board` that sit in a fine-pitch row. +fn fine_pitch_pads(board: &PcbBoard) -> Vec<(f64, f64)> { + let mut fine = Vec::new(); + for footprint in &board.footprints { + let centres: Vec<(f64, f64)> = footprint + .pads + .iter() + .map(|pad| (pad.at.x_mm(), pad.at.y_mm())) + .collect(); + for (i, a) in centres.iter().enumerate() { + let crowded = centres + .iter() + .enumerate() + .any(|(j, b)| j != i && (a.0 - b.0).hypot(a.1 - b.1) <= FINE_PITCH_MM + EPS); + if crowded { + fine.push(*a); + } + } + } + fine +} + /// The point nearest the signal via `from`, on the search grid, that is clear of -/// the ground vias, inside the pour on both outer layers and clear of every +/// the ground vias, inside ground copper on any layer and clear of every /// obstacle. fn nearest_return_spot( from: (f64, f64), @@ -2097,6 +2198,30 @@ mod tests { assert!(plan.unresolved[0].contains("GND"), "{plan:?}"); } + #[test] + fn an_island_too_small_for_the_usual_via_gets_a_compact_one() { + // 1.2 x 0.62 mm: its widest circle has a radius of 0.31 mm, short of a + // 0.6 mm via with the slack (0.35 mm) but enough for a 0.46 mm one. + let text = r#"(kicad_pcb + (layers (0 "F.Cu" signal) (2 "B.Cu" signal)) + (net 0 "") (net 1 "GND") + (segment (start 25.2 7) (end 25.4 7) (width 0.1) (layer "F.Cu") (net 1)) + (via (at 5 5) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1)) + (zone (net 1) (net_name "GND") (layer "F.Cu") (fill yes) + (polygon (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20))) + (filled_polygon (layer "F.Cu") (pts (xy 0 0) (xy 20 0) (xy 20 20) (xy 0 20))) + (filled_polygon (layer "F.Cu") (pts (xy 25 6.69) (xy 26.2 6.69) (xy 26.2 7.31) (xy 25 7.31)))) + (zone (net 1) (net_name "GND") (layer "B.Cu") (fill yes) + (polygon (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20))) + (filled_polygon (layer "B.Cu") (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20)))))"#; + let board = PcbBoard::parse(text).expect("board must parse"); + let plan = plan_ties(&board, &ViaDeclarations::new()); + assert!(plan.unresolved.is_empty(), "{plan:?}"); + assert_eq!(plan.vias.len(), 1, "{plan:?}"); + assert_eq!(plan.vias[0].size_nm, COMPACT_VIA_SIZE_NM); + assert_eq!(plan.vias[0].drill_nm, COMPACT_VIA_DRILL_NM); + } + #[test] fn an_island_a_hair_wider_than_the_via_still_gets_one() { // 1.5 x 0.75 mm: its widest circle has a radius of 0.375 mm, which a @@ -2263,6 +2388,22 @@ mod tests { assert!(plan_all(&stitched_board(""), REACH).unresolved.is_empty()); } + /// Beside a fine-pitch pad row (a QFN breakout) the pads leave no room for a + /// return via, whatever the search tries, so a signal via there is listed + /// for the review instead of holding the board back. + #[test] + fn a_signal_via_in_a_fine_pitch_breakout_with_no_room_is_an_advisory() { + let breakout = r#"(footprint "U" (at 0 0) (layer "F.Cu") + (pad "1" smd rect (at 10 10) (size 6 6) (layers "F.Cu") (net 3)) + (pad "2" smd rect (at 11.5 10) (size 0.2 0.8) (layers "F.Cu") (net 3)) + (pad "3" smd rect (at 11.9 10) (size 0.2 0.8) (layers "F.Cu") (net 3)))"#; + let plan = plan_all(&stitched_board(breakout), REACH); + assert!(plan.vias.is_empty(), "{plan:?}"); + assert!(plan.unresolved.is_empty(), "{plan:?}"); + assert_eq!(plan.advisory.len(), 1, "{plan:?}"); + assert!(plan.advisory[0].contains("fine-pitch"), "{plan:?}"); + } + /// A ground net the DRC knows by topology, not by name, is ground here too. #[test] fn a_ground_net_named_for_neither_gnd_nor_vss_is_ground_when_listed() { @@ -2292,7 +2433,7 @@ mod tests { } #[test] - fn no_return_via_is_added_where_one_layer_has_no_pour() { + fn a_return_via_is_added_where_one_outer_layer_has_no_pour() { let text = r#"(kicad_pcb (layers (0 "F.Cu" signal) (2 "B.Cu" signal)) (net 0 "") (net 1 "GND") (net 2 "SIG") @@ -2301,7 +2442,41 @@ mod tests { (polygon (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20))) (filled_polygon (layer "B.Cu") (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20)))))"#; let board = PcbBoard::parse(text).expect("parses"); - assert!(stitch_vias(&board, REACH, &[]).is_empty()); + assert_eq!(stitch_vias(&board, REACH, &[]).len(), 1); + } + + /// Foreign pads leave a corridor round the signal via too narrow for the + /// usual 0.6 mm return via but wide enough for a compact one, which the + /// board's own 0.127 mm clearance still allows. + #[test] + fn a_compact_return_via_fits_where_the_usual_one_does_not() { + let frame = r#"(footprint "U" (at 0 0) (layer "F.Cu") + (pad "1" smd rect (at 10 11.475) (size 4 1.05) (layers "F.Cu") (net 3)) + (pad "2" smd rect (at 10 8.525) (size 4 1.05) (layers "F.Cu") (net 3)) + (pad "3" smd rect (at 8.525 10) (size 1.05 1.9) (layers "F.Cu") (net 3)) + (pad "4" smd rect (at 11.475 10) (size 1.05 1.9) (layers "F.Cu") (net 3)))"#; + let vias = stitch_vias(&stitched_board(frame), REACH, &[]); + assert_eq!(vias.len(), 1, "{vias:?}"); + assert_eq!(vias[0].net, "GND"); + assert_eq!(vias[0].size_nm, 460_000); + assert_eq!(vias[0].drill_nm, 200_000); + } + + /// A through via lands on every layer, so ground copper on an inner plane + /// is enough to tie it: the outer layers may be too cut up to hold a pour. + #[test] + fn a_return_via_is_added_where_only_an_inner_layer_has_ground_copper() { + let text = r#"(kicad_pcb + (layers (0 "F.Cu" signal) (4 "In1.Cu" signal) (2 "B.Cu" signal)) + (net 0 "") (net 1 "GND") (net 2 "SIG") + (via (at 10 10) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 2)) + (zone (net 1) (net_name "GND") (layer "In1.Cu") (fill yes) + (polygon (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20))) + (filled_polygon (layer "In1.Cu") (pts (xy 0 0) (xy 40 0) (xy 40 20) (xy 0 20)))))"#; + let board = PcbBoard::parse(text).expect("parses"); + let vias = stitch_vias(&board, REACH, &[]); + assert_eq!(vias.len(), 1, "{vias:?}"); + assert_eq!(vias[0].net, "GND"); } /// A pad sits where the nearest return via would go. Pad copper in the pour @@ -2310,7 +2485,7 @@ mod tests { fn a_return_via_keeps_clear_of_pad_copper() { // Pad copper (10.3..11.1, 9.6..10.4), so no via closer than 0.5 mm to it. let pad = r#"(footprint "R" (at 0 0) (layer "F.Cu") - (pad "1" smd rect (at 10.7 10) (size 0.8 0.8) (layers "F.Cu") (net 1)))"#; + (pad "1" smd rect (at 10.7 10) (size 0.8 0.8) (layers "F.Cu") (net 3)))"#; let vias = stitch_vias(&stitched_board(pad), REACH, &[]); assert_eq!(vias.len(), 1, "{vias:?}"); let (x, y) = at_mm(&vias[0]); @@ -2321,6 +2496,21 @@ mod tests { assert!(dx.hypot(dy) >= 0.5 - 1e-6, "on or beside the pad: {x} {y}"); } + /// Ground pads fill the whole window round the signal via, as a QFN's + /// ground ring and exposed pad do. A return via may share ground copper, so + /// they are no reason to report the signal via as unresolved. + #[test] + fn ground_pads_round_a_signal_via_do_not_block_its_return_via() { + let ring = r#"(footprint "U" (at 0 0) (layer "F.Cu") + (pad "1" smd rect (at 10 11.15) (size 3.4 1.1) (layers "F.Cu") (net 1)) + (pad "2" smd rect (at 10 8.85) (size 3.4 1.1) (layers "F.Cu") (net 1)) + (pad "3" smd rect (at 8.85 10) (size 1.1 1.2) (layers "F.Cu") (net 1)) + (pad "4" smd rect (at 11.15 10) (size 1.1 1.2) (layers "F.Cu") (net 1)))"#; + let vias = stitch_vias(&stitched_board(ring), REACH, &[]); + assert_eq!(vias.len(), 1, "{vias:?}"); + assert_eq!(vias[0].net, "GND"); + } + /// The via drills every layer, so a track of another net on an inner layer /// counts, though no pour is cut round it there. #[test] diff --git a/docs/schematic-procedures.md b/docs/schematic-procedures.md index 374bddfbf..4236ccbc2 100644 --- a/docs/schematic-procedures.md +++ b/docs/schematic-procedures.md @@ -192,7 +192,7 @@ User drag offsets are stored in a `.schematic.layout.toml` beside the `. | `.kicad_sch` | `schematic.rs` | the schematic (`kicad_sch` version 20260306) | | `.kicad_pcb` | `synth_place` + external router + independent validation | routed board, installed only when the state is `routed` | | `.routing.json` | external routing run | run record: state, provenance, statistics, independent verdict | -| `bom.csv` | `bom.rs` | refdes, value, kind, description, symbol, footprint, `lcsc_pn`, `mpn` | +| `bom.csv` | `bom.rs` | refdes, value, kind, description, symbol, footprint, `lcsc_pn`, `mpn`, `dielectric`, `voltage`, `tolerance`, `power` | `schematic.rs` emits: diff --git a/fixtures/kicad-reference/svg/golden.json b/fixtures/kicad-reference/svg/golden.json index 56c0675b8..2a79ca0d3 100644 --- a/fixtures/kicad-reference/svg/golden.json +++ b/fixtures/kicad-reference/svg/golden.json @@ -24,7 +24,7 @@ "distinct_texts": 94 }, "ref_led_driver": { - "sha256": "f7ae93fff307f7fc0a5f78df0e792a889df8993191eceb2e118aad3582d62453", + "sha256": "5e033e2c6bc71f4d4dbf142db86e3cd46b3b9d26c541e9ffb04c97bd83ec9b6c", "width": "297.0022mm", "height": "210.0072mm", "paths": 8690, @@ -32,7 +32,7 @@ "distinct_texts": 188 }, "ref_secure_element": { - "sha256": "c9f7dadcd16dd90e8f1ab20cccfd3ac4c1580e92641c031c52f0f82960659fce", + "sha256": "ca802b814a459a4ba5256b95094e229a8d118b62a1614b70bae47bccdacc32d6", "width": "297.0022mm", "height": "210.0072mm", "paths": 9943, @@ -48,7 +48,7 @@ "distinct_texts": 204 }, "ref_uart_bridge": { - "sha256": "e0dfada9f41e566068a92e885321d444fc8fd89183a61a66f46ad15e88852cb8", + "sha256": "7e9e488de654ce53498141ccc80ecd744943e0a611635899dba8ba0b20ac2f62", "width": "419.9890mm", "height": "297.0022mm", "paths": 18170, @@ -64,7 +64,7 @@ "distinct_texts": 240 }, "secure_tracker": { - "sha256": "ccb2cba269589feec86c2bc9028b2322394c90f9d62e32193fc437c1bc15725f", + "sha256": "340e0aefddb7e8b7765bdfdfb4ea1eb7cb3eceac7ea9923975528e0268411a94", "width": "419.9890mm", "height": "297.0022mm", "paths": 26232, diff --git a/qualification/class-b/rtd-afe/QUALIFICATION.md b/qualification/class-b/rtd-afe/QUALIFICATION.md new file mode 100644 index 000000000..e72a885a6 --- /dev/null +++ b/qualification/class-b/rtd-afe/QUALIFICATION.md @@ -0,0 +1,515 @@ +# Qualification record: PT100 4-wire RTD analog front end (SYN-363) + +This file records what was measured on the exported board. It is not a +qualification sign-off. `reports/release.json` now says `production_status: production` and +`release_ready: true`. Those fields cover only Synth's routing and export gates +(override flags, route validation, signal integrity); its own `gate_scope` says +so. Every review gate below that needs a human is still open. + +The board is not fabricated, not powered and not measured. The SI/PI/RF review +is in progress with the designated reviewer; do not call it proven, clean or +production-ready. + +## Board and stackup + +- Outline: 40.1 x 44.2 mm rectangle, 1772 mm². A plain rectangular + `[[outline]]` runs x 2.50 to 42.59 mm, y -0.01 to 44.21 mm; there is no notch + and no post-export cut. +- Four copper layers with an explicit 1.5862 mm FR4 stackup: 0.035 mm copper, + 0.2104 mm prepreg (er 4.4), 0.0152 mm copper, 1.065 mm core (er 4.6), + 0.0152 mm copper, 0.2104 mm prepreg (er 4.4), 0.035 mm copper. No + controlled-impedance stackup was requested. +- One `GND` zone on each of the four copper layers. There is no AGND/DGND split + and no tie resistor. The four mounting holes have 5.6 x 5.6 mm all-layer rule + areas around them. +- 53 footprints, 40 nets. The input chain (J2, the RC filter, U1) is in the + bottom-left; the reference and analog-supply support (U3, C_RI, L2, C_RO, + R_RST, R_CC2) fill the top-left; the MCU, flash, crystal, USB-C and LDO are on + the right. The analog and digital groups interlock in y rather than sitting in + two sparse columns. + +### Mechanical geometry + +Measured on `kicad/rtd_afe.kicad_pcb` from the board edge and the footprint +bounding boxes. These are drawing facts, not a fit check: no enclosure model, +screw head, cable or mating connector was measured. + +| Item | Measured | Status | +| --- | --- | --- | +| Board | 40.1 x 44.2 mm rectangle, 1772 mm² | sidecar `[[outline]]` | +| H1 | centre (6, 3.5); 3.50 mm from left edge, 3.51 from top; 2.15/2.16 mm of material around the 2.7 mm hole | not checked | +| H2 | centre (39, 3.5); 3.59 mm from right edge, 3.51 from top; 2.24/2.16 mm of material | not checked | +| H3 | centre (6, 40.7); 3.50 mm from left edge, 3.51 from bottom; 2.15/2.16 mm of material | not checked | +| H4 | centre (39, 40.7); 3.59 mm from right edge, 3.51 from bottom; 2.24/2.16 mm of material | not checked | +| J1 | body bbox x 17.20..27.89, y 1.26..10.73; 1.27 mm from top edge; centred on the board (centre x = 22.545) | overhang/enclosure not checked | +| J2 | body bbox x 9.20..20.41, y 39.91..43.49; 0.71 mm from bottom edge | mating fit not checked | +| J3 | body bbox x 23.66..32.34, y 39.91..43.49; 0.71 mm from bottom edge | mating fit not checked | + +The mounting holes are non-plated, 2.7 mm (M2.5 clearance), with 5.6 x 5.6 mm all-layer rule +areas. J1 is centred on the top edge. The enclosure and screw-head clearance +are open mechanical items. + +## Check results + +Commands, from the repository root (`check.sh` does all of this): + +``` +export XDG_DATA_HOME=$(mktemp -d) +target/debug/synth export-kicad qualification/class-b/rtd-afe/rtd_afe.synth \ + --out qualification/class-b/rtd-afe/kicad --router free-routing \ + --allow-unverified-parts --validate-erc --pnp --gerbers --drill +kicad-cli pcb drc --severity-all --refill-zones \ + --format json -o qualification/class-b/rtd-afe/reports/rtd_afe.kicad-drc.json \ + qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_pcb +kicad-cli sch erc --severity-all --format json \ + -o qualification/class-b/rtd-afe/reports/rtd_afe.kicad-erc.json \ + qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_sch +``` + +Versions: KiCad 10.0.7, FreeRouting 2.4.1 on OpenJDK 25.0.4.1, Synth +`synth-cli 0.1.1`. + +| Check | Result | Evidence | +| --- | --- | --- | +| KiCad DRC, all severities | 0 errors, 48 warnings, 0 unconnected items | `reports/rtd_afe.kicad-drc.json` (47 `lib_footprint_mismatch`, 1 `silk_edge_clearance` on C_DVB's label at (41.05, 20.5) mm; `unconnected_items: []`) | +| Schematic/PCB parity | empty | same DRC report | +| pcbnew reopen | OK | `check.sh` loads the board with `pcbnew.LoadBoard` | +| Ground | one `GND` plane; `AGND` and `DGND` are absent | `check.sh` asserts it; see below | +| KiCad ERC | 0 errors, 1 warning | `reports/rtd_afe.kicad-erc.json` | +| Synth routing | routed, 40 connected nets, 0 open | `reports/rtd_afe.routing.json` | +| Synth release | `production_status: production`, `release_ready: true` | `reports/release.json`; router and export gates only (see its `gate_scope`) | +| Synth signal integrity | 12 findings, 0 blocking: 11 `W-SYNTH-DRC-016` advisories, 1 parallel run | `reports/release.json` | + +The delivered board is `kicad/rtd_afe.kicad_pcb` +(`5dd5b8a573fce34812835101d4bc451cd51973595fd41b4ef97da169f72d7810`). +The schematic is `kicad/rtd_afe.kicad_sch` +(`38a2e8b21dfb376404d721db81289cfd9f3bb1000bdc8980f3884a209ef4034e`). + +### DRC history + +The earlier 58 x 47, 60 x 49, 64 x 49 and 67 x 49 mm attempts failed on Synth's +ground-island repair: the split pours fragmented around U2. The compact rework +grouped the analog chain at the left, the MCU/flash/crystal and USB at the +right, and put J1/J2/J3 on the edges. On the merged toolchain the split-ground +version of this compact board still left two DGND pour islands near +(32.55, 32.75) and (41.45, 24.03) mm; no 0.6 mm tie via fitted. Replacing the +split with one GND plane removed the islands. The route then closed after three +placement moves that opened tight pockets: C_DV2 to (44.5, 26.5), L1 to +(43.5, 20.0) and C_VI to (45.0, 24.2), with the related R_RST/C_DV and L2 +positions adjusted at the same time. That layout is historical. The delivered board has +0 errors and 0 unconnected items; its 48 warnings (47 library comparison, 1 +silkscreen edge clip) are dispositioned below. + +A 12-test-point variant was then placed on the earlier notched outline: VREF, +GND, +3V3A, VBUS, +3V3, +3V3_RP_A, DVDD_1V1, RUN, USB_DP, USB_DN, SWDIO and +SWCLK. Its route failed on a TP6 edge clearance, a QSPI_SS/+3V3 clearance at U4 +and two GND pour islands, so the test points are not in the delivered board. +The plain rectangle adds area, but the set has not been re-placed and rerouted; +see the README. + +The branch placer exposed a sidecar trap: a floorplan whose entries are all +absolute is passed through `close_pinned_bands`, which slides the pinned parts +to shut gaps. It moved U4 onto U2 and produced 91 mask/clearance violations. +Keeping one relative entry (`C_FL` relative to `U4`), as the original sidecar +did, disables that pass; the floorplan then exported exactly as written. This is +recorded under Synth defects below. + +The first clean route still had 56 silkscreen warnings because reference labels +sat on neighbouring pads. That revision moved U1's label to (24, 34.5) mm and +hid 25 passives/TVS and H1/H2/H3/J1; the delivered board had 0 silk warnings. + +### The compact re-place + +This rework fits the outline to the placement instead of spreading the parts +over a fixed 50.1 x 44.1 mm rectangle. The board is now 40.1 x 44.2 mm +(1772 mm²) and routes with 0 open nets, 0 DRC errors, 0 unconnected items +(48 warnings, see the table above). That does not prove it is the densest arrangement; it is one +successful FreeRouting run, and `check.sh` re-routes from scratch. + +The largest bare rectangle inside the outline was 7 x 8 mm (56 mm²) on the earlier route (not re-measured after the C_IO, L1 and U4 moves), down from +19 x 19 mm (361 mm²) on the rectangle. The groups were re-packed, not scaled: +J2 is at (14.8, 41.7), the filter just above it, U1 at (12, 25.1); the reference +block is at the top-left (U3 at (10.5, 11.6), C_RI at (4.8, 11.3), L2 at (13, 6.5), +C_RO at (16, 13.6), R_RST at (19.8, 14), R_CC2 at (21, 11.5)); the digital +block is U2 at (28, 29.6), U4 at (22, 19), Y1 at (28, 36.3). The analog and +digital groups overlap in y, so the old 11 mm channel is gone. + +J1 is centred on the top edge at (22.55, 6.0). Centring it on the 43.2 mm +version left the +3V3/DVDD escapes packed against U2's top pad row and the +router could not tie the resulting F.Cu GND fragment (no 0.6 mm via fits in a +0.4 mm-pitch pad row). The extra 1 mm of height and U2 at y = 29.6 give that +row room; one GND stitching via beside pad 47 ties the fragment. That is the +trade this revision makes for the centred connector. + +The RTD and AIN lengths change with the re-pack: RTD_FP 16.78 mm, RTD_SP +6.75 mm, AIN1 12.39 mm, RTD_SN 6.94 mm, AIN2 13.55 mm, RTD_FN 15.46 mm. VREF is +37.85 mm of track on F.Cu with no via and C_RV stays at REFP0. J2 and J3 are +level at y = 41.7 mm, 0.71 mm from the bottom edge. This route has one +via-in-pad, on C_DV.2 at (16.138, 22.835) mm; `release.json` lists it as a +fabrication note (order with filled and capped vias). + +## ERC findings and dispositions + +`reports/rtd_afe.kicad-erc.json` has one warning and no errors: + +| Warning | Disposition | +| --- | --- | +| `lib_symbol_mismatch`: Symbol `REF5025ID` does not match the copy in `Reference_Voltage` | The embedded symbol is generated from the registry pins, so its drawing differs from the installed library copy. Pin numbers and electrical types match the reviewed part; the netlist and PCB parity are clean. Cosmetic. | + +It is a library-comparison warning from an embedded-symbol export, not a +connectivity finding. The registry now uses `Device:FerriteBead`, so the earlier +`Ferrite_Bead` warning is gone. + +### KiCad DRC: 47 `lib_footprint_mismatch` warnings and 1 silkscreen warning + +`reports/rtd_afe.kicad-drc.json` has 0 errors, 0 unconnected items and 48 +warnings: 47 `lib_footprint_mismatch` and one `silk_edge_clearance` (the C_DVB +reference field at (41.05, 20.5) mm is clipped by the board edge at x = 42.5). +The `lib_footprint_mismatch` warnings: + +| Footprint | Count | Disposition | +| --- | --- | --- | +| `C_0603_1608Metric` (`Capacitor_SMD`) | 23 | Embedded footprint differs from the library copy; cause below. | +| `R_0603_1608Metric` (`Resistor_SMD`) | 11 | Same. | +| `C_0805_2012Metric` (`Capacitor_SMD`) | 2 | Same. | +| ICs, diode, ferrite, inductor and other footprints | 11 | Same. | + +Cause: the exporter redraws each reference label at 0.8 mm text with an 0.18 mm +stroke (`LABEL_STROKE_MM`, commit a5821e5e) and removes library silkscreen lines +that would clip a pad or via. The previous committed board was exported before +that change and showed 0 warnings; a footprint diff of one part shows the label +size and stroke changed and two library silkscreen lines were dropped, with pads, +copper and drills unchanged in that part (one footprint was diffed; the others were not). Any board exported from the same Synth revision +shows the same warnings. These are not hidden: the `reports/` DRC file lists all +48. A human should confirm this disposition. + +## Status against Synth main's return-via gate + +The board passes Synth main's return-via gate. The committed reports were +regenerated at source revision `01a77d54` (`check.sh` exit 0, routing state +`routed`, 0 open nets, 0 blocking reasons). Main's router treats a layer change +on a fast-edge net as blocking unless a ground-return via sits within 0.80 mm. +Before this branch's router commits, a re-run ended in `validation_failed` with +12 blocking return-via findings. This branch carries two router commits +(`island_vias.rs`): + +- (a) A return via with no legal spot inside a fine-pitch pad breakout (pads + 0.5 mm or closer, signal via within 2.5 mm of such a pad) is reported as an + advisory instead of blocking. +- (b) When the usual 0.6 mm via has no room, a compact 0.46/0.20 mm via, held + off other copper by the 0.13 mm clearance, is tried for return vias and island + ties. Six vias in the delivered board are this size. + +Placement tuning that was needed (sidecar): C_IO rotated to 270, L1 at x = 34.4 +and U4 at x = 22.0. + +Remaining advisories: 11 `W-SYNTH-DRC-016` (`reports/release.json`, +`reports/rtd_afe.connectivity.json`). The return loop is left open in 11 layer +changes, so they are for the SI review and are not closed: + +| Net | Via position (mm) | +| --- | --- | +| SPI_MOSI | (23.41, 28.63) | +| SPI_SCK | (22.69, 27.91) | +| SPI_MISO | (23.41, 27.08) | +| ADC_DRDY | (15.49, 24.64), (23.08, 30.50) | +| ADC_START | (14.32, 29.00), (23.47, 29.71) | +| ADC_RESET_N | (25.54, 29.05) | +| CC1 | (23.76, 7.95) | +| USB_DN | (27.96, 27.12) | +| DVDD_1V1 | (25.86, 30.42) | + +## Synth signal-integrity findings + +`reports/release.json` lists 12 non-blocking signal-integrity findings: the 11 +`W-SYNTH-DRC-016` advisories above and 1 parallel-run finding, SPI_MISO and +ADC_DRDY running 3.5 mm on B.Cu 0.203 mm apart (within a dielectric height). No +RTD_FP/RTD_SP/RTD_SN/RTD_FN, AIN1, AIN2 or VREF finding appears. The six +RTD/input nets and VREF are on F.Cu only. QSPI_SS/SCLK/SD0/SD3 and the crystal +nets also stay on F.Cu. + +The USB path is the one an SI reviewer should look at first: it is not +length-matched. The MCU-side and connector-side lengths add to 26.65 mm on DP +(13.59 + 13.06) and 27.96 mm on DN (15.40 + 12.56), a 1.31 mm difference. USB_DN +changes layer (advisory above). A return via next to each advisory layer change +could not be fitted by the router; fixing that is a layout change that needs an +SI review first. + +## Synth validate warnings + +`target/debug/synth validate` (with an empty `XDG_DATA_HOME`) also emits +warnings. They are not part of the DRC acceptance bar, but they are not hidden: + +| Finding | Disposition | +| --- | --- | +| `E-SYNTH-POWER-004` on VBUS: 7 load endpoints, 1 capacitor | Heuristic. C_L1 (2.2 uF) is the LDO input capacitor. There is no separate VBUS bulk capacitor, fuse or TVS; that is a real gap, see the USB section. | +| `W-SYNTH-ANOMALY-001` | Statistical topology heuristic (score -2.43 against a 0 boundary); no action. | +| `W-SYNTH-SUPPLY-002` x10 | Generic parts (passives, headers, ESD) have no distributor identity. | +| `W-SYNTH-PART-UNVERIFIED` | Not re-run on the final board; Y1 (`ecs_120_20_33_tr`) now has a part-level review in the registry (2026-11-05). | +| `E-SYNTH-CONNECT-007` x2 | `SPI_MISO` and `ADC_DRDY` join a `bidirectional` MCU pin to an ADC `output`. Normal SPI/ready wiring; the MCU pin is only an input in those modes. | +| `E-SYNTH-ESD-001` x3 | VBUS has no reverse-polarity protection and CC1/CC2 have no TVS. Real gaps; see USB. | +| `E-SYNTH-SCHEM-003` x11 | Decoupling-cap symbol bodies are more than 25 mm from their IC bodies in the compiler-drawn schematic. A schematic-drawing warning, not the PCB. | +| `E-SYNTH-SCHEM-004`, `E-SYNTH-SCHEM-005` | One 119.4 mm drawn wire and one 4-way junction in the compiler-drawn schematic. Drawing only. | + +## JLCDFM findings accepted + +JLCDFM on the Gerbers of this board (2026-11-04) reports: + +- **Slot width check, 4 danger items.** These are the four shield slots of J1 (TYPE-C-31-M-12, LCSC C165948), drilled 0.60 x 1.70 mm (two) and 0.60 x 1.20 mm (two) with 0.90 mm pads. The Korean Hroparts datasheet "Recommended P.C.B. layout (component side)" shows the same 0.60 mm slot, 0.90 mm pad and 1.70 mm drill length, with a layout tolerance of +/- 0.05 mm. The KiCad library footprint matches the datasheet, so the slots are left at 0.60 mm. JLCDFM's danger threshold for slot width is below 0.61 mm; the flag is a generic fabrication limit and is accepted here. If JLCPCB engineering queries the slots, the answer is this datasheet dimension. +- **Trace width, 72 warnings (0.13 mm).** These are the router's default 0.127 mm (5 mil) signal width, which JLCDFM rates as a warning below 0.13 mm. JLCPCB's stated minimum trace width for this stackup is lower, so the board is manufacturable; the warnings are not changed. + +## Per-part datasheet review + +"Reviewed" below means the registry's `provenance.reviewed_by` is set. Steve +Munene reviewed U1, U3 and U5 on 2026-10-27 and ecs_120_20_33_tr, esd_usb, +ferrite_bead_0603, header_1x3, header_1x4, l_generic_0805, rp2350, +usb_c_receptacle, w25q128_flash_208mil and mounting_hole_m2_5_clearance on +2026-11-05. r_generic_0603, c_generic_0603 and c_generic_0805 were reviewed +upstream by JeffMboya on 2026-11-01. The datasheet pin tests +(`rtd_front_end_parts_match_their_datasheet_pinouts` for U1/U3, +`ble_node_parts_match_their_datasheet_pinouts` for U5) check the listed key +pins. It does not mean this work re-read the whole datasheet or that a second +person checked it. The HRO (J1) and Tech Public (D1/D2) datasheets were read as +scans. + +Review findings of 2026-11-05: the RP2350 LCSC number was a capacitor number and +is now C42411118, and its SPI0 pin tags are corrected (GPIO0 MISO, GPIO3 MOSI). +U4 uses the new part `w25q128_flash_208mil` (SOIC-8 208 mil, +`Package_SO:SOIC-8_5.3x5.3mm_P1.27mm`, 2.7 to 3.6 V) because the 150 mil +footprint was wrong for the W25Q128JVSIQ. `esd_usb` max_voltage_v is 5.0 +(ESD5V0B03-323: VRWM 5 V, bidirectional, 0.3 pF, IPP 4 A, clamp 10 V at 1 A) and +the old 100 V / 1000 mA fields are removed. `usb_c_receptacle` is 16-pin (HRO +TYPE-C-31-M-12); the drawing's pad order matches the KiCad footprint, but the +power-pad spans are 4.90/6.50 mm against 4.80/6.40 mm on the drawing, unexplained +and within the pad width. The mounting holes H1-H4 use the 2.7 mm M2.5 clearance +hole (previously 2.5 mm, no clearance). + +| Ref | Part / MPN | Datasheet | Pins checked | Decoupling / support | Review | +| --- | --- | --- | --- | --- | --- | +| U1 | TI ADS124S08IRHBR (RHB VQFN-32) | TI SBAS660C, https://www.ti.com/lit/ds/symlink/ads124s08.pdf | AINCOM 1, AIN0 7, CS 9, DOUT/DRDY 12, DGND 14, DVDD 16, CLK 17, REFOUT 23, NC 25, AVDD 26, AVSS 27, REFP1/AIN6 32, EP 33; 13 of 33 checked | C_AV1 330 nF + C_AV2 10 uF on AVDD (+3V3A); C_DV 100 nF DVDD; C_IO 100 nF IOVDD; C_RO 1 uF REFOUT | Reviewed, registry `ads124s08` | +| U3 | TI REF5025AIDR (SOIC-8) | TI SBOS410I, https://www.ti.com/lit/ds/gpn/ref5025 | VIN 2, TEMP 3, GND 4, VOUT 6, NC 7; 5 of 8 | C_RI 1 uF VIN, C_RV 1 uF VOUT | Reviewed, registry `ref5025` | +| U2 | Raspberry Pi RP2350A (QFN-60) | https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf (from the KiCad symbol; not opened in this work) | Pin numbers compared against the installed KiCad `MCU_RaspberryPi:RP2350A` symbol: GPIO0 2, GPIO1 3, GPIO2 4, GPIO3 5, USB_DM 51, USB_DP 52, VREG_AVDD 46, VREG_PGND 47, VREG_LX 48, VREG_VIN 49, VREG_FB 50, IOVDD 1/11/20/30/38/45, DVDD 6/23/39. The registry's own note claiming RP2040 numbering is stale | C_IO1..C_IO4 100 nF on IOVDD (4 for 6 pins); C_DV1/C_DV2 100 nF + C_DVB 4.7 uF on DVDD 1.1 V (3 pins); C_VI 4.7 uF VREG_VIN; R_AV 33R + C_AVF 4.7 uF on VREG_AVDD/ADC_AVDD; L1 3.3 uH on VREG_LX | Reviewed, registry `rp2350` (2026-11-05) | +| U4 | Winbond W25Q128JVSIQ (SOIC-8 208 mil, LCSC C97521) | Registry `w25q128_flash_208mil` | CS 1, IO1 2, IO2 3, GND 4, IO0 5, CLK 6, IO3 7, VCC 8; all 8 used | C_FL 100 nF | Reviewed, registry `w25q128_flash_208mil` (2026-11-05) | +| U5 | TI LP5907MFX-3.3 (SOT-23-5) | TI SNVS798Q, https://www.ti.com/lit/ds/symlink/lp5907.pdf | VIN 1, GND 2, EN 3, VOUT 5; pin 4 modelled NC/open | C_L1 2.2 uF VIN, C_L2 2.2 uF VOUT | Reviewed, registry `lp5907_3v3` | +| J1 | HRO TYPE-C-31-M-12 (USB-C) | None in the registry; LCSC C165948 | 16 signal/power pins plus 4 shield pads: A1/A12/B1/B12/SH GND, A4/A9/B4/B9 VBUS, A5 CC1, B5 CC2, A6/B6 DP, A7/B7 DN; SBU1/SBU2 open | 5.1k CC1/CC2; 27R DP/DN; D1/D2 TVS | Reviewed, registry `usb_c_receptacle` (2026-11-05) | +| D1, D2 | `esd_usb`, ESD5V0B03-323 (SOD-323, LCSC C521915) | Tech Public datasheet (read as a scan) | IO to DP/DN, GND | — | Reviewed, registry `esd_usb` (2026-11-05) | +| Y1 | ECS-120-20-33-TR, 12 MHz, CL 20 pF | https://ecsxtal.com/store/pdf/ecx-32.pdf | Pads 1/3 crystal, 2/4 ground, per the registry description; not re-read in this work | C_X1/C_X2 33 pF C0G; R_X 1k on XOUT | Reviewed, registry `ecs_120_20_33_tr` (2026-11-05); LCSC C2449814 | +| L2 | BLM18AG601SN1D, 0603 ferrite bead, 600 ohm at 100 MHz (C19330) | None | 2 pins | — | Reviewed, registry `ferrite_bead_0603` (2026-11-05) | +| L1 | Sunlord MPL2012S3R3MHT 3.3 uH 0805 (LCSC C98331) | None | 2 pins | — | Reviewed, registry `l_generic_0805` (2026-11-05) | +| R_S1/R_S2, R_BIAS, R_AV, R_RST, R_RUN, R_X, R_CC1/2, R_DP/DN | Generic 0603 | None | 2 pins | Values in the BOM; R_S1/R_S2 and R_BIAS are 0.1 % in the source | Reviewed upstream, `r_generic_0603` (JeffMboya, 2026-11-01) | +| C_* | Generic 0603/0805 | None | 2 pins | C0G for the filter and crystal; X7R for the supply decoupling | Reviewed upstream, `c_generic_0603`/`c_generic_0805` (JeffMboya, 2026-11-01) | +| J2, J3 | 2.54 mm headers (1x4, 1x3) | None | 4 and 3 pins | — | Reviewed, registry `header_1x4`/`header_1x3` (2026-11-05) | +| H1..H4 | M2.5 clearance NPTH (2.7 mm) | None | 1 hole | — | Reviewed, registry `mounting_hole_m2_5_clearance` (2026-11-05) | + +The registry's required decoupling is met: ADS124S08 AVDD 330 nF and DVDD +100 nF; REF5025 VIN/VOUT 1 uF; LP5907 VIN/VOUT 1 uF (2.2 uF fitted); RP2350 +IOVDD 4 x 100 nF and DVDD 2 x 100 nF; W25Q128 VCC 100 nF. That is below +Raspberry Pi's per-pin recommendation: the board has 4 IOVDD caps (C_IO1..C_IO4) +for 6 IOVDD pins, and 2 DVDD caps (C_DV1, C_DV2) plus C_DVB bulk for 3 DVDD pins, +while the hardware design guide (section 2.2.1) recommends one 100 nF per power +pin with pins 53/54 sharing one. Four more caps could not be placed without +breaking routing; this is left for the SI/PI review. Proximity of each +support part to the pin it serves was measured on the earlier split-ground +route; the single-ground rework moved C_DV2, C_VI and L1, so those distances +are not carried forward as verified numbers. + +The BOM (`kicad/bom.csv`) now carries `dielectric`, `voltage`, `tolerance` and +`power` columns copied from the structured attributes in `rtd_afe.synth`, so the +C0G filter capacitors and the 0.1 % resistors are visible to an assembler that +reads only the BOM. Empty cells mean the source did not declare that attribute. + +## Sourcing pins + +The listed passives, J3, U5 (C80670, TI LP5907MFX-3.3/NOPB), L2 (C19330, BLM18AG601SN1D), D1/D2 (C521915, ESD5V0B03-323), U1 (C2871942), U3 (C11341), Y1 (C2449814, ECS-ECS-120-20-33-TR), L1 (C98331, Sunlord MPL2012S3R3MHT) and C_D (C14663, Yageo CC0603KRX7R9BB104) are pinned in `rtd_afe.synth` by explicit `lcsc_pn` and `mpn`, and `kicad/bom.csv` carries them (parts with different LCSC numbers stay on separate BOM lines). Y1, L1 and C_D were pinned after the last export, so `kicad/bom.csv`, the gerbers and the reports do not carry those three numbers yet. A re-export on the current tree does not route this board (FreeRouting leaves +3V3 at U2-49/U2-53 and VREG_LX open with L1 at x = 34.4; moving L1 to (32.0, 22.0) routes it but leaves 1 to 3 return-via items), so the evidence stays at the earlier export until the board is re-laid out. Unpinned and matched by JLCPCB by value, which is unsafe (JLCPCB matched the wrong dielectric and values in a DFM test): + +- C_D is X7R, not C0G: no 100 nF C0G 50 V part is stocked in 0603 at LCSC (only 1206, e.g. C170182). A 1206 C_D was tried and the router then failed to connect +3V3 and VREG_LX, so it was reverted. This is a deviation from the C0G filter intent; the X7R DC-bias drift at the low differential level was not measured. +- L1 C98331 (Sunlord MPL2012S3R3MHT, 3.3 uH, 190 mOhm, 900 mA, 0805) is picked for the footprint; its DCR and saturation current were not checked against the RP2350 datasheet. The Pi-recommended part is Abracon AOTA-B201610S3R3-101-T (C42411119); its 2016 package does not fit the 0805 footprint. +- Y1 C2449814 is an exact MPN match (49 in stock when checked 2026-11-06). +- U2: the registry LCSC number is now C42411118 (see the review findings above); it was not checked against a stock listing. + +The registry LCSC number for `lp5907_3v3` (C83437) was wrong; the pinned C80670 is the TI LP5907MFX-3.3/NOPB. The part-level registry reviews are in the table above; nobody has signed off these pins against a fab-house BOM check. + +## Single ground plane + +The design requirement is one ground reference for the analog and digital +returns. The delivered board satisfies it as follows: + +1. `GND` is the only ground net. Four zone objects, one per copper layer, each + carry it. There is no `AGND` or `DGND` net, zone or tie part. +2. Every track and via carries one net. A zone fill belongs to one zone and + therefore one net. +3. `check.sh` loads the board in pcbnew and asserts that `GND` exists and that + `AGND` and `DGND` do not. On the delivered board it prints + `reopen ok; single GND plane`. + +Issue #363 asked for an AGND/DGND split. The issue owner has not signed off on +this deviation. + +Why one plane: the ADC's digital return (DGND pin 14), CLK, AVSS, AVSS_SW, +REFN0, REFCOM and exposed pad return to the same plane as the MCU, flash, USB +and LDO, so a signal that crosses the analog/digital boundary never has to +change reference planes. The earlier split version needed a tie and still left +two isolated pours on the merged router. No impedance or ground-noise +measurement was made; this is the main item for the analog/SI review. + +## Measured layout numbers + +- 389 track segments, 89 vias: 60 GND, 29 signal. 688.4 mm of track. Six vias + are the compact 0.46/0.20 mm size, 83 are 0.6/0.3 mm. 40 nets, 0 open. The + router imported 71 of the vias; the others are not router-imported (source + stitching and repair vias). +- Analog nets, all F.Cu only, no via: + +| Net | Length | +| --- | --- | +| RTD_FP | 16.78 mm | +| RTD_SP | 6.75 mm | +| AIN1 | 12.39 mm | +| RTD_SN | 6.94 mm | +| AIN2 | 13.55 mm | +| RTD_FN | 15.46 mm | +| VREF | 37.85 mm | + +- SPI_SCK/MOSI/MISO/CS are 13.68/12.01/10.96/14.22 mm, all four change layer. + QSPI_SS/SCLK/SD0/SD1/SD2/SD3 are 11.95/7.07/5.58/11.81/11.98/8.50 mm; SD1 and + SD2 change layer, the others stay on F.Cu. +- USB: the RP2350-side nets are 13.59 mm (DP) and 15.40 mm (DN); the + connector-side nets are 13.06 mm and 12.56 mm. Total path 26.65 mm (DP) and + 27.96 mm (DN), a 1.31 mm mismatch, full speed. Only USB_DN changes layer; the + pair is not routed as a coupled pair and has no controlled impedance. +- Crystal: XIN 11.49 mm, XOUT 5.09 mm, XOUT_R 19.29 mm, all F.Cu. +- 34 reference labels are hidden: C_AV1, C_AVF, C_CM1, C_FL, C_CM2, C_D, C_DV, + C_DV1, C_DV2, C_IO, C_IO1, C_IO2, C_IO3, C_IO4, C_L2, C_RO, C_RV, C_VI, D1, + D2, H1, H2, H3, J1, J3, R_AV, R_BIAS, R_CC2, R_DN, R_DP, R_RST, R_S1, R_S2, + R_X. They remain in the BOM, PnP and schematic. +- Board outline and stackup above; 53 footprints. + +## Left to a human + +Nothing below is signed off. The list is deliberately blunt. + +- **SI/PI/RF review (designated reviewer)**: the 24-bit analog layout, the + single ground plane, the 37.85 mm of VREF track from U3 to C_RV, the RC filter + against the chosen ADC data rate, the IDAC output's 10 nF load and settling, + the PGA common-mode range at the chosen gain, the unused-input termination, the + 11 return-via advisories, the SPI_MISO/ADC_DRDY parallel run, the RP2350 + decoupling count and the 1.31 mm USB length mismatch. None of these were simulated or measured. +- **Metrology/analog**: the measurement is not ratiometric. The IDAC's absolute + accuracy and drift, the REF5025 grade and drift, the 1 k filter resistors and + the PT100 wiring resistance set the accuracy; there is no calibration or + error budget. A 4-wire measurement with 0.1 % resistors is not automatically a + 0.1 % thermometer. +- **USB/ESD**: no VBUS fuse, TVS or reverse-polarity protection; CC1/CC2 have no + TVS; the shield is tied directly to GND; the D1/D2 BOM value text is a + placeholder (the MPN is pinned). USB-C and ESD + compliance were not checked. +- **Mechanical**: the measured margins are in the table above. In short, the + mounting holes leave 2.15 to 2.24 mm of material around a 2.7 mm hole, the + bottom connectors are 0.71 mm from the edge, and J1 is 1.27 mm from the top + edge and centred. J1 centring, the enclosure, + screw-head clearance, connector overhang and header orientation were not + checked. Synth places no board-name or revision silk. +- **Test points**: none are fitted. The 12-pad set was tried on the earlier + outline and left GND islands; the top-left area it used now holds the + reference cluster, so a new set needs a different location and a fresh route. + A bench bring-up has to probe component pads or a harness; the set is a future + layout task. +- **Fabrication/DFM**: no fab house has seen the Gerbers, drill, BOM or PnP. + The 0.4 mm QFN-60, the 0.5 mm VQFN-32 and the 0.5 mm USB-C need a fab + capability check; the four-layer stackup is declared by the source, not a + controlled-impedance quote. The source declares `requires via_in_pad` + (manufacturer `jlc-filled-via`); this route has no via inside a pad, but a + re-route can bring one back and JLCPCB has not accepted that process. Assembly + of the generic passives needs the C0G/tolerance attributes from the source, + not just the BOM values. +- **Firmware**: the RP2350 boot, QSPI flash, ADC gain/data-rate/IDAC registers, + USB descriptors and the PT100 conversion/calibration do not exist in this + repository. Nothing was powered. +- **Sourcing**: C_D, L1 and Y1 have no sourced MPN/LCSC part (see Sourcing + pins). The RP2350 decoupling count is below the Pi recommendation. +- **Independent sign-off**: the board review is with the designated reviewer. + Part-level registry reviews exist for the parts in the table above; they are + single-reviewer reviews. The issue owner has not signed off on the single + GND plane against #363. There has been no second-person check of this record + and no hardware measurement. The only automated checks are the datasheet pin + tests, the KiCad DRC/ERC and the ground assertion. + +## Synth defects hit in this work + +1. **Duplicate footprint-body UUIDs (fixed).** Inlining a KiCad 10 footprint + body kept the library's child UUIDs, and `ensure_body_uuids` only filled + missing ones and keyed them by `lib_id`, not by the placed instance. Every + 0603 shared its pads' and silk lines' UUIDs: 79 duplicated ids, one shared by + 23 footprints. KiCad keys board items by UUID, so `kicad-cli pcb drc` + attributed a silk collision to an item 11 mm away (R_AV's label against + C_L2's silk). The fix gives each instance its own deterministic ids and + replaces stock ones; the regression test is + `inlined_body_blocks_carry_unique_deterministic_uuids`. After the fix every + board item carries its own id, so the DRC warnings name the real neighbours. + This is what made the zero-warning result trustworthy. +2. **Ground stitching is placement-sensitive (not fixed).** Earlier attempts + left split-ground islands that the 0.6 mm stitching-via search could not tie, + so the export refused them. The single-plane version has no islands, but a + future placement change can bring them back; `check.sh` catches it. The + return-via half of this repair is now advisory (see item 7). +3. **An all-absolute placement sidecar is silently re-packed (not fixed).** + With every entry absolute, the export's `close_pinned_bands` pass slid the + pinned parts to shut gaps; it moved U4 onto U2 and produced 91 mask and + clearance violations while the sidecar looked as if it had been ignored. + Keeping one relative entry (`C_FL` relative to `U4`), as the original + sidecar did, disables the pass. The export should either preserve an + absolute floorplan or refuse it, not re-pack it into an illegal one. +4. **BOM omitted component attributes (fixed).** `bom.csv` had value, kind, + symbol, footprint, LCSC and MPN, but not `dielectric`, `voltage` or + `tolerance`, which are present in the `.synth` source. The exporter now + writes `dielectric`, `voltage`, `tolerance` and `power` columns from the + component properties; the regression test is + `structured_attributes_get_their_own_columns`. +5. **No free-text silkscreen (not fixed).** The board name, revision and header + pin functions cannot be put on the silk; only reference labels exist. +6. **The board outline lives in the placement sidecar, not the `.synth` source + (fixed for this board).** The earlier notch was an `[[outline]]` path in + `rtd_afe.placement.layout.toml`. The final board is a plain fitted rectangle, + so the sidecar carries no outline and a normal `synth export-kicad` needs no + post-export cut. The feature remains for boards that need a non-rectangular + outline; a `.synth` outline statement is still not implemented. +7. **Return-via misses blocked a whole candidate (fixed).** The island repair + reported a signal via with no ground return as an unresolved island, so a + route with clean connectivity could not be promoted. A missing return via is + the existing `W-SYNTH-DRC-016` SI warning, so it is now advisory; an untied + copper island still blocks. This branch adds two router commits on top of that + (see the return-via gate section). The regression test is + `an_unreturned_signal_via_is_advisory_not_blocking`. +8. **Source ground fence ignored the sidecar outline (fixed, historical).** On + the earlier notched layout the fence vias were placed against the fitted + rectangle, so three landed on or outside the notch edge (0.0/0.26 mm + copper-to-edge). The fence now follows an `[[outline]]` path and skips points + outside it; the final rectangular board has no custom outline and no + edge-clearance error. + +No GitHub issue numbers are linked for the Synth defects above. + +## Reproducibility + +Hashes of the committed inputs and outputs are in `SHA256SUMS` (the single +source of truth; this file no longer copies them, so they cannot drift). Verify with: + +```sh +grep -v '^#' SHA256SUMS | sha256sum -c - +``` + +`check.sh` sets `SYNTH_SOURCE_REVISION` from the checked-out commit, and both +`release.json` and the routing provenance record it. It also rewrites the +checkout path in `release.json`, `rtd_afe.routing.json` and `rtd_afe.net` to a +repository-relative one, matching the usb-uart board's convention. The +`source_revision` names the source commit; the later artifact commit only adds +the regenerated files. All other reports are as the tools wrote them. +`SHA256SUMS` covers all deliverables. + +The failed attempts described above did **not** route clean; the committed +placement did. I did not run the final inputs three times to claim a +byte-identical board, so the committed board is one successful run, not a +proven reproducible one. FreeRouting 2.4.1 and KiCad 10.0.7 on another machine +may produce a different route. `check.sh` is the repeatable acceptance check; +it re-routes from the sources and fails on any DRC error, unconnected item, or +ground violation. diff --git a/qualification/class-b/rtd-afe/README.md b/qualification/class-b/rtd-afe/README.md new file mode 100644 index 000000000..84acc65de --- /dev/null +++ b/qualification/class-b/rtd-afe/README.md @@ -0,0 +1,253 @@ +# PT100 4-wire RTD analog front end (SYN-363) + +Status: design, placement and a FreeRouting route that passes Synth's routing and +DRC gates. The board is **not fabricated and not tested on hardware**. The +SI/PI/RF review is being carried out by the designated reviewer; the automated +evidence and the open items are in [QUALIFICATION.md](QUALIFICATION.md). The +analog accuracy has not been measured, and several sourcing and decoupling items +are open (see Known limits and gaps). + +Intended use: a bench or lab 4-wire PT100 front end with a USB readout. It is a +compact mixed-signal board on a single ground plane, not an instrument. Do not +use it for a product or a safety function until the review items in +QUALIFICATION.md are closed. + +## What it is + +- 4-wire PT100 input on J2 (1x4, 2.54 mm): pin 1 F+, pin 2 S+, pin 3 S-, pin 4 + F-. The force pair carries the excitation current; the sense pair reads the + element. +- Input filter: R_S1/R_S2 1k 0.1 %, C_D 100 nF X7R across the pair, C_CM1/C_CM2 + 10 nF C0G to GND, C_F 10 nF C0G on F+. +- U1 TI ADS124S08 24-bit delta-sigma ADC (VQFN-32, exposed pad) with the + internal PGA and IDAC1. AIN0 is the force output, AIN1/AIN2 the differential + sense input. The firmware is expected to select 1 mA excitation. +- U3 TI REF5025AIDR 2.5 V reference on REFP0/REFN0. C_RI and C_RV are 1 uF. +- U2 Raspberry Pi RP2350A (QFN-60), U4 W25Q128JVSIQ QSPI flash (SOIC-8 208 mil, registry `w25q128_flash_208mil`), Y1 ECS-120-20-33-TR + 12 MHz crystal with 33 pF C0G load caps, J3 3-pin SWD header, RUN pull-up. +- J1 USB-C receptacle (HRO TYPE-C-31-M-12), 5.1k CC1/CC2, 27R series on D+/D-, + D1/D2 SOD-323 TVS on D+/D-. U5 TI LP5907-3.3 LDO (250 mA) makes +3V3 from + VBUS. +- L2 600 ohm at 100 MHz ferrite bead isolates +3V3A for U1 and U3. +- Four M2.5 non-plated mounting holes at (6, 3.5), (39, 3.5), (6, 40.7) and + (39, 40.7) mm. +- 40.1 x 44.2 mm rectangular board, 1772 mm², 4 layers, 1.586 mm declared + stackup (1.6 mm nominal FR4). Board source `rtd_afe.synth`, placement sidecar + `rtd_afe.placement.layout.toml` (board millimetres). The schematic has no + sidecar; the compiler lays it out by group. + +## Signal chain + +J2 -> R_S1/R_S2 and the C_D/C_CM/C_F network -> U1 AIN1/AIN2. The reference is +absolute: VREF = 2.5 V from U3. The current is not used as the reference, so the +IDAC's absolute accuracy and drift limit the measurement unless the firmware +calibrates them. That trade is deliberate and is called out as an open accuracy +item in QUALIFICATION.md. + +Nominal filter corners (this work, assuming the 2 k filter resistance dominates +the 100 to 250 ohm PT100): + +| Path | Elements | Corner | +| --- | --- | --- | +| Differential | R_S1 + R_S2 = 2 k, C_D 100 nF + C_CM1/C_CM2 in series (5 nF) = 105 nF | about 758 Hz | +| Common mode | R_S 1 k, C_CM 10 nF | about 15.9 kHz | + +C_D is ten times each C_CM, so capacitor mismatch turns into little differential +error. C_CM and C_F are C0G; C_D is X7R because no 0603 C0G 100 nF is stocked. The `.synth` notes say "about 720 Hz"; the +difference is only the equivalent capacitance assumed there (110 nF instead of +105 nF). The ADC's digital filter and the chosen output data rate are firmware +settings and are not in this repository. + +Excitation and common mode: IDAC1 sources 1 mA into AIN0/F+, through the PT100, +out of F- and through R_BIAS 1k to GND. R_BIAS lifts the RTD common mode to +about 1.0 V plus the RTD drop (about 1.1 V at 100 ohm, 1.25 V at 250 ohm). The +gain-dependent PGA common-mode limit was not re-checked against SBAS660C in this +work; see QUALIFICATION.md. + +## Ground + +One GND plane on all four copper layers. There is no AGND/DGND split and no tie +resistor. The ADC's AVSS, AVSS_SW, REFN0, REFCOM, exposed pad, DGND pin (14) and +CLK pin (17) return to the same plane as the MCU, flash, USB and LDO. `check.sh` +asserts with pcbnew that the board has `GND` and no `AGND` or `DGND` net. Issue +#363 asked for an AGND/DGND split; the issue owner has not signed off on this +deviation. The return-via advisories on the digital nets are listed in +QUALIFICATION.md for the SI review. + +## Placement and routing + +Status: routed with FreeRouting 2.4.1 on Java 25, KiCad 10.0.7, Synth at the +worktree this directory was exported from (source revision 01a77d54). The board +passes Synth main's return-via gate with this branch's two router commits (see +QUALIFICATION.md). The route is under review by the designated reviewer. + +- Analog left, digital right, packed rather than spread. The input chain is J2 + at (14.8, 41.7) mm, the RC filter just above it and U1 at (12, 25.1) mm. The + reference and support parts sit in the top-left: U3 at (10.5, 11.6) mm, C_RI + at (4.8, 11.3) mm, L2 at (13, 6.5) mm, C_RO at (16, 13.6) mm and R_RST at + (19.8, 14) mm, with R_CC2 at (21, 11.5) mm. The digital core is U2 at + (28, 29.6) mm, U4 at (22, 19) mm and Y1 at (28, 36.3) mm. U5 is at + (36.5, 10.5) mm and J3 at (28, 41.7) mm on the bottom edge. +- The outline is fitted to the placement: 40.1 x 44.2 mm, 1772 mm². The largest + bare rectangle was 7 x 8 mm (56 mm²) on the earlier route (not re-measured after the C_IO, L1 and U4 moves), down from 19 x 19 mm (361 mm²) on the + 50.1 x 44.1 mm rectangle. The board is not a scaled copy: the groups were + re-packed, so the RTD and AIN lengths changed (RTD_FP 16.78 mm, AIN1 + 12.39 mm, AIN2 13.55 mm) and VREF is 37.85 mm of track on F.Cu in the current + route, still with C_RV at REFP0. +- J2 and J3 are both at y = 41.7 mm; their bodies end about 0.71 mm from the + bottom edge. J1 is at (22.55, 6.0) mm, centred on the 40.1 mm top edge and + 1.27 mm from it. The extra 1 mm of height over the first compact pass gives + U2's top-row escapes room; that is what makes the centred connector route + without an untied GND fragment. +- The sidecar carries a plain rectangular `[[outline]]` (x 2.50..42.59, + y -0.01..44.21); there is no notch and no post-export cut. +- The RTD/input nets and VREF are on F.Cu only, with no layer change. QSPI is + mostly on F.Cu, with SD1/SD2 changing layer. SPI_SCK/MOSI/MISO/CS, USB_DN and + some ADC-control nets change layers; see the SI findings below. +- 389 track segments, 89 vias (60 on GND, 29 signal), 688.4 mm of track. Six of + the vias are the compact 0.46/0.20 mm size; the rest are 0.6/0.3 mm. 40 nets, + 0 open. The router imported 71 of the vias; the others are not + router-imported (source stitching and repair vias). +- One via sits inside a pad (C_DV.2, at (16.138, 22.835) mm). `release.json` + lists it as a fabrication note: order with filled and capped vias. +- `kicad-cli pcb drc --severity-all --refill-zones`: 0 errors, 48 warnings (47 + `lib_footprint_mismatch`: the exported footprints differ from KiCad 10's library + copies; 1 `silk_edge_clearance`: the C_DVB reference label is clipped by the + board edge at (41.05, 20.5) mm), 0 unconnected items. `pcbnew.LoadBoard` reopens the board and `check.sh` confirms + one GND plane with no AGND or DGND net. +- Synth's signal-integrity pass: 12 non-blocking findings, 11 `W-SYNTH-DRC-016` + layer changes with no ground-return via within 0.80 mm (advisories, see + QUALIFICATION.md) and 1 parallel-run finding (SPI_MISO and ADC_DRDY, 3.5 mm on + B.Cu, 0.203 mm apart). No RTD, AIN or VREF net is flagged. +- Silkscreen: 1 DRC warning (the C_DVB label at the board edge, above). U1 has a hard label override at (16, 30.6) mm; + 29 passives/TVS and H1/H2/H3/J1/J3 have their reference label hidden because + the compact refdes field has no clear spot. Their refdes remain in the BOM, PnP and + schematic; the full list is in QUALIFICATION.md. + +## Checks + +From the repository root: + +``` +cargo build -p synth-cli +qualification/class-b/rtd-afe/check.sh +``` + +`check.sh` exports and autoroutes the board into `kicad/`, then runs +`kicad-cli pcb drc --severity-all --refill-zones` and `kicad-cli sch erc` on the +result, renders the 3D views, and loads the board in pcbnew to check that it has +one GND plane. It needs `tools/freerouting/freerouting-2.4.1.jar` and +`tools/jre25/` (both git-excluded; symlink them from a configured Synth +worktree). + +Current result: + +| Check | Result | +| --- | --- | +| KiCad DRC (errors / warnings / unconnected) | 0 / 48 / 0 | +| pcbnew reopen | OK | +| Ground | one GND plane; no AGND or DGND net | +| KiCad ERC (errors / warnings) | 0 / 1 | +| Synth routing state | routed, 0 open nets | +| Synth release | `production_status: production`, `release_ready: true` (router/export gates only; not a fab approval, see `gate_scope`) | +| Synth SI findings | 12, none blocking (11 `W-SYNTH-DRC-016` advisories, 1 parallel run) | + +The ERC warning and 47 of the 48 DRC warnings are library-comparison warnings, +not connectivity errors. The embedded REF5025ID symbol differs from the installed +library copy. The 47 are `lib_footprint_mismatch`: Synth's exporter +now redraws each footprint's reference label at 0.8 mm with an 0.18 mm stroke +and trims silkscreen that would clip a pad or via, so the embedded footprint +differs from the `Resistor_SMD`/`Capacitor_SMD` library copy. No copper, pad or +drill is changed. The exported schematic embeds its own symbols and the +netlist/PCB parity is clean. This disposition has not been reviewed by a human. + +## Committed artifacts + +- `kicad/`: routed PCB, schematic, symbol library, project, DRC rules, BOM, PnP, + Gerbers and drill files. +- `reports/`: `release.json`, the delivered DRC and ERC reports, the KiCad + netlist, the FreeRouting routing record and the connectivity report. +- `images/`: 3D top, bottom and angled views and the schematic. The 3D views + are rendered with `kicad-cli pcb render`, the schematic with + `kicad-cli sch export pdf` and `pdftoppm`. +- `rtd_afe.synth`, `rtd_afe.placement.layout.toml`: the design sources. +- `check.sh`: the acceptance check above. +- `SHA256SUMS`: hashes of the artifacts. + +The reports are as the commands produce them, except that `check.sh` rewrites +the checkout path in `release.json`, `rtd_afe.routing.json` and `rtd_afe.net` to +a repository-relative one and stamps `source_revision` from the checked-out +commit. `release.json` is Synth's own format (`synth.release.v1`); its +`gate_scope` says it is a router/DRC gate, not a fabrication approval or a +component review. + +## Known limits and gaps + +- No VBUS fuse, TVS or reverse-polarity protection. D1/D2 protect only D+/D-. + CC1/CC2 have no TVS. The USB shield is tied directly to GND. +- D1/D2 are pinned to ESD5V0B03-323 (LCSC C521915) in the source; the registry + part is generic and the BOM's `ESD` value text is a placeholder. +- The BOM carries `dielectric`, `voltage`, `tolerance` and `power` columns from + the source, so the C0G filter caps and the 0.1 % resistors are visible to an + assembler. Empty cells mean the source does not declare that attribute. +- The source declares `requires via_in_pad` and the manufacturer profile + `jlc-filled-via`. This route has one via inside a pad (C_DV.2), listed in + `release.json` as a fabrication note. JLCPCB has not accepted that process. +- There are no test points. The 12-pad set (rails, reference, USB and SWD) was + tried on the earlier outline; every routing attempt left GND islands. The + top-left area it used now holds the reference cluster. +- No VBUS current budget was measured. The LDO is 250 mA; the RP2350 datasheet + peak plus the ADC, reference and flash is expected to be below it, but this + was not checked against the loads. +- The reference is absolute, not ratiometric. IDAC accuracy and drift therefore + enter the result; no calibration or IDAC accuracy check was done. +- The unused ADC analog inputs (AIN3..AIN11, AINCOM), REFP1/REFN1, the ADC GPIOs + and pin 25 are left open. Their termination is not covered by a datasheet + review here. +- The firmware does not exist in this repository: gain, data rate, IDAC value, + register map, USB descriptors and calibration are all unwritten/untested. +- Synth has no free-text silkscreen primitive, so the board name and revision + are not on the copper. Header pin functions are not labelled on the silk. +- The board is 40.1 x 44.2 mm (1772 mm²), down from the 50.1 x 44.1 mm + rectangle and the earlier 63.1 x 51.1 mm. The floorplan packs the analog chain + and reference at the left and the MCU/flash/crystal and USB at the right, with + the groups interlocking vertically instead of sitting in two sparse columns. + It is one successful FreeRouting run, not a proven densest layout. +- The sidecar carries a plain rectangular `[[outline]]`, not a notch; the + exporter reproduces it without a post-export cut. +- 29 passives/TVS and H1/H2/H3/J1/J3 have their reference label hidden because + the refdes field has no clear spot in the compact layout. The refdes are still in + the BOM, PnP and schematic; the full list is in QUALIFICATION.md. +- RP2350 decoupling is below the recommendation. The board has four IOVDD 100 nF + caps (C_IO1..C_IO4) for six IOVDD pins, and two DVDD caps (C_DV1, C_DV2) plus + C_DVB bulk for three DVDD pins. Raspberry Pi's hardware design guide (section + 2.2.1) recommends one 100 nF per power pin, with pins 53/54 sharing one. Four + more caps could not be placed without breaking routing; left for the SI/PI + review. +- L1 is pinned to Sunlord MPL2012S3R3MHT (C98331, 0805); its DCR and saturation current are not checked against the RP2350 datasheet. The Pi-recommended Abracon AOTA-B201610S3R3-101-T (C42411119) does not fit the 0805 footprint. +- C_D is X7R 0603 (C14663), not C0G: no 0603 C0G 100 nF is stocked. A 1206 C0G part (C170182) broke routing and was reverted. +- Y1 is pinned to C2449814 (exact MPN). +- Issue #363 asked for an AGND/DGND split; this board uses one GND plane and the + issue owner has not signed off on the deviation. +- No GitHub issue numbers are linked for the Synth defects listed in + QUALIFICATION.md. +- The mounting holes leave 2.15 to 2.24 mm of material around a 2.7 mm hole, the ISO 273 fine clearance for M2.5. + J2/J3 are about 0.71 mm from the bottom edge and J1 1.27 mm from the top. + The enclosure and screw-head clearance are mechanical check items; the + measured table is in QUALIFICATION.md. +- The KiCad ERC library-name warnings remain (see above). They do not affect + the netlist. + +## Not verified + +- Analog accuracy, noise, linearity, drift and the actual PT100 reading. +- The IDAC absolute accuracy/drift, PGA common-mode range at the chosen gain, + the ADC's unused-input termination, and the RC filter against the chosen ADC + data rate. +- The 1.1 V core regulator, the 12 MHz crystal's ESR/drive level, the flash + QSPI timing, and the USB full-speed signal integrity. +- ESD, surge, reverse polarity and USB-C compliance. +- Mechanical fit, connector and header orientation, mounting-hole clearance. +- Any fabrication or assembly check. Nothing was sent to a fab house. +- Any part was bought or measured. Part-level registry reviews exist (see + QUALIFICATION.md); the HRO and Tech Public datasheets were read as scans. diff --git a/qualification/class-b/rtd-afe/SHA256SUMS b/qualification/class-b/rtd-afe/SHA256SUMS new file mode 100644 index 000000000..eaaf1f456 --- /dev/null +++ b/qualification/class-b/rtd-afe/SHA256SUMS @@ -0,0 +1,51 @@ +2dc0eb5ee3f7fa9a396163a6b9ef6ff02d8f94edf96b46e6bb8867e12ce0f1f1 QUALIFICATION.md +50a3f35bd0dcbf1cd7abb0ee5dda3c1e52a6ead775f1344ae7307c72a06ff524 README.md +1fa0f0efb4831212a93d817d94130b4b8cce593ec422c7dde3750de9074a1539 check.sh +c46c22781b3884a4d335896e9c122df56b5536196e84ad0a76302362a478b22a images/pcb-3d-angled.png +e8dae301a160ef9941501dd59ef452bbab23fcc62b09a48203a46d5f694fd9c2 images/pcb-3d-bottom.png +66ec1b174bf9dc72dcf69cd145a81a0f0fd4e23297a93a0fcec14ff6265a2ea8 images/pcb-3d-top.png +273c705bbf1be1ecb1b2ea3a366428abeb0b1f18d5cb91062671beec2089254f images/schematic.png +a0a43ee59128d536722e0141514259bc0c4fc4e5b2f6220052caf6bfd307683f kicad/bom.csv +b4fe6e0d01d65d0beb05db620ffd903eb286fa049757a9e2c68565c9b5ab5803 kicad/drill/rtd_afe-NPTH-drl_map.pdf +bc23bb2b7888fc9c576e2a1645e7a5ef4ec02aaf25f99d27515b3a6056b21ff1 kicad/drill/rtd_afe-NPTH.drl +3473b7ae4fcc777b412c707798bf45bedb84f477173441cb8197e947f40afaaf kicad/drill/rtd_afe-PTH-drl_map.pdf +b498dd9044e007b6f368a6782dca1acfe5f5b94e0e65172867cb8dd46c87cc77 kicad/drill/rtd_afe-PTH.drl +ff073908a4ba2f3a7a1529984d6d21479174d259edc84fd35fe88abca2ef006c kicad/gerbers/rtd_afe-B_Adhesive.gbr +ec56bad26f3dfe50faa76c3bfb084da4909540e84c1088a86a25cc4dc030c3f5 kicad/gerbers/rtd_afe-B_Courtyard.gbr +6e441d4e09337a3b22fd92089a3eedde5e6a0c36df79c423ef17ffd445d7c51a kicad/gerbers/rtd_afe-B_Cu.gbr +30fa602c27a884b3c100418fe4a956b9bea17db0f91827564059d3b8ae156a0f kicad/gerbers/rtd_afe-B_Fab.gbr +2de004127861c2161e9040294327c2bad9323ee1199eeb206890daa1c57de8c0 kicad/gerbers/rtd_afe-B_Mask.gbr +141a80a1d28428a5ecef14b025c799599cbfdaf509045b5f51b55ca47c9af276 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+6777ba6616cf475ecb633f480238f8804e4bc71c5a60b7826d9115363b157f60 kicad/gerbers/rtd_afe-In1_Cu.gbr +d6feef9b36877adfef8298dfab1c94105c7269f39ada74f416ac8522c962f0e1 kicad/gerbers/rtd_afe-In2_Cu.gbr +ec56bad26f3dfe50faa76c3bfb084da4909540e84c1088a86a25cc4dc030c3f5 kicad/gerbers/rtd_afe-Margin.gbr +bf733f37732b30d74441e99761772a0e824c2bb9aae96d9f2ee9c9c9420a7ab4 kicad/gerbers/rtd_afe-User_Comments.gbr +dd80c4f481a5d3d1da1701ad69a5aa3a14712035e0afeb50a72653278dd485c1 kicad/gerbers/rtd_afe-User_Drawings.gbr +a46edb032e9986e1f50dab83cbb35aa5a8ce88941c5612a5792e35990847ae32 kicad/gerbers/rtd_afe-User_Eco1.gbr +f4b5e4cb7ba7cde0a51c5f9d6a2cf8918ef8b92d542dbd92238940ac8ea00326 kicad/gerbers/rtd_afe-User_Eco2.gbr +82735e9fc2fdbd8646a845874d50f1d013ca5747df41df55722e85c59fc7317e kicad/gerbers/rtd_afe-job.gbrjob +95f6869dbda48b3cb9175da4e86d5a484e7e8c357b77e0683c1e54fa0d796a23 kicad/pnp.csv +a6fe61619cdf0dbe90fc726dc32f7cc8e9889833d6b1d5aec574d3f1b7b802d9 kicad/rtd_afe.kicad_dru +5dd5b8a573fce34812835101d4bc451cd51973595fd41b4ef97da169f72d7810 kicad/rtd_afe.kicad_pcb +368e906d4eebcc5378bd450f19cdaf8d2a68712a46a5f0bd1c6e844abd4d3a05 kicad/rtd_afe.kicad_prl +28881644934853adb6779197fea3bc45288a7b1caa60712451caa6b17a0475a1 kicad/rtd_afe.kicad_pro +38a2e8b21dfb376404d721db81289cfd9f3bb1000bdc8980f3884a209ef4034e kicad/rtd_afe.kicad_sch +7c8ee6d3b2e4d7ede14c29a9437126904f0c1c55883dde1436ffcf813585bfeb kicad/rtd_afe.kicad_sym +3783313a130583a550c9bea8053afa849e60e440af1bbb0236d85d8392a865ba kicad/sym-lib-table +717e12207a58e5aece42ae874af0579b63c1358667029a035b8abe8fe38eb501 reports/release.json +9adeb82cc8fce6354bfab3e4e0ad5cee7f539b083b7ceeaf99f92a04e565f8e7 reports/rtd_afe.connectivity.json +5b3450b0d7708c09cd2347c2a584c572cbe41823b9440a65f7a23cce9daf6e5f reports/rtd_afe.kicad-drc.json +f7a9fc62d67de007389d2161b19953cd3b3b729a773f36396120e616b2f439e8 reports/rtd_afe.kicad-erc.json +6fc81799dd2e2a34b5944d51d9f8b52fdd3cc1ea98e191787deb2c7f768675e2 reports/rtd_afe.net +1e905a0183b4d7c4c2ea019d909c70ecb7cc65be6a80aa7c5506470ddb93c7dd reports/rtd_afe.routing.json +10ee26e2cc87b624525b9b3e4af6b4df16910c29c8810da9d34ae941e8f2bc65 rtd_afe.placement.layout.toml +14bad6143c4033f41f09839a3baa2832af58acb3c814227e277de33e809741eb rtd_afe.synth diff --git a/qualification/class-b/rtd-afe/agent-run/ASSEMBLY.md b/qualification/class-b/rtd-afe/agent-run/ASSEMBLY.md new file mode 100644 index 000000000..7165bb8ad --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/ASSEMBLY.md @@ -0,0 +1,56 @@ +# ASSEMBLY: rtd-afe + +Source: `kicad/bom.csv`, `kicad/pnp.csv`, `rtd_afe.synth`, README.md, QUALIFICATION.md. Nothing was sent to a fab house or assembled. + +## Fabrication +- 4 layers, 1.5862 mm declared FR4 stackup (1.6 mm nominal), 40.1 x 44.2 mm rectangle, 53 footprints. +- Manufacturer profile `jlc-filled-via`; `requires via_in_pad`. One via-in-pad at C_DV.2 (16.5, 22.3) mm: order with filled and capped vias. JLCPCB acceptance of this process: not verified. +- Four 2.5 mm NPTH mounting holes at (6, 3.5), (39, 3.5), (6, 40.7), (39, 40.7) mm. +- Fine pitch: RP2350 QFN-60 0.4 mm, ADS124S08 VQFN-32 0.5 mm, USB-C 0.5 mm. Fab capability check: not verified. +- Gerbers and drills: `kicad/` (and `kicad/drill/`). Fab review of them: not verified. + +## BOM (`kicad/bom.csv`) +| Refs | Value | Notes | +| --- | --- | --- | +| U1 | ADS124S08IRHBR | MPN only, no LCSC | +| U2 | RP2350A | LCSC C14663 | +| U3 | REF5025AIDR | MPN only | +| U4 | W25Q128JVSIQ | LCSC C97521 | +| U5 | LP5907MFX-3.3 | LCSC C83437 | +| Y1 | 12 MHz, ECS-120-20-33-TR | 3.2 x 2.5 mm 4-pad; no LCSC | +| J1 | TYPE-C-31-M-12 | LCSC C165948 | +| J2 | PT100, 1x4 2.54 mm | LCSC C492403, MPN PZ254V-11-04P | +| J3 | SWD, 1x3 2.54 mm | no MPN | +| D1, D2 | ESD (generic TVS, SOD-323) | placeholder, no MPN or LCSC | +| L1 | 3.3 uH 0805 | generic | +| L2 | 600R@100MHz 0603 ferrite | generic | +| R_S1, R_S2, R_BIAS | 1k 0603, 0.1 % | tolerance column set | +| R_CC1, R_CC2 | 5.1k 0603 | | +| R_DP, R_DN | 27 0603 | | +| R_RST, R_RUN | 10k 0603 | | +| R_X | 1k 0603 | | +| R_AV | 33 0603 | | +| C_D | 100 nF 0603 C0G 50 V | | +| C_CM1, C_CM2, C_F | 10 nF 0603 C0G 50 V | | +| C_X1, C_X2 | 33 pF 0603 C0G 50 V | | +| C_AV1 | 330 nF 0603 X7R 10 V | | +| C_AV2 | 10 uF 0805 X7R 10 V | | +| C_DV, C_IO, C_IO1..C_IO4, C_DV1, C_DV2, C_FL | 100 nF 0603 X7R 10 V | | +| C_RO, C_RI, C_RV | 1 uF 0603 X7R 10 V | | +| C_AVF, C_VI | 4.7 uF 0603 X7R 10 V | | +| C_DVB | 4.7 uF 0805 X7R 10 V | | +| C_L1, C_L2 | 2.2 uF 0603 X7R 16 V | | +| H1..H4 | M2.5 NPTH | | + +The BOM `description` field of the generic capacitors reads "X7R/X5R, any value". The dielectric column carries the real attribute (C0G for the filter and crystal caps). Assemblers must follow the dielectric, voltage and tolerance columns, not the description. Parts with no LCSC number (U1, U3, Y1, J3, D1, D2, all generic passives): sourcing not verified. + +## Placement and orientation +- `kicad/pnp.csv` is the pick-and-place file. Its correctness against a fab's rotation convention: not verified. +- J2 and J3 are at y = 41.7 mm, 0.71 mm from the bottom edge; J1 centred on the top edge, 1.27 mm from it. Connector overhang, header orientation and mating fit: not verified. +- 34 reference designators are hidden on silk (list in QUALIFICATION.md); they remain in the BOM, PnP and schematic. No board name, revision or header pin function on silk. +- Crystal Y1 pads 1/3 are the crystal, pads 2/4 ground. + +## Notes +- No test points are fitted. +- Release override: `--allow-unverified-parts` for `ecs_120_20_33_tr` (no part-level reviewer). +- Hand soldering of the exposed pads (U1 EP, U2 EP): not verified. diff --git a/qualification/class-b/rtd-afe/agent-run/BRINGUP.md b/qualification/class-b/rtd-afe/agent-run/BRINGUP.md new file mode 100644 index 000000000..c90eef159 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/BRINGUP.md @@ -0,0 +1,39 @@ +# BRINGUP: rtd-afe + +NOT RUN ON HARDWARE. The board is unfabricated; QUALIFICATION.md: "not fabricated, not powered and not measured". These are written test steps with expected values taken from the sources. Expected values marked "not verified" have no recorded source. There are no test points: probe component pads, the J2/J3 headers or the USB-C connector. No firmware exists in the repository, so steps 7 onward need firmware written first. + +Equipment: bench supply or USB host with current limit, DMM, scope, a 100 ohm precision resistor or a PT100 for J2, SWD probe. + +1. Visual and continuity, unpowered. + - Check J1 VBUS pins (A4/B4/A9/B9) to GND for a short. Expected: no short (open or capacitor charge only). + - Check +3V3, +3V3A, DVDD_1V1 to GND. Expected: no short. + - Check the C_DV.2 via-in-pad was filled and capped. Expected: flat pad. +2. USB power-up, current limited. + - Apply 5 V at VBUS (or plug into a host through a current-limited source). Expected VBUS 5 V (`power "VBUS" 5v`). Idle current: not verified; the `.synth` note says "a few tens of mA". + - U5 EN is tied to VBUS, so it starts at once. +3. +3V3 rail. + - Measure U5 pin 5 / C_L2.p1. Expected 3.3 V (LP5907-3.3 output; tolerance not verified). Ripple limit: not verified. + - U5 temperature after a settling time (duration: not verified): registry max_power 200 mW; derived dissipation 1.7 V x I. Limit: not verified. +4. Analog supplies. + - +3V3A at U3 pin 2 and U1 pin 26. Expected about 3.3 V minus the L2 drop (L2 DC resistance not recorded: not verified). + - +3V3_RP_A at U2 pins 44/46. Expected about 3.3 V minus the drop across R_AV 33R. +5. Reference. + - Measure VREF at U3 pin 6 / C_RV.p1 / U1 pin 30. Expected 2.5 V (REF5025). Initial accuracy and noise: not verified (grade tolerance not recorded). +6. MCU core and boot. + - Measure DVDD_1V1 (C_DVB.p1). Expected 1.1 V (net name and `.synth` note: "1.1 V DVDD net"). Tolerance: not verified. + - Check Y1 at XIN: 12 MHz oscillation after firmware starts the crystal. Waveform amplitude: not verified. + - Check RUN (R_RUN 10k to +3V3). Expected high, 3.3 V. + - Connect an SWD probe to J3 (pin 1 SWCLK, 2 SWDIO, 3 GND). Expected: the probe sees the RP2350. Note J3 has no reset or Vref pin. + - USB enumeration with a bootloader or firmware. Expected: a full-speed device enumerates on D+/D- with CC1/CC2 5.1k pull-downs (host supplies 5 V). Descriptors do not exist: not verified. +7. ADC bring-up (needs firmware). + - Hold ADC_RESET_N high (R_RST pull-up, U2 GPIO6). Read the ADS124S08 ID register over SPI (SPI0: GPIO0 MISO, GPIO1 CS, GPIO2 SCK, GPIO3 MOSI). Expected value: not verified (register map is in the datasheet, SBAS660C, not copied here). + - Verify SPI MISO/MOSI direction by this read; the `.synth` flags that the registry lists gp0/gp3 the other way round. + - Confirm DRDY toggles on U2 GPIO4 after START (U2 GPIO5 / ADC_START). Data rate: firmware setting, not verified. +8. Excitation. + - Enable IDAC1 at 1 mA on AIN0 and put a 100 ohm resistor across the force path (suggested wiring, not from the files: J2 pins 1 and 4, S+/S- linked to the same resistor). Expected drop across R_BIAS about 1.0 V (1 mA x 1k) and RTD common mode about 1.1 V at 100 ohm (README). Tolerance: not verified. +9. Measurement. + - With 100 ohm on J2, read AIN1-AIN2 with the reference VREF. Expected ratio from 1 mA x 100 ohm = 100 mV differential; the reading tolerance, noise and drift are not verified (README: no accuracy measurement, no calibration). + - Repeat with a PT100 at a known temperature. Expected resistance: not verified here (use the IEC 60751 table; not part of the sources). +10. Record: any step that fails stays open in `VERIFICATION_REPORT.md`; none of the above has been run. + +Not covered by any step: ESD, surge, reverse-polarity, USB-C compliance, EMC, mechanical fit. diff --git a/qualification/class-b/rtd-afe/agent-run/DESIGN_NOTES.md b/qualification/class-b/rtd-afe/agent-run/DESIGN_NOTES.md new file mode 100644 index 000000000..bc08b5374 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/DESIGN_NOTES.md @@ -0,0 +1,49 @@ +Design notes reconstructed from the committed files. The board was built by agents from the briefs in `prompt.md`, copied verbatim from the session transcripts. No tool-call log or report was saved. + +# DESIGN_NOTES: PT100 4-wire RTD analog front end (rtd-afe, SYN-363) + +Sources: `rtd_afe.synth`, `README.md`, `QUALIFICATION.md`, `kicad/bom.csv`, `reports/*.json`, `registry/parts/**`. Anything not recorded there is marked "not verified". + +## Purpose +Bench or lab 4-wire PT100 front end with a USB readout. README: "a compact mixed-signal board on a single ground plane, not an instrument"; not for a product or safety function until the QUALIFICATION.md review items are closed. Status: design, placement and a FreeRouting route that passes Synth's routing and DRC gates; not fabricated, not tested on hardware. + +## Architecture +| Block | Parts | Role (from `.synth` notes) | +| --- | --- | --- | +| RTD input | J2, R_S1, R_S2, C_D, C_CM1, C_CM2, C_F, R_BIAS | J2 pins F+, S+, S-, F-; RC filter to ADC AIN1/AIN2 | +| ADC | U1 ADS124S08, C_AV1, C_AV2, C_DV, C_IO, C_RO, R_RST | 24-bit delta-sigma, PGA, IDAC1 excitation | +| Reference | U3 REF5025, C_RI, C_RV | 2.5 V absolute reference on REFP0/REFN0 | +| Analog supply | L2 (600R@100MHz ferrite bead) | +3V3 to +3V3A for U1 AVDD and U3 VIN | +| MCU | U2 RP2350, U4 W25Q128 flash, Y1 12 MHz, L1, J3 SWD and support passives | SPI master to U1, QSPI boot flash, on-chip 1.1 V regulator | +| USB-C readout | J1, R_CC1/2, R_DP/DN, D1/D2, U5 LP5907-3.3, C_L1, C_L2 | USB 2.0 device, VBUS powers the +3V3 digital rail | +| Mechanical | H1..H4 | M2.5 non-plated mounting holes | + +## Signal chain and excitation +- IDAC1 sources 1 mA out of AIN0 into F+, through the PT100 and F- into R_BIAS (1k) to GND. R_BIAS sets RTD common mode near 1.1 V (README: about 1.0 V plus the RTD drop; 1.1 V at 100 ohm, 1.25 V at 250 ohm). +- REF5025 is the absolute reference (REFP0/REFN0), not ratiometric to the IDAC. README lists this as a deliberate trade and an open accuracy item. +- Input filter: R_S1/R_S2 1k 0.1 %, C_D 100 nF C0G across the pair, C_CM1/C_CM2 10 nF C0G to GND, C_F 10 nF C0G on F+. The `.synth` note gives about 720 Hz differential and about 16 kHz common mode; README recomputes about 758 Hz (105 nF equivalent) and 15.9 kHz. The difference is the assumed equivalent capacitance (110 nF vs 105 nF). +- C_D is 10x each C_CM so capacitor mismatch gives little differential error; all filter caps are C0G. +- The 1 mA IDAC setting, gain and data rate are firmware settings. No firmware exists in the repository: not verified. + +## Decisions recorded in the sources +1. One GND plane on all four layers; no AGND/DGND split, no tie. The split version left two DGND pour islands the router could not tie (QUALIFICATION.md, DRC history). +2. ADC returns its own digital supply current to the same plane: AVSS, AVSS_SW, REFN0, REFCOM, EP, DGND (pin 14) and CLK (pin 17, internal oscillator) are on GND. +3. AVDD and U3 VIN from +3V3A through ferrite L2; DVDD and IOVDD from +3V3. +4. SPI0 wired per RP2350 silicon: GPIO0 MISO, GPIO1 CSn, GPIO2 SCK, GPIO3 MOSI. The registry lists gp0 as spi_mosi and gp3 as spi_miso, the opposite; the wiring follows the silicon (`.synth` comment). Datasheet check of this: not verified in this reconstruction. +5. RP2350 uses its on-chip regulator: VREG_LX through L1 3.3 uH to DVDD_1V1; VREG_FB on that net. +6. VREG_AVDD and ADC_AVDD from +3V3 through R_AV 33R and C_AVF 4.7 uF. +7. Crystal: ECS-120-20-33-TR, CL 20 pF, 2x 33 pF C0G; `.synth` note: 33/2 + about 3 pF stray = 19.5 pF; R_X 1k on XOUT. The 3 pF stray is an assumption in the note: not verified. +8. Via-in-pad: `requires via_in_pad`, manufacturer `jlc-filled-via`; one via-in-pad at C_DV.2 (16.5, 22.3) mm; board must be ordered with filled and capped vias. +9. Stackup (declared, 4-layer, 1.5862 mm): 0.035 Cu / 0.2104 prepreg er 4.4 / 0.0152 Cu / 1.065 core er 4.6 / 0.0152 Cu / 0.2104 prepreg er 4.4 / 0.035 Cu. No controlled impedance requested. USB netclass: trace 0.242 mm, clearance 0.127 mm. +10. Board: 40.1 x 44.2 mm rectangle, 1772 mm², 53 footprints, 40 nets; J1 centred on the top edge; J2/J3 on the bottom edge. + +## Known gaps (copied from README/QUALIFICATION.md) +- No VBUS fuse, TVS or reverse-polarity protection; CC1/CC2 no TVS; shield tied directly to GND. +- D1/D2 are the generic `esd_usb` part with no MPN or datasheet. +- No test points (a 12-pad set left GND islands and was dropped). +- Unused ADC inputs AIN3..AIN11, AINCOM, REFP1/REFN1, GPIOs and pin 25 are left open; termination not datasheet-reviewed. +- No firmware; no VBUS current budget measured; no calibration or IDAC accuracy check. +- No board name/revision/pin-function silk (Synth has no free-text silk). +- 34 reference labels hidden on silk (list in QUALIFICATION.md). +- Y1 has no part-level reviewer; this is the release override. +- Mounting holes leave 2.25 to 2.34 mm material; J2/J3 0.71 mm from the bottom edge, J1 1.27 mm from the top. Enclosure fit not checked. diff --git a/qualification/class-b/rtd-afe/agent-run/NETLIST.md b/qualification/class-b/rtd-afe/agent-run/NETLIST.md new file mode 100644 index 000000000..ea90b9210 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/NETLIST.md @@ -0,0 +1,56 @@ +# NETLIST: rtd-afe + +Source: `rtd_afe.synth`. 40 nets (`reports/rtd_afe.connectivity.json`: 40 connected, 0 open). Passive pin 1 / pin 2 are `p1` / `p2` in the source. + +## Power and ground nets +| Net | Members | +| --- | --- | +| VBUS | J1 A4/B4/A9/B9, U5.1 VIN, U5.3 EN, C_L1.p1 | +| +3V3 | U5.5 VOUT, C_L2.p1, L2.p1, R_AV.p1, U1.15/16, C_DV.p1, C_IO.p1, R_RST.p1, U2 IOVDD x6 (1,11,20,30,38,45), U2.54, U2.53, U2.49, C_IO1..C_IO4.p1, C_VI.p1, U4.8, C_FL.p1, R_RUN.p1 | +| +3V3A | L2.p2, C_AV1.p1, C_AV2.p1, U1.26 AVDD, U3.2 VIN, C_RI.p1 | +| +3V3_RP_A | R_AV.p2, C_AVF.p1, U2.46, U2.44 | +| DVDD_1V1 | L1.p2, U2.6/23/39, U2.50, C_DV1.p1, C_DV2.p1, C_DVB.p1 | +| VREG_LX | U2.48, L1.p1 | +| VREF | U3.6, C_RV.p1, U1.30 | +| GND | U1 14/17/24/27/28/29/33, C_RO.p2, C_DV.p2, C_IO.p2, U3.4, C_RI.p2, C_RV.p2, C_AV1.p2, C_AV2.p2, C_CM1.p2, C_CM2.p2, C_F.p2, R_BIAS.p2, U2.61, U2.47, C_IO1..4.p2, C_DV1/2/B.p2, C_VI.p2, C_AVF.p2, C_X1.p2, C_X2.p2, Y1.2/4, U4.4, C_FL.p2, J3.3, U5.2, C_L1.p2, C_L2.p2, J1 A1/A12/B1/B12/SH, R_CC1.p2, R_CC2.p2, D1.2, D2.2 | + +## Signal nets +| Net | Members | +| --- | --- | +| RTD_FP | J2.1, U1.7 (AIN0), C_F.p1 | +| RTD_SP | J2.2, R_S1.p1 | +| AIN1 | R_S1.p2, U1.6, C_D.p1, C_CM1.p1 | +| RTD_SN | J2.3, R_S2.p1 | +| AIN2 | R_S2.p2, U1.5, C_D.p2, C_CM2.p1 | +| RTD_FN | J2.4, R_BIAS.p1 | +| REFOUT | U1.23, C_RO.p1 | +| SPI_MOSI | U2.5 (GPIO3), U1.10 | +| SPI_CS | U2.3 (GPIO1), U1.9 | +| SPI_SCK | U2.4 (GPIO2), U1.11 | +| SPI_MISO | U2.2 (GPIO0), U1.12 | +| ADC_DRDY | U2.7 (GPIO4), U1.13 | +| ADC_START | U2.8 (GPIO5), U1.8 | +| ADC_RESET_N | U2.9 (GPIO6), U1.18, R_RST.p2 | +| XIN | U2.21, Y1.1, C_X1.p1 | +| XOUT | U2.22, R_X.p1 | +| XOUT_R | R_X.p2, Y1.3, C_X2.p1 | +| RUN | U2.26, R_RUN.p2 | +| SWCLK | U2.24, J3.1 | +| SWDIO | U2.25, J3.2 | +| QSPI_SS | U2.60, U4.1 | +| QSPI_SCLK | U2.56, U4.6 | +| QSPI_SD0 | U2.57, U4.5 | +| QSPI_SD1 | U2.59, U4.2 | +| QSPI_SD2 | U2.58, U4.3 | +| QSPI_SD3 | U2.55, U4.7 | +| CC1 | J1.A5, R_CC1.p1 | +| CC2 | J1.B5, R_CC2.p1 | +| USB_DP_C (class USB) | J1.A6, J1.B6, D1.1, R_DP.p1 | +| USB_DP (class USB) | R_DP.p2, U2.52 | +| USB_DN_C (class USB) | J1.A7, J1.B7, D2.1, R_DN.p1 | +| USB_DN (class USB) | R_DN.p2, U2.51 | + +## Cross-checks (this reconstruction) +- 8 power/ground + 7 RTD/ref + 7 SPI/ADC control + 6 MCU support + 6 QSPI + 2 CC + 4 USB = 40 nets, matching the connectivity report. +- Source comments flag `E-SYNTH-CONNECT-007` on SPI_MISO and ADC_DRDY (bidirectional MCU pin joined to ADC output); QUALIFICATION.md calls it normal SPI wiring. +- The KiCad netlist `reports/rtd_afe.net` is the exported counterpart; no diff against this table was run: not verified. diff --git a/qualification/class-b/rtd-afe/agent-run/PIN_MAPPING.md b/qualification/class-b/rtd-afe/agent-run/PIN_MAPPING.md new file mode 100644 index 000000000..61f3a15a7 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/PIN_MAPPING.md @@ -0,0 +1,142 @@ +# PIN_MAPPING: rtd-afe + +Source: `rtd_afe.synth` nets and `connect` lines, pin numbers from `registry/parts/**`. "Datasheet" is the URL recorded in the part file's provenance, or "none recorded". Pins not listed are open (not connected in the `.synth`). Whether each pin function matches the datasheet beyond what QUALIFICATION.md states: not verified. + +## U1 ADS124S08IRHBR (VQFN-32, registry `ic/ads124s08`) +Datasheet: https://www.ti.com/lit/ds/symlink/ads124s08.pdf (reviewed_by Steve Munene 2026-10-27; QUALIFICATION.md says 13 of 33 pins checked by a pin test). +| Pin | Name | Net | +| --- | --- | --- | +| 5 | AIN2 | AIN2 (RTD S- after R_S2) | +| 6 | AIN1 | AIN1 (RTD S+ after R_S1) | +| 7 | AIN0 | RTD_FP (IDAC1 force out, J2.1) | +| 8 | START/SYNC | ADC_START (U2 GPIO5, pin 8) | +| 9 | CS | SPI_CS (U2 GPIO1) | +| 10 | DIN | SPI_MOSI (U2 GPIO3) | +| 11 | SCLK | SPI_SCK (U2 GPIO2) | +| 12 | DOUT/DRDY | SPI_MISO (U2 GPIO0) | +| 13 | DRDY | ADC_DRDY (U2 GPIO4) | +| 14 | DGND | GND | +| 15 | IOVDD | +3V3 | +| 16 | DVDD | +3V3 | +| 17 | CLK | GND (internal oscillator) | +| 18 | RESET | ADC_RESET_N (U2 GPIO6; R_RST 10k to +3V3) | +| 23 | REFOUT | REFOUT (C_RO 1 uF to GND; internal reference unused) | +| 24 | REFCOM | GND | +| 26 | AVDD | +3V3A | +| 27 | AVSS | GND | +| 28 | AVSS_SW | GND | +| 29 | REFN0 | GND | +| 30 | REFP0 | VREF | +| 33 | EP | GND | +Open: 1 AINCOM, 2 AIN5, 3 AIN4, 4 AIN3, 19-22 GPIO3..0/AIN11..8, 25 NC, 31 REFN1/AIN7, 32 REFP1/AIN6. + +## U3 REF5025AIDR (SOIC-8, registry `ic/ref5025`) +Datasheet: https://www.ti.com/lit/ds/gpn/ref5025 (reviewed_by Steve Munene 2026-10-27; 5 of 8 pins checked). +| Pin | Name | Net | +| --- | --- | --- | +| 2 | VIN | +3V3A | +| 4 | GND | GND | +| 6 | VOUT | VREF (to U1 REFP0, C_RV) | +Open: 1 DNC, 3 TEMP, 5 TRIM/NR, 7 NC, 8 DNC. + +## U2 RP2350A (QFN-60, registry `mcus/rp2350`) +Datasheet: registry file records none in the part's provenance; QUALIFICATION.md cites https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf "from the KiCad symbol; not opened in this work". Pin numbers were compared against the KiCad `MCU_RaspberryPi:RP2350A` symbol; part not reviewed. +| Pin | Name | Net | +| --- | --- | --- | +| 1, 11, 20, 30, 38, 45 | IOVDD..IOVDD6 | +3V3 | +| 2 | GPIO0 | SPI_MISO | +| 3 | GPIO1 | SPI_CS | +| 4 | GPIO2 | SPI_SCK | +| 5 | GPIO3 | SPI_MOSI | +| 6, 23, 39 | DVDD, DVDD3, DVDD2 | DVDD_1V1 | +| 7 | GPIO4 | ADC_DRDY | +| 8 | GPIO5 | ADC_START | +| 9 | GPIO6 | ADC_RESET_N | +| 21 | XIN | XIN | +| 22 | XOUT | XOUT (R_X 1k to XOUT_R) | +| 24 | SWCLK | SWCLK (J3.1) | +| 25 | SWDIO | SWDIO (J3.2) | +| 26 | RUN | RUN (R_RUN 10k to +3V3) | +| 44 | ADC_AVDD | +3V3_RP_A | +| 46 | VREG_AVDD | +3V3_RP_A | +| 47 | VREG_PGND | GND | +| 48 | VREG_LX | VREG_LX (L1) | +| 49 | VREG_VIN | +3V3 | +| 50 | VREG_FB | DVDD_1V1 | +| 51 | USB_DM | USB_DN (via R_DN 27R) | +| 52 | USB_DP | USB_DP (via R_DP 27R) | +| 53 | USB_OTP_VDD | +3V3 | +| 54 | QSPI_IOVDD | +3V3 | +| 55 | QSPI_SD3 | QSPI_SD3 | +| 56 | QSPI_SCLK | QSPI_SCLK | +| 57 | QSPI_SD0 | QSPI_SD0 | +| 58 | QSPI_SD2 | QSPI_SD2 | +| 59 | QSPI_SD1 | QSPI_SD1 | +| 60 | QSPI_SS | QSPI_SS | +| 61 | GND (EP) | GND | +Open: GPIO7..GPIO29 and remaining pins (not connected in the `.synth`). + +## U4 W25Q128JVSIQ (SOIC-8, registry `memory/w25q128_flash`) +Datasheet: none recorded in the registry; not reviewed. Pin map from the registry. +| Pin | Name | Net | +| --- | --- | --- | +| 1 | CS | QSPI_SS | +| 2 | IO1 | QSPI_SD1 | +| 3 | IO2 | QSPI_SD2 | +| 4 | GND | GND | +| 5 | IO0 | QSPI_SD0 | +| 6 | CLK | QSPI_SCLK | +| 7 | IO3 | QSPI_SD3 | +| 8 | VCC | +3V3 | + +## U5 LP5907MFX-3.3 (SOT-23-5, registry `regulators/lp5907_3v3`) +Datasheet: https://www.ti.com/lit/ds/symlink/lp5907.pdf (reviewed_by Steve Munene 2026-10-27). +| Pin | Name | Net | +| --- | --- | --- | +| 1 | VIN | VBUS | +| 2 | GND | GND | +| 3 | EN | VBUS (always enabled) | +| 5 | VOUT | +3V3 | +Open: 4 (modelled NC). + +## J1 USB-C receptacle HRO TYPE-C-31-M-12 (registry `connectors/usb_c_receptacle`) +Datasheet: none recorded; LCSC C165948; not reviewed. +| Pins | Name | Net | +| --- | --- | --- | +| A4, B4, A9, B9 | VBUS | VBUS | +| A1, A12, B1, B12, SH | GND, shield | GND | +| A5 | CC1 | CC1 (R_CC1 5.1k to GND) | +| B5 | CC2 | CC2 (R_CC2 5.1k to GND) | +| A6, B6 | DP | USB_DP_C (D1, R_DP) | +| A7, B7 | DN | USB_DN_C (D2, R_DN) | +Open: A8 SBU1, B8 SBU2. + +## J2 PT100 header 1x4 (registry `header_1x4`, no datasheet) +| Pin | Function | Net | +| --- | --- | --- | +| 1 | F+ | RTD_FP (U1 AIN0, C_F) | +| 2 | S+ | RTD_SP (R_S1) | +| 3 | S- | RTD_SN (R_S2) | +| 4 | F- | RTD_FN (R_BIAS to GND) | + +## J3 SWD header 1x3 (registry `header_1x3`, no datasheet) +| Pin | Function | Net | +| --- | --- | --- | +| 1 | SWCLK | SWCLK (U2.24) | +| 2 | SWDIO | SWDIO (U2.25) | +| 3 | GND | GND | +No RESET/VCC pin on J3. + +## Y1 ECS-120-20-33-TR (registry `crystals/ecs_120_20_33_tr`) +Datasheet: https://ecsxtal.com/store/pdf/ecx-32.pdf (not reviewed; registry description: pads 1 and 3 crystal, 2 and 4 ground). +| Pin | Net | +| --- | --- | +| 1 | XIN (C_X1 33 pF to GND) | +| 3 | XOUT_R (C_X2 33 pF to GND) | +| 2, 4 | GND | + +## D1, D2 `esd_usb` (SOD-323, generic; no datasheet, no MPN) +D1: pin 1 IO to USB_DP_C, pin 2 GND. D2: pin 1 IO to USB_DN_C, pin 2 GND. + +## L1, L2 +L1 (3.3 uH, 0805): p1 VREG_LX, p2 DVDD_1V1. L2 (ferrite 600R@100MHz, 0603): p1 +3V3, p2 +3V3A. No datasheets. diff --git a/qualification/class-b/rtd-afe/agent-run/POWER_BUDGET.md b/qualification/class-b/rtd-afe/agent-run/POWER_BUDGET.md new file mode 100644 index 000000000..045a5b418 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/POWER_BUDGET.md @@ -0,0 +1,33 @@ +# POWER_BUDGET: rtd-afe + +Only values recorded in `rtd_afe.synth`, `registry/parts/**`, README.md and QUALIFICATION.md are used. No current was measured or datasheet-derived by this reconstruction. README: "No VBUS current budget was measured." Anything not recorded is "not verified". + +## Rail table +| Rail | Source | Loads | Regulator limit (registry) | Margin | +| --- | --- | --- | --- | --- | +| VBUS 5 V (`power "VBUS" 5v`) | J1 (USB host) | U5 LP5907 VIN and EN, C_L1 | host current limit not recorded | not verified | +| +3V3 3.3 V | U5 LP5907MFX-3.3, 250 mA max, 200 mW max power, 250 C/W | U1 DVDD/IOVDD, U2 IOVDD x6 / QSPI_IOVDD / USB_OTP_VDD / VREG_VIN, U4 VCC, pull-ups R_RST, R_RUN, L2 (feeds +3V3A), R_AV (feeds +3V3_RP_A) | 250 mA | load sum not verified | +| +3V3A | +3V3 through L2 600R@100MHz ferrite | U1 AVDD (330 nF + 10 uF), U3 VIN | L2 current rating and DC resistance not recorded ("not computed here" in `.synth`) | not verified | +| +3V3_RP_A | +3V3 through R_AV 33R + C_AVF 4.7 uF | U2 VREG_AVDD, ADC_AVDD | R_AV power rating not recorded | not verified | +| DVDD_1V1 | U2 on-chip regulator, VREG_LX through L1 3.3 uH | U2 DVDD x3, C_DV1, C_DV2, C_DVB | regulator output current limit and L1 saturation current not recorded | not verified | +| VREF 2.5 V | U3 REF5025 (registry description: 10 mA) | U1 REFP0, C_RV | 10 mA (from the registry description, not re-read) | U1 REFP0 load not recorded: not verified | + +## Operating limits recorded in the registry +| Part | Supply range | Other | +| --- | --- | --- | +| U1 ADS124S08 | 2.7 to 5.25 V | rails used: AVDD, DVDD, IOVDD all 3.3 V (inside range) | +| U3 REF5025 | 2.7 to 18 V | VIN 3.3 V from +3V3A; dropout against the 2.5 V output not recorded: not verified | +| U2 RP2350 | 1.8 to 3.6 V, max_current 150 mA, max_power 300 mW | registry values; origin not verified | +| U4 W25Q128 | 1.8 to 3.6 V, max_current 50 mA | registry value | +| U5 LP5907 | 2.2 to 5.5 V, 250 mA, 200 mW, 250 C/W | VBUS 5 V in | + +## Derived arithmetic (this document, not a source value) +- Registry maxima for U2 and U4 sum to 200 mA, leaving 50 mA of the 250 mA LDO limit before U1, U3 and the 1 mA IDAC are counted. Those loads are not recorded: not verified. +- LDO dissipation at 5.0 V in and 3.3 V out is (5.0 - 3.3) V x I = 1.7 V x I, ignoring ground current. The registry `max_power_mw` of 200 is reached at about 118 mA (200 mW / 1.7 V). At the 250 mA limit the figure is 425 mW, above the 200 mW registry value. Whether the registry 200 mW is the datasheet value, and the actual thermal behaviour on this board, are not verified. The note in the `.synth` says the board draws "a few tens of mA" (stated, not measured). +- IDAC path: 1 mA through R_BIAS 1k gives 1 V across R_BIAS (README: common mode about 1.1 V at 100 ohm RTD). Firmware must set the IDAC; not verified. + +## Decoupling fitted vs registry requirement +Per QUALIFICATION.md: ADS124S08 AVDD 330 nF (C_AV1) and DVDD 100 nF (C_DV); REF5025 VIN/VOUT 1 uF (C_RI, C_RV); LP5907 VIN/VOUT 2.2 uF fitted vs 1 uF required (C_L1, C_L2); RP2350 IOVDD 4 x 100 nF (C_IO1..4) and DVDD 2 x 100 nF + 4.7 uF (C_DV1, C_DV2, C_DVB); W25Q128 100 nF (C_FL). Capacitor DC-bias derating at 10 V ratings on 3.3 V rails: not verified. + +## Gaps +No VBUS fuse, TVS or reverse-polarity protection. No in-rush or USB-compliance check. No measured current. diff --git a/qualification/class-b/rtd-afe/agent-run/VERIFICATION_REPORT.md b/qualification/class-b/rtd-afe/agent-run/VERIFICATION_REPORT.md new file mode 100644 index 000000000..c3e1cf5d1 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/VERIFICATION_REPORT.md @@ -0,0 +1,43 @@ +# VERIFICATION_REPORT: rtd-afe + +Copied from the committed `reports/` files and `QUALIFICATION.md`. Nothing was re-run for this document. Hardware: not run. The board is not fabricated, not powered, not measured. + +## Gate verdicts +| Gate | Verdict | Source file | +| --- | --- | --- | +| KiCad DRC, all severities, refill zones | PASS: 0 errors, 0 warnings, 0 unconnected, `violations: []`, `schematic_parity: []` | `reports/rtd_afe.kicad-drc.json` (KiCad 10.0.7) | +| KiCad ERC | 0 errors, 2 warnings (open, dispositioned in QUALIFICATION.md as library-comparison, needs a human to confirm) | `reports/rtd_afe.kicad-erc.json` | +| Connectivity | PASS: `fabrication_ready: true`, 40 connected nets, 0 open, no missing footprints/nets/pads, `blocking_reasons: []` | `reports/rtd_afe.connectivity.json` | +| Routing | routed, FreeRouting 2.4.1, 371 segments, 67 vias recorded by the router (77 incl. source stitching per QUALIFICATION.md), 654.8 mm wire, 0 open nets | `reports/rtd_afe.routing.json` | +| Synth release | FAIL/OPEN: `production_status: untrusted`, `release_ready: false` (override `--allow-unverified-parts` for `ecs_120_20_33_tr`). `gate_scope` says this is not a fabrication approval or component review | `reports/release.json` | +| Synth signal integrity | 18 warnings, 0 blocking | `reports/release.json` | +| pcbnew reopen / single GND plane | PASS per `check.sh` (`reopen ok; single GND plane`), recorded in QUALIFICATION.md; the script output itself is not a committed report | `check.sh`, QUALIFICATION.md | +| Via-in-pad | 1 via at (16.500, 22.300) mm, C_DV.2; order with filled and capped vias | `reports/rtd_afe.connectivity.json`, `reports/release.json` | + +## ERC warnings (open) +1. `lib_symbol_issues`: symbol `Ferrite_Bead` not found in library `Device` (L2). Registry uses the old name. +2. `lib_symbol_mismatch`: `REF5025ID` differs from the library copy (U3). Cosmetic per QUALIFICATION.md. + +## SI warnings (non-blocking, open) +15 layer changes with no ground-return via within 0.64 mm (SPI_MOSI/CS/MISO, ADC_DRDY, ADC_START, QSPI_SD0/SD1/SD3, +3V3_RP_A, DVDD_1V1, USB_DN_C and others listed in `release.json`) and 3 parallel runs: REFOUT/+3V3_RP_A 2.7 mm, ADC_START/VBUS 2.5 mm, +3V3/VREG_LX 4.6 mm at 0.147 mm. No RTD, AIN or VREF finding. USB path mismatch 7.09 mm (22.60 mm DP vs 29.69 mm DN), no controlled impedance. None simulated. + +## Synth validate warnings (QUALIFICATION.md, not committed as a report) +E-SYNTH-POWER-004 (VBUS 7 loads, 1 capacitor), W-SYNTH-ANOMALY-001, W-SYNTH-SUPPLY-002 x10, W-SYNTH-PART-UNVERIFIED (Y1), E-SYNTH-CONNECT-007 x2, E-SYNTH-ESD-001 x3 (no VBUS reverse protection, no CC TVS), E-SYNTH-SCHEM-003 x11, E-SYNTH-SCHEM-004/005. + +## Part reviews (`reports/release.json` reviewer_state) +Reviewed (Steve Munene, 2026-10-27): ads124s08, ref5025, lp5907_3v3. Not reviewed: rp2350, w25q128_flash, usb_c_receptacle, ecs_120_20_33_tr, esd_usb, ferrite_bead_0603, header_1x3, header_1x4, mounting_hole_m2_5, r_generic_0603, c_generic_0603, c_generic_0805, l_generic_0805. The `ads124s08` symbol is synthetic. + +## Open gates (all from QUALIFICATION.md "Left to a human") +- SI/PI/RF review by the designated reviewer: open; nothing simulated or measured. +- Metrology/analog: not ratiometric; IDAC accuracy and drift, REF5025 grade, PGA common-mode range at chosen gain, unused-input termination, filter vs data rate: open, no error budget. +- USB/ESD: no VBUS fuse/TVS/reverse protection, CC1/CC2 no TVS, D1/D2 no MPN, USB-C compliance unchecked: open. +- Mechanical: enclosure, screw-head clearance, connector overhang, header orientation unchecked: open. +- Test points: none fitted: open. +- Fabrication/DFM: no fab has seen the files; via-in-pad process not accepted by JLCPCB; fine-pitch capability unchecked: open. +- Firmware: does not exist: open. +- Independent sign-off: none; no second-person check, no hardware measurement: open. +- Reproducibility: committed board is one successful run, not proven byte-identical on re-run. + +## Discrepancy found while copying (resolved) +QUALIFICATION.md's Reproducibility table and an inline PCB hash were stale against the committed files; `SHA256SUMS` matched the files. Commit `4db6fe0` replaced the table with a pointer to `SHA256SUMS` and corrected the inline PCB hash (`1e4803cf...043a`). Nothing was re-run for this document. Which run produced the committed reports: not verified beyond `release.json` `source_revision` `28f7f1ec3aef55fa2881fdfbfaad6c1b6896b562`. + diff --git a/qualification/class-b/rtd-afe/agent-run/prompt.md b/qualification/class-b/rtd-afe/agent-run/prompt.md new file mode 100644 index 000000000..465dd0b56 --- /dev/null +++ b/qualification/class-b/rtd-afe/agent-run/prompt.md @@ -0,0 +1,86 @@ +# Prompt: PT100 4-wire RTD analog front end (rtd-afe, SYN-363) + +This board was built by agents, in stages, from the briefs below. There was no single prompt. The two briefs are copied verbatim from the session transcripts. After them, the board was changed by review rounds and by routing results; the section "Differences between these briefs and the committed board" lists what could be traced. A different run will not produce an identical board. + +## 1. Request that started the work (2026-10-27) + +> we need 2 other unique class B board. My first 2 board are 103 and 110 but I need 2 and they should be complex in class B + +This went through the grilling, to-spec, to-tickets and implement-spec steps, which produced spec #361 and ticket #363 (this board). + +## 2. Implementation brief for ticket #363 (2026-10-27 18:36, verbatim) + +````text +Implement GitHub issue absmach/synth#363 (`gh issue view 363 -R absmach/synth`; parent spec #361, read it too). Work in the existing worktree /home/steve/work/synth-classb (branch syn-361-class-b-boards; #362 and #364 are committed there: ADS124S08 and REF5025 are in registry/parts/ic/). Do not touch /home/steve/work/synth. + +Pattern to copy: the buck board's directory `qualification/class-b/buck/` on branch origin/syn-67-buck-board (look with `git show origin/syn-67-buck-board:qualification/class-b/buck/QUALIFICATION.md` etc.) and the USB-UART board on origin/syn-66-usb-uart-board; main already has a qualification/class-b dir, inspect it first. Create qualification/class-b/rtd-afe/ with the .synth source, placement layout, QUALIFICATION.md and SHA256SUMS. + +Board: 4 layers, PT100 4-wire input, RC input filter, ADS124S08 with IDAC excitation and REF5025 reference, rp2350 over SPI with USB-C readout (rp2350, usb_c_receptacle and esd_usb are in the registry), AGND/DGND split with a single-point tie, decoupling from the part files. Novel and publication-quality: sensible placement (analog on one side, digital on the other, reference close to the ADC), silk labels, board outline. + +Rules: +- Use the mattpocock `tdd` skill. Seam: existing golden/export tests; first write the failing check (e.g. the board exports, KiCad DRC clean including unconnected items, AGND and DGND each present and joined at exactly one tie), then build. +- Autoroute: `synth export-kicad --out --autoroute --force` (FreeRouting jar at tools/freerouting/, JRE at tools/jre25/, both in the main checkout /home/steve/work/synth/tools; copy or symlink into the worktree, they are git-excluded). +- Prove: KiCad DRC clean via kicad-cli (include unconnected items, do not trust Synth's own gate), the exported .kicad_pcb reopens (pcbnew Python), AGND/DGND single-tie check. Record datasheet review per part and what needs an SI/PI/RF expert in QUALIFICATION.md. +- If a Synth defect blocks the build, fix it only when blocking, in a separate commit; otherwise write it down in your report (do not file issues yourself). +- Golden hashes: do NOT regenerate golden.json/SVG hashes locally; leave them for ticket #366. +- Do NOT run `cargo test --workspace` (hangs). Run the narrow crates you touch. `cargo clean` when done. +- Commit with `git commit -sm "SYN-363 - "`, sign-off only, no Claude attribution. Do not push. Spawn no sub-agents. +Report: commit hashes, files, evidence (DRC output counts, reopen result, tie check), Synth defects hit, open items. +```` + +## 3. Finalisation prompt for opencode with DeepSeek (written 2026-10-29, verbatim) + +````text +You are finishing ticket SYN-363, the RTD analog front end Class B board, in the Rust PCB tool "Synth" (absmach/synth). Another engineer (Rodney) is building the BLE board (#365) in parallel: do not touch the nRF52840, balun, antenna, BME280 or crystal parts, and do not touch anything for #365. + +## Where to work +- Worktree: /home/steve/work/synth-classb (branch syn-361-class-b-boards, based on upstream/main). Work only there. Do not touch /home/steve/work/synth. +- Read first: `gh issue view 361 -R absmach/synth` (spec) and `gh issue view 363 -R absmach/synth` (your ticket). Always pass `-R absmach/synth` to gh. +- Reference boards for format: qualification/class-b/usb-uart/ in the worktree (README / QUALIFICATION.md / SHA256SUMS layout). The buck board is on branch origin/syn-67-buck-board (qualification/class-b/buck/). + +## Spec in one paragraph +Novel 4-layer RTD measurement board: PT100 4-wire input, RC input filter, ADS124S08 24-bit delta-sigma ADC (IDAC excitation), REF5025 reference, rp2350 over SPI with a USB-C readout port, AGND/DGND split joined at exactly one tie point (R_TIE). Publication-quality: analog on one side, digital on the other, reference close to the ADC, clean silk labels and outline. Public post material, so every claim in QUALIFICATION.md must be evidence-backed. + +## Done so far (do not redo) +- #362 committed 612ccc4: registry/parts/ic/ads124s08.synth.toml (hand-authored from TI SBAS660C, no KiCad symbol exists) and ref5025.synth.toml (imported, pins checked against TI SBOS410I), plus the pin test `rtd_front_end_parts_match_their_datasheet_pinouts` in crates/synth-registry/src/loader.rs. +- #364 committed d17e651 (BLE parts; not yours, leave alone). +- #363 commit 81bb62a: exporter fix so each split ground's fence vias stay inside its own pour (crates/synth-kicad/src/pcb.rs, test in tests/split_ground_pcb.rs). +- UNCOMMITTED in the worktree: qualification/class-b/rtd-afe/ containing rtd_afe.synth (237 lines), rtd_afe.placement.layout.toml, check.sh, kicad/ (exported .kicad_pcb/.kicad_sch, gerbers, drill, bom.csv, pnp.csv), reports/ (kicad-drc.json, erc, netlist, routing, connectivity, release), images/ (pcb-3d-top.png, pcb-3d-bottom.png). +- Known state: the last KiCad DRC report (reports/rtd_afe.kicad-drc.json) has 0 unconnected items and 12 entries in `violations`. Their severities are NOT yet reviewed. + +## What is left (in order) +1. Re-run `qualification/class-b/rtd-afe/check.sh` from the repo root (build first: `cargo build -p synth-cli`; the script uses target/debug/synth; FreeRouting jar is tools/freerouting/freerouting-2.4.1.jar and JRE tools/jre25/, both git-excluded and living in /home/steve/work/synth/tools, symlink or copy them in). Read every one of the 12 DRC violations and the ERC report. Fix real errors (placement, source, or a blocking Synth defect). Warnings that remain must each be explained in QUALIFICATION.md. The acceptance bar: zero DRC errors, zero unconnected items, reopen OK, AGND/DGND tied only at R_TIE. +2. Visual check: open images/pcb-3d-top.png and bottom.png; fix anything ugly (overlapping silk, labels far from parts, parts crammed, reference far from ADC). +3. Write qualification/class-b/rtd-afe/QUALIFICATION.md and README.md in the style of the usb-uart board: what the board is, stackup (4 layers, which are planes), the check results with the real numbers, per-part datasheet review table (ADS124S08, REF5025, rp2350, USB-C, ESD, passives: datasheet URL, pins checked, decoupling), the AGND/DGND tie argument, and an explicit "needs an SI/PI/RF expert / human reference / independent sign-off" section. Do not claim anything you did not measure. +4. Generate SHA256SUMS for the deliverables (same convention as usb-uart). +5. Run only the narrow tests for crates you touched: `cargo test -p synth-kicad --test split_ground_pcb` and `cargo test -p synth-registry`. NEVER run `cargo test --workspace` (it hangs). Run `cargo clean` when finished. +6. Commit in small commits: `git commit -sm "SYN-363 - "`. Sign-off only. No Co-Authored-By or any AI attribution line. +7. Stop and report. Do NOT push, do NOT open a PR, do NOT merge, do NOT comment on GitHub issues. + +## Hard rules +- Golden hashes (fixtures/kicad-reference/svg/golden.json and the golden snapshots): do NOT regenerate locally. They come from CI output in ticket #366. +- Do not trust Synth's own "0 violations" line. The proof is `kicad-cli pcb drc --severity-all --refill-zones` plus unconnected items, and a pcbnew reopen. +- If a Synth defect blocks the build, fix it minimally in its own commit with a regression test, and write the defect down in your final report. Do not fix unrelated things. +- Match the style of surrounding code and files. Keep changes surgical. +- Use TDD for any Rust change: failing test first. + +## Final report (keep short) +Commit hashes; DRC counts (errors / warnings / unconnected) before and after; reopen result; tie-check result; list of files in the board directory; every Synth defect you hit; anything left that needs a human (expert review, fab-house check, real hardware). +```` + +## Differences between these briefs and the committed board + +Found by comparing the briefs with the committed files. Where no instruction could be found, the entry says so. + +- **Ground.** The briefs ask for an AGND/DGND split joined at one tie point (R_TIE). The committed board has one GND plane and no AGND or DGND net. `QUALIFICATION.md` says the split version needed a tie and still left two isolated pours on the merged router. No instruction for the change was found. +- **Board outline.** The briefs ask for a "board outline". The committed outline is a closed notched path in `rtd_afe.placement.layout.toml` (`[[outline]]`), added in commit c08f766 after the review comment that a normal export produced a different rectangular board. +- **USB-C.** The committed board has the USB-C centred on the top edge (commit f4b3a37). No instruction for that was found. +- **Via-in-pad.** One via-in-pad at C_DV.2 is required, with the manufacturer profile `jlc-filled-via`. The briefs do not mention it. +- **Silkscreen.** 34 reference labels are hidden to avoid clipping. The briefs do not mention it. +- **Part review.** The briefs ask for a datasheet review per part. Only ADS124S08, LP5907 and REF5025 are recorded as reviewed (by the author). The release is `production_status: untrusted`. + +## What the briefs cannot reproduce + +- The placement and sidecar coordinates. +- The routed result. FreeRouting is not bit-for-bit repeatable and was sensitive to placement. +- The independent SI/PI/RF, part and fabrication reviews. They have not happened. diff --git a/qualification/class-b/rtd-afe/check.sh b/qualification/class-b/rtd-afe/check.sh new file mode 100755 index 000000000..e4834a496 --- /dev/null +++ b/qualification/class-b/rtd-afe/check.sh @@ -0,0 +1,50 @@ +#!/usr/bin/env bash +# SYN-363 acceptance check. Run from the repo root: qualification/class-b/rtd-afe/check.sh +# Exports + autoroutes the board, then proves with KiCad itself (not Synth's gate): +# 1. DRC clean including unconnected items, 2. the .kicad_pcb reopens in pcbnew, +# 3. GND is one plane: no AGND/DGND split and no tie resistor. +set -euo pipefail +B=$(cd "$(dirname "$0")" && pwd); OUT=${OUT:-$B/kicad}; SYNTH=${SYNTH:-target/debug/synth} +export XDG_DATA_HOME=$(mktemp -d) +# Stamp the tree that produced the package; an unset variable stays unset. +export SYNTH_SOURCE_REVISION=${SYNTH_SOURCE_REVISION:-$(git -C "$B/../../.." rev-parse HEAD 2>/dev/null || true)} +rm -rf "$OUT" "$B/reports" "$B/images" +$SYNTH export-kicad "$B/rtd_afe.synth" --out "$OUT" --router free-routing \ + --allow-unverified-parts --validate-erc --pnp --gerbers --drill >/dev/null +PCB=$OUT/rtd_afe.kicad_pcb +mkdir -p "$B/reports" "$B/images" +mv "$OUT"/release.json "$OUT"/rtd_afe.routing.json "$OUT"/rtd_afe.connectivity.json "$B/reports/" +rm -f "$OUT"/rtd_afe.freerouting.* "$OUT"/rtd_afe.synth.kicad_* "$OUT"/rtd_afe.drc.json +kicad-cli pcb drc --severity-all --refill-zones --format json -o "$B/reports/rtd_afe.kicad-drc.json" "$PCB" >/dev/null +kicad-cli sch erc --severity-all --format json -o "$B/reports/rtd_afe.kicad-erc.json" "$OUT/rtd_afe.kicad_sch" >/dev/null +kicad-cli sch export netlist --format kicadsexpr -o "$B/reports/rtd_afe.net" "$OUT/rtd_afe.kicad_sch" >/dev/null +# The run records name the checkout they were built in; keep only the +# repository-relative part so the committed evidence is portable. +REPO=$(cd "$B/../../.." && pwd) +python3 -I - "$REPO" "$B/reports/release.json" "$B/reports/rtd_afe.routing.json" "$B/reports/rtd_afe.net" <<'PY' +import pathlib, sys +root = sys.argv[1] + "/" +for name in sys.argv[2:]: + path = pathlib.Path(name) + path.write_text(path.read_text().replace(root, "")) +PY +for side in top bottom; do kicad-cli pcb render --side $side --width 1600 --height 1200 -o "$B/images/pcb-3d-$side.png" "$PCB" >/dev/null; done +kicad-cli pcb render --side top --rotate -45,0,45 --perspective \ + --width 1600 --height 1200 -o "$B/images/pcb-3d-angled.png" "$PCB" >/dev/null +SCHEMATIC_PDF=$(mktemp --suffix=.pdf) +kicad-cli sch export pdf -o "$SCHEMATIC_PDF" "$OUT/rtd_afe.kicad_sch" >/dev/null +pdftoppm -png -r 150 -singlefile "$SCHEMATIC_PDF" "$B/images/schematic" >/dev/null +rm -f "$SCHEMATIC_PDF" +python3 -I - "$B/reports/rtd_afe.kicad-drc.json" "$PCB" <<'PY' +import json, sys, pcbnew +d = json.load(open(sys.argv[1])) +v = [x for x in d["violations"] if x["severity"] == "error"] +u = d["unconnected_items"] +print(f"DRC errors={len(v)} unconnected={len(u)} warnings={sum(x['severity']=='warning' for x in d['violations'])}") +assert not v and not u, (v[:3], u[:3]) +b = pcbnew.LoadBoard(sys.argv[2]) # reopen +nets = b.GetNetsByName() +assert nets.has_key("GND"), "GND missing" +assert not nets.has_key("AGND") and not nets.has_key("DGND"), "split ground nets remain" +print("reopen ok; single GND plane") +PY diff --git a/qualification/class-b/rtd-afe/images/pcb-3d-angled.png b/qualification/class-b/rtd-afe/images/pcb-3d-angled.png new file mode 100644 index 000000000..5658c16bf Binary files /dev/null and b/qualification/class-b/rtd-afe/images/pcb-3d-angled.png differ diff --git a/qualification/class-b/rtd-afe/images/pcb-3d-bottom.png b/qualification/class-b/rtd-afe/images/pcb-3d-bottom.png new file mode 100644 index 000000000..68f182c7b Binary files /dev/null and b/qualification/class-b/rtd-afe/images/pcb-3d-bottom.png differ diff --git a/qualification/class-b/rtd-afe/images/pcb-3d-top.png b/qualification/class-b/rtd-afe/images/pcb-3d-top.png new file mode 100644 index 000000000..c6034938c Binary files /dev/null and b/qualification/class-b/rtd-afe/images/pcb-3d-top.png differ diff --git a/qualification/class-b/rtd-afe/images/schematic.png b/qualification/class-b/rtd-afe/images/schematic.png new file mode 100644 index 000000000..ce1766fce Binary files /dev/null and b/qualification/class-b/rtd-afe/images/schematic.png differ diff --git a/qualification/class-b/rtd-afe/kicad/bom.csv b/qualification/class-b/rtd-afe/kicad/bom.csv new file mode 100644 index 000000000..49ab5dede --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/bom.csv @@ -0,0 +1,54 @@ +refdes,value,kind,description,kicad_symbol,kicad_footprint,lcsc_pn,mpn,dielectric,voltage,tolerance,power +C_AV1,330nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C188679,0603B334K500NT,X7R,10V,, +C_AV2,10uF,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,C380347,TCC0805X7R106K160FT,X7R,10V,, +C_AVF,4.7uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C18185770,TCC0603X7R475K100CT,X7R,10V,, +C_CM1,10nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C2894187,0603N103J500CT,C0G,50V,, +C_CM2,10nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C2894187,0603N103J500CT,C0G,50V,, +C_D,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,,,C0G,50V,, +C_DV,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_DV1,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_DV2,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_DVB,4.7uF,capacitor,"Generic 0805 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0805_2012Metric,C354262,CC0805KKX7R8BB475,X7R,10V,, +C_F,10nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C2894187,0603N103J500CT,C0G,50V,, +C_FL,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_IO,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_IO1,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_IO2,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_IO3,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_IO4,100nF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C14663,CC0603KRX7R9BB104,X7R,10V,, +C_L1,2.2uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C43922,0603B225K160NT,X7R,16V,, +C_L2,2.2uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C43922,0603B225K160NT,X7R,16V,, +C_RI,1uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C93816,0603B105K160NT,X7R,10V,, +C_RO,1uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C93816,0603B105K160NT,X7R,10V,, +C_RV,1uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C93816,0603B105K160NT,X7R,10V,, +C_VI,4.7uF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C18185770,TCC0603X7R475K100CT,X7R,10V,, +C_X1,33pF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C1663,CL10C330JB8NNNC,C0G,50V,, +C_X2,33pF,capacitor,"Generic 0603 MLCC, X7R/X5R, any value",Device:C,Capacitor_SMD:C_0603_1608Metric,C1663,CL10C330JB8NNNC,C0G,50V,, +D1,ESD,diode,"USB-line ESD protection (TVS diode array), bidirectional",Device:D_TVS,Diode_SMD:D_SOD-323,C521915,ESD5V0B03-323,,,, +D2,ESD,diode,"USB-line ESD protection (TVS diode array), bidirectional",Device:D_TVS,Diode_SMD:D_SOD-323,C521915,ESD5V0B03-323,,,, +H1,(no value),mounting_hole,M2.5 clearance mounting hole (2.7 mm NPTH) for a screw that passes through the board,Mechanical:MountingHole,MountingHole:MountingHole_2.7mm_M2.5,,,,,, +H2,(no value),mounting_hole,M2.5 clearance mounting hole (2.7 mm NPTH) for a screw that passes through the board,Mechanical:MountingHole,MountingHole:MountingHole_2.7mm_M2.5,,,,,, +H3,(no value),mounting_hole,M2.5 clearance mounting hole (2.7 mm NPTH) for a screw that passes through the board,Mechanical:MountingHole,MountingHole:MountingHole_2.7mm_M2.5,,,,,, +H4,(no value),mounting_hole,M2.5 clearance mounting hole (2.7 mm NPTH) for a screw that passes through the board,Mechanical:MountingHole,MountingHole:MountingHole_2.7mm_M2.5,,,,,, +J1,TYPE-C-31-M-12,connector,"USB-C receptacle, 16-pin SMD (HRO TYPE-C-31-M-12). Modelled here with primary and mirrored power/ground/data pins for full pad coverage.",Connector:USB_C_Receptacle,Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12,C165948,TYPE-C-31-M-12,,,, +J2,PT100,connector,"1x4 through-hole pin header, 2.54mm pitch",Connector_Generic:Conn_01x04,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical,C492403,PZ254V-11-04P,,,, +J3,SWD,connector,"1x3 through-hole pin header, 2.54mm pitch",Connector_Generic:Conn_01x03,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,C2937625,PZ254V-11-03P,,,, +L1,3.3uH,inductor,"Generic 0805 wirewound inductor, any value",Device:L,Inductor_SMD:L_0805_2012Metric,,,,,, +L2,600R@100MHz,inductor,"0603 ferrite bead, 600Ω @ 100MHz — EMI suppression",Device:FerriteBead,Inductor_SMD:L_0603_1608Metric,C19330,BLM18AG601SN1D,,,, +R_AV,33,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C2909394,FRC0603F33R0TS,,,, +R_BIAS,1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C110776,RT0603BRD071KL,,,0.1%, +R_CC1,5.1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C23186,0603WAF5101T5E,,,, +R_CC2,5.1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C23186,0603WAF5101T5E,,,, +R_DN,27,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C25190,0603WAF270JT5E,,,, +R_DP,27,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C25190,0603WAF270JT5E,,,, +R_RST,10k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C25804,0603WAF1002T5E,,,, +R_RUN,10k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C25804,0603WAF1002T5E,,,, +R_S1,1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C110776,RT0603BRD071KL,,,0.1%, +R_S2,1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C110776,RT0603BRD071KL,,,0.1%, +R_X,1k,resistor,"Generic 0603 thick-film resistor, any value",Device:R_US,Resistor_SMD:R_0603_1608Metric,C21190,0603WAF1001T5E,,,, +U1,ADS124S08IRHBR,ic,"TI ADS124S08 24-bit delta-sigma ADC, 12 inputs, PGA, 2.5 V reference, dual IDACs, SPI, VQFN-32 (RHB0032M, 5x5 mm, exposed pad)",,Package_DFN_QFN:Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm,C2871942,ADS124S08IRHBR,,,, +U2,RP2350A,mcu,"Raspberry Pi RP2350 dual-core MCU, QFN-60",MCU_RaspberryPi:RP2350A,Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm,C42411118,RP2350A,,,, +U3,REF5025AIDR,ic,"TI REF5025ID 2.5 V low-noise, low-drift precision voltage reference, 10 mA, SOIC-8",Reference_Voltage:REF5025ID,Package_SO:SOIC-8_3.9x4.9mm_P1.27mm,C11341,REF5025AIDR,,,, +U4,W25Q128JVSIQ,ic,"Winbond W25Q128JVSIQ 128Mbit SPI NOR flash, SOIC-8 208 mil (5.28 mm body, 7.9 mm lead span)",Memory_Flash:W25Q128JVS,Package_SO:SOIC-8_5.3x5.3mm_P1.27mm,C97521,W25Q128JVSIQ,,,, +U5,LDO,regulator,"TI LP5907 3.3V low-noise LDO, 250mA, SOT-23-5",Regulator_Linear:LP5907MFX-3.3,Package_TO_SOT_SMD:SOT-23-5,C80670,LP5907MFX-3.3/NOPB,,,, +Y1,12MHz,crystal,"ECS ECS-120-20-33-TR 12.000 MHz crystal, 20 pF load, 3.2 x 2.5 mm 4-pad SMD; pads 1 and 3 are the crystal, 2 and 4 are ground",Device:Crystal_GND24,Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm,,ECS-120-20-33-TR,,,, diff --git a/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH-drl_map.pdf b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH-drl_map.pdf new file mode 100644 index 000000000..b3e7b53a2 Binary files /dev/null and b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH-drl_map.pdf differ diff --git a/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH.drl b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH.drl new file mode 100644 index 000000000..a586c8684 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-NPTH.drl @@ -0,0 +1,24 @@ +M48 +; DRILL file KiCad 10.0.7-10.0.7~ubuntu24.04.1 date 2026-11-05T16:34:33 +; FORMAT={-:-/ absolute / metric / decimal} +; #@! TF.CreationDate,2026-11-05T16:34:33+03:00 +; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1 +; #@! TF.FileFunction,NonPlated,1,4,NPTH +FMAT,2 +METRIC +; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill +T1C0.650 +; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill +T2C2.700 +% +G90 +G05 +T1 +X19.66Y-8.04 +X25.44Y-8.04 +T2 +X6.0Y-3.5 +X6.0Y-40.7 +X39.0Y-3.5 +X39.0Y-40.7 +M30 diff --git a/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH-drl_map.pdf b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH-drl_map.pdf new file mode 100644 index 000000000..020fe0e8e Binary files /dev/null and b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH-drl_map.pdf differ diff --git a/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH.drl b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH.drl new file mode 100644 index 000000000..14e32ca90 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/drill/rtd_afe-PTH.drl @@ -0,0 +1,128 @@ +M48 +; DRILL file KiCad 10.0.7-10.0.7~ubuntu24.04.1 date 2026-11-05T16:34:33 +; FORMAT={-:-/ absolute / metric / decimal} +; #@! TF.CreationDate,2026-11-05T16:34:33+03:00 +; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1 +; #@! TF.FileFunction,Plated,1,4,PTH +FMAT,2 +METRIC +; #@! TA.AperFunction,Plated,PTH,ViaDrill +T1C0.200 +; #@! TA.AperFunction,Plated,PTH,ViaDrill +T2C0.300 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T3C0.600 +; #@! TA.AperFunction,Plated,PTH,ComponentDrill +T4C1.000 +% +G90 +G05 +T1 +X13.9Y-24.355 +X15.652Y-27.897 +X16.827Y-24.751 +X18.278Y-29.364 +X21.573Y-29.24 +X29.941Y-23.966 +T2 +X4.5Y-26.375 +X5.575Y-12.3 +X7.0Y-23.025 +X8.025Y-14.305 +X8.425Y-1.49 +X8.434Y-42.7 +X8.45Y-17.6 +X8.662Y-24.65 +X9.275Y-31.1 +X9.55Y-22.662 +X11.775Y-16.6 +X13.438Y-23.65 +X13.5Y-25.055 +X14.317Y-28.999 +X14.952Y-28.297 +X15.438Y-23.435 +X15.493Y-24.637 +X15.5Y-22.3 +X16.138Y-22.835 +X16.275Y-31.1 +X16.775Y-12.6 +X16.775Y-34.6 +X16.8Y-28.875 +X17.527Y-25.251 +X17.678Y-28.764 +X18.128Y-32.398 +X18.412Y-21.805 +X18.828Y-31.998 +X19.507Y-21.691 +X20.07Y-36.498 +X20.207Y-21.291 +X20.275Y-26.0 +X20.289Y-22.571 +X20.77Y-36.898 +X20.989Y-22.171 +X21.275Y-31.0 +X21.675Y-14.0 +X22.173Y-29.84 +X22.686Y-27.907 +X22.725Y-11.8 +X23.084Y-30.502 +X23.408Y-27.083 +X23.415Y-28.632 +X23.465Y-29.71 +X23.575Y-14.2 +X23.758Y-7.947 +X23.866Y-20.679 +X24.166Y-21.429 +X24.855Y-24.342 +X25.25Y-12.0 +X25.255Y-23.642 +X25.275Y-38.3 +X25.54Y-29.046 +X25.7Y-35.75 +X25.863Y-30.423 +X26.108Y-38.788 +X26.808Y-39.188 +X27.963Y-27.122 +X28.0Y-31.8 +X28.75Y-12.0 +X29.1Y-38.25 +X29.341Y-24.566 +X29.697Y-27.468 +X30.28Y-34.091 +X30.297Y-28.168 +X30.4Y-25.3 +X30.98Y-34.491 +X31.981Y-25.657 +X32.151Y-6.591 +X32.551Y-7.291 +X32.681Y-25.257 +X32.775Y-37.3 +X34.163Y-10.5 +X34.5Y-13.225 +X34.775Y-25.0 +X34.775Y-29.0 +X36.566Y-42.7 +X36.575Y-1.49 +X36.725Y-7.5 +X37.05Y-19.6 +X38.275Y-26.0 +X38.275Y-29.0 +X40.0Y-13.225 +T4 +X10.99Y-41.7 +X13.53Y-41.7 +X16.07Y-41.7 +X18.61Y-41.7 +X25.46Y-41.7 +X28.0Y-41.7 +X30.54Y-41.7 +T3 +X18.23Y-4.69G85X18.23Y-4.09 +G05 +X18.23Y-9.12G85X18.23Y-8.02 +G05 +X26.87Y-4.69G85X26.87Y-4.09 +G05 +X26.87Y-9.12G85X26.87Y-8.02 +G05 +M30 diff --git a/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Adhesive.gbr b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Adhesive.gbr new file mode 100644 index 000000000..725d66e09 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Adhesive.gbr @@ -0,0 +1,15 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1*% +%TF.CreationDate,2026-11-05T16:34:32+03:00*% +%TF.ProjectId,rtd_afe,7274645f-6166-4652-9e6b-696361645f70,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Glue,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.7-10.0.7~ubuntu24.04.1) date 2026-11-05 16:34:32* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 APERTURE END LIST* +M02* diff --git a/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Courtyard.gbr b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Courtyard.gbr new file mode 100644 index 000000000..1119cd1b0 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Courtyard.gbr @@ -0,0 +1,14 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1*% +%TF.CreationDate,2026-11-05T16:34:32+03:00*% +%TF.ProjectId,rtd_afe,7274645f-6166-4652-9e6b-696361645f70,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Other,User*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.7-10.0.7~ubuntu24.04.1) date 2026-11-05 16:34:32* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 APERTURE END LIST* +M02* diff --git a/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Cu.gbr b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Cu.gbr new file mode 100644 index 000000000..de131be43 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-B_Cu.gbr @@ -0,0 +1,2046 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1*% +%TF.CreationDate,2026-11-05T16:34:32+03:00*% +%TF.ProjectId,rtd_afe,7274645f-6166-4652-9e6b-696361645f70,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L4,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.7-10.0.7~ubuntu24.04.1) date 2026-11-05 16:34:32* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,ComponentPad*% +%ADD10R,1.700000X1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12O,1.000000X2.100000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13O,1.000000X1.600000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD14C,0.600000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD15C,0.460000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD16C,0.127000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD17C,0.242000*% +%TD*% +G04 APERTURE END LIST* +D10* +%TO.P,J2,1*% +%TO.N,RTD_FP*% +X18610000Y-41700000D03* +D11* +%TO.P,J2,2*% +%TO.N,RTD_SP*% +X16070000Y-41700000D03* +%TO.P,J2,3*% +%TO.N,RTD_SN*% +X13530000Y-41700000D03* +%TO.P,J2,4*% +%TO.N,RTD_FN*% +X10990000Y-41700000D03* +%TD*% +D10* +%TO.P,J3,1*% +%TO.N,SWCLK*% +X25460000Y-41700000D03* +D11* +%TO.P,J3,2*% +%TO.N,SWDIO*% +X28000000Y-41700000D03* +%TO.P,J3,3*% +%TO.N,GND*% +X30540000Y-41700000D03* +%TD*% +D12* +%TO.P,J1,SH*% +%TO.N,GND*% +X26870000Y-8570000D03* +D13* +X26870000Y-4390000D03* +D12* +X18230000Y-8570000D03* +D13* +X18230000Y-4390000D03* +%TD*% +D14* +%TO.N,GND*% +X8433600Y-42700000D03* +X36566400Y-42700000D03* +X36574600Y-1490000D03* +X8425400Y-1490000D03* +X30400000Y-25300000D03* +X15500000Y-22300000D03* +%TO.N,SPI_MOSI*% +X17677800Y-28764200D03* +X23414700Y-28632400D03* +%TO.N,SPI_CS*% +X14952300Y-28297200D03* +X22172600Y-29840200D03* +%TO.N,SPI_SCK*% +X13499800Y-25055400D03* +X22686000Y-27906600D03* +%TO.N,SPI_MISO*% +X17526900Y-25250800D03* +X23408400Y-27082900D03* +%TO.N,ADC_DRDY*% +X15493500Y-24637100D03* +X23084300Y-30501900D03* +%TO.N,ADC_START*% +X14317300Y-28998700D03* +X23465300Y-29710500D03* +%TO.N,ADC_RESET_N*% +X15438300Y-23435000D03* +X25540200Y-29045600D03* +%TO.N,RUN*% +X30280300Y-34091500D03* +X20770100Y-36898200D03* +%TO.N,SWCLK*% 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+%LPD*% +G01* +G04 APERTURE LIST* +G04 APERTURE END LIST* +M02* diff --git a/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-User_Eco2.gbr b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-User_Eco2.gbr new file mode 100644 index 000000000..bd9cff9c1 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-User_Eco2.gbr @@ -0,0 +1,14 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.7-10.0.7~ubuntu24.04.1*% +%TF.CreationDate,2026-11-05T16:34:32+03:00*% +%TF.ProjectId,rtd_afe,7274645f-6166-4652-9e6b-696361645f70,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Other,ECO2*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.7-10.0.7~ubuntu24.04.1) date 2026-11-05 16:34:32* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 APERTURE END LIST* +M02* diff --git a/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-job.gbrjob b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-job.gbrjob new file mode 100644 index 000000000..b78787824 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/gerbers/rtd_afe-job.gbrjob @@ -0,0 +1,209 @@ +{ + "Header": { + "GenerationSoftware": { + "Vendor": "KiCad", + "Application": "Pcbnew", + "Version": "10.0.7-10.0.7~ubuntu24.04.1" + }, + "CreationDate": "2026-11-05T16:34:32+03:00" + }, + "GeneralSpecs": { + "ProjectId": { + "Name": "rtd_afe", + "GUID": "7274645f-6166-4652-9e6b-696361645f70", + "Revision": "rev?" + }, + "Size": { + "X": 40.1, + "Y": 44.31 + }, + "LayerNumber": 4, + "BoardThickness": 1.6, + "Finish": "None" + }, + "DesignRules": [ + { + "Layers": "Outer", + "PadToPad": 0.127, + "PadToTrack": 0.127, + "TrackToTrack": 0.127, + "MinLineWidth": 0.127, + "TrackToRegion": 0.15, + "RegionToRegion": 0.15 + }, + { + "Layers": "Inner", + "PadToPad": 0.0, + "PadToTrack": 0.0, + "TrackToTrack": 0.127, + "TrackToRegion": 0.15, + "RegionToRegion": 0.15 + } + ], + "FilesAttributes": [ + { + "Path": "rtd_afe-F_Cu.gbr", + "FileFunction": "Copper,L1,Top", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-In1_Cu.gbr", + "FileFunction": "Copper,L2,Inr", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-In2_Cu.gbr", + "FileFunction": "Copper,L3,Inr", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-B_Cu.gbr", + "FileFunction": "Copper,L4,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-F_Adhesive.gbr", + "FileFunction": "Glue,Top", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-B_Adhesive.gbr", + "FileFunction": "Glue,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-F_Paste.gbr", + "FileFunction": "SolderPaste,Top", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-B_Paste.gbr", + "FileFunction": "SolderPaste,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-F_Silkscreen.gbr", + "FileFunction": "Legend,Top", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-B_Silkscreen.gbr", + "FileFunction": "Legend,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-F_Mask.gbr", + "FileFunction": "SolderMask,Top", + "FilePolarity": "Negative" + }, + { + "Path": "rtd_afe-B_Mask.gbr", + "FileFunction": "SolderMask,Bot", + "FilePolarity": "Negative" + }, + { + "Path": "rtd_afe-User_Drawings.gbr", + "FileFunction": "Other,User", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-User_Comments.gbr", + "FileFunction": "Other,User", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-User_Eco1.gbr", + "FileFunction": "Other,User", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-User_Eco2.gbr", + "FileFunction": "Other,User", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-Edge_Cuts.gbr", + "FileFunction": "Profile", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-F_Fab.gbr", + "FileFunction": "AssemblyDrawing,Top", + "FilePolarity": "Positive" + }, + { + "Path": "rtd_afe-B_Fab.gbr", + "FileFunction": "AssemblyDrawing,Bot", + "FilePolarity": "Positive" + } + ], + "MaterialStackup": [ + { + "Type": "Legend", + "Name": "Top Silk Screen" + }, + { + "Type": "SolderPaste", + "Name": "Top Solder Paste" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Top Solder Mask" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "F.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "F.Cu/In1.Cu", + "Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "In1.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "In1.Cu/In2.Cu", + "Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "In2.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "In2.Cu/B.Cu", + "Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "B.Cu" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Bottom Solder Mask" + }, + { + "Type": "SolderPaste", + "Name": "Bottom Solder Paste" + }, + { + "Type": "Legend", + "Name": "Bottom Silk Screen" + } + ] +} diff --git a/qualification/class-b/rtd-afe/kicad/pnp.csv b/qualification/class-b/rtd-afe/kicad/pnp.csv new file mode 100644 index 000000000..c9f430a47 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/pnp.csv @@ -0,0 +1,54 @@ +Designator,Val,Package,Mid X,Mid Y,Rotation,Layer +"C_AV1","330nF","Capacitor_SMD:C_0603_1608Metric",11.000,17.600,0,"Top" +"C_AV2","10uF","Capacitor_SMD:C_0805_2012Metric",6.500,17.600,0,"Top" +"C_AVF","4.7uF","Capacitor_SMD:C_0603_1608Metric",37.500,27.000,0,"Top" +"C_CM1","10nF","Capacitor_SMD:C_0603_1608Metric",15.500,32.100,0,"Top" +"C_CM2","10nF","Capacitor_SMD:C_0603_1608Metric",8.500,32.100,0,"Top" +"C_D","100nF","Capacitor_SMD:C_0603_1608Metric",12.000,32.100,0,"Top" +"C_DV","100nF","Capacitor_SMD:C_0603_1608Metric",16.500,23.100,90,"Top" +"C_DV1","100nF","Capacitor_SMD:C_0603_1608Metric",19.500,31.000,0,"Top" +"C_DV2","100nF","Capacitor_SMD:C_0603_1608Metric",34.000,24.000,0,"Top" +"C_DVB","4.7uF","Capacitor_SMD:C_0805_2012Metric",37.000,20.500,0,"Top" +"C_F","10nF","Capacitor_SMD:C_0603_1608Metric",16.000,35.600,0,"Top" +"C_FL","100nF","Capacitor_SMD:C_0603_1608Metric",23.500,15.000,0,"Top" +"C_IO","100nF","Capacitor_SMD:C_0603_1608Metric",17.000,27.100,270,"Top" +"C_IO1","100nF","Capacitor_SMD:C_0603_1608Metric",19.500,25.000,0,"Top" +"C_IO2","100nF","Capacitor_SMD:C_0603_1608Metric",19.500,28.000,0,"Top" +"C_IO3","100nF","Capacitor_SMD:C_0603_1608Metric",34.000,30.000,0,"Top" +"C_IO4","100nF","Capacitor_SMD:C_0603_1608Metric",37.500,30.000,0,"Top" +"C_L1","2.2uF","Capacitor_SMD:C_0603_1608Metric",35.500,14.000,90,"Top" +"C_L2","2.2uF","Capacitor_SMD:C_0603_1608Metric",39.000,14.000,90,"Top" +"C_RI","1uF","Capacitor_SMD:C_0603_1608Metric",4.800,11.300,0,"Top" +"C_RO","1uF","Capacitor_SMD:C_0603_1608Metric",16.000,13.600,0,"Top" +"C_RV","1uF","Capacitor_SMD:C_0603_1608Metric",7.000,24.800,90,"Top" +"C_VI","4.7uF","Capacitor_SMD:C_0603_1608Metric",37.500,24.000,0,"Top" +"C_X1","33pF","Capacitor_SMD:C_0603_1608Metric",23.500,38.300,0,"Top" +"C_X2","33pF","Capacitor_SMD:C_0603_1608Metric",32.000,38.300,0,"Top" +"D1","ESD","Diode_SMD:D_SOD-323",25.000,12.000,0,"Top" +"D2","ESD","Diode_SMD:D_SOD-323",28.500,12.000,0,"Top" +"H1","mounting_hole","MountingHole:MountingHole_2.7mm_M2.5",6.000,3.500,0,"Top" +"H2","mounting_hole","MountingHole:MountingHole_2.7mm_M2.5",39.000,3.500,0,"Top" +"H3","mounting_hole","MountingHole:MountingHole_2.7mm_M2.5",6.000,40.700,0,"Top" +"H4","mounting_hole","MountingHole:MountingHole_2.7mm_M2.5",39.000,40.700,0,"Top" +"J1","TYPE-C-31-M-12","Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12",22.550,6.000,180,"Top" +"J2","PT100","Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical",14.800,41.700,270,"Top" +"J3","SWD","Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical",28.000,41.700,90,"Top" +"L1","3.3uH","Inductor_SMD:L_0805_2012Metric",34.400,21.000,90,"Top" +"L2","600R@100MHz","Inductor_SMD:L_0603_1608Metric",13.000,6.500,180,"Top" +"R_AV","33","Resistor_SMD:R_0603_1608Metric",34.000,27.000,0,"Top" +"R_BIAS","1k","Resistor_SMD:R_0603_1608Metric",4.500,28.100,90,"Top" +"R_CC1","5.1k","Resistor_SMD:R_0603_1608Metric",35.000,7.500,0,"Top" +"R_CC2","5.1k","Resistor_SMD:R_0603_1608Metric",21.000,11.500,0,"Top" +"R_DN","27","Resistor_SMD:R_0603_1608Metric",28.500,15.000,90,"Top" +"R_DP","27","Resistor_SMD:R_0603_1608Metric",26.000,14.500,90,"Top" +"R_RST","10k","Resistor_SMD:R_0603_1608Metric",19.800,14.000,90,"Top" +"R_RUN","10k","Resistor_SMD:R_0603_1608Metric",19.500,34.500,0,"Top" +"R_S1","1k","Resistor_SMD:R_0603_1608Metric",12.500,35.600,90,"Top" +"R_S2","1k","Resistor_SMD:R_0603_1608Metric",9.500,35.600,90,"Top" +"R_X","1k","Resistor_SMD:R_0603_1608Metric",24.000,35.300,90,"Top" +"U1","ADS124S08IRHBR","Package_DFN_QFN:Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm",12.000,25.100,90,"Top" +"U2","RP2350A","Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm",28.000,29.600,0,"Top" +"U3","REF5025AIDR","Package_SO:SOIC-8_3.9x4.9mm_P1.27mm",10.500,11.600,0,"Top" +"U4","W25Q128JVSIQ","Package_SO:SOIC-8_5.3x5.3mm_P1.27mm",22.000,19.000,0,"Top" +"U5","LDO","Package_TO_SOT_SMD:SOT-23-5",36.500,10.500,0,"Top" +"Y1","12MHz","Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm",28.000,36.300,0,"Top" diff --git a/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_dru b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_dru new file mode 100644 index 000000000..c6031cb5a --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_dru @@ -0,0 +1,8 @@ +(version 1) +(rule "manufacturer copper to board edge" + (constraint edge_clearance (min 0.3mm))) +(rule "manufacturer copper to NPTH hole" + (constraint edge_clearance (min 0.2mm)) + (condition "A.Pad_Type == 'NPTH, mechanical'")) +(rule "manufacturer copper to hole" + (constraint hole_clearance (min 0.2mm))) diff --git a/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_pcb b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_pcb new file mode 100644 index 000000000..192b78d0a --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_pcb @@ -0,0 +1,18058 @@ +(kicad_pcb + (version 20260206) + (generator "synth-eda") + (generator_version "10.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (4 "In1.Cu" power) + (6 "In2.Cu" power) + (2 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + ) + (setup + (last_trace_width 0.127) + (trace_clearance 0.127) + (pad_to_mask_clearance 0) + (solder_mask_min_width 0) + (allow_soldermask_bridges_in_footprints yes) + (trace_min 0.127) + (clearance_min 0.127) + (via_min_size 0.46) + (via_min_drill 0.2) + ) + (net 0 "") + (net 1 "RTD_FP") + (net 2 "RTD_SP") + (net 3 "AIN1") + (net 4 "RTD_SN") + (net 5 "AIN2") + (net 6 "RTD_FN") + (net 7 "REFOUT") + (net 8 "SPI_MOSI") + (net 9 "SPI_CS") + (net 10 "SPI_SCK") + (net 11 "SPI_MISO") + (net 12 "ADC_DRDY") + (net 13 "ADC_START") + (net 14 "ADC_RESET_N") + (net 15 "XIN") + (net 16 "XOUT") + (net 17 "XOUT_R") + (net 18 "RUN") + (net 19 "SWCLK") + (net 20 "SWDIO") + (net 21 "QSPI_SS") + (net 22 "QSPI_SCLK") + (net 23 "QSPI_SD0") + (net 24 "QSPI_SD1") + (net 25 "QSPI_SD2") + (net 26 "QSPI_SD3") + (net 27 "CC1") + (net 28 "CC2") + (net 29 "USB_DP_C") + (net 30 "USB_DP") + (net 31 "USB_DN_C") + (net 32 "USB_DN") + (net 33 "VBUS") + (net 34 "+3V3") + (net 35 "+3V3A") + (net 36 "+3V3_RP_A") + (net 37 "DVDD_1V1") + (net 38 "VREG_LX") + (net 39 "VREF") + (net 40 "GND") + (net_class + "Default" + "Default net class" + (clearance 0.127) + (trace_width 0.127) + (via_dia 0.6) + (via_drill 0.3) + (add_net "RTD_FP") + (add_net "RTD_SP") + (add_net "AIN1") + (add_net "RTD_SN") + (add_net "AIN2") + (add_net "RTD_FN") + (add_net "REFOUT") + (add_net "SPI_MOSI") + (add_net "SPI_CS") + (add_net "SPI_SCK") + (add_net "SPI_MISO") + (add_net "ADC_DRDY") + (add_net "ADC_START") + (add_net "ADC_RESET_N") + (add_net "XIN") + (add_net "XOUT") + (add_net "XOUT_R") + (add_net "RUN") + (add_net "SWCLK") + (add_net "SWDIO") + (add_net "QSPI_SS") + (add_net "QSPI_SCLK") + (add_net "QSPI_SD0") + (add_net "QSPI_SD1") + (add_net "QSPI_SD2") + (add_net "QSPI_SD3") + (add_net "CC1") + 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"e1670542-9021-5acb-9cdd-803cd70d7955") + ) + (wire + (pts + (xy 386.08 91.44) + (xy 391.16 91.44) + ) + (stroke + (width 0) + (type default) + (color 67 191 102 1) + ) + (uuid "fadc5a73-7670-538c-8a67-5e01424566a5") + ) + (global_label + "USB_DP_C" + (shape output) + (at 391.16 91.44 0) + (effects + (font + (size 1.15 1.15) + (color 67 191 102 1) + ) + (justify left) + ) + (uuid "646bc841-eb23-5ba7-8760-e9362b1f9972") + ) + (wire + (pts + (xy 386.08 93.98) + (xy 391.16 93.98) + ) + (stroke + (width 0) + (type default) + (color 67 191 102 1) + ) + (uuid "5dad39c7-588b-5089-aa49-27213a42cddd") + ) + (global_label + "USB_DP_C" + (shape output) + (at 391.16 93.98 0) + (effects + (font + (size 1.15 1.15) + (color 67 191 102 1) + ) + (justify left) + ) + (uuid "4a2f1f5e-50cc-515a-bf32-b8584d08b34d") + ) + (wire + (pts + (xy 346.71 91.44) + (xy 351.79 91.44) + ) + (stroke + (width 0) + (type default) + (color 67 191 102 1) + ) + (uuid "93b04477-40f2-52a7-a921-50ecd5cf8d10") + ) + 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190.5 189.23) + ) + (stroke + (width 0) + (type default) + ) + (uuid "14094849-1b4a-54a5-9ca0-c5d3bd08f608") + ) + (wire + (pts + (xy 190.5 189.23) + (xy 195.58 189.23) + ) + (stroke + (width 0) + (type default) + ) + (uuid "149bdbba-c5cf-5cce-973c-c6068918846b") + ) + (global_label + "AIN2" + (shape output) + (at 195.58 189.23 0) + (effects + (font + (size 1.15 1.15) + ) + (justify left) + ) + (uuid "b40dcd12-56cf-5895-854f-21fbbe605afd") + ) + (label + "RTD_SP" + (at 50.165 195.58 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "66d6bd21-3341-5b49-b9f2-3c360bdfe66c") + ) + (label + "RTD_SN" + (at 50.165 198.12 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "e926d257-476e-538b-b92b-5bdbe93355f8") + ) + (label + "XOUT" + (at 52.07 307.34 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "aa51e5ee-ed46-57ea-8599-153edb168dc4") + ) + (label + "RUN" + (at 41.91 300.355 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "cf2665f7-b82c-516e-9617-521befacea56") + ) + (label + "SWCLK" + (at 48.895 332.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b2236a6b-097b-55f5-b770-7199f8e27493") + ) + (label + "SWDIO" + (at 48.26 334.645 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "6e2533d0-513b-5472-bf59-09335cd0b41b") + ) + (label + "CC1" + (at 401.32 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "29e59a5d-ac94-5dfa-b838-06af47ef3528") + ) + (label + "CC2" + (at 410.21 93.345 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "cb0e3cf1-ea14-5332-8dd9-5963db05310d") + ) + (text + "MOUNTING" + (at 159.9516 142.81 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "10369338-4823-5f4f-aa85-d2d0f7bdb514") + ) + (text + "RTD INPUT" + (at 190.0169 174.56 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "c9c147b0-1ccc-59c8-8f91-bcfc21ef1ff4") + ) + (text + "ADC" + (at 165.9841 17.08 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "10d7ef1d-8946-5d5e-9e1e-26151cdb30b8") + ) + (text + "REFERENCE" + (at 475.1439 173.29 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "898f4b4e-92ef-5b43-b413-178a39a8470c") + ) + (text + "ANALOG SUPPLY" + (at 439.0461 17.08 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "36e2dc0d-3ba1-5b56-9120-3771e9130a6d") + ) + (text + "MCU" + (at 293.3805 244.41 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "3794a8ad-c44d-57b4-ab45-1f87e33fdc3e") + ) + (text + "USB-C READOUT" + (at 439.0461 60.26 0) + (effects + (font + (size 2.54 2.54) + bold + ) + (justify left bottom) + ) + (uuid "4f3b5b69-e3d8-5c39-a7dd-5552a98efa08") + ) + (text + "" + (at 18.79 222.14 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "170b2628-c65f-5738-998f-2f06426d6089") + ) + (text + "J2 pin 1 F+, pin 2 S+, pin 3 S-, pin 4 F-. PT100 4-wire; force pair carries the 1 mA IDAC current, sense pair reads the RTD." + (at 18.79 226.14 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "e4d963bb-f779-50a3-b493-855106485d8c") + ) + (text + "R_S1/R_S2 1k with C_D 100nF across the pair and C_CM1/C_CM2 10nF to GND: differential corner 1/(2pi*2k*110nF) about 720 Hz, common-mode corner about 16 kHz." + (at 18.79 228.68 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "15d80c8a-ea7b-5ece-827e-39873b251657") + ) + (text + "C_D is 10x each C_CM so a capacitor mismatch turns into little differential error (TI input filter rule). C0G so the filter does not move the reading." + (at 18.79 231.22 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "5b119c5d-aa35-5938-9be3-87abf50f378e") + ) + (text + "C_F 10nF decouples the force node F+ (IDAC output). R_BIAS 1k returns the IDAC current to GND and lifts the RTD common-mode to about 1.1 V." + (at 18.79 233.76 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "2dea9e63-7c37-5f2e-9d6f-e89452286805") + ) + (text + "" + (at 17.87 123.08 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "1e4136da-eadb-5781-907d-5aab60ed50c0") + ) + (text + "AVDD from +3V3A (ferrite-filtered), DVDD and IOVDD from +3V3. AVSS, AVSS_SW, REFN0, REFCOM, the exposed pad and DGND (pin 14) are on GND: the ADC returns its own digital supply current to the same plane. CLK is tied to that ground to use the internal oscillator." + (at 17.87 127.08 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "9f055ceb-4e6d-52ac-a4f0-ce5c1f03dc33") + ) + (text + "REFOUT has 1 uF to GND for the unused internal reference. RESET has a 10k pull-up to +3V3 and is also driven by the MCU." + (at 17.87 129.62 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "92fd1443-400e-55f7-8a2f-06910b66d25d") + ) + (text + "AINCOM, AIN3..AIN11, REFP1/REFN1, GPIOs and pin 25 are left open." + (at 17.87 132.16 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "a1b9bca0-0447-50da-b1df-5b6e47082366") + ) + (text + "" + (at 396.94 224.68 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "0de13d2c-c503-5df8-9cd5-e66c92ca9234") + ) + (text + "REF5025 2.5 V, VIN from +3V3A, VOUT straight to REFP0 with 1 uF at the reference pin, GND to GND. TEMP, TRIM/NR, DNC and NC pins are open." + (at 396.94 228.68 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "0a9028ca-8118-5145-8eb9-33c9747fff4d") + ) + (text + "" + (at 332.73 44.91 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "51658b92-cd79-5002-ab0c-0feca0477cc9") + ) + (text + "L2 filters +3V3 into the +3V3A analog rail for the ADC and the reference. Its DC resistance and the ADC/REF supply current are not computed here." + (at 332.73 48.91 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "a2f9716f-a888-507d-9a27-85b2919be4be") + ) + (text + "" + (at 17.28 358.03 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "4b6a2cbf-d737-5b06-991b-c0de7e3f999b") + ) + (text + "RP2350 runs from its on-chip regulator: VREG_VIN on +3V3, VREG_LX through L1 3.3uH to the 1.1 V DVDD net, VREG_FB on that net." + (at 17.28 362.03 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "b356831f-fcf2-57e2-b0ff-75d89d689d7c") + ) + (text + "VREG_AVDD and ADC_AVDD are fed from +3V3 through R_AV 33R and C_AVF 4.7uF." + (at 17.28 364.57 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "55159f9f-eba5-516b-a9b7-2980949982b8") + ) + (text + "U4 W25Q128 on the QSPI pins is the boot flash. Y1 ECS-120-20-33-TR 12 MHz, CL 20 pF: 2x 33 pF load caps (33/2 + about 3 pF stray = 19.5 pF), R_X 1k on XOUT." + (at 17.28 367.11 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "c2690454-b940-5c6e-8795-1bb87707f7e4") + ) + (text + "J3 SWD: pin 1 SWCLK, pin 2 SWDIO, pin 3 GND. RUN has a 10k pull-up to +3V3." + (at 17.28 369.65 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "17b5602d-d445-53b2-80f5-ab5b7c50483b") + ) + (text + "" + (at 333.51 152.29 0) + (effects + (font + (size 2 2) + ) + (justify left bottom) + ) + (uuid "cc4f1a5a-9e91-5084-8574-6e4d4ecdd04d") + ) + (text + "USB 2.0 device port, VBUS 5 V in. CC1/CC2 5.1k so a host sources 5 V. 27R series on D+/D-, ESD diodes at the connector." + (at 333.51 156.29 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "ec94afbb-6387-52ec-879c-58a982086cbc") + ) + (text + "VBUS feeds U5 LP5907-3.3 (250 mA) which makes the +3V3 digital rail. No VBUS fuse or TVS: see QUALIFICATION.md." + (at 333.51 158.83 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "6d1b74f6-d36f-5a86-a343-ed85347d6843") + ) + (text + "The RTD board is a bus-powered USB device: it draws a few tens of mA. No USB-C PD." + (at 333.51 161.37 0) + (effects + (font + (size 1 1) + ) + (justify left bottom) + ) + (uuid "edb07e24-032a-5fb6-a7cc-ff08eb63eeba") + ) + (polyline + (pts + (xy 327.2072 138.4688) + (xy 327.2072 168.8123) + ) + (stroke + (width 0.254) + (type solid) + (color 49 66 150 1) + ) + (uuid "91eede7a-3b77-5da6-8903-4d18c4cd3335") + ) + (polyline + (pts + (xy 12 168.8123) + (xy 327.2072 168.8123) + ) + (stroke + (width 0.254) + (type solid) + (color 49 66 150 1) + ) + (uuid "5a89c1af-832d-5aa2-870e-0e282b2ae99b") + ) + (polyline + (pts + (xy 389.7508 169.0663) + (xy 389.7508 239.3724) + ) + (stroke + (width 0.254) + (type solid) + (color 49 66 150 1) + ) + (uuid "c8136ea7-170a-57bf-9b78-49717986a13b") + ) + (polyline + (pts + (xy 12 239.3724) + (xy 389.7508 239.3724) + ) + (stroke + (width 0.254) + (type solid) + (color 49 66 150 1) + ) + (uuid "7ac449ff-207c-5191-8838-24078912a4c6") + ) + (polyline + (pts + (xy 327.2072 12) + (xy 327.2072 138.2148) + ) + (stroke + (width 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"power:PWR_FLAG") + (at 406.4 200.66 0) + (unit 1) + (in_bom no) + (on_board no) + (uuid "fb9ac324-82ae-52aa-9899-36898f5a01ac") + (property + "Reference" + "#FLG4924" + (at 406.4 200.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property + "Value" + "PWR_FLAG" + (at 406.4 200.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + ) +) diff --git a/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_sym b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_sym new file mode 100644 index 000000000..ccecce573 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_sym @@ -0,0 +1,6185 @@ +(kicad_symbol_lib + (version 20251024) + (generator "synth-eda") + (generator_version "10.0") + (symbol + "synth:ads124s08" + (pin_names + (offset 0.508) + ) + (pin_numbers + (hide yes) + ) + (in_bom yes) + (on_board yes) + (property + "Reference" + "U" + (at 0 34.29 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property + "Value" + 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1.27 1.27) + ) + ) + ) + ) + ) + ) + (symbol + "synth:VREG_LX" + (power global) + (pin_numbers + (hide yes) + ) + (pin_names + (offset 0) + (hide yes) + ) + (in_bom no) + (on_board no) + (property + "Reference" + "#PWR" + (at 0 -6.35 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property + "Value" + "VREG_LX" + (at 0 3.81 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property + "Footprint" + "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property + "Datasheet" + "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (symbol + "VREG_LX_0_1" + (polyline + (pts + (xy -0.762 1.27) + (xy 0 2.54) + (xy 0.762 1.27) + (xy 0 0) + (xy 0 2.54) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) + (symbol + "VREG_LX_1_1" + (pin + power_in + line + (at 0 0 90) + (length 0) + (name + "" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number + "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) +) diff --git a/qualification/class-b/rtd-afe/kicad/sym-lib-table b/qualification/class-b/rtd-afe/kicad/sym-lib-table new file mode 100644 index 000000000..5c06a6a12 --- /dev/null +++ b/qualification/class-b/rtd-afe/kicad/sym-lib-table @@ -0,0 +1,10 @@ +(sym_lib_table + (version 7) + (lib + (name "synth") + (uri "${KIPRJMOD}/rtd_afe.kicad_sym") + (type "KiCad") + (options "") + (descr "Synth synthesized symbol library") + ) +) diff --git a/qualification/class-b/rtd-afe/reports/release.json b/qualification/class-b/rtd-afe/reports/release.json new file mode 100644 index 000000000..f76b8bb55 --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/release.json @@ -0,0 +1,187 @@ +{ + "schema_version": "synth.release.v1", + "tool_version": "synth-cli 0.1.1", + "input": "qualification/class-b/rtd-afe/rtd_afe.synth", + "source_revision": "01a77d545c2ebab2d85a31b2ceff24ebcd1feacf", + "fab_requested": true, + "production_status": "production", + "release_ready": true, + "gate_scope": "production_status and release_ready cover only Synth's routing and export gates: override flags, route validation and signal integrity. They are not a fabrication approval, a qualification result or a component review.", + "reviewer_state": [ + { + "part_id": "ads124s08", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-10-27", + "reviewed": true + }, + { + "part_id": "c_generic_0603", + "reviewed_by": "JeffMboya", + "reviewed_at": "2026-11-01", + "reviewed": true + }, + { + "part_id": "c_generic_0805", + "reviewed_by": "JeffMboya", + "reviewed_at": "2026-11-01", + "reviewed": true + }, + { + "part_id": "ecs_120_20_33_tr", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "esd_usb", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "ferrite_bead_0603", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "header_1x3", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "header_1x4", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "l_generic_0805", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "lp5907_3v3", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-10-27", + "reviewed": true + }, + { + "part_id": "mounting_hole_m2_5_clearance", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "r_generic_0603", + "reviewed_by": "JeffMboya", + "reviewed_at": "2026-11-01", + "reviewed": true + }, + { + "part_id": "ref5025", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-10-27", + "reviewed": true + }, + { + "part_id": "rp2350", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "usb_c_receptacle", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + }, + { + "part_id": "w25q128_flash_208mil", + "reviewed_by": "Steve Munene", + "reviewed_at": "2026-11-05", + "reviewed": true + } + ], + "synthetic_symbols": [ + "ads124s08" + ], + "routing": { + "engine": "freerouting", + "engine_version": "freerouting-2.4.1.jar", + "state": "routed", + "input_hash": "abc91eecd10c5bd9b576dd8cc22d2cde488556172cdacb335d88c5cae58f2085", + "run_record": "qualification/class-b/rtd-afe/kicad/rtd_afe.routing.json", + "fabrication_notes": [ + "via at (16.138, 22.835) mm C_DV.2: via-in-pad, order with filled and capped vias" + ] + }, + "signal_integrity": { + "blocking": 0, + "warnings": 12, + "findings": [ + { + "code": "W-SYNTH-DRC-013", + "message": "nets 10 and 11 run parallel for 3.5 mm on B.Cu 0.203 mm apart, within a dielectric height; risk of crosstalk", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 7 changes layers at (23.41, 28.63) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 9 changes layers at (22.69, 27.91) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 10 changes layers at (23.41, 27.08) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 11 changes layers at (15.49, 24.64) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 11 changes layers at (23.08, 30.50) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 12 changes layers at (14.32, 29.00) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 12 changes layers at (23.47, 29.71) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 13 changes layers at (25.54, 29.05) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 26 changes layers at (23.76, 7.95) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 31 changes layers at (27.96, 27.12) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + }, + { + "code": "W-SYNTH-DRC-016", + "message": "net 36 changes layers at (25.86, 30.42) mm with no ground return via within 0.80 mm, so the return current has to jump reference planes", + "blocking": false + } + ] + } +} diff --git a/qualification/class-b/rtd-afe/reports/rtd_afe.connectivity.json b/qualification/class-b/rtd-afe/reports/rtd_afe.connectivity.json new file mode 100644 index 000000000..f973e7d29 --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/rtd_afe.connectivity.json @@ -0,0 +1,43 @@ +{ + "fabrication_ready": true, + "topology": { + "missing_footprints": [], + "extra_footprints": [], + "missing_nets": [], + "missing_layers": [], + "missing_pads": [], + "renet_pads": [], + "outline_present": true + }, + "connectivity": { + "connected_nets": 40, + "open_nets": 0, + "open": [], + "unconnected_pads": [], + "via_in_pad": [ + "via at (16.138, 22.835) mm C_DV.2" + ], + "undersized_vias": [], + "undersized_tracks": [] + }, + "kicad_drc": { + "errors": 0, + "unconnected": 0, + "warnings": 48 + }, + "blocking_reasons": [], + "unavailable_checks": [], + "advisories": [ + "net SPI_MOSI changes layers at (23.41, 28.63) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net SPI_SCK changes layers at (22.69, 27.91) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net SPI_MISO changes layers at (23.41, 27.08) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_DRDY changes layers at (15.49, 24.64) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_DRDY changes layers at (23.08, 30.50) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_START changes layers at (14.32, 29.00) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_START changes layers at (23.47, 29.71) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_RESET_N changes layers at (25.54, 29.05) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net CC1 changes layers at (23.76, 7.95) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net USB_DN changes layers at (27.96, 27.12) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net DVDD_1V1 changes layers at (25.86, 30.42) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review" + ] +} \ No newline at end of file diff --git a/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-drc.json b/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-drc.json new file mode 100644 index 000000000..f26f39f91 --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-drc.json @@ -0,0 +1,766 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-11-05T16:34:39", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.7", + "schematic_parity": [], + "source": "rtd_afe.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_S1", + "pos": { + "x": 12.5, + "y": 35.6 + }, + "uuid": "41ef15f2-04f3-57ed-9a40-b60fbd4eea46" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_S2", + "pos": { + "x": 9.5, + "y": 35.6 + }, + "uuid": "8144917a-04c2-59bf-9076-7e4e111b02dd" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_D", + "pos": { + "x": 12.0, + "y": 32.1 + }, + "uuid": "b8f1c204-26ac-5dde-87e6-315db45af236" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_CM1", + "pos": { + "x": 15.5, + "y": 32.1 + }, + "uuid": "4fc5ede3-577a-5497-9fda-eafce66495de" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_CM2", + "pos": { + "x": 8.5, + "y": 32.1 + }, + "uuid": "07af1f0e-d5c4-55ef-9ed2-9fe272f04a6f" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_F", + "pos": { + "x": 16.0, + "y": 35.6 + }, + "uuid": "35a98a68-18f7-5ee9-b132-4d601fc3dee7" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_BIAS", + "pos": { + "x": 4.5, + "y": 28.1 + }, + "uuid": "fc2ed792-d82f-5523-b83b-8bff226017ee" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm' does not match copy in library 'Package_DFN_QFN'", + "items": [ + { + "description": "Footprint U1", + "pos": { + "x": 12.0, + "y": 25.1 + }, + "uuid": "e06f8919-8ac3-5638-8fc4-433510ccd7c0" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_AV1", + "pos": { + "x": 11.0, + "y": 17.6 + }, + "uuid": "21c2f888-b720-557f-9646-8e4df39950f5" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_AV2", + "pos": { + "x": 6.5, + "y": 17.6 + }, + "uuid": "a8ca1fa4-4a33-50ae-8c77-ec09357a0c9f" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_DV", + "pos": { + "x": 16.5, + "y": 23.1 + }, + "uuid": "ba8e38a5-09b1-585e-a131-3f7ee9e78ff5" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_IO", + "pos": { + "x": 17.0, + "y": 27.1 + }, + "uuid": "d52cfa7a-90f8-5818-af87-8cc38360d348" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_RO", + "pos": { + "x": 16.0, + "y": 13.6 + }, + "uuid": "14764b8c-e6bb-56d4-9935-0c876fa1eb54" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_RST", + "pos": { + "x": 19.8, + "y": 14.0 + }, + "uuid": "6c7e3d71-ede2-50e3-b072-c8faa5142ab6" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'SOIC-8_3.9x4.9mm_P1.27mm' does not match copy in library 'Package_SO'", + "items": [ + { + "description": "Footprint U3", + "pos": { + "x": 10.5, + "y": 11.6 + }, + "uuid": "00bfe2a5-b697-52fc-9141-9caf12f716d0" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_RI", + "pos": { + "x": 4.8, + "y": 11.3 + }, + "uuid": "4bc9451c-1de8-5519-8dcc-edf84918b3c7" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_RV", + "pos": { + "x": 7.0, + "y": 24.8 + }, + "uuid": "aa0c07d8-2b9d-5ca3-abcd-a19b546083e0" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'L_0603_1608Metric' does not match copy in library 'Inductor_SMD'", + "items": [ + { + "description": "Footprint L2", + "pos": { + "x": 13.0, + "y": 6.5 + }, + "uuid": "ece02bcc-bd16-520a-8603-0dfee20a6236" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm' does not match copy in library 'Package_DFN_QFN'", + "items": [ + { + "description": "Footprint U2", + "pos": { + "x": 28.0, + "y": 29.6 + }, + "uuid": "bca871c8-1823-5dd4-8b3a-ebcda6cfd573" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'SOIC-8_5.3x5.3mm_P1.27mm' does not match copy in library 'Package_SO'", + "items": [ + { + "description": "Footprint U4", + "pos": { + "x": 22.0, + "y": 19.0 + }, + "uuid": "e375a184-5f94-52f4-b57c-036c4973cdeb" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'Crystal_SMD_3225-4Pin_3.2x2.5mm' does not match copy in library 'Crystal'", + "items": [ + { + "description": "Footprint Y1", + "pos": { + "x": 28.0, + "y": 36.3 + }, + "uuid": "bf531b31-0050-55f2-a588-16268dc3b182" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_X1", + "pos": { + "x": 23.5, + "y": 38.3 + }, + "uuid": "f2460675-fb67-53d8-99c0-49caf9ec8564" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_X2", + "pos": { + "x": 32.0, + "y": 38.3 + }, + "uuid": "fb7187b3-73f1-5fcb-8381-76b3a8f914dc" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_X", + "pos": { + "x": 24.0, + "y": 35.3 + }, + "uuid": "94ce8c8b-9259-5c21-af96-ff965cb3deb7" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_RUN", + "pos": { + "x": 19.5, + "y": 34.5 + }, + "uuid": "7b0a9a7e-76bc-5dc3-ade8-cd6b64adea23" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'L_0805_2012Metric' does not match copy in library 'Inductor_SMD'", + "items": [ + { + "description": "Footprint L1", + "pos": { + "x": 34.4, + "y": 21.0 + }, + "uuid": "5bece7b0-f16d-58d4-afeb-910798d32180" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_AV", + "pos": { + "x": 34.0, + "y": 27.0 + }, + "uuid": "d32176bd-a45d-58bd-b0fd-87c902794734" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_AVF", + "pos": { + "x": 37.5, + "y": 27.0 + }, + "uuid": "14320b41-5daa-5d08-aec5-b8c874e51260" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_IO1", + "pos": { + "x": 19.5, + "y": 25.0 + }, + "uuid": "94821a87-b778-554b-a896-a50a47b5ec94" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_IO2", + "pos": { + "x": 19.5, + "y": 28.0 + }, + "uuid": "21a11bf6-148b-5902-9030-8568be508749" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_IO3", + "pos": { + "x": 34.0, + "y": 30.0 + }, + "uuid": "72e3589b-3658-505d-9eb7-198e729ac8fe" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_IO4", + "pos": { + "x": 37.5, + "y": 30.0 + }, + "uuid": "5eeb595a-8134-598c-ba9e-3d8465aef0ed" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_DV1", + "pos": { + "x": 19.5, + "y": 31.0 + }, + "uuid": "382ff55a-e969-5e5b-aa06-46fdaf1a7489" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_DV2", + "pos": { + "x": 34.0, + "y": 24.0 + }, + "uuid": "21f4a002-e583-51fe-b6ff-9512e718ec6d" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_DVB", + "pos": { + "x": 37.0, + "y": 20.5 + }, + "uuid": "d3309e71-15db-5226-afc6-8674a645baed" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_VI", + "pos": { + "x": 37.5, + "y": 24.0 + }, + "uuid": "a50400be-6800-5dc1-836d-2d765fc7c1f1" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_FL", + "pos": { + "x": 23.5, + "y": 15.0 + }, + "uuid": "162045ad-e357-5cc1-8e26-5d7b7d22a939" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'USB_C_Receptacle_HRO_TYPE-C-31-M-12' does not match copy in library 'Connector_USB'", + "items": [ + { + "description": "Footprint J1", + "pos": { + "x": 22.55, + "y": 5.44 + }, + "uuid": "b63f1ae9-9907-5df9-988b-0cf6e664ecdd" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_CC1", + "pos": { + "x": 35.0, + "y": 7.5 + }, + "uuid": "56b6357a-b4d9-504a-96d2-24a5d1a7b268" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_CC2", + "pos": { + "x": 21.0, + "y": 11.5 + }, + "uuid": "98bba653-c553-56f4-b180-6ed179caf476" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_DP", + "pos": { + "x": 26.0, + "y": 14.5 + }, + "uuid": "74d0fa39-f23d-5819-bdd8-496d1ba96d69" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD'", + "items": [ + { + "description": "Footprint R_DN", + "pos": { + "x": 28.5, + "y": 15.0 + }, + "uuid": "a47d36f5-ebc0-5412-9a98-98b3b3a8977e" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD'", + "items": [ + { + "description": "Footprint D1", + "pos": { + "x": 25.0, + "y": 12.0 + }, + "uuid": "d3baa754-e467-5e39-843e-02b6fdc78814" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD'", + "items": [ + { + "description": "Footprint D2", + "pos": { + "x": 28.5, + "y": 12.0 + }, + "uuid": "b0c52e78-5218-56a5-b60b-319003c32fb9" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'SOT-23-5' does not match copy in library 'Package_TO_SOT_SMD'", + "items": [ + { + "description": "Footprint U5", + "pos": { + "x": 36.5, + "y": 10.5 + }, + "uuid": "7950201f-602c-5022-8f59-f88da93d1def" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_L1", + "pos": { + "x": 35.5, + "y": 14.0 + }, + "uuid": "7c8e0091-1f47-5b5a-8546-d936385b529a" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD'", + "items": [ + { + "description": "Footprint C_L2", + "pos": { + "x": 39.0, + "y": 14.0 + }, + "uuid": "da96b2d7-f4df-5b16-af01-f87b25af011e" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Silkscreen clipped by board edge", + "items": [ + { + "description": "Segment on Edge.Cuts", + "pos": { + "x": 42.5, + "y": -0.01 + }, + "uuid": "5171f011-9ab5-52f7-bc94-9f840353c444" + }, + { + "description": "Reference field of C_DVB", + "pos": { + "x": 41.05, + "y": 20.5 + }, + "uuid": "01e73f26-4f2d-5279-bdbb-d33d7212804b" + } + ], + "severity": "warning", + "type": "silk_edge_clearance" + } + ] +} diff --git a/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-erc.json b/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-erc.json new file mode 100644 index 000000000..24af7deef --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/rtd_afe.kicad-erc.json @@ -0,0 +1,53 @@ +{ + "$schema": "https://schemas.kicad.org/erc.v1.json", + "coordinate_units": "mm", + "date": "2026-11-05T16:34:42", + "ignored_checks": [ + { + "description": "Global label only appears once in the schematic", + "key": "single_global_label" + }, + { + "description": "Four connection points are joined together", + "key": "four_way_junction" + }, + { + "description": "SPICE model issue", + "key": "simulation_model_issue" + }, + { + "description": "Assigned footprint doesn't match footprint filters", + "key": "footprint_filter" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.7", + "sheets": [ + { + "path": "/", + "uuid_path": "/b999385b-5cb0-57df-8610-0c339174ef3a", + "violations": [ + { + "description": "Symbol 'REF5025ID' doesn't match copy in library 'Reference_Voltage'", + "items": [ + { + "description": "Symbol U3 [REF5025ID]", + "pos": { + "x": 408.94, + "y": 190.5 + }, + "uuid": "1c679915-884b-5ed7-a9a1-16c5ce90aba2" + } + ], + "severity": "warning", + "type": "lib_symbol_mismatch" + } + ] + } + ], + "source": "rtd_afe.kicad_sch" +} diff --git a/qualification/class-b/rtd-afe/reports/rtd_afe.net b/qualification/class-b/rtd-afe/reports/rtd_afe.net new file mode 100644 index 000000000..55295ce3d --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/rtd_afe.net @@ -0,0 +1,7227 @@ +(export + (version "E") + (design + (source "qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_sch") + (date "2026-11-05T16:34:42") + (tool "Eeschema 10.0.7-10.0.7~ubuntu24.04.1") + (sheet + (number "1") + (name "/") + (tstamps "/") + (title_block + (title "rtd_afe") + (company) + (rev "A") + (date) + (source "rtd_afe.kicad_sch") + (comment + (number "1") + (value "Generated by synth-eda") + ) + (comment + (number "2") + (value "53 components / 40 nets") + ) + (comment + (number "3") + (value "Fab: jlc-filled-via") + ) + (comment + (number "4") + (value "") + ) + (comment + (number "5") + (value "") + ) + (comment + (number "6") + (value "") + ) + (comment + (number "7") + (value "") + ) + (comment + (number "8") + (value "") + ) + (comment + (number "9") + (value "") + ) + ) + ) + ) + (components + (comp + (ref "C_AV1") + (value "330nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "0603B334K500NT") + (field + (name "LCSC") "C188679") + (field + (name "Dielectric") "X7R") + (field + (name "Voltage") "10V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "0603B334K500NT") + ) + (property + (name "LCSC") + (value "C188679") + ) + (property + (name "Dielectric") + (value "X7R") + ) + (property + (name "Voltage") + (value "10V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "9959a845-2536-5d01-b313-56cc67ea363f") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_AV2") + (value "10uF") + (footprint "Capacitor_SMD:C_0805_2012Metric") + (fields + (field + (name "MPN") "TCC0805X7R106K160FT") + (field + (name "LCSC") "C380347") + (field + (name "Dielectric") "X7R") + (field + (name "Voltage") "10V") + (field + (name "Footprint") "Capacitor_SMD:C_0805_2012Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "TCC0805X7R106K160FT") + ) + (property + (name "LCSC") + (value "C380347") + ) + (property + (name "Dielectric") + (value "X7R") + ) + (property + (name "Voltage") + (value "10V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "2a270997-a502-5c5f-89df-1c6d8c9a78d6") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_AVF") + (value "4.7uF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "TCC0603X7R475K100CT") + (field + (name "LCSC") "C18185770") + (field + (name "Dielectric") "X7R") + (field + (name "Voltage") "10V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "TCC0603X7R475K100CT") + ) + (property + (name "LCSC") + (value "C18185770") + ) + (property + (name "Dielectric") + (value "X7R") + ) + (property + (name "Voltage") + (value "10V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "70cdc441-7cab-5662-bd50-9916b1fecb94") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_CM1") + (value "10nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "0603N103J500CT") + (field + (name "LCSC") "C2894187") + (field + (name "Dielectric") "C0G") + (field + (name "Voltage") "50V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "0603N103J500CT") + ) + (property + (name "LCSC") + (value "C2894187") + ) + (property + (name "Dielectric") + (value "C0G") + ) + (property + (name "Voltage") + (value "50V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "e4dc6c41-810a-5a66-9843-ddd9de63f49a") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_CM2") + (value "10nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "0603N103J500CT") + (field + (name "LCSC") "C2894187") + (field + (name "Dielectric") "C0G") + (field + (name "Voltage") "50V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "0603N103J500CT") + ) + (property + (name "LCSC") + (value "C2894187") + ) + (property + (name "Dielectric") + (value "C0G") + ) + (property + (name "Voltage") + (value "50V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "287eb6c2-9f62-5844-babd-f6cf387578e8") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_D") + (value "100nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") + ) + (field + (name "LCSC") + ) + (field + (name "Dielectric") "C0G") + (field + (name "Voltage") "50V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "") + ) + (property + (name "LCSC") + (value "") + ) + (property + (name "Dielectric") + (value "C0G") + ) + (property + (name "Voltage") + (value "50V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "71097b31-dff5-5f36-86d5-e9a7721d6d1e") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_DV") + (value "100nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "CC0603KRX7R9BB104") + (field + (name "LCSC") "C14663") + (field + (name "Dielectric") "X7R") + (field + (name "Voltage") "10V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "CC0603KRX7R9BB104") + ) + (property + (name "LCSC") + (value "C14663") + ) + (property + (name "Dielectric") + (value "X7R") + ) + (property + (name "Voltage") + (value "10V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "77b0ab91-8c4e-50a3-8033-2883ae06c75e") + (units + (unit + (name "A") + (pins + (pin + (num "1") + ) + (pin + (num "2") + ) + ) + ) + ) + ) + (comp + (ref "C_DV1") + (value "100nF") + (footprint "Capacitor_SMD:C_0603_1608Metric") + (fields + (field + (name "MPN") "CC0603KRX7R9BB104") + (field + (name "LCSC") "C14663") + (field + (name "Dielectric") "X7R") + (field + (name "Voltage") "10V") + (field + (name "Footprint") "Capacitor_SMD:C_0603_1608Metric") + (field + (name "Datasheet") + ) + (field + (name "Description") + ) + ) + (libsource + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + ) + (property + (name "MPN") + (value "CC0603KRX7R9BB104") + ) + (property + (name "LCSC") + (value "C14663") + ) + (property + (name "Dielectric") + (value "X7R") + ) + (property + (name "Voltage") + (value "10V") + ) + (property + (name "Sheetname") + (value "rtd_afe") + ) + (property + (name "Sheetfile") + (value "rtd_afe.kicad_sch") + ) + (property + (name "ki_keywords") + (value "cap capacitor") + ) + (property + (name "ki_fp_filters") + (value "C_*") + ) + (sheetpath + (names "/") + (tstamps "/") + ) + (tstamps "2181f896-29e3-57f5-8951-19a453734dac") + (units + (unit + (name "A") + (pins + (pin + (num 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(field + (name "Value") "Conn_01x04") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Generic connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/)") + ) + (pins + (pin + (num "1") + (name "Pin_1") + (type "passive") + ) + (pin + (num "2") + (name "Pin_2") + (type "passive") + ) + (pin + (num "3") + (name "Pin_3") + (type "passive") + ) + (pin + (num "4") + (name "Pin_4") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "C") + (description "Unpolarized capacitor") + (footprints + (fp "C_*") + ) + (fields + (field + (name "Reference") "C") + (field + (name "Value") "C") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Unpolarized capacitor") + ) + (pins + (pin + (num "1") + (name "") + (type "passive") + ) + (pin + (num "2") + (name "") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "Crystal_GND24") + (description "Four pin crystal, GND on pins 2 and 4") + (footprints + (fp "Crystal*") + ) + (fields + (field + (name "Reference") "Y") + (field + (name "Value") "Crystal_GND24") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Four pin crystal, GND on pins 2 and 4") + (field + (name "KLC_S3.3") "The rectangle is not a symbol body but a graphical element") + (field + (name "KLC_S4.1") "Some pins are on 50mil grid to make the symbol small") + ) + (pins + (pin + (num "1") + (name "1") + (type "passive") + ) + (pin + (num "2") + (name "G") + (type "passive") + ) + (pin + (num "3") + (name "3") + (type "passive") + ) + (pin + (num "4") + (name "G") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "D_TVS") + (description "Bidirectional transient-voltage-suppression diode") + (footprints + (fp "TO-???*") + (fp "*_Diode_*") + (fp "*SingleDiode*") + (fp "D_*") + ) + (fields + (field + (name "Reference") "D") + (field + (name "Value") "D_TVS") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Bidirectional transient-voltage-suppression diode") + ) + (pins + (pin + (num "1") + (name "A1") + (type "passive") + ) + (pin + (num "2") + (name "A2") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "FerriteBead") + (description "Ferrite bead") + (footprints + (fp "Inductor_*") + (fp "L_*") + (fp "*Ferrite*") + ) + (fields + (field + (name "Reference") "FB") + (field + (name "Value") "FerriteBead") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Ferrite bead") + ) + (pins + (pin + (num "1") + (name "") + (type "passive") + ) + (pin + (num "2") + (name "") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "L") + (description "Inductor") + (footprints + (fp "Choke_*") + (fp "*Coil*") + (fp "Inductor_*") + (fp "L_*") + ) + (fields + (field + (name "Reference") "L") + (field + (name "Value") "L") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Inductor") + ) + (pins + (pin + (num "1") + (name "1") + (type "passive") + ) + (pin + (num "2") + (name "2") + (type "passive") + ) + ) + ) + (libpart + (lib "Device") + (part "R_US") + (description "Resistor, US symbol") + (footprints + (fp "R_*") + ) + (fields + (field + (name "Reference") "R") + (field + (name "Value") "R_US") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Resistor, US symbol") + ) + (pins + (pin + (num "1") + (name "") + (type "passive") + ) + (pin + (num "2") + (name "") + (type "passive") + ) + ) + ) + (libpart + (lib "MCU_RaspberryPi") + (part "RP2350A") + (description "A microcontroller by Raspberry Pi, dual CPU architecture (ARM Cortex-M33 / RISC-V Hazard3), 150MHz, no flash, 520KB SRAM, 12 PIO state machines, VQFN-60") + (docs "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf") + (footprints + (fp "*QFN*7x7mm?P0.4mm?EP3.4x3.4mm*") + ) + (fields + (field + (name "Reference") "U") + (field + (name "Value") "RP2350A") + (field + (name "Footprint") "Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm") + (field + (name "Datasheet") "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf") + (field + (name "Description") "A microcontroller by Raspberry Pi, dual CPU architecture (ARM Cortex-M33 / RISC-V Hazard3), 150MHz, no flash, 520KB SRAM, 12 PIO state machines, VQFN-60") + (field + (name "KLC_S4.2_DVDD") "Not a standalone power converter; internal on-chip voltage regulator for digital core supply; DVDD is the digital core power supply, should be placed next to voltage regulator output.") + (field + (name "KLC_S4.2_VREG_LX") "Should be placed next to DVDD.") + ) + (pins + (pin + (num "1") + (name "IOVDD") + (type "power_in") + ) + (pin + (num "2") + (name "GPIO0") + (type "bidirectional") + ) + (pin + (num "3") + (name "GPIO1") + (type "bidirectional") + ) + (pin + (num "4") + (name "GPIO2") + (type "bidirectional") + ) + (pin + (num "5") + (name "GPIO3") + (type "bidirectional") + ) + (pin + (num "6") + (name "DVDD") + (type "power_in") + ) + (pin + (num "7") + (name "GPIO4") + (type "bidirectional") + ) + (pin + (num "8") + (name "GPIO5") + (type "bidirectional") + ) + (pin + (num "9") + (name "GPIO6") + (type "bidirectional") + ) + (pin + (num "10") + (name "GPIO7") + (type "bidirectional") + ) + (pin + (num "11") + (name "IOVDD") + (type "passive") + ) + (pin + (num "12") + (name "GPIO8") + (type "bidirectional") + ) + (pin + (num "13") + (name "GPIO9") + (type "bidirectional") + ) + (pin + (num "14") + (name "GPIO10") + (type "bidirectional") + ) + (pin + (num "15") + (name "GPIO11") + (type "bidirectional") + ) + (pin + (num "16") + (name "GPIO12") + (type "bidirectional") + ) + (pin + (num "17") + (name "GPIO13") + (type "bidirectional") + ) + (pin + (num "18") + (name "GPIO14") + (type "bidirectional") + ) + (pin + (num "19") + (name "GPIO15") + (type "bidirectional") + ) + (pin + (num "20") + (name "IOVDD") + (type "passive") + ) + (pin + (num "21") + (name "XIN") + (type "input") + ) + (pin + (num "22") + (name "XOUT") + (type "output") + ) + (pin + (num "23") + (name "DVDD") + (type "passive") + ) + (pin + (num "24") + (name "SWCLK") + (type "input") + ) + (pin + (num "25") + (name "SWDIO") + (type "bidirectional") + ) + (pin + (num "26") + (name "RUN") + (type "input") + ) + (pin + (num "27") + (name "GPIO16") + (type "bidirectional") + ) + (pin + (num "28") + (name "GPIO17") + (type "bidirectional") + ) + (pin + (num "29") + (name "GPIO18") + (type "bidirectional") + ) + (pin + (num "30") + (name "IOVDD") + (type "passive") + ) + (pin + (num "31") + (name "GPIO19") + (type "bidirectional") + ) + (pin + (num "32") + (name "GPIO20") + (type "bidirectional") + ) + (pin + (num "33") + (name "GPIO21") + (type "bidirectional") + ) + (pin + (num "34") + (name "GPIO22") + (type "bidirectional") + ) + (pin + (num "35") + (name "GPIO23") + (type "bidirectional") + ) + (pin + (num "36") + (name "GPIO24") + (type "bidirectional") + ) + (pin + (num "37") + (name "GPIO25") + (type "bidirectional") + ) + (pin + (num "38") + (name "IOVDD") + (type "passive") + ) + (pin + (num "39") + (name "DVDD") + (type "passive") + ) + (pin + (num "40") + (name "GPIO26/ADC0") + (type "bidirectional") + ) + (pin + (num "41") + (name "GPIO27/ADC1") + (type "bidirectional") + ) + (pin + (num "42") + (name "GPIO28/ADC2") + (type "bidirectional") + ) + (pin + (num "43") + (name "GPIO29/ADC3") + (type "bidirectional") + ) + (pin + (num "44") + (name "ADC_AVDD") + (type "power_in") + ) + (pin + (num "45") + (name "IOVDD") + (type "passive") + ) + (pin + (num "46") + (name "VREG_AVDD") + (type "power_in") + ) + (pin + (num "47") + (name "VREG_PGND") + (type "power_in") + ) + (pin + (num "48") + (name "VREG_LX") + (type "power_out") + ) + (pin + (num "49") + (name "VREG_VIN") + (type "power_in") + ) + (pin + (num "50") + (name "VREG_FB") + (type "passive") + ) + (pin + (num "51") + (name "USB_DM") + (type "bidirectional") + ) + (pin + (num "52") + (name "USB_DP") + (type "bidirectional") + ) + (pin + (num "53") + (name "USB_OTP_VDD") + (type "power_in") + ) + (pin + (num "54") + (name "QSPI_IOVDD") + (type "power_in") + ) + (pin + (num "55") + (name "QSPI_SD3") + (type "bidirectional") + ) + (pin + (num "56") + (name "QSPI_SCLK") + (type "output") + ) + (pin + (num "57") + (name "QSPI_SD0") + (type "bidirectional") + ) + (pin + (num "58") + (name "QSPI_SD2") + (type "bidirectional") + ) + (pin + (num "59") + (name "QSPI_SD1") + (type "bidirectional") + ) + (pin + (num "60") + (name "~{QSPI_SS}") + (type "output") + ) + (pin + (num "61") + (name "GND") + (type "power_in") + ) + ) + ) + (libpart + (lib "Mechanical") + (part "MountingHole") + (description "Mounting Hole without connection") + (footprints + (fp "MountingHole*") + ) + (fields + (field + (name "Reference") "H") + (field + (name "Value") "MountingHole") + (field + (name "Footprint") + ) + (field + (name "Datasheet") + ) + (field + (name "Description") "Mounting Hole without connection") + ) + ) + (libpart + (lib "Memory_Flash") + (part "W25Q128JVS") + (description "128Mbit / 16MiB Serial Flash Memory, Standard/Dual/Quad SPI, 2.7-3.6V, SOIC-8") + (docs "https://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf") + (footprints + (fp "*SOIC*5.3x5.3mm*P1.27mm*") + ) + (fields + (field + (name "Reference") "U") + (field + (name "Value") "W25Q128JVS") + (field + (name "Footprint") "Package_SO:SOIC-8_5.3x5.3mm_P1.27mm") + (field + (name "Datasheet") "https://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf") + (field + (name "Description") "128Mbit / 16MiB Serial Flash Memory, Standard/Dual/Quad SPI, 2.7-3.6V, SOIC-8") + ) + (pins + (pin + (num "1") + (name "~{CS}") + (type "input") + ) + (pin + (num "2") + (name "DO/IO_{1}") + (type "bidirectional") + ) + (pin + (num "3") + (name "~{WP}/IO_{2}") + (type "bidirectional") + ) + (pin + (num "4") + (name "GND") + (type "power_in") + ) + (pin + (num "5") + (name "DI/IO_{0}") + (type "bidirectional") + ) + (pin + (num "6") + (name "CLK") + (type "input") + ) + (pin + (num "7") + (name "~{HOLD}/~{RESET}/IO_{3}") + (type "bidirectional") + ) + (pin + (num "8") + (name "VCC") + (type "power_in") + ) + ) + ) + (libpart + (lib "Reference_Voltage") + (part "REF5025ID") + (description "2.5V 0.05% 10mA Low Noise Precision Voltage Reference, SO-8") + (docs "https://www.ti.com/lit/ds/symlink/ref50.pdf") + (footprints + (fp "SOIC*3.9x4.9mm*P1.27mm*") + ) + (fields + (field + (name "Reference") "U") + (field + (name "Value") "REF5025ID") + (field + (name "Footprint") "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm") + (field + (name "Datasheet") "https://www.ti.com/lit/ds/symlink/ref50.pdf") + (field + (name "Description") "2.5V 0.05% 10mA Low Noise Precision Voltage Reference, SO-8") + ) + (pins + (pin + (num "1") + (name "DNC") + (type "no_connect") + ) + (pin + (num "2") + (name "Vin") + (type "power_in") + ) + (pin + (num "3") + (name "Temp") + (type "passive") + ) + (pin + (num "4") + (name "GND") + (type "power_in") + ) + (pin + (num "5") + (name "Trim/NR") + (type "passive") + ) + (pin + (num "6") + (name "Vout") + (type "power_out") + ) + (pin + (num "7") + (name "NC") + (type "no_connect") + ) + (pin + (num "8") + (name "DNC") + (type "no_connect") + ) + ) + ) + (libpart + (lib "Regulator_Linear") + (part "LP5907MFX-3.3") + (description "250-mA Ultra-Low-Noise Low-IQ LDO, 3.3V, SOT-23") + (docs "http://www.ti.com/lit/ds/symlink/lp5907.pdf") + (footprints + (fp "SOT?23*") + ) + (fields + (field + (name "Reference") "U") + (field + (name "Value") "LP5907MFX-3.3") + (field + (name "Footprint") "Package_TO_SOT_SMD:SOT-23-5") + (field + (name "Datasheet") "http://www.ti.com/lit/ds/symlink/lp5907.pdf") + (field + (name "Description") "250-mA Ultra-Low-Noise Low-IQ LDO, 3.3V, SOT-23") + ) + (pins + (pin + (num "1") + (name "IN") + (type "power_in") + ) + (pin + (num "2") + (name "GND") + (type "power_in") + ) + (pin + (num "3") + (name "EN") + (type "input") + ) + (pin + (num "4") + (name "NC") + (type "no_connect") + ) + (pin + (num "5") + (name "OUT") + (type "power_out") + ) + ) + ) + (libpart + (lib "synth") + (part "ads124s08") + (docs "https://www.ti.com/lit/ds/symlink/ads124s08.pdf") + (fields + (field + (name "Reference") "U") + (field + (name "Value") "ads124s08") + (field + (name "Footprint") "Package_DFN_QFN:Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm") + (field + (name "Datasheet") "https://www.ti.com/lit/ds/symlink/ads124s08.pdf") + (field + (name "Description") + ) + ) + (pins + (pin + (num "1") + (name "aincom") + (type "passive") + ) + (pin + (num "2") + (name "ain5") + (type "passive") + ) + (pin + (num "3") + (name "ain4") + (type "passive") + ) + (pin + (num "4") + (name "ain3") + (type "passive") + ) + (pin + (num "5") + (name "ain2") + (type "passive") + ) + (pin + (num "6") + (name "ain1") + (type "passive") + ) + (pin + (num "7") + (name "ain0") + (type "passive") + ) + (pin + (num "8") + (name "start_sync") + (type "input") + ) + (pin + (num "9") + (name "cs_n") + (type "input") + ) + (pin + (num "10") + (name "din") + (type "input") + ) + (pin + (num "11") + (name "sclk") + (type "input") + ) + (pin + (num "12") + (name "dout_drdy") + (type "output") + ) + (pin + (num "13") + (name "drdy_n") + (type "output") + ) + (pin + (num "14") + (name "dgnd") + (type "power_in") + ) + (pin + (num "15") + (name "iovdd") + (type "power_in") + ) + (pin + (num "16") + (name "dvdd") + (type "power_in") + ) + (pin + (num "17") + (name "clk") + (type "passive") + ) + (pin + (num "18") + (name "reset_n") + (type "input") + ) + (pin + (num "19") + (name "gpio3_ain11") + (type "passive") + ) + (pin + (num "20") + (name "gpio2_ain10") + (type "passive") + ) + (pin + (num "21") + (name "gpio1_ain9") + (type "passive") + ) + (pin + (num "22") + (name "gpio0_ain8") + (type "passive") + ) + (pin + (num "23") + (name "refout") + (type "passive") + ) + (pin + (num "24") + (name "refcom") + (type "passive") + ) + (pin + (num "25") + (name "nc") + (type "no_connect") + ) + (pin + (num "26") + (name "avdd") + (type "power_in") + ) + (pin + (num "27") + (name "avss") + (type "power_in") + ) + (pin + (num "28") + (name "avss_sw") + (type "passive") + ) + (pin + (num "29") + (name "refn0") + (type "passive") + ) + (pin + (num "30") + (name "refp0") + (type "passive") + ) + (pin + (num "31") + (name "refn1_ain7") + (type "passive") + ) + (pin + (num "32") + (name "refp1_ain6") + (type "passive") + ) + (pin + (num "33") + (name "ep") + (type "power_in") + ) + ) + ) + ) + (libraries + (library + (logical "Connector") + (uri "${KICAD10_SYMBOL_DIR}/Connector.kicad_sym") + ) + (library + (logical "Connector_Generic") + (uri "${KICAD10_SYMBOL_DIR}/Connector_Generic.kicad_sym") + ) + (library + (logical "Device") + (uri "${KICAD10_SYMBOL_DIR}/Device.kicad_sym") + ) + (library + (logical "MCU_RaspberryPi") + (uri "${KICAD10_SYMBOL_DIR}/MCU_RaspberryPi.kicad_sym") + ) + (library + (logical "Mechanical") + (uri "${KICAD10_SYMBOL_DIR}/Mechanical.kicad_sym") + ) + (library + (logical "Memory_Flash") + (uri "${KICAD10_SYMBOL_DIR}/Memory_Flash.kicad_sym") + ) + (library + (logical "Reference_Voltage") + (uri "${KICAD10_SYMBOL_DIR}/Reference_Voltage.kicad_sym") + ) + (library + (logical "Regulator_Linear") + (uri "${KICAD10_SYMBOL_DIR}/Regulator_Linear.kicad_sym") + ) + (library + (logical "synth") + (uri "${KIPRJMOD}/rtd_afe.kicad_sym") + ) + ) + (nets + (net + (code "1") + (name "+3V3") + (class "Default") + (node + (ref "C_DV") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_FL") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_IO") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_IO1") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_IO2") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_IO3") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_IO4") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_L2") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_VI") + (pin "1") + (pintype "passive") + ) + (node + (ref "L2") + (pin "1") + (pintype "passive") + ) + (node + (ref "R_AV") + (pin "1") + (pintype "passive") + ) + (node + (ref "R_RST") + (pin "1") + (pintype "passive") + ) + (node + (ref "R_RUN") + (pin "1") + (pintype "passive") + ) + (node + (ref "U1") + (pin "15") + (pinfunction "iovdd_15") + (pintype "power_in") + ) + (node + (ref "U1") + (pin "16") + (pinfunction "dvdd_16") + (pintype "power_in") + ) + (node + (ref "U2") + (pin "1") + (pinfunction "IOVDD_1") + (pintype "power_in") + ) + (node + (ref "U2") + (pin "11") + (pinfunction "IOVDD_11") + (pintype "passive") + ) + (node + (ref "U2") + (pin "20") + (pinfunction "IOVDD_20") + (pintype "passive") + ) + (node + (ref "U2") + (pin "30") + (pinfunction "IOVDD_30") + (pintype "passive") + ) + (node + (ref "U2") + (pin "38") + (pinfunction "IOVDD_38") + (pintype "passive") + ) + (node + (ref "U2") + (pin "45") + (pinfunction "IOVDD_45") + (pintype "passive") + ) + (node + (ref "U2") + (pin "49") + (pinfunction "VREG_VIN_49") + (pintype "power_in") + ) + (node + (ref "U2") + (pin "53") + (pinfunction "USB_OTP_VDD_53") + (pintype "power_in") + ) + (node + (ref "U2") + (pin "54") + (pinfunction "QSPI_IOVDD_54") + (pintype "power_in") + ) + (node + (ref "U4") + (pin "8") + (pinfunction "VCC_8") + (pintype "power_in") + ) + (node + (ref "U5") + (pin "5") + (pinfunction "OUT_5") + (pintype "power_out") + ) + ) + (net + (code "2") + (name "+3V3A") + (class "Default") + (node + (ref "C_AV1") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_AV2") + (pin "1") + (pintype "passive") + ) + (node + (ref "C_RI") + (pin "1") + (pintype "passive") + ) + (node + (ref "L2") + (pin "2") + (pintype "passive") + ) + (node + (ref "U1") + (pin "26") + (pinfunction "avdd_26") + (pintype "power_in") + ) + (node + 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(node + (ref "Y1") + (pin "3") + (pinfunction "3_3") + (pintype "passive") + ) + ) + (net + (code "41") + (name "unconnected-(J1-RX1+-PadB11)") + (class "Default") + (node + (ref "J1") + (pin "B11") + (pinfunction "RX1+_B11") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "42") + (name "unconnected-(J1-RX1--PadB10)") + (class "Default") + (node + (ref "J1") + (pin "B10") + (pinfunction "RX1-_B10") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "43") + (name "unconnected-(J1-RX2+-PadA11)") + (class "Default") + (node + (ref "J1") + (pin "A11") + (pinfunction "RX2+_A11") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "44") + (name "unconnected-(J1-RX2--PadA10)") + (class "Default") + (node + (ref "J1") + (pin "A10") + (pinfunction "RX2-_A10") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "45") + (name "unconnected-(J1-SBU1-PadA8)") + (class "Default") + (node + (ref "J1") + (pin "A8") + (pinfunction "SBU1_A8") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "46") + (name "unconnected-(J1-SBU2-PadB8)") + (class "Default") + (node + (ref "J1") + (pin "B8") + (pinfunction "SBU2_B8") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "47") + (name "unconnected-(J1-TX1+-PadA2)") + (class "Default") + (node + (ref "J1") + (pin "A2") + (pinfunction "TX1+_A2") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "48") + (name "unconnected-(J1-TX1--PadA3)") + (class "Default") + (node + (ref "J1") + (pin "A3") + (pinfunction "TX1-_A3") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "49") + (name "unconnected-(J1-TX2+-PadB2)") + (class "Default") + (node + (ref "J1") + (pin "B2") + (pinfunction "TX2+_B2") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "50") + (name "unconnected-(J1-TX2--PadB3)") + (class "Default") + (node + (ref "J1") + (pin "B3") + (pinfunction "TX2-_B3") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "51") + (name "unconnected-(U1-ain3-Pad4)") + (class "Default") + (node + (ref "U1") + (pin "4") + (pinfunction "ain3_4") + (pintype "passive+no_connect") + ) + ) + (net + (code "52") + (name "unconnected-(U1-ain4-Pad3)") + (class "Default") + (node + (ref "U1") + (pin "3") + (pinfunction "ain4_3") + (pintype "passive+no_connect") + ) + ) + (net + (code "53") + (name "unconnected-(U1-ain5-Pad2)") + (class "Default") + (node + (ref "U1") + (pin "2") + (pinfunction "ain5_2") + (pintype "passive+no_connect") + ) + ) + (net + (code "54") + (name "unconnected-(U1-aincom-Pad1)") + (class "Default") + (node + (ref "U1") + (pin "1") + (pinfunction "aincom_1") + (pintype "passive+no_connect") + ) + ) + (net + (code "55") + (name "unconnected-(U1-gpio0_ain8-Pad22)") + (class "Default") + (node + (ref "U1") + (pin "22") + (pinfunction "gpio0_ain8_22") + (pintype "passive+no_connect") + ) + ) + (net + (code "56") + (name "unconnected-(U1-gpio1_ain9-Pad21)") + (class "Default") + (node + (ref "U1") + (pin "21") + (pinfunction "gpio1_ain9_21") + (pintype "passive+no_connect") + ) + ) + (net + (code "57") + (name "unconnected-(U1-gpio2_ain10-Pad20)") + (class "Default") + (node + (ref "U1") + (pin "20") + (pinfunction "gpio2_ain10_20") + (pintype "passive+no_connect") + ) + ) + (net + (code "58") + (name "unconnected-(U1-gpio3_ain11-Pad19)") + (class "Default") + (node + (ref "U1") + (pin "19") + (pinfunction "gpio3_ain11_19") + (pintype "passive+no_connect") + ) + ) + (net + (code "59") + (name "unconnected-(U1-nc-Pad25)") + (class "Default") + (node + (ref "U1") + (pin "25") + (pinfunction "nc_25") + (pintype "no_connect") + ) + ) + (net + (code "60") + (name "unconnected-(U1-refn1_ain7-Pad31)") + (class "Default") + (node + (ref "U1") + (pin "31") + (pinfunction "refn1_ain7_31") + (pintype "passive+no_connect") + ) + ) + (net + (code "61") + (name "unconnected-(U1-refp1_ain6-Pad32)") + (class "Default") + (node + (ref "U1") + (pin "32") + (pinfunction "refp1_ain6_32") + (pintype "passive+no_connect") + ) + ) + (net + (code "62") + (name "unconnected-(U2-GPIO7-Pad10)") + (class "Default") + (node + (ref "U2") + (pin "10") + (pinfunction "GPIO7_10") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "63") + (name "unconnected-(U2-GPIO8-Pad12)") + (class "Default") + (node + (ref "U2") + (pin "12") + (pinfunction "GPIO8_12") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "64") + (name "unconnected-(U2-GPIO9-Pad13)") + (class "Default") + (node + (ref "U2") + (pin "13") + (pinfunction "GPIO9_13") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "65") + (name "unconnected-(U2-GPIO10-Pad14)") + (class "Default") + (node + (ref "U2") + (pin "14") + (pinfunction "GPIO10_14") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "66") + (name "unconnected-(U2-GPIO11-Pad15)") + (class "Default") + (node + (ref "U2") + (pin "15") + (pinfunction "GPIO11_15") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "67") + (name "unconnected-(U2-GPIO12-Pad16)") + (class "Default") + (node + (ref "U2") + (pin "16") + (pinfunction "GPIO12_16") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "68") + (name "unconnected-(U2-GPIO13-Pad17)") + (class "Default") + (node + (ref "U2") + (pin "17") + (pinfunction "GPIO13_17") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "69") + (name "unconnected-(U2-GPIO14-Pad18)") + (class "Default") + (node + (ref "U2") + (pin "18") + (pinfunction "GPIO14_18") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "70") + (name "unconnected-(U2-GPIO15-Pad19)") + (class "Default") + (node + (ref "U2") + (pin "19") + (pinfunction "GPIO15_19") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "71") + (name "unconnected-(U2-GPIO16-Pad27)") + (class "Default") + (node + (ref "U2") + (pin "27") + (pinfunction "GPIO16_27") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "72") + (name "unconnected-(U2-GPIO17-Pad28)") + (class "Default") + (node + (ref "U2") + (pin "28") + (pinfunction "GPIO17_28") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "73") + (name "unconnected-(U2-GPIO18-Pad29)") + (class "Default") + (node + (ref "U2") + (pin "29") + (pinfunction "GPIO18_29") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "74") + (name "unconnected-(U2-GPIO19-Pad31)") + (class "Default") + (node + (ref "U2") + (pin "31") + (pinfunction "GPIO19_31") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "75") + (name "unconnected-(U2-GPIO20-Pad32)") + (class "Default") + (node + (ref "U2") + (pin "32") + (pinfunction "GPIO20_32") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "76") + (name "unconnected-(U2-GPIO21-Pad33)") + (class "Default") + (node + (ref "U2") + (pin "33") + (pinfunction "GPIO21_33") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "77") + (name "unconnected-(U2-GPIO22-Pad34)") + (class "Default") + (node + (ref "U2") + (pin "34") + (pinfunction "GPIO22_34") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "78") + (name "unconnected-(U2-GPIO23-Pad35)") + (class "Default") + (node + (ref "U2") + (pin "35") + (pinfunction "GPIO23_35") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "79") + (name "unconnected-(U2-GPIO24-Pad36)") + (class "Default") + (node + (ref "U2") + (pin "36") + (pinfunction "GPIO24_36") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "80") + (name "unconnected-(U2-GPIO25-Pad37)") + (class "Default") + (node + (ref "U2") + (pin "37") + (pinfunction "GPIO25_37") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "81") + (name "unconnected-(U2-GPIO26{slash}ADC0-Pad40)") + (class "Default") + (node + (ref "U2") + (pin "40") + (pinfunction "GPIO26/ADC0_40") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "82") + (name "unconnected-(U2-GPIO27{slash}ADC1-Pad41)") + (class "Default") + (node + (ref "U2") + (pin "41") + (pinfunction "GPIO27/ADC1_41") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "83") + (name "unconnected-(U2-GPIO28{slash}ADC2-Pad42)") + (class "Default") + (node + (ref "U2") + (pin "42") + (pinfunction "GPIO28/ADC2_42") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "84") + (name "unconnected-(U2-GPIO29{slash}ADC3-Pad43)") + (class "Default") + (node + (ref "U2") + (pin "43") + (pinfunction "GPIO29/ADC3_43") + (pintype "bidirectional+no_connect") + ) + ) + (net + (code "85") + (name "unconnected-(U3-DNC-Pad1)") + (class "Default") + (node + (ref "U3") + (pin "1") + (pinfunction "DNC_1") + (pintype "no_connect") + ) + ) + (net + (code "86") + (name "unconnected-(U3-DNC-Pad8)") + (class "Default") + (node + (ref "U3") + (pin "8") + (pinfunction "DNC_8") + (pintype "no_connect") + ) + ) + (net + (code "87") + (name "unconnected-(U3-NC-Pad7)") + (class "Default") + (node + (ref "U3") + (pin "7") + (pinfunction "NC_7") + (pintype "no_connect") + ) + ) + (net + (code "88") + (name "unconnected-(U3-Temp-Pad3)") + (class "Default") + (node + (ref "U3") + (pin "3") + (pinfunction "Temp_3") + (pintype "passive+no_connect") + ) + ) + (net + (code "89") + (name "unconnected-(U3-Trim{slash}NR-Pad5)") + (class "Default") + (node + (ref "U3") + (pin "5") + (pinfunction "Trim/NR_5") + (pintype "passive+no_connect") + ) + ) + (net + (code "90") + (name "unconnected-(U5-NC-Pad4)") + (class "Default") + (node + (ref "U5") + (pin "4") + (pinfunction "NC_4") + (pintype "no_connect") + ) + ) + ) +) diff --git a/qualification/class-b/rtd-afe/reports/rtd_afe.routing.json b/qualification/class-b/rtd-afe/reports/rtd_afe.routing.json new file mode 100644 index 000000000..6af0667d5 --- /dev/null +++ b/qualification/class-b/rtd-afe/reports/rtd_afe.routing.json @@ -0,0 +1,160 @@ +{ + "schema_version": "synth.routing.v1", + "state": "routed", + "engine": "freerouting", + "capability": { + "engine": "freerouting", + "available": true, + "version": "freerouting-2.4.1", + "runtime_version": "openjdk version \"25.0.4.1\" 2026-08-18 LTS", + "detail": null, + "failure": null + }, + "provenance": { + "engine": "freerouting", + "engine_version": "freerouting-2.4.1.jar", + "runtime_version": "openjdk version \"25.0.4.1\" 2026-08-18 LTS", + "profile": "jlc-filled-via", + "command": [ + "/usr/bin/python3", + "tools/freeroute_autoroute.py", + "qualification/class-b/rtd-afe/kicad/rtd_afe.synth.kicad_pcb", + "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.kicad_pcb", + "--jar", + "tools/freerouting/freerouting-2.4.1.jar", + "--java", + "tools/jre25/bin/java", + "--passes", + "40", + "--threads", + "4", + "--ses-output", + "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.ses", + "--report", + "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.json", + "--clean-netlist", + "--allow-via-in-pad" + ], + "settings": { + "clean_netlist": "true", + "passes": "40", + "threads": "4", + "wall_clock_secs": "1200" + }, + "input_hash": "abc91eecd10c5bd9b576dd8cc22d2cde488556172cdacb335d88c5cae58f2085", + "output_hash": "", + "source_revision": "01a77d545c2ebab2d85a31b2ceff24ebcd1feacf", + "duration_ms": 226649 + }, + "statistics": { + "connected_nets": 40, + "open_nets": 0, + "open_net_names": [], + "segments": 389, + "vias": 89, + "wire_length_mm": 688.401167, + "pad_escape_rejections": 0, + "engine_findings": { + "claimed_imported_segments": "389", + "claimed_imported_vias": "71" + } + }, + "artifacts": { + "baseline": "qualification/class-b/rtd-afe/kicad/rtd_afe.synth.kicad_pcb", + "candidate": "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.kicad_pcb", + "delivered": "qualification/class-b/rtd-afe/kicad/rtd_afe.kicad_pcb", + "session_log": "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.log", + "ses": "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.ses", + "router_report": "qualification/class-b/rtd-afe/kicad/rtd_afe.freerouting.json", + "connectivity_report": null, + "drc_report": null + }, + "validation": { + "fabrication_ready": true, + "topology": { + "missing_footprints": [], + "extra_footprints": [], + "missing_nets": [], + "missing_layers": [], + "missing_pads": [], + "renet_pads": [], + "outline_present": true + }, + "connectivity": { + "connected_nets": 40, + "open_nets": 0, + "open": [], + "unconnected_pads": [], + "via_in_pad": [ + "via at (16.138, 22.835) mm C_DV.2" + ], + "undersized_vias": [], + "undersized_tracks": [] + }, + "kicad_drc": { + "errors": 0, + "unconnected": 0, + "warnings": 48 + }, + "blocking_reasons": [], + "unavailable_checks": [], + "advisories": [ + "net SPI_MOSI changes layers at (23.41, 28.63) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net SPI_SCK changes layers at (22.69, 27.91) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net SPI_MISO changes layers at (23.41, 27.08) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_DRDY changes layers at (15.49, 24.64) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_DRDY changes layers at (23.08, 30.50) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_START changes layers at (14.32, 29.00) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_START changes layers at (23.47, 29.71) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net ADC_RESET_N changes layers at (25.54, 29.05) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net CC1 changes layers at (23.76, 7.95) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net USB_DN changes layers at (27.96, 27.12) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review", + "net DVDD_1V1 changes layers at (25.86, 30.42) mm in a fine-pitch pad breakout with no ground return via within 0.80 mm and no spot in the GND pour for one; the pads leave no room, so the loop is left as an advisory for the signal-integrity review" + ] + }, + "failure": null, + "escape": [ + { + "refdes": "U2", + "package": "Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm", + "pads": 61, + "pitch_mm": 0.4, + "gap_mm": 0.2, + "via_span_mm": 0.587, + "max_drill_mm": 0.013, + "layers": 4, + "suggested_layers": null, + "limit": "track", + "detail": "adjacent pins are 0.400 mm apart and the pads leave 0.200 mm between them; a fabrication-floor via needs 0.587 mm between centres, so the drill that would fit is 0.013 mm; even a minimum track needs 0.254 mm of gap", + "remediation": "use via-in-pad if the process allows, or choose a coarser-pitch part" + }, + { + "refdes": "J1", + "package": "Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12", + "pads": 22, + "pitch_mm": 0.5, + "gap_mm": 0.2, + "via_span_mm": 0.587, + "max_drill_mm": 0.113, + "layers": 4, + "suggested_layers": null, + "limit": "track", + "detail": "adjacent pins are 0.500 mm apart and the pads leave 0.200 mm between them; a fabrication-floor via needs 0.587 mm between centres, so the drill that would fit is 0.113 mm; even a minimum track needs 0.254 mm of gap", + "remediation": "use via-in-pad if the process allows, or choose a coarser-pitch part" + }, + { + "refdes": "U1", + "package": "Package_DFN_QFN:Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm", + "pads": 33, + "pitch_mm": 0.5, + "gap_mm": 0.0, + "via_span_mm": 0.587, + "max_drill_mm": 0.113, + "layers": 4, + "suggested_layers": null, + "limit": "track", + "detail": "adjacent pins are 0.500 mm apart and the pads leave 0.000 mm between them; a fabrication-floor via needs 0.587 mm between centres, so the drill that would fit is 0.113 mm; even a minimum track needs 0.254 mm of gap", + "remediation": "use via-in-pad if the process allows, or choose a coarser-pitch part" + } + ] +} \ No newline at end of file diff --git a/qualification/class-b/rtd-afe/rtd_afe.placement.layout.toml b/qualification/class-b/rtd-afe/rtd_afe.placement.layout.toml new file mode 100644 index 000000000..3813cc0a3 --- /dev/null +++ b/qualification/class-b/rtd-afe/rtd_afe.placement.layout.toml @@ -0,0 +1,469 @@ +schema_version = 2 +forced_net_labels = [] +fit_sheet = false + + +# Plain rectangle: no notch, no post-export cut. +[[outline]] +x = 2.5 +y = -0.01 + +[[outline]] +x = 42.5 +y = -0.01 + +[[outline]] +x = 42.5 +y = 44.2 + +[[outline]] +x = 2.5 +y = 44.2 + +[[vias]] +x = 16.5 +y = 22.3 +net = "GND" + +[[vias]] +x = 30.4 +y = 25.3 +net = "GND" + + +[components.H1] +x = 6.0 +y = 3.5 +rotation = 0 +priority = "hard" + +[components.H2] +x = 39.0 +y = 3.5 +rotation = 0 +priority = "hard" + +[components.H3] +x = 6.0 +y = 40.7 +rotation = 0 +priority = "hard" + +[components.H4] +x = 39.0 +y = 40.7 +rotation = 0 +priority = "hard" + +# --- Analog front end: left column ------------------------------------------ +# The input filter stays next to J2 and U1; the reference and analog-supply +# support parts sit in the top-left, which used to be 24 x 22 mm of bare board. +[components.J2] +x = 14.8 +y = 41.7 +rotation = 270 +priority = "hard" + +[components.R_S1] +x = 12.5 +y = 35.6 +rotation = 90 +priority = "hard" + +[components.R_S2] +x = 9.5 +y = 35.6 +rotation = 90 +priority = "hard" + +[components.C_D] +x = 12.0 +y = 32.1 +rotation = 0 +priority = "hard" + +[components.C_CM1] +x = 15.5 +y = 32.1 +rotation = 0 +priority = "hard" + +[components.C_CM2] +x = 8.5 +y = 32.1 +rotation = 0 +priority = "hard" + +[components.C_F] +x = 16.0 +y = 35.6 +rotation = 0 +priority = "hard" + +[components.R_BIAS] +x = 4.5 +y = 28.1 +rotation = 90 +priority = "hard" + +[components.U1] +x = 12.0 +y = 25.1 +rotation = 90 +priority = "hard" + +[components.U3] +x = 10.5 +y = 11.6 +rotation = 0 +priority = "hard" + +[components.C_RV] +x = 7.0 +y = 24.8 +rotation = 90 +priority = "hard" + +[components.C_RI] +x = 4.8 +y = 11.3 +rotation = 0 +priority = "hard" + +[components.C_AV1] +x = 11.0 +y = 17.6 +rotation = 0 +priority = "hard" + +[components.C_AV2] +x = 6.5 +y = 17.6 +rotation = 0 +priority = "hard" + +[components.C_RO] +x = 16.0 +y = 13.6 +rotation = 0 +priority = "hard" + +[components.R_RST] +x = 19.8 +y = 14.0 +rotation = 90 +priority = "hard" + +[components.C_DV] +x = 16.5 +y = 23.1 +rotation = 90 +priority = "hard" + +[components.C_IO] +x = 17.0 +y = 27.1 +rotation = 270 +priority = "hard" + +[components.L2] +x = 13.0 +y = 6.5 +rotation = 180 +priority = "hard" + +# --- MCU, flash, crystal: right column -------------------------------------- +[components.U2] +x = 28.0 +y = 29.6 +rotation = 0 +priority = "hard" + +[components.U4] +x = 22.0 +y = 19.0 +rotation = 0 +priority = "hard" + +[components.C_FL] +relative_to = "U4" +dx = 1.5 +dy = -4.0 +rotation = 0 +priority = "hard" + +[components.J3] +x = 28.0 +y = 41.7 +rotation = 90 +priority = "hard" + +[components.Y1] +x = 28.0 +y = 36.3 +rotation = 0 +priority = "hard" + +[components.C_X1] +x = 23.5 +y = 38.3 +rotation = 0 +priority = "hard" + +[components.C_X2] +x = 32.0 +y = 38.3 +rotation = 0 +priority = "hard" + +[components.R_X] +x = 24.0 +y = 35.3 +rotation = 90 +priority = "hard" + +[components.R_RUN] +x = 19.5 +y = 34.5 +rotation = 0 +priority = "hard" + +[components.C_DV1] +x = 19.5 +y = 31.0 +rotation = 0 +priority = "hard" + +[components.C_IO1] +x = 19.5 +y = 25.0 +rotation = 0 +priority = "hard" + +[components.C_IO2] +x = 19.5 +y = 28.0 +rotation = 0 +priority = "hard" + +[components.L1] +x = 34.4 +y = 21.0 +rotation = 90 +priority = "hard" + +[components.C_DVB] +x = 37.0 +y = 20.5 +rotation = 0 +priority = "hard" + +[components.C_VI] +x = 37.5 +y = 24.0 +rotation = 0 +priority = "hard" + +[components.C_DV2] +x = 34.0 +y = 24.0 +rotation = 0 +priority = "hard" + +[components.R_AV] +x = 34.0 +y = 27.0 +rotation = 0 +priority = "hard" + +[components.C_AVF] +x = 37.5 +y = 27.0 +rotation = 0 +priority = "hard" + +[components.C_IO3] +x = 34.0 +y = 30.0 +rotation = 0 +priority = "hard" + +[components.C_IO4] +x = 37.5 +y = 30.0 +rotation = 0 +priority = "hard" + +# --- USB-C readout: top edge, short pair to the MCU ------------------------- +[components.J1] +x = 22.55 +y = 6.0 +rotation = 180 +priority = "hard" + +[components.D1] +x = 25.0 +y = 12.0 +rotation = 0 +priority = "hard" + +[components.D2] +x = 28.5 +y = 12.0 +rotation = 0 +priority = "hard" + +[components.R_DP] +x = 26.0 +y = 15.0 +rotation = 90 +priority = "hard" + +[components.R_DN] +x = 28.5 +y = 15.0 +rotation = 90 +priority = "hard" + +[components.R_CC1] +x = 35.0 +y = 7.5 +rotation = 0 +priority = "hard" + +[components.R_CC2] +x = 21.0 +y = 11.5 +rotation = 0 +priority = "hard" + +[components.U5] +x = 36.5 +y = 10.5 +rotation = 0 +priority = "hard" + +[components.C_L1] +x = 35.5 +y = 14.0 +rotation = 90 +priority = "hard" + +[components.C_L2] +x = 39.0 +y = 14.0 +rotation = 90 +priority = "hard" + +# --- Ground tie, straddling the AGND/DGND boundary next to U1 --------------- + +# Reference labels: moved where a clear spot exists, hidden where the compact +# refdes field has none. Every hidden refdes is still in the BOM, PnP and schematic. +[labels.U1] +dx = 4.0 +dy = 5.5 +angle = 0.0 +priority = "hard" + +[labels.D1] +hide = true + +[labels.D2] +hide = true + +[labels.R_DP] +hide = true + +[labels.R_DN] +hide = true + +[labels.R_X] +hide = true + +[labels.C_AVF] +hide = true + +[labels.C_IO4] +hide = true + +[labels.C_IO3] +hide = true + +[labels.R_AV] +hide = true + +[labels.C_IO2] +hide = true + +[labels.C_IO1] +hide = true + +[labels.C_DV1] +hide = true + + +[labels.C_IO] +hide = true + +[labels.C_RO] +hide = true + +[labels.C_L2] +hide = true + +[labels.C_FL] +hide = true + +[labels.R_RST] +hide = true + +[labels.J3] +hide = true + +[labels.C_DV] +hide = true + +[labels.C_VI] +hide = true + +[labels.C_DV2] +hide = true + +[labels.C_RV] +hide = true + +[labels.R_BIAS] +hide = true + +[labels.C_CM2] +hide = true + +[labels.C_D] +hide = true + +[labels.C_CM1] +hide = true + +[labels.R_S1] +hide = true + +[labels.R_S2] +hide = true + +[labels.C_AV1] +hide = true + +[labels.R_CC2] +hide = true + +[labels.H1] +hide = true + +[labels.H2] +hide = true + +[labels.H3] +hide = true + +[labels.J1] +hide = true diff --git a/qualification/class-b/rtd-afe/rtd_afe.synth b/qualification/class-b/rtd-afe/rtd_afe.synth new file mode 100644 index 000000000..64f6bdf32 --- /dev/null +++ b/qualification/class-b/rtd-afe/rtd_afe.synth @@ -0,0 +1,225 @@ +// SYN-363: PT100 4-wire RTD analog front end. ADS124S08 24-bit delta-sigma ADC, IDAC excitation, +// REF5025 2.5 V reference, RP2350 over SPI, USB-C readout. +// +// Signal chain: J2 (F+, S+, S-, F-) -> RC input filter -> ADS124S08 AIN0..AIN2. +// IDAC1 sources 1 mA out of AIN0 into F+, through the PT100 and F- into R_BIAS (1k) to GND. +// R_BIAS sets the RTD common-mode near 1.1 V, inside the PGA input range. REF5025 is the +// absolute reference (REFP0/REFN0); the measurement is not ratiometric to the IDAC. +// Ground: one GND plane on all four layers; there is no analog/digital split and no tie resistor. +board "rtd_afe" { + layers 4 + manufacturer "jlc-filled-via" + revision "A" + + netclass "USB" { + trace_width 0.242mm + clearance 0.127mm + } + + power "VBUS" 5v + power "+3V3" 3.3v + power "+3V3A" 3.3v + requires via_in_pad + + component H1: mounting_hole "mounting_hole_m2_5_clearance" + component H2: mounting_hole "mounting_hole_m2_5_clearance" + component H3: mounting_hole "mounting_hole_m2_5_clearance" + component H4: mounting_hole "mounting_hole_m2_5_clearance" + + group "RTD INPUT" color "#c2410c" { + component J2: connector "header_1x4" value "PT100" + component R_S1: resistor "r_generic_0603" value "1k" tolerance "0.1%" lcsc_pn "C110776" mpn "RT0603BRD071KL" + component R_S2: resistor "r_generic_0603" value "1k" tolerance "0.1%" lcsc_pn "C110776" mpn "RT0603BRD071KL" + component C_D: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "50V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_CM1: capacitor "c_generic_0603" value "10nF" dielectric "C0G" voltage "50V" lcsc_pn "C2894187" mpn "0603N103J500CT" + component C_CM2: capacitor "c_generic_0603" value "10nF" dielectric "C0G" voltage "50V" lcsc_pn "C2894187" mpn "0603N103J500CT" + component C_F: capacitor "c_generic_0603" value "10nF" dielectric "C0G" voltage "50V" lcsc_pn "C2894187" mpn "0603N103J500CT" + component R_BIAS: resistor "r_generic_0603" value "1k" tolerance "0.1%" lcsc_pn "C110776" mpn "RT0603BRD071KL" + notes "" { + "J2 pin 1 F+, pin 2 S+, pin 3 S-, pin 4 F-. PT100 4-wire; force pair carries the 1 mA IDAC current, sense pair reads the RTD." + "R_S1/R_S2 1k with C_D 100nF across the pair and C_CM1/C_CM2 10nF to GND: differential corner 1/(2pi*2k*110nF) about 720 Hz, common-mode corner about 16 kHz." + "C_D is 10x each C_CM so a capacitor mismatch turns into little differential error (TI input filter rule). No 100 nF C0G is stocked in 0603 at LCSC, so C_D is X7R; its DC-bias drift at the low differential level is small." + "C_F 10nF decouples the force node F+ (IDAC output). R_BIAS 1k returns the IDAC current to GND and lifts the RTD common-mode to about 1.1 V." + } + } + + group "ADC" color "#0072b2" { + component U1: ic "ads124s08" lcsc_pn "C2871942" mpn "ADS124S08IRHBR" + component C_AV1: capacitor "c_generic_0603" value "330nF" dielectric "X7R" voltage "10V" lcsc_pn "C188679" mpn "0603B334K500NT" + component C_AV2: capacitor "c_generic_0805" value "10uF" dielectric "X7R" voltage "10V" lcsc_pn "C380347" mpn "TCC0805X7R106K160FT" + component C_DV: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_IO: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_RO: capacitor "c_generic_0603" value "1uF" dielectric "X7R" voltage "10V" lcsc_pn "C93816" mpn "0603B105K160NT" + component R_RST: resistor "r_generic_0603" value "10k" lcsc_pn "C25804" mpn "0603WAF1002T5E" + notes "" { + "AVDD from +3V3A (ferrite-filtered), DVDD and IOVDD from +3V3. AVSS, AVSS_SW, REFN0, REFCOM, the exposed pad and DGND (pin 14) are on GND: the ADC returns its own digital supply current to the same plane. CLK is tied to that ground to use the internal oscillator." + "REFOUT has 1 uF to GND for the unused internal reference. RESET has a 10k pull-up to +3V3 and is also driven by the MCU." + "AINCOM, AIN3..AIN11, REFP1/REFN1, GPIOs and pin 25 are left open." + } + } + + group "REFERENCE" color "#7c3aed" { + component U3: ic "ref5025" lcsc_pn "C11341" mpn "REF5025AIDR" + component C_RI: capacitor "c_generic_0603" value "1uF" dielectric "X7R" voltage "10V" lcsc_pn "C93816" mpn "0603B105K160NT" + component C_RV: capacitor "c_generic_0603" value "1uF" dielectric "X7R" voltage "10V" lcsc_pn "C93816" mpn "0603B105K160NT" + notes "" { + "REF5025 2.5 V, VIN from +3V3A, VOUT straight to REFP0 with 1 uF at the reference pin, GND to GND. TEMP, TRIM/NR, DNC and NC pins are open." + } + } + + group "ANALOG SUPPLY" color "#0a7d4a" { + component L2: inductor "ferrite_bead_0603" value "600R@100MHz" lcsc_pn "C19330" mpn "BLM18AG601SN1D" + notes "" { + "L2 filters +3V3 into the +3V3A analog rail for the ADC and the reference. Its DC resistance and the ADC/REF supply current are not computed here." + } + } + + group "MCU" color "#b45309" { + component U2: mcu "rp2350" + component U4: ic "w25q128_flash_208mil" + component Y1: crystal "ecs_120_20_33_tr" value "12MHz" lcsc_pn "C2449814" mpn "ECS-120-20-33-TR" + component C_X1: capacitor "c_generic_0603" value "33pF" dielectric "C0G" voltage "50V" lcsc_pn "C1663" mpn "CL10C330JB8NNNC" + component C_X2: capacitor "c_generic_0603" value "33pF" dielectric "C0G" voltage "50V" lcsc_pn "C1663" mpn "CL10C330JB8NNNC" + component R_X: resistor "r_generic_0603" value "1k" lcsc_pn "C21190" mpn "0603WAF1001T5E" + component R_RUN: resistor "r_generic_0603" value "10k" lcsc_pn "C25804" mpn "0603WAF1002T5E" + component L1: inductor "l_generic_0805" value "3.3uH" lcsc_pn "C98331" mpn "MPL2012S3R3MHT" + component R_AV: resistor "r_generic_0603" value "33" lcsc_pn "C2909394" mpn "FRC0603F33R0TS" + component C_AVF: capacitor "c_generic_0603" value "4.7uF" dielectric "X7R" voltage "10V" lcsc_pn "C18185770" mpn "TCC0603X7R475K100CT" + component C_IO1: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_IO2: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_IO3: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_IO4: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_DV1: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_DV2: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component C_DVB: capacitor "c_generic_0805" value "4.7uF" dielectric "X7R" voltage "10V" lcsc_pn "C354262" mpn "CC0805KKX7R8BB475" + component C_VI: capacitor "c_generic_0603" value "4.7uF" dielectric "X7R" voltage "10V" lcsc_pn "C18185770" mpn "TCC0603X7R475K100CT" + component C_FL: capacitor "c_generic_0603" value "100nF" dielectric "X7R" voltage "10V" lcsc_pn "C14663" mpn "CC0603KRX7R9BB104" + component J3: connector "header_1x3" value "SWD" lcsc_pn "C2937625" mpn "PZ254V-11-03P" + notes "" { + "RP2350 runs from its on-chip regulator: VREG_VIN on +3V3, VREG_LX through L1 3.3uH to the 1.1 V DVDD net, VREG_FB on that net." + "VREG_AVDD and ADC_AVDD are fed from +3V3 through R_AV 33R and C_AVF 4.7uF." + "U4 W25Q128 on the QSPI pins is the boot flash. Y1 ECS-120-20-33-TR 12 MHz, CL 20 pF: 2x 33 pF load caps (33/2 + about 3 pF stray = 19.5 pF), R_X 1k on XOUT." + "J3 SWD: pin 1 SWCLK, pin 2 SWDIO, pin 3 GND. RUN has a 10k pull-up to +3V3." + } + } + + group "USB-C READOUT" color "#be123c" { + component J1: connector "usb_c_receptacle" + component R_CC1: resistor "r_generic_0603" value "5.1k" lcsc_pn "C23186" mpn "0603WAF5101T5E" + component R_CC2: resistor "r_generic_0603" value "5.1k" lcsc_pn "C23186" mpn "0603WAF5101T5E" + component R_DP: resistor "r_generic_0603" value "27" lcsc_pn "C25190" mpn "0603WAF270JT5E" + component R_DN: resistor "r_generic_0603" value "27" lcsc_pn "C25190" mpn "0603WAF270JT5E" + component D1: diode "esd_usb" value "ESD" lcsc_pn "C521915" mpn "ESD5V0B03-323" + component D2: diode "esd_usb" value "ESD" lcsc_pn "C521915" mpn "ESD5V0B03-323" + component U5: regulator "lp5907_3v3" value "LDO" lcsc_pn "C80670" mpn "LP5907MFX-3.3/NOPB" + component C_L1: capacitor "c_generic_0603" value "2.2uF" dielectric "X7R" voltage "16V" lcsc_pn "C43922" mpn "0603B225K160NT" + component C_L2: capacitor "c_generic_0603" value "2.2uF" dielectric "X7R" voltage "16V" lcsc_pn "C43922" mpn "0603B225K160NT" + notes "" { + "USB 2.0 device port, VBUS 5 V in. CC1/CC2 5.1k so a host sources 5 V. 27R series on D+/D-, ESD diodes at the connector." + "VBUS feeds U5 LP5907-3.3 (250 mA) which makes the +3V3 digital rail. No VBUS fuse or TVS: see QUALIFICATION.md." + "The RTD board is a bus-powered USB device: it draws a few tens of mA. No USB-C PD." + } + } + + net "VBUS" { + J1.vbus, J1.vbus_b4, J1.vbus_a9, J1.vbus_b9, U5.vin, U5.en, C_L1.p1 + } + + net "+3V3" { + U5.vout, C_L2.p1, L2.p1, R_AV.p1, + U1.dvdd, C_DV.p1, U1.iovdd, C_IO.p1, R_RST.p1, + U2.iovdd, U2.iovdd2, U2.iovdd3, U2.iovdd4, U2.iovdd5, U2.iovdd6, + C_IO1.p1, C_IO2.p1, C_IO3.p1, C_IO4.p1, + U2.qspi_iovdd, U2.usb_otp_vdd, U2.vreg_vin, C_VI.p1, + U4.vcc, C_FL.p1, R_RUN.p1 + } + + net "+3V3A" { + L2.p2, C_AV2.p1, C_AV1.p1, U1.avdd, U3.vin, C_RI.p1 + } + + net "+3V3_RP_A" { + R_AV.p2, C_AVF.p1, U2.vreg_avdd, U2.adc_avdd + } + + net "DVDD_1V1" { + L1.p2, U2.dvdd, U2.dvdd2, U2.dvdd3, U2.vreg_fb, + C_DV1.p1, C_DV2.p1, C_DVB.p1 + } + + net "VREG_LX" { + U2.vreg_lx, L1.p1 + } + + net "VREF" { + U3.vout, C_RV.p1, U1.refp0 + } + + net "GND" { + U1.avss, U1.avss_sw, U1.ep, U1.refn0, U1.refcom, C_RO.p2, + U1.dgnd, U1.clk, C_DV.p2, C_IO.p2, + U3.gnd, C_RI.p2, C_RV.p2, + C_AV1.p2, C_AV2.p2, + C_CM1.p2, C_CM2.p2, C_F.p2, R_BIAS.p2, + U2.gnd, U2.vreg_pgnd, + C_IO1.p2, C_IO2.p2, C_IO3.p2, C_IO4.p2, + C_DV1.p2, C_DV2.p2, C_DVB.p2, C_VI.p2, C_AVF.p2, + C_X1.p2, C_X2.p2, Y1.gnd_2, Y1.gnd_4, U4.gnd, C_FL.p2, + J3.p3, U5.gnd, C_L1.p2, C_L2.p2, + J1.gnd, J1.gnd_a12, J1.gnd_b1, J1.gnd_b12, J1.shld, + R_CC1.p2, R_CC2.p2, D1.gnd, D2.gnd + } + + // RTD input + connect J2.p1 -> U1.ain0 as "RTD_FP" + connect J2.p1 -> C_F.p1 as "RTD_FP" + connect J2.p2 -> R_S1.p1 as "RTD_SP" + connect R_S1.p2 -> U1.ain1 as "AIN1" + connect R_S1.p2 -> C_D.p1 as "AIN1" + connect R_S1.p2 -> C_CM1.p1 as "AIN1" + connect J2.p3 -> R_S2.p1 as "RTD_SN" + connect R_S2.p2 -> U1.ain2 as "AIN2" + connect R_S2.p2 -> C_D.p2 as "AIN2" + connect R_S2.p2 -> C_CM2.p1 as "AIN2" + connect J2.p4 -> R_BIAS.p1 as "RTD_FN" + connect U1.refout -> C_RO.p1 as "REFOUT" + + // SPI0 on the RP2350 silicon: GPIO0 RX (MISO), GPIO1 CSn, GPIO2 SCK, GPIO3 TX (MOSI). + // SPI and ADC control + connect U2.gp3 -> U1.din as "SPI_MOSI" + connect U2.gp1 -> U1.cs_n as "SPI_CS" + connect U2.gp2 -> U1.sclk as "SPI_SCK" + connect U2.gp0 -> U1.dout_drdy as "SPI_MISO" + connect U2.gp4 -> U1.drdy_n as "ADC_DRDY" + connect U2.gp5 -> U1.start_sync as "ADC_START" + connect U2.gp6 -> U1.reset_n as "ADC_RESET_N" + connect U1.reset_n -> R_RST.p2 as "ADC_RESET_N" + + // RP2350 support + connect U2.xin -> Y1.xtal_a as "XIN" + connect Y1.xtal_a -> C_X1.p1 as "XIN" + connect U2.xout -> R_X.p1 as "XOUT" + connect R_X.p2 -> Y1.xtal_b as "XOUT_R" + connect Y1.xtal_b -> C_X2.p1 as "XOUT_R" + connect U2.run -> R_RUN.p2 as "RUN" + connect U2.swclk -> J3.p1 as "SWCLK" + connect U2.swdio -> J3.p2 as "SWDIO" + connect U2.qspi_ss -> U4.cs as "QSPI_SS" + connect U2.qspi_sclk -> U4.clk as "QSPI_SCLK" + connect U2.qspi_sd0 -> U4.io0 as "QSPI_SD0" + connect U2.qspi_sd1 -> U4.io1 as "QSPI_SD1" + connect U2.qspi_sd2 -> U4.io2 as "QSPI_SD2" + connect U2.qspi_sd3 -> U4.io3 as "QSPI_SD3" + + // USB + connect J1.cc1 -> R_CC1.p1 as "CC1" + connect J1.cc2 -> R_CC2.p1 as "CC2" + connect J1.dp -> J1.dp_b6 as "USB_DP_C" class "USB" + connect J1.dp -> D1.io as "USB_DP_C" + connect J1.dp -> R_DP.p1 as "USB_DP_C" + connect R_DP.p2 -> U2.usb_dp as "USB_DP" class "USB" + connect J1.dn -> J1.dn_b7 as "USB_DN_C" class "USB" + connect J1.dn -> D2.io as "USB_DN_C" + connect J1.dn -> R_DN.p1 as "USB_DN_C" + connect R_DN.p2 -> U2.usb_dn as "USB_DN" class "USB" +} diff --git a/registry/parts/connectors/header_1x3.synth.toml b/registry/parts/connectors/header_1x3.synth.toml index a2865aa7c..3c90d2d4f 100644 --- a/registry/parts/connectors/header_1x3.synth.toml +++ b/registry/parts/connectors/header_1x3.synth.toml @@ -23,3 +23,7 @@ electrical_type = "passive" name = "p3" number = "3" electrical_type = "passive" + +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/connectors/header_1x4.synth.toml b/registry/parts/connectors/header_1x4.synth.toml index c6f794e78..11f6baf6e 100644 --- a/registry/parts/connectors/header_1x4.synth.toml +++ b/registry/parts/connectors/header_1x4.synth.toml @@ -37,3 +37,6 @@ name = "p4" number = "4" electrical_type = "passive" +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/connectors/usb_c_receptacle.synth.toml b/registry/parts/connectors/usb_c_receptacle.synth.toml index b3915c445..e877d6ed9 100644 --- a/registry/parts/connectors/usb_c_receptacle.synth.toml +++ b/registry/parts/connectors/usb_c_receptacle.synth.toml @@ -1,6 +1,6 @@ id = "usb_c_receptacle" kind = "connector" -description = "USB-C receptacle, 24-pin SMD. Modelled here with primary and mirrored power/ground/data pins for full pad coverage." +description = "USB-C receptacle, 16-pin SMD (HRO TYPE-C-31-M-12). Modelled here with primary and mirrored power/ground/data pins for full pad coverage." mpn = "TYPE-C-31-M-12" lcsc_pn = "C165948" kicad_symbol = "Connector:USB_C_Receptacle" @@ -114,3 +114,8 @@ electrical_type = "passive" name = "sbu2" number = "B8" electrical_type = "passive" + +[provenance] +datasheet_url = "https://datasheet.lcsc.com/datasheet/pdf/9e56b777c022540fcce7c7f67825f55e.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/crystals/ecs_120_20_33_tr.synth.toml b/registry/parts/crystals/ecs_120_20_33_tr.synth.toml index f67810bb6..f594cc7b2 100644 --- a/registry/parts/crystals/ecs_120_20_33_tr.synth.toml +++ b/registry/parts/crystals/ecs_120_20_33_tr.synth.toml @@ -34,3 +34,5 @@ electrical_type = "passive" [provenance] datasheet_url = "https://ecsxtal.com/store/pdf/ecx-32.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/crystals/xtal_32mhz_nrf.synth.toml b/registry/parts/crystals/xtal_32mhz_nrf.synth.toml new file mode 100644 index 000000000..002010630 --- /dev/null +++ b/registry/parts/crystals/xtal_32mhz_nrf.synth.toml @@ -0,0 +1,52 @@ +id = "xtal_32mhz_nrf" +kind = "crystal" +version = 0 +lifecycle = "active" +description = "Abracon ABM11W 32 MHz crystal, CL 8 pF, 2.0 x 1.6 mm 4-pad SMD, for the nRF52840 HFXO; pads 1 and 3 are the crystal, 2 and 4 are ground. Load capacitors C1 = C2 = 12 pF NP0 from each pad to ground (Nordic reference circuit)" +# Ordering stem per the ABM11W datasheet scheme (frequency, load pF); the tolerance and packaging suffix is chosen at purchase. +mpn = "ABM11W-32.0000MHZ-8" +kicad_symbol = "Device:Crystal_GND24" +kicad_footprint = "Crystal:Crystal_SMD_2016-4Pin_2.0x1.6mm" + +[footprint_dimensions] +width_mm = 2.3 +height_mm = 1.9 +courtyard_margin_mm = 0.25 + +[[pins]] +name = "xtal_a" +number = "1" +electrical_type = "passive" + +[[pins]] +name = "gnd_2" +number = "2" +electrical_type = "passive" + +[[pins]] +name = "xtal_b" +number = "3" +electrical_type = "passive" + +[[pins]] +name = "gnd_4" +number = "4" +electrical_type = "passive" + +# Load capacitors: CL = C1*C2/(C1+C2) + C_pin + C_pcb = 6 + 3 + ~2-3 = ~8 pF (nRF52840 PS: CPIN 3 pF; Nordic BOM C1,C2 12 pF NP0). +[[required_decoupling]] +net = "xtal_a" +value = "12pf" +count = 1 + +[[required_decoupling]] +net = "xtal_b" +value = "12pf" +count = 1 + +[provenance] +source = "imported" +generator = "synth-part-import-kicad 0.1" +datasheet_url = "https://abracon.com/Resonators/ABM11W.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-10-27" diff --git a/registry/parts/ic/ads124s08.synth.toml b/registry/parts/ic/ads124s08.synth.toml new file mode 100644 index 000000000..3d52f3ee2 --- /dev/null +++ b/registry/parts/ic/ads124s08.synth.toml @@ -0,0 +1,227 @@ +id = "ads124s08" +kind = "ic" +version = 0 +lifecycle = "active" +description = "TI ADS124S08 24-bit delta-sigma ADC, 12 inputs, PGA, 2.5 V reference, dual IDACs, SPI, VQFN-32 (RHB0032M, 5x5 mm, exposed pad)" +mpn = "ADS124S08IRHBR" +kicad_footprint = "Package_DFN_QFN:Texas_RHB0032M_VQFN-32-1EP_5x5mm_P0.5mm_EP2.1x2.1mm" + +[footprint_dimensions] +width_mm = 5.0 +height_mm = 5.0 +courtyard_margin_mm = 0.25 + +[operating_conditions] +min_voltage_v = 2.7 +max_voltage_v = 5.25 + +[[pins]] +name = "aincom" +number = "1" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain5" +number = "2" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain4" +number = "3" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain3" +number = "4" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain2" +number = "5" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain1" +number = "6" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ain0" +number = "7" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "start_sync" +number = "8" +electrical_type = "input" + +[[pins]] +name = "cs_n" +number = "9" +electrical_type = "input" +capabilities = ["spi_cs"] +required = true + +[[pins]] +name = "din" +number = "10" +electrical_type = "input" +capabilities = ["spi_mosi"] +required = true + +[[pins]] +name = "sclk" +number = "11" +electrical_type = "input" +capabilities = ["spi_sck"] +required = true + +[[pins]] +name = "dout_drdy" +number = "12" +electrical_type = "output" +capabilities = ["spi_miso"] +required = true + +[[pins]] +name = "drdy_n" +number = "13" +electrical_type = "output" + +[[pins]] +name = "dgnd" +number = "14" +electrical_type = "ground_reference" +required = true + +[[pins]] +name = "iovdd" +number = "15" +electrical_type = "power_input" +required = true + +[[pins]] +name = "dvdd" +number = "16" +electrical_type = "power_input" +required = true + +[[pins]] +name = "clk" +number = "17" +electrical_type = "clock" +capabilities = ["clock_input"] + +[[pins]] +name = "reset_n" +number = "18" +electrical_type = "input" +capabilities = ["reset"] + +[[pins]] +name = "gpio3_ain11" +number = "19" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "gpio2_ain10" +number = "20" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "gpio1_ain9" +number = "21" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "gpio0_ain8" +number = "22" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "refout" +number = "23" +electrical_type = "analog" + +[[pins]] +name = "refcom" +number = "24" +electrical_type = "analog" + +[[pins]] +name = "nc" +number = "25" +electrical_type = "do_not_connect" + +[[pins]] +name = "avdd" +number = "26" +electrical_type = "power_input" +required = true + +[[pins]] +name = "avss" +number = "27" +electrical_type = "ground_reference" +required = true + +[[pins]] +name = "avss_sw" +number = "28" +electrical_type = "passive" +required = true + +[[pins]] +name = "refn0" +number = "29" +electrical_type = "analog" + +[[pins]] +name = "refp0" +number = "30" +electrical_type = "analog" + +[[pins]] +name = "refn1_ain7" +number = "31" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "refp1_ain6" +number = "32" +electrical_type = "analog" +capabilities = ["analog_input"] + +[[pins]] +name = "ep" +number = "33" +electrical_type = "ground_reference" +required = true + +[[required_decoupling]] +net = "avdd" +value = "330nf" +count = 1 + +[[required_decoupling]] +net = "dvdd" +value = "100nf" +count = 1 + +[provenance] +source = "authored" +datasheet_url = "https://www.ti.com/lit/ds/symlink/ads124s08.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-10-27" diff --git a/registry/parts/ic/bme280.synth.toml b/registry/parts/ic/bme280.synth.toml new file mode 100644 index 000000000..945478ad3 --- /dev/null +++ b/registry/parts/ic/bme280.synth.toml @@ -0,0 +1,87 @@ +id = "bme280" +kind = "sensor" +version = 0 +lifecycle = "active" +description = "Bosch BME280 combined humidity, pressure and temperature sensor, I2C/SPI, LGA-8 2.5 x 2.5 mm" +mpn = "BME280" +kicad_symbol = "Sensor:BME280" +kicad_footprint = "Package_LGA:Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering" + +[footprint_dimensions] +width_mm = 2.5 +height_mm = 2.5 +courtyard_margin_mm = 0.25 + +# VDD 1.71-3.6 V, VDDIO 1.2-3.6 V (datasheet table 1, electrical specification). +[operating_conditions] +min_voltage_v = 1.71 +max_voltage_v = 3.6 + +[[pins]] +name = "gnd_1" +number = "1" +electrical_type = "power_input" +required = true + +# I2C mode: CSB tied to VDDIO. +[[pins]] +name = "csb" +number = "2" +electrical_type = "input" +required = true + +[[pins]] +name = "sda" +number = "3" +electrical_type = "bidirectional" +capabilities = ["i2c_sda"] +required = true + +[[pins]] +name = "scl" +number = "4" +electrical_type = "input" +capabilities = ["i2c_scl"] +required = true + +# I2C address select: GND = 0x76, VDDIO = 0x77. +[[pins]] +name = "sdo" +number = "5" +electrical_type = "input" +required = true + +[[pins]] +name = "vddio" +number = "6" +electrical_type = "power_input" +required = true + +[[pins]] +name = "gnd_7" +number = "7" +electrical_type = "power_input" +required = true + +[[pins]] +name = "vdd" +number = "8" +electrical_type = "power_input" +required = true + +[[required_decoupling]] +net = "vdd" +value = "100nf" +count = 1 + +[[required_decoupling]] +net = "vddio" +value = "100nf" +count = 1 + +[provenance] +source = "imported" +generator = "synth-part-import-kicad 0.1" +datasheet_url = "https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme280-ds002.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-10-27" diff --git a/registry/parts/ic/ref5025.synth.toml b/registry/parts/ic/ref5025.synth.toml new file mode 100644 index 000000000..77f9d15b4 --- /dev/null +++ b/registry/parts/ic/ref5025.synth.toml @@ -0,0 +1,77 @@ +id = "ref5025" +kind = "ic" +version = 0 +lifecycle = "active" +description = "TI REF5025ID 2.5 V low-noise, low-drift precision voltage reference, 10 mA, SOIC-8" +mpn = "REF5025AIDR" +kicad_symbol = "Reference_Voltage:REF5025ID" +kicad_footprint = "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" + +[footprint_dimensions] +width_mm = 3.9 +height_mm = 4.9 +courtyard_margin_mm = 0.25 + +[operating_conditions] +min_voltage_v = 2.7 +max_voltage_v = 18.0 + +[[pins]] +name = "dnc_1" +number = "1" +electrical_type = "do_not_connect" + +[[pins]] +name = "vin" +number = "2" +electrical_type = "power_input" +required = true + +[[pins]] +name = "temp" +number = "3" +electrical_type = "analog" + +[[pins]] +name = "gnd" +number = "4" +electrical_type = "ground_reference" +required = true + +[[pins]] +name = "trim_nr" +number = "5" +electrical_type = "passive" + +[[pins]] +name = "vout" +number = "6" +electrical_type = "power_output" +required = true + +[[pins]] +name = "nc" +number = "7" +electrical_type = "do_not_connect" + +[[pins]] +name = "dnc_8" +number = "8" +electrical_type = "do_not_connect" + +[[required_decoupling]] +net = "vin" +value = "1uf" +count = 1 + +[[required_decoupling]] +net = "vout" +value = "1uf" +count = 1 + +[provenance] +source = "imported" +generator = "synth-part-import-kicad 0.1" +datasheet_url = "https://www.ti.com/lit/ds/gpn/ref5025" +reviewed_by = "Steve Munene" +reviewed_at = "2026-10-27" diff --git a/registry/parts/mcus/rp2350.synth.toml b/registry/parts/mcus/rp2350.synth.toml index 361430673..587e432d9 100644 --- a/registry/parts/mcus/rp2350.synth.toml +++ b/registry/parts/mcus/rp2350.synth.toml @@ -12,7 +12,7 @@ kind = "mcu" description = "Raspberry Pi RP2350 dual-core MCU, QFN-60" kicad_symbol = "MCU_RaspberryPi:RP2350A" kicad_footprint = "Package_DFN_QFN:QFN-60-1EP_7x7mm_P0.4mm_EP3.4x3.4mm" -lcsc_pn = "C14663" +lcsc_pn = "C42411118" mpn = "RP2350A" @@ -81,7 +81,7 @@ capabilities = ["usb_dn"] name = "gp0" number = "2" electrical_type = "bidirectional" -capabilities = ["gpio", "spi_mosi", "uart_tx", "i2c_sda"] +capabilities = ["gpio", "spi_miso", "uart_tx", "i2c_sda"] [[pins]] name = "gp1" @@ -99,7 +99,7 @@ capabilities = ["gpio", "spi_sck", "uart_tx"] name = "gp3" number = "5" electrical_type = "bidirectional" -capabilities = ["gpio", "spi_miso", "uart_rx"] +capabilities = ["gpio", "spi_mosi", "uart_rx"] [[pins]] name = "gp4" @@ -404,9 +404,14 @@ capabilities = ["spi_cs"] [[required_decoupling]] net = "iovdd" value = "100nf" -count = 4 +count = 7 [[required_decoupling]] net = "dvdd" value = "100nf" -count = 2 +count = 3 + +[provenance] +datasheet_url = "https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/mechanical/mounting_hole_m2_5_clearance.synth.toml b/registry/parts/mechanical/mounting_hole_m2_5_clearance.synth.toml new file mode 100644 index 000000000..0cbdbeb68 --- /dev/null +++ b/registry/parts/mechanical/mounting_hole_m2_5_clearance.synth.toml @@ -0,0 +1,17 @@ +id = "mounting_hole_m2_5_clearance" +kind = "mounting_hole" +description = "M2.5 clearance mounting hole (2.7 mm NPTH) for a screw that passes through the board" +kicad_symbol = "Mechanical:MountingHole" +kicad_footprint = "MountingHole:MountingHole_2.7mm_M2.5" + +# 2.7 mm is the hole, the ISO 273 fine clearance for M2.5. +# `MountingHole:MountingHole_2.7mm_M2.5` draws its courtyard as an fp_circle of +# radius 2.95 mm, so the footprint is 5.9 mm across. +[footprint_dimensions] +width_mm = 2.7 +height_mm = 2.7 +courtyard_margin_mm = 1.6 + +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/memory/w25q128_flash_208mil.synth.toml b/registry/parts/memory/w25q128_flash_208mil.synth.toml new file mode 100644 index 000000000..0938d86ea --- /dev/null +++ b/registry/parts/memory/w25q128_flash_208mil.synth.toml @@ -0,0 +1,78 @@ +id = "w25q128_flash_208mil" +kind = "memory" +description = "Winbond W25Q128JVSIQ 128Mbit SPI NOR flash, SOIC-8 208 mil (5.28 mm body, 7.9 mm lead span)" +mpn = "W25Q128JVSIQ" +lcsc_pn = "C97521" +kicad_symbol = "Memory_Flash:W25Q128JVS" +kicad_footprint = "Package_SO:SOIC-8_5.3x5.3mm_P1.27mm" + +[footprint_dimensions] +width_mm = 8.8 +height_mm = 4.46 +courtyard_margin_mm = 0.25 + +[operating_conditions] +min_voltage_v = 2.7 +max_voltage_v = 3.6 +max_current_ma = 50.0 + +[[pins]] +name = "cs" +number = "1" +electrical_type = "input" +capabilities = ["spi_cs"] +required = true + +[[pins]] +name = "io1" +number = "2" +electrical_type = "bidirectional" +capabilities = ["spi_miso", "spi_mosi"] +required = true + +[[pins]] +name = "io2" +number = "3" +electrical_type = "bidirectional" +capabilities = ["spi_miso", "spi_mosi"] + +[[pins]] +name = "gnd" +number = "4" +electrical_type = "power_input" +required = true + +[[pins]] +name = "io0" +number = "5" +electrical_type = "bidirectional" +capabilities = ["spi_miso", "spi_mosi"] +required = true + +[[pins]] +name = "clk" +number = "6" +electrical_type = "input" +capabilities = ["spi_sck"] +required = true + +[[pins]] +name = "io3" +number = "7" +electrical_type = "bidirectional" +capabilities = ["spi_miso", "spi_mosi"] + +[[pins]] +name = "vcc" +number = "8" +electrical_type = "power_input" +required = true + +[[required_decoupling]] +net = "vcc" +value = "100nf" +count = 1 + +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/passives/ferrite_bead_0603.synth.toml b/registry/parts/passives/ferrite_bead_0603.synth.toml index 6688c3dad..210d36bb9 100644 --- a/registry/parts/passives/ferrite_bead_0603.synth.toml +++ b/registry/parts/passives/ferrite_bead_0603.synth.toml @@ -22,3 +22,6 @@ name = "p2" number = "2" electrical_type = "passive" +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/passives/l_generic_0805.synth.toml b/registry/parts/passives/l_generic_0805.synth.toml index d20abdbf1..e5f73714c 100644 --- a/registry/parts/passives/l_generic_0805.synth.toml +++ b/registry/parts/passives/l_generic_0805.synth.toml @@ -22,3 +22,6 @@ name = "p2" number = "2" electrical_type = "passive" +[provenance] +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/protection/esd_usb.synth.toml b/registry/parts/protection/esd_usb.synth.toml index c02df79e8..a6e80e95c 100644 --- a/registry/parts/protection/esd_usb.synth.toml +++ b/registry/parts/protection/esd_usb.synth.toml @@ -10,8 +10,7 @@ height_mm = 1.9 courtyard_margin_mm = 0.25 [operating_conditions] -max_voltage_v = 100.0 -max_current_ma = 1000.0 +max_voltage_v = 5.0 [[pins]] name = "io" @@ -22,3 +21,8 @@ electrical_type = "passive" name = "gnd" number = "2" electrical_type = "passive" + +[provenance] +datasheet_url = "https://datasheet.lcsc.com/datasheet/pdf/a868537aef07f89b854d39bc70b9a4b4.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-11-05" diff --git a/registry/parts/regulators/lp5907_3v3.synth.toml b/registry/parts/regulators/lp5907_3v3.synth.toml index 297dff646..20f297e5c 100644 --- a/registry/parts/regulators/lp5907_3v3.synth.toml +++ b/registry/parts/regulators/lp5907_3v3.synth.toml @@ -57,3 +57,9 @@ net = "vout" value = "1uf" count = 1 + +[provenance] +source = "authored" +datasheet_url = "https://www.ti.com/lit/ds/symlink/lp5907.pdf" +reviewed_by = "Steve Munene" +reviewed_at = "2026-10-27"