From 1a53cbefe2bfbde896d0c3d4a7c3f065a27e555a Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Wed, 30 Sep 2026 10:32:01 +0800 Subject: [PATCH 01/11] dt-bindings: riscv: zhihe: rename A210 board to Melon Pi dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 board is marketed as the Melon Pi. Replace its generic compatible string with the product-specific name. Signed-off-by: Zhiguo Zhu --- Documentation/devicetree/bindings/riscv/zhihe.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/zhihe.yaml b/Documentation/devicetree/bindings/riscv/zhihe.yaml index 2cfff7665b040..724e6c5fc66ee 100644 --- a/Documentation/devicetree/bindings/riscv/zhihe.yaml +++ b/Documentation/devicetree/bindings/riscv/zhihe.yaml @@ -20,7 +20,7 @@ properties: - description: Zhihe A210 evaluation board items: - enum: - - zhihe,a210-dev + - zhihe,melon-pi - zhihe,a210-evb - const: zhihe,a210 From 42a476b2eac26ca02059777ec126195b169a880b Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Wed, 30 Sep 2026 10:32:02 +0800 Subject: [PATCH 02/11] riscv: dts: zhihe: rename A210 board to Melon Pi dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 board is marketed as the Melon Pi. Rename its DTS, model, and compatible strings to use the board's product name. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/Makefile | 2 +- arch/riscv/boot/dts/zhihe/{a210-dev.dts => a210-melon-pi.dts} | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/zhihe/{a210-dev.dts => a210-melon-pi.dts} (98%) diff --git a/arch/riscv/boot/dts/zhihe/Makefile b/arch/riscv/boot/dts/zhihe/Makefile index 22f3b16152880..acb14b258bf06 100644 --- a/arch/riscv/boot/dts/zhihe/Makefile +++ b/arch/riscv/boot/dts/zhihe/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ZHIHE) += a210-evb.dtb a210-dev.dtb +dtb-$(CONFIG_ARCH_ZHIHE) += a210-evb.dtb a210-melon-pi.dtb diff --git a/arch/riscv/boot/dts/zhihe/a210-dev.dts b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts similarity index 98% rename from arch/riscv/boot/dts/zhihe/a210-dev.dts rename to arch/riscv/boot/dts/zhihe/a210-melon-pi.dts index 4ce480e525274..d6945f3cdb93e 100644 --- a/arch/riscv/boot/dts/zhihe/a210-dev.dts +++ b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts @@ -4,8 +4,8 @@ #include "a210.dtsi" / { - model = "Zhihe A210 Development Board"; - compatible = "zhihe,a210-dev", "zhihe,a210"; + model = "Zhihe Melon Pi"; + compatible = "zhihe,melon-pi", "zhihe,a210"; aliases { ethernet0 = &gmac0; From f930ce7b472ea40af5d8fb9a981f02182967b2b1 Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 03/11] dt-bindings: dma: snps,dw-axi-dmac: add ZhiHe A210 dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- Allow the ZhiHe A210 AXI DMAC compatible string in the DW AXI DMAC binding. Signed-off-by: Zhiguo Zhu --- .../bindings/dma/snps,dw-axi-dmac.yaml | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 363cf8bd150da..26422a863c931 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -14,6 +14,27 @@ description: allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: zhihe,a210-axi-dma + then: + properties: + dma-channels: + maximum: 16 + snps,priority: + maxItems: 16 + snps,block-size: + maxItems: 16 + else: + properties: + dma-channels: + maximum: 8 + snps,priority: + maxItems: 8 + snps,block-size: + maxItems: 8 properties: compatible: @@ -21,6 +42,7 @@ properties: - snps,axi-dma-1.01a - intel,kmb-axi-dma - starfive,jh7110-axi-dma + - zhihe,a210-axi-dma reg: minItems: 1 @@ -56,7 +78,7 @@ properties: dma-channels: minimum: 1 - maximum: 8 + maximum: 16 resets: minItems: 1 @@ -80,14 +102,14 @@ properties: Channel priority specifier associated with the DMA channels. $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 - maxItems: 8 + maxItems: 16 snps,block-size: description: | Channel block size specifier associated with the DMA channels. $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 - maxItems: 8 + maxItems: 16 snps,axi-max-burst-len: description: | @@ -117,6 +139,7 @@ if: contains: enum: - starfive,jh7110-axi-dma + - zhihe,a210-axi-dma then: properties: resets: From 67ca24bd6afaf7bc4c38ccec9562c418c510e290 Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 04/11] dmaengine: dw-axi-dmac: add ZhiHe A210 support dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- Add ZhiHe A210 compatible data to the DW AXI DMAC platform driver. Signed-off-by: Zhiguo Zhu --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index f6a1fa7fadd17..1d23a689e6263 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1675,6 +1675,9 @@ static const struct of_device_id dw_dma_of_id_table[] = { }, { .compatible = "xuantie,th1520-axi-dma", .data = (void *)(AXI_DMA_FLAG_USE_CFG2), + }, { + .compatible = "zhihe,a210-axi-dma", + .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2), }, {} }; From 4fde0290720836a5ab6b0fc1d2155c9f9a1fa485 Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 05/11] riscv: dts: zhihe: add A210 DMA controllers dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 has a 16-channel AXI DMAC for peripheral transfers and a 4-channel AXI DMAC in the trusted execution environment. Add the DMA controller nodes for the ZhiHe A210 SoC. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210.dtsi | 37 +++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index b41f273dc44e2..669f933b7092c 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -909,6 +909,43 @@ resets = <&rst_peri0 PERI0_WDT0_PRST>; }; + dmac0: dma-controller@520000 { + compatible = "zhihe,a210-axi-dma"; + reg = <0x00 0x00520000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <264>; + clocks = <&clk_peri PERI3_DMAC_ACLK_EN>, <&clk_peri PERI3_DMAC_HCLK_EN>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&rst_peri3 PERI3_DMAC_ARST>, <&rst_peri3 PERI3_DMAC_HRST>; + #dma-cells = <1>; + dma-channels = <16>; + snps,block-size = <65536 65536 65536 65536 + 65536 65536 65536 65536 + 65536 65536 65536 65536 + 65536 65536 65536 65536>; + snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <4>; + }; + + dmac1: dma-controller@27540000 { + compatible = "zhihe,a210-axi-dma"; + reg = <0x00 0x27540000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <259>; + clocks = <&clk_peri TEE_DMAC_CLKEN>, <&clk_peri TEE_DMAC_CLKEN>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&rst_tee TEE_DMAC_ARST>, <&rst_tee TEE_DMAC_HRST>; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 0 0 0>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + }; + uart0: serial@2014000 { compatible = "snps,dw-apb-uart"; reg = <0x00 0x02014000 0x0 0x400>; From 9f1fdc76b3d4067fe62990b00360847e7357a6dd Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 06/11] riscv: dts: zhihe: add A210 GPIO controllers dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 provides two always-on GPIO banks and five peripheral GPIO banks. Each bank also supplies a GPIO interrupt controller. Add the controller nodes and keep them disabled until a board selects the banks that are routed for use. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210.dtsi | 166 ++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index 669f933b7092c..e7b8557346e9d 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -1175,6 +1175,172 @@ clock-names = "pclk"; }; + aon_gpio0: gpio@30841000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x30841000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&aon_110m>, <&osc_32k>; + clock-names = "bus", "db"; + status = "disabled"; + + ao_gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <17>; + }; + }; + + aon_gpio1: gpio@30897000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x30897000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&aon_110m>, <&osc_32k>; + clock-names = "bus", "db"; + status = "disabled"; + + ao_gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <10>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <10>; + }; + }; + + peri1_gpio0: gpio@2012000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x02012000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_peri PERI1_GPIO0_PCLK_EN>, + <&clk_peri PERI1_GPIO0_DBCLK_EN>; + clock-names = "bus", "db"; + status = "disabled"; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <289>; + }; + }; + + peri1_gpio1: gpio@2013000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x02013000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_peri PERI1_GPIO1_PCLK_EN>, + <&clk_peri PERI1_GPIO1_DBCLK_EN>; + clock-names = "bus", "db"; + status = "disabled"; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <18>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <290>; + }; + }; + + peri2_gpio2: gpio@8410000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x08410000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_peri PERI2_GPIO2_PCLK_EN>, + <&clk_peri PERI2_GPIO2_DBCLK_EN>; + clock-names = "bus", "db"; + status = "disabled"; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <291>; + }; + }; + + peri2_gpio3: gpio@8412000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x08412000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_peri PERI2_GPIO3_PCLK_EN>, + <&clk_peri PERI2_GPIO3_DBCLK_EN>; + clock-names = "bus", "db"; + status = "disabled"; + + gpio3: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <11>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <292>; + }; + }; + + peri3_gpio: gpio@550000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x00550000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_peri PERI3_GPIO4_PCLK_EN>, + <&clk_peri PERI3_GPIO4_DBCLK_EN>; + clock-names = "bus", "db"; + status = "disabled"; + + gpio4: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <52>; + }; + }; + mbox_920: mailbox@321000 { compatible = "zhihe,a210-mailbox-v2"; reg = <0x00 0x00321000 0x0 0x1000>, From 881d3f11207872a9be86649cc88657dc03344c0d Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 07/11] riscv: dts: zhihe: add A210 DW APB timers dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 has eight DesignWare APB timer channels arranged in two four-channel blocks with shared clocks and resets. Add the timer channel nodes for the ZhiHe A210 SoC. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210.dtsi | 88 +++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index e7b8557346e9d..57be3e9083d95 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -1341,6 +1341,94 @@ }; }; + timer0: timer@303000 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00303000 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <313>; + clocks = <&clk_peri PERI0_TIMER0_CCLK_EN>, + <&clk_peri PERI0_TIMER0_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER0_RST>; + }; + + timer1: timer@303014 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00303014 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <314>; + clocks = <&clk_peri PERI0_TIMER0_CCLK_EN>, + <&clk_peri PERI0_TIMER0_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER0_RST>; + }; + + timer2: timer@303028 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00303028 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <315>; + clocks = <&clk_peri PERI0_TIMER0_CCLK_EN>, + <&clk_peri PERI0_TIMER0_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER0_RST>; + }; + + timer3: timer@30303c { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x0030303c 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <316>; + clocks = <&clk_peri PERI0_TIMER0_CCLK_EN>, + <&clk_peri PERI0_TIMER0_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER0_RST>; + }; + + timer4: timer@304000 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00304000 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <317>; + clocks = <&clk_peri PERI0_TIMER1_CCLK_EN>, + <&clk_peri PERI0_TIMER1_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER1_RST>; + }; + + timer5: timer@304014 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00304014 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <318>; + clocks = <&clk_peri PERI0_TIMER1_CCLK_EN>, + <&clk_peri PERI0_TIMER1_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER1_RST>; + }; + + timer6: timer@304028 { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x00304028 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <319>; + clocks = <&clk_peri PERI0_TIMER1_CCLK_EN>, + <&clk_peri PERI0_TIMER1_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER1_RST>; + }; + + timer7: timer@30403c { + compatible = "snps,dw-apb-timer"; + reg = <0x00 0x0030403c 0x0 0x14>; + interrupt-parent = <&intc>; + interrupts = <320>; + clocks = <&clk_peri PERI0_TIMER1_CCLK_EN>, + <&clk_peri PERI0_TIMER1_PCLK_EN>; + clock-names = "timer", "pclk"; + resets = <&rst_peri0 PERI0_TIMER1_RST>; + }; + mbox_920: mailbox@321000 { compatible = "zhihe,a210-mailbox-v2"; reg = <0x00 0x00321000 0x0 0x1000>, From 6d2b7c96f3e915af4095d59f6ed462f5112b49db Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:14 +0800 Subject: [PATCH 08/11] riscv: dts: zhihe: add A210 I2C controllers dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 provides eight peripheral DesignWare I2C controllers and one controller in the always-on subsystem. Add the controller nodes and keep them disabled until enabled by a board that routes the corresponding buses. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210.dtsi | 126 ++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index 57be3e9083d95..d68bc6805f7ef 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -1429,6 +1429,132 @@ resets = <&rst_peri0 PERI0_TIMER1_RST>; }; + i2c0: i2c@2020000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x02020000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <293>; + clocks = <&clk_peri PERI1_I2C0_IC_CLK_EN>, + <&clk_peri PERI1_I2C0_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri1 PERI1_I2C0_RST>; + dmas = <&dmac0 21>, <&dmac0 20>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2021000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x02021000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <294>; + clocks = <&clk_peri PERI1_I2C1_IC_CLK_EN>, + <&clk_peri PERI1_I2C1_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri1 PERI1_I2C1_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2022000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x02022000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <295>; + clocks = <&clk_peri PERI1_I2C2_IC_CLK_EN>, + <&clk_peri PERI1_I2C2_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri1 PERI1_I2C2_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@8415000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x08415000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <296>; + clocks = <&clk_peri PERI2_I2C3_IC_CLK_EN>, + <&clk_peri PERI2_I2C3_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri2 PERI2_I2C3_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@8416000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x08416000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <297>; + clocks = <&clk_peri PERI2_I2C4_IC_CLK_EN>, + <&clk_peri PERI2_I2C4_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri2 PERI2_I2C4_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@8417000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x08417000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <298>; + clocks = <&clk_peri PERI2_I2C5_IC_CLK_EN>, + <&clk_peri PERI2_I2C5_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri2 PERI2_I2C5_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@8418000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x08418000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <299>; + clocks = <&clk_peri PERI2_I2C6_IC_CLK_EN>, + <&clk_peri PERI2_I2C6_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri2 PERI2_I2C6_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@8419000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x08419000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <300>; + clocks = <&clk_peri PERI2_I2C7_IC_CLK_EN>, + <&clk_peri PERI2_I2C7_PCLK_EN>; + clock-names = "ref", "pclk"; + resets = <&rst_peri2 PERI2_I2C7_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + aoi2c1: i2c@30891000 { + compatible = "snps,designware-i2c"; + reg = <0x00 0x30891000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <20>; + clocks = <&aon_110m>; + clock-names = "ref"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mbox_920: mailbox@321000 { compatible = "zhihe,a210-mailbox-v2"; reg = <0x00 0x00321000 0x0 0x1000>, From 3d4be82fea69d0971fa70a0fbb5d6bb3f3cb1a51 Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:14 +0800 Subject: [PATCH 09/11] riscv: dts: zhihe: add A210 SPI controllers dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 has two DesignWare APB SSI controllers with DMA support and two chip selects per controller. Add the controller nodes and keep them disabled until enabled by a board that routes the corresponding buses. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210.dtsi | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index d68bc6805f7ef..647dc197675f5 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -1066,6 +1066,42 @@ reg-io-width = <4>; }; + spi0: spi@2023000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x00 0x02023000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <310>; + clocks = <&clk_peri PERI1_SPI0_SSI_CLK_EN>, + <&clk_peri PERI1_SPI0_PCLK_EN>; + clock-names = "ssi_clk", "pclk"; + resets = <&rst_peri1 PERI1_SPI0_RST>; + reset-names = "spi"; + dmas = <&dmac0 9>, <&dmac0 8>; + dma-names = "tx", "rx"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@8413000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x00 0x08413000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <311>; + clocks = <&clk_peri PERI2_SPI1_SSI_CLK_EN>, + <&clk_peri PERI2_SPI1_PCLK_EN>; + clock-names = "ssi_clk", "pclk"; + resets = <&rst_peri2 PERI2_SPI1_RST>; + reset-names = "spi"; + dmas = <&dmac0 62>, <&dmac0 61>; + dma-names = "tx", "rx"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + emmc: mmc@500000 { compatible = "zhihe,a210-dwcmshc"; reg = <0x0 0x00500000 0x0 0x10000>; From 3dfaf0eca3ac4da85896744d59fd3948b9072131 Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:13 +0800 Subject: [PATCH 10/11] riscv: dts: zhihe: enable GPIO controllers on A210 boards dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- Enable the GPIO banks available on the A210 evaluation board and Melon Pi. Keep the EVB peripheral GPIO 3 bank disabled because its associated pad controller is not used on that board. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210-evb.dts | 24 ++++++++++++++++++ arch/riscv/boot/dts/zhihe/a210-melon-pi.dts | 28 +++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/riscv/boot/dts/zhihe/a210-evb.dts b/arch/riscv/boot/dts/zhihe/a210-evb.dts index 90f9564cb683a..2e929a56d1081 100644 --- a/arch/riscv/boot/dts/zhihe/a210-evb.dts +++ b/arch/riscv/boot/dts/zhihe/a210-evb.dts @@ -527,3 +527,27 @@ }; /delete-node/ &power; + +&aon_gpio0 { + status = "okay"; +}; + +&aon_gpio1 { + status = "okay"; +}; + +&peri1_gpio0 { + status = "okay"; +}; + +&peri1_gpio1 { + status = "okay"; +}; + +&peri2_gpio2 { + status = "okay"; +}; + +&peri2_gpio3 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts index d6945f3cdb93e..946a720f4ba8d 100644 --- a/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts +++ b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts @@ -443,3 +443,31 @@ &uart9 { status = "disabled"; }; + +&aon_gpio0 { + status = "okay"; +}; + +&aon_gpio1 { + status = "okay"; +}; + +&peri1_gpio0 { + status = "okay"; +}; + +&peri1_gpio1 { + status = "okay"; +}; + +&peri2_gpio2 { + status = "okay"; +}; + +&peri2_gpio3 { + status = "okay"; +}; + +&peri3_gpio { + status = "okay"; +}; From 361c718191f5f55aa1d3206a5ff00173b78e2c9e Mon Sep 17 00:00:00 2001 From: Zhiguo Zhu Date: Mon, 21 Sep 2026 16:16:14 +0800 Subject: [PATCH 11/11] riscv: dts: zhihe: disable unused A210 UARTs by default dist inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck/issues/381 -------------------------------- The A210 contains ten DesignWare APB UART instances, but only a subset is routed and used on each board. Disable the UARTs in the SoC description. Enable UART4 as the EVB console and UART4, UART5, and UART8 on the Melon Pi. Signed-off-by: Zhiguo Zhu --- arch/riscv/boot/dts/zhihe/a210-evb.dts | 37 +-------------------- arch/riscv/boot/dts/zhihe/a210-melon-pi.dts | 31 ++--------------- arch/riscv/boot/dts/zhihe/a210.dtsi | 10 ++++++ 3 files changed, 14 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/zhihe/a210-evb.dts b/arch/riscv/boot/dts/zhihe/a210-evb.dts index 2e929a56d1081..32f8c73ba8f8f 100644 --- a/arch/riscv/boot/dts/zhihe/a210-evb.dts +++ b/arch/riscv/boot/dts/zhihe/a210-evb.dts @@ -392,6 +392,7 @@ }; &uart4 { + status = "okay"; /* * Keep the console UART independent of the optional A210 pinctrl * driver. The boot firmware has already configured these pins. @@ -478,42 +479,6 @@ }; }; -&uart0 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "disabled"; -}; - -&uart3 { - status = "disabled"; -}; - -&uart5 { - status = "disabled"; -}; - -&uart6 { - status = "disabled"; -}; - -&uart7 { - status = "disabled"; -}; - -&uart8 { - status = "disabled"; -}; - -&uart9 { - status = "disabled"; -}; - &peri3_padctrl { status = "disabled"; }; diff --git a/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts index 946a720f4ba8d..785494d8ae72d 100644 --- a/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts +++ b/arch/riscv/boot/dts/zhihe/a210-melon-pi.dts @@ -330,6 +330,7 @@ }; &uart4 { + status = "okay"; /* * Keep the console UART independent of the optional A210 pinctrl * driver. The boot firmware has already configured these pins. @@ -342,6 +343,7 @@ }; &uart8 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart8_pins>; }; @@ -357,6 +359,7 @@ }; &uart5 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; }; @@ -416,34 +419,6 @@ }; }; -&uart0 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "disabled"; -}; - -&uart3 { - status = "disabled"; -}; - -&uart6 { - status = "disabled"; -}; - -&uart7 { - status = "disabled"; -}; - -&uart9 { - status = "disabled"; -}; - &aon_gpio0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi index 647dc197675f5..82be330cd8bee 100644 --- a/arch/riscv/boot/dts/zhihe/a210.dtsi +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi @@ -956,6 +956,7 @@ resets = <&rst_peri1 PERI1_UART0_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart1: serial@2015000 { @@ -968,6 +969,7 @@ resets = <&rst_peri1 PERI1_UART1_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart2: serial@2016000 { @@ -980,6 +982,7 @@ resets = <&rst_peri1 PERI1_UART2_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart3: serial@2017000 { @@ -992,6 +995,7 @@ resets = <&rst_peri1 PERI1_UART3_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart4: serial@8401000 { @@ -1004,6 +1008,7 @@ /* Firmware has already configured the boot console UART. */ reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart5: serial@8402000 { @@ -1016,6 +1021,7 @@ resets = <&rst_peri2 PERI2_UART5_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart6: serial@8403000 { @@ -1028,6 +1034,7 @@ resets = <&rst_peri2 PERI2_UART6_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart7: serial@8404000 { @@ -1040,6 +1047,7 @@ resets = <&rst_peri2 PERI2_UART7_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart8: serial@8405000 { @@ -1052,6 +1060,7 @@ resets = <&rst_peri2 PERI2_UART8_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart9: serial@8406000 { @@ -1064,6 +1073,7 @@ resets = <&rst_peri2 PERI2_UART9_PRST>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; spi0: spi@2023000 {