diff --git a/.github/workflows/arty-a7-toy.yml b/.github/workflows/arty-a7-toy.yml index 84962fb..1a5401f 100644 --- a/.github/workflows/arty-a7-toy.yml +++ b/.github/workflows/arty-a7-toy.yml @@ -27,6 +27,7 @@ jobs: run: | python3 scripts/verify_target.py python3 scripts/verify_linux_gemmini_archive.py + python3 scripts/verify_rob_hardware.py python3 scripts/verify_linux_gemmini.py --build-record evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json --hardware-result evidence/2026-10-12/linux-gemmini/hardware/RESULT.json python3 -m compileall -q scripts tests host software bash -n scripts/elaborate.sh scripts/build_test_programs.sh software/build.sh diff --git a/README.md b/README.md index db20565..099c67b 100644 --- a/README.md +++ b/README.md @@ -14,11 +14,15 @@ The Arty A7 platforms have their own pinned Chisel build, serial loader, firmwar constraints and verification record. Follow its guide directly; the setup and demo below describe the existing Kintex-7 flow. +Arty A7-100T 的 Toy/Linux 已验证位流、配套软件与烧录脚本可直接下载： +[中文下载与使用说明](platforms/arty-a7-toy/DOWNLOADS.md)。 +提供临时 UART 加载、Flash 掉电启动两套包，另附对应源码和 SHA256 校验值。 + The Toy/Linux target passes complete board implementation, Linux RTL checks and a physical Arty A7-100T boot with full image readback and five Linux checks. -Its PCB revision remains unconfirmed and physical Gemmini testing is pending; -see [the hardware record](platforms/arty-a7-toy/evidence/2026-10-12/README.md) -and its build/programming guide before using another board. +PCB 修订号仍未确认；最新临时镜像已通过 Linux/Gemmini 实物回归，完整模型等仍未验收。 +详见 [中文测试报告](platforms/arty-a7-toy/evidence/2026-10-12/linux-gemmini/REPORT.md) +及对应构建/烧录指南，不能直接认定其他板卡也已验证。 ## Kintex-7 setup diff --git a/platforms/arty-a7-toy/DOWNLOADS.md b/platforms/arty-a7-toy/DOWNLOADS.md new file mode 100644 index 0000000..0fee50f --- /dev/null +++ b/platforms/arty-a7-toy/DOWNLOADS.md @@ -0,0 +1,50 @@ +# 已验证烧录文件下载 + +烧录产物通过 [GitHub Release：arty-a7-toy-2026-10-12](https://github.com/DangoSys/fpga/releases/tag/arty-a7-toy-2026-10-12) +提供；源码与测试证据仍保存在 Git。下载包自带配套软件、Tcl、中文操作说明和逐文件摘要， +无需重新运行 Chisel、Vivado 综合/布线或 Linux 编译。 + +仅面向 **Digilent Arty A7-100T / XC7A100T-CSG324-1**，Vivado part 为 +`xc7a100tcsg324-1`。采用官方 E.0 MIG，实测 PCB 修订号未知；此 Release 标为 +工程预发布，未完成整模型、全面浮点和长期稳定性验收。 + +## 选择下载包 + +| 文件 | 用途 | 软件与掉电行为 | +|---|---|---| +| [arty-a7-toy-uart.zip](https://github.com/DangoSys/fpga/releases/download/arty-a7-toy-2026-10-12/arty-a7-toy-uart.zip) | 联调、修改软件、复现最新测试 | 最新 Linux/Gemmini 镜像，完整 DDR 读回；掉电后需要重新加载 | +| [arty-a7-toy-flash.zip](https://github.com/DangoSys/fpga/releases/download/arty-a7-toy-2026-10-12/arty-a7-toy-flash.zip) | 固化演示、脱机运行 | 配套 MCS、旧标准 Linux 镜像；已通过实际断电重接与五项系统检查 | +| [arty-a7-toy-sources.zip](https://github.com/DangoSys/fpga/releases/download/arty-a7-toy-2026-10-12/arty-a7-toy-sources.zip) | 检查、修改与重新构建 | 仓库快照、固定软件依赖源码、实际配置、许可证与证据 | + +Flash 包保留 CPU、虚拟内存、FPU 和 Gemmini 8×8，但其 rootfs **没有最新 14 个 +Gemmini 测试程序**。最新用例验证结论对应 UART 包，不能据此认定 Flash 中已经有它们。 +两个包均有 Linux，用途不同；不建议只下载 `.bit` 后省略配套软件。 + +## 直接下载位流 + +- [toy_a7_uart.bit](https://github.com/DangoSys/fpga/releases/download/arty-a7-toy-2026-10-12/toy_a7_uart.bit)：临时 JTAG 配置，需要串口加载 `fw_payload.bin` 到 DDR。 +- [toy_a7_flash.bit](https://github.com/DangoSys/fpga/releases/download/arty-a7-toy-2026-10-12/toy_a7_flash.bit)：Flash 启动目标，需要配套压缩软件；固化时使用完整 Flash 包的 MCS。 + +Release 的 `SHA256SUMS.txt` 校验下载文件，`RELEASE_MANIFEST.json` 绑定源码提交和 +各附件摘要；每个 ZIP 的 `MANIFEST.json` 再校验包内全部文件。 +UART 位流 SHA256 为 `ccc33c511e613561fb9dd1e9c847bd3b84037da1d078c44cd3de197d55dffde1`； +Flash 位流为 `78d2e703372c13c5044674c8d4eea5b775d6b12771d21df37ba0f90617723c18`。 + +## 使用与复现 + +后续 ROB RAM 优化候选已完成独立实物复测，记录见 +[新位流实物报告](evidence/2026-10-12/rob-ram-hardware/REPORT.md)。该候选摘要为 +`dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c`，源码在 +[PR #11](https://github.com/DangoSys/fpga/pull/11)。此处追加验证资料；上述 Release +仍提供原摘要的 UART/Flash 文件，候选的 Flash 冷启动没有在本轮测试。 + +解压后按包内中文 `README.md` 执行 `run_uart.ps1` 或 `run_flash.ps1`，脚本先校验 +产物再烧录。安装 Python/pyserial、Vivado Hardware Manager、Digilent/FTDI 驱动， +连接 PROG/UART；替换真实串口和 Vivado 路径。Flash 入口要求明确指定实际 Flash 条目， +先备份再擦写。记录均保存在解压目录的新 `build/` 子目录中。 + +打包源码在 `scripts/package_downloads.py`，输入为五个已归档摘要固定的二进制和 +`--os-inputs` 目录，输出目录必须不存在。该入口不构建、不连接板卡，只打包已验证 +产物。软件依赖归档需与实物构建日志 CACHE 摘要一致，目录结构与传入参数见脚本。 +上板测试方法见 [Linux/Gemmini 指南](software/GEMMINI_LINUX.md)， +固化流程见 [Flash 指南](FLASH_BOOT.md)。 diff --git a/platforms/arty-a7-toy/README.md b/platforms/arty-a7-toy/README.md index 042cfd9..092f577 100644 --- a/platforms/arty-a7-toy/README.md +++ b/platforms/arty-a7-toy/README.md @@ -1,5 +1,8 @@ # Toy/Linux on Arty A7-100T +无需重新构建时，可从 [中文下载指南](DOWNLOADS.md) 获取已验证的 `.bit`、 +配套软件、烧录脚本和校验值；临时加载与 Flash 掉电启动分别提供下载包。 + A Chisel-generated Toy platform for `xc7a100tcsg324-1`, with CPU, Sv39, full FP16/32/64 support and Gemmini 8×8. Complete board implementation, timing, CDC checks and Linux RTL tests pass. On 2026-10-12 the connected board was programmed, @@ -17,6 +20,11 @@ Runtime DDR and changes to the initramfs remain volatile. ## 2026-10-12：Linux/Gemmini 实物回归 +后续 [ROB RAM 候选实物复测](evidence/2026-10-12/rob-ram-hardware/REPORT.md) +也已通过：完整镜像读回、两轮各 15 个程序、Linux 五项检查、原 Gemmini 13 项及 +每轮 16 项矩阵比较。优化源码在 PR #11，本 PR 追加实际日志和复现入口； +现有 Release 文件与 Flash 镜像保留原版本。 + 按标准 rootfs/bbkernel 流程构建的新镜像已完成全部 DDR 读回和实物启动； 15 个程序返回 0，覆盖五项 Linux 系统检查、原 13 项 Gemmini 测试及新增 16 项 OS/WS 矩阵对照（包含分块和尾块）。最终运行器回归与看门狗清理检查均通过。 diff --git a/platforms/arty-a7-toy/SOURCE_LOCK.json b/platforms/arty-a7-toy/SOURCE_LOCK.json index 49248f5..3c29b7e 100644 --- a/platforms/arty-a7-toy/SOURCE_LOCK.json +++ b/platforms/arty-a7-toy/SOURCE_LOCK.json @@ -5,8 +5,9 @@ ".gitattributes": "8d9ebca04236fcd49c43562b5c6ca1d88ded1ff8c8d437fbdfe3822a5ec22d74", ".gitignore": "5eaf4f0d4cbefc5292732eb17cd984839a8fe4cfc65f39352c187fd73c95947a", ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", + "DOWNLOADS.md": "938cd1d9a84b7bab75593f6461ee4be4e1b0929267d0937cc788b39795f4fe1f", "FLASH_BOOT.md": "471bcd9c9704bd2eedf11880c27c48d0505a56498e62e68ada84d5cd5ed70686", - "README.md": "d1a1326934b5f211f617b0528ca6d85fde5771d8ca32f0c85add7ffcb8310264", + "README.md": "a24ecc9e0fa78067713a3264b5ac6ac9bc9931d75182275efc81e9b5fbf12c9f", "SOFTWARE_BASELINE.json": "3a5c9f65771e6fd7f8172674baf22263ba7c2d9244993c9162ba526344a7b0aa", "THIRDPARTY.md": "02ed1d3ddd4fc26a8b1580eb4948ff6cf4f548c0434c89f1c6c2220bed3d4a42", "UPSTREAM_MANIFEST.json": "c4a96343e318c452420cf86b34d6008140560eeffa91cd85b4b87b229717c9be", @@ -43,6 +44,12 @@ "build.sbt": "e41d7a540c61879ccf1adde9cb1dae2a203b0f619c625a51838c323cce24c966", "config/gemmini-8.toml": "7a34b166586b25e2bcb0849764a4f0d969b60493ba2d8d59f4e2176771c07195", "dependencies.json": "932815e2f03b3caf8a1ab4c17baa9bc1962633d1fe8a26168f97d60f0a6844c4", + "distribution/FLASH_README.md": "2cafe8eb98da39a1865d00e719722b3e22d23e6bc8cf2b33edc6b6c5bf1ca166", + "distribution/SOURCES_README.md": "55d1858ae4f57e1225d21c19ef8fd0301e17b4b9b23ced5bbafd576d95c3bba2", + "distribution/UART_README.md": "8c0a12e051360d22245cb08395ba0c36d2f88d63811ccbb56b900aaf77fee20c", + "distribution/run_flash.ps1": "70574a5573f7a5cd99a2e36bd6e79ca7aeca14ca71c64a1680bb940dade17309", + "distribution/run_uart.ps1": "213b81106eb24211d8b1cb9cfa8c418380cc7199667b70544a9e300d29811d17", + "distribution/verify_bundle.py": "e7e33932bb987a9c524c4b4fce42d18262ce31c89b2530e9345db5d488db901b", "evidence/2026-10-11/BOARD_REPORT.md": "a349e25ba696c037c54a7a44bcadda163dc43092f6dc5c573968db6b27908366", "evidence/2026-10-11/BOARD_RESULT.json": "ee1568766df33ee52a9a0a624b017939c499ef507cb074699d15959515297ab3", "evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md": "f8147d1e0e242e5d6f4bd32f3195ab593c3245874bc67f2e61cd8c48dc07ac2d", @@ -243,8 +250,76 @@ "evidence/2026-10-12/linux-gemmini/sources/software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", "evidence/2026-10-12/linux-gemmini/watchdog/RESULT.json": "efc60f10a891ba2e224ee3130d4e776c00fc04eea5cc2e522690f85ddfb0475e", "evidence/2026-10-12/linux-gemmini/watchdog/check.log": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303", + "evidence/2026-10-12/rob-ram-hardware/HARDWARE_RESULT.json": "82899cdb4f090927dc1a41864b604c8d02b7011997d2ffe9eea856a3f6e496cd", + "evidence/2026-10-12/rob-ram-hardware/MANIFEST.json": "c0a002c6d5bc4b9f8406808d827bce03dff83b26af752702bf0ba13f44c4f866", + "evidence/2026-10-12/rob-ram-hardware/REPORT.md": "daf3bb87edfb8a9926bce97fa20b3f6b80c185a38999cffcdb7196d0e248bf14", + "evidence/2026-10-12/rob-ram-hardware/SESSION.json": "9a0ac867271f706695f853d48a5668d9377971acc73042a0bbd4fd9b465bf066", + "evidence/2026-10-12/rob-ram-hardware/first-pass/PERFORMANCE.json": "8a965e7d11aa0f8f579d35369757de8e52dd7675ab495b8c19c6ade423b438f9", + "evidence/2026-10-12/rob-ram-hardware/first-pass/RESULT.json": "9a4439e54f79b35e8baa7b79251d223aa5d3c4a2a7bc6d5d227a4e400f15b816", + "evidence/2026-10-12/rob-ram-hardware/first-pass/linux-console.log": "492038f8ed6f1ca9af22fe8d04e95bcde597b714fc5e61119a1ab030c9bf2c7f", + "evidence/2026-10-12/rob-ram-hardware/first-pass/program-console.log": "a804aadc44522767d581be24b083ded876a27243c75cb673a674e3ded7692913", + "evidence/2026-10-12/rob-ram-hardware/first-pass/program.jou": "4c9fb890a73372af4aa95cea71fbcd6b779fa43ff573654600b57182f97a4ddb", + "evidence/2026-10-12/rob-ram-hardware/first-pass/program.log": "91bc5daf46b6ab3ad89e36cdac360250b55b3f104c5263b77c16287083c2fddb", + "evidence/2026-10-12/rob-ram-hardware/first-pass/transfer-console.log": "87bc321513fb3603245b13c2a30be9e8c4bb8897795a8f8f4c0ca77e163d0a55", + "evidence/2026-10-12/rob-ram-hardware/implementation/MEMORY_MANIFEST.json": "35a43d93e5bde0cd6b0379dc2755497d660e179a5ed190cec3de259e427226b4", + "evidence/2026-10-12/rob-ram-hardware/implementation/OPTIN_RESULT.json": "bdb1d489c2d4e7d7fa4757d104bbc155f504f75ab75be26f79005b546f0c8b9b", + "evidence/2026-10-12/rob-ram-hardware/implementation/RESULT.json": "c415cbbe90ff1ae4bd699c8312453847f025e0ece0bdbdc0722650e972ca8b1d", + "evidence/2026-10-12/rob-ram-hardware/implementation/RUN.json": "905863a76131fcac84f7164b461f03186497c61753565b08209a0872a722bcaa", + "evidence/2026-10-12/rob-ram-hardware/implementation/ToyLinuxChip.profile.json": "57e251b00a486f406e5e27f666f4416be730b4e08c8838584e4aac49ebb30f86", + "evidence/2026-10-12/rob-ram-hardware/implementation/cdc.rpt": "135fb071ef679e297772e213428481193b604b70e122ae57df1b397c7a73c17f", + "evidence/2026-10-12/rob-ram-hardware/implementation/drc.rpt": "e0c062aa6e13a01a4feed37ea85bff0a8f6ae05ca266d77967bcf432e2195769", + "evidence/2026-10-12/rob-ram-hardware/implementation/route-status.rpt": "940f9a8a05963ffdc7ffc304e6f4226be99a07b3f5a83199d5bcd6e289897742", + "evidence/2026-10-12/rob-ram-hardware/implementation/routed-timing.rpt": "3c02fb09120654dba434c5b438117228bf2965953a5fb23f82d162736904bafe", + "evidence/2026-10-12/rob-ram-hardware/implementation/routed-utilization.rpt": "c5e97613245378c1cf377f5d464b93354ec980376e6a63c272d379d96db1bf5e", + "evidence/2026-10-12/rob-ram-hardware/post-check/RESULT.json": "6145883e9bd39a79dc52dc0188dbc828ed360ec3f41e8428915fc968be0be24e", + "evidence/2026-10-12/rob-ram-hardware/post-check/post-console.log": "4d2effa33782000122133d05e2b351679e3e068fea45c397f730848e3d88460f", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/LOAD_RESULT.json": "9a4439e54f79b35e8baa7b79251d223aa5d3c4a2a7bc6d5d227a4e400f15b816", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/PERFORMANCE.json": "5dda26f0cb420b06213b92559c9a230084309a430c33de0074c2bf971b6d896a", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/RESULT.json": "6ae9ce316eec352943e2622374c6158d3ab21200aeb8ddc85b6ab66c2eead964", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/boot-console.log": "492038f8ed6f1ca9af22fe8d04e95bcde597b714fc5e61119a1ab030c9bf2c7f", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/linux-console.log": "5fcf06aa8c9078e948ed2b66a7f1ebd9142c203b7d7d17d01ae96e1a9594822e", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/program-console.log": "a804aadc44522767d581be24b083ded876a27243c75cb673a674e3ded7692913", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.jou": "4c9fb890a73372af4aa95cea71fbcd6b779fa43ff573654600b57182f97a4ddb", + "evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.log": "91bc5daf46b6ab3ad89e36cdac360250b55b3f104c5263b77c16287083c2fddb", + "evidence/2026-10-12/rob-ram-hardware/software/LINUX_GEMMINI_BUILD.json": "4d9229135d7f92b711c385628fcd96839ad0e667a6579f87d8f604ce8dd7cda3", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/CMakeLists.txt": "4ea8d92e23c19d780fff7d6a2c1369ef3363dc1fe87acf1195656ce852684f4f", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/PREPARED.json": "890d8a759be94610a16a5ac976f0775e99220a4e4de3e44abd3c3aeeff99819e", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/ballISA.h": "8f74e9230c45bc270c99b4b31fde6db6ed61b01c0055c7c62855de11bb571606", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_atranspose_test.c": "d4b44df5f004b4e1d4ada02c247e5f66a6596dfa80cf70a09c54d7448b572712", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_basic_test.c": "481733138780de0ef2ce7d867bc375cd22a64990f33b9eabd8a03a45c2e8861c", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_btranspose_test.c": "efdf1cefe9277fde1dce1d62eb7c3364ddbb27926e99ddce9800f1fb54be1fec", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_shift_test.c": "9676b4e45945de9cbe005be695ffd8d0f3a406fa0448875a8372cc1d1c20fb4c", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_abtranspose_test.c": "641982f9adc4b898a27d23967807d9f350c3db717b7c276df42281b7c6ba3558", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_atranspose_test.c": "4583e36cbea777a439e65fb4ca58e51574e2f7686217088922128c36fa8d74f9", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_basic_test.c": "cd8102c88b58a2ea289212779bd2bf50f9e35806e9039f4cc5a6abf73eef131f", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_btranspose_test.c": "01ee05bb7a92de708e1bac4041354d9f0363c70a4f5b898af784f47410f63798", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_shift_test.c": "aae1a632fd3fabc1ae9fea89daf9dc0693880c718f100c86b946257935a4076d", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_cisc_conv_test.c": "ab75719d036a6b61b4369514c6771ebac94a04e7448f2127b1be60bab2e8f28b", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_basic_test.c": "f5aab861cf0f764e6179e24c70c75d9f3c7e9a0364a4e3aa818784f7f309c03a", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_btranspose_test.c": "fff4938ea7c16864e3e1b91a2d30ef2d3eabeb3ed4a1153964f5d351d6980279", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_shift_test.c": "a22209c0c02cd5d5b258525dd6266bbe3a7447b410a082e8da19a268478b6307", + "evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/params.h": "cc6bbe816a15f9a7bd133fbeb45d039733a22a6a6f94dace16eecea5eef61b24", + "evidence/2026-10-12/rob-ram-hardware/sources/board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "evidence/2026-10-12/rob-ram-hardware/sources/build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "evidence/2026-10-12/rob-ram-hardware/sources/diagnostics/run_rob_hardware.py": "00877023c88828cbfa06ce6d5111fa6b13552f96be19984dd1cef68a201991d7", + "evidence/2026-10-12/rob-ram-hardware/sources/host/check_linux_gemmini.py": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", + "evidence/2026-10-12/rob-ram-hardware/sources/host/check_live_shell.py": "3b8b1c0a884a79c2255d45bbe53ce68587e2709ef53ea72aafa48f7475741e52", + "evidence/2026-10-12/rob-ram-hardware/sources/host/check_watchdog.py": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573", + "evidence/2026-10-12/rob-ram-hardware/sources/host/ftdi_transport.py": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7", + "evidence/2026-10-12/rob-ram-hardware/sources/host/load.py": "a62e48b779c9ce1d6f8f6669523e427cf48bd19be3bf50a554dc391b09b3e3b2", + "evidence/2026-10-12/rob-ram-hardware/sources/patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", + "evidence/2026-10-12/rob-ram-hardware/sources/program.tcl": "0ff928503cf00798dae132117435e34981a176c586d7aa16e587c47877ba031f", + "evidence/2026-10-12/rob-ram-hardware/sources/scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", + "evidence/2026-10-12/rob-ram-hardware/sources/software/build_gemmini_image.py": "949a59cbc4bd494cbe793b392aaccc237637c809667b6bd5dd211e2176e6fcbf", + "evidence/2026-10-12/rob-ram-hardware/sources/software/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "evidence/2026-10-12/rob-ram-hardware/sources/software/linux_system_check.c": "c1cedf2ce6e2583393c9e7f51fe20558c1402b8d81faf2152e8f6eeaf8058315", + "evidence/2026-10-12/rob-ram-hardware/sources/software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", + "evidence/2026-10-12/rob-ram-hardware/watchdog/RESULT.json": "0982a18bad6beda608ad5191b2380bbe03683ecf16a2152011ca0f1838d11bbc", + "evidence/2026-10-12/rob-ram-hardware/watchdog/check.log": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303", "evidence/README.md": "058e5d4580d68897450dd08eb114469007f9d931bfcd5423809cd1d12811cde0", "host/check_linux_gemmini.py": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", + "host/check_live_shell.py": "3b8b1c0a884a79c2255d45bbe53ce68587e2709ef53ea72aafa48f7475741e52", "host/check_watchdog.py": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573", "host/flash.py": "47ad35043c9a04e9f6730dd4d53cf84f0d7bb018a03f76754d549f7bebe936dc", "host/ftdi_transport.py": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7", @@ -291,6 +366,7 @@ "scripts/elaborate.sh": "fc23feeac3ddaedb3368b87d2dd5f97025242ac59ecc664b974fa7ce313cd2da", "scripts/export_capabilities.py": "d741bddf8ef92fa3116bc5b33f24b9c9403c1b39b98c4c9701a8015cd02de78d", "scripts/make_flash_image.py": "7944308a95cf3c99b42203496a95ebd269a929aff1f6b3bdccb9efa7383bce23", + "scripts/package_downloads.py": "81e3ae170b7572c4db820293121b25860447146e932d0160068cdbda12bd75c0", "scripts/prepare_flash_boot.py": "75ff16be3f820dc2e9e167132d0ca4f20e67ca359a95398413e80430eebf2101", "scripts/prepare_fpga_memories.py": "e9914433d01be3cbc253f237934d674a360dd4b97c2b0799b1e67cab5f5fe294", "scripts/prepare_sources.py": "eb3637a141d4ef30659eb8086d1d59ec159c710ee81d9f8e64fc38b811632799", @@ -302,6 +378,7 @@ "scripts/verify_hardware_evidence.py": "60f3555a6b6ac6a9f567cf1b22caca9755bd4179dcea1f6731a70f8bd26a1202", "scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", "scripts/verify_linux_gemmini_archive.py": "cf8ab6737b2ad3525cf91e528aab64d78261146dec7473596d321812f3bad5e0", + "scripts/verify_rob_hardware.py": "f52b1392c7918ea422c0e4637f3ce9d5cc44eb9ddd34f1c83de2c36d085b6b03", "scripts/verify_target.py": "39bdd529e55f2b36bed4ba6b10a4b0a400fcb685f6f3e5886d537e8c549932cd", "software/GEMMINI_LINUX.md": "31d991de14e315a1cf8ca24f5d3715a25a13d8601c8334687730a5b47959a963", "software/MODEL_COMPATIBILITY.md": "1e3a78574d019f4a3e1442b899cc654f2c5a3e41cf55a7650610eed75618a1cf", diff --git a/platforms/arty-a7-toy/distribution/FLASH_README.md b/platforms/arty-a7-toy/distribution/FLASH_README.md new file mode 100644 index 0000000..c1e92c5 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/FLASH_README.md @@ -0,0 +1,50 @@ +# Arty A7-100T：Flash 固化与断电启动 + +本包包含已通过实际断电重接验证的 `toy_a7_flash.bit`、配套 `toy_flash.mcs`、 +压缩软件、校验记录和烧写脚本。MCS 已包含 FPGA 配置及 Linux 启动镜像， +无需在每次上电时连接电脑传输软件。 + +**这是先前固化验证的软件版本：含五项 Linux 系统检查，不含最新 14 个 Gemmini +测试程序。** 最新测试镜像在临时加载包中；不能把它与本包配套摘要混用。 +CPU/Sv39/FPU/Gemmini 8×8 均保留。 + +目标仅为 **Digilent Arty A7-100T / xc7a100tcsg324-1**。使用官方 E.0 MIG， +实测 PCB 修订号未知。本次 Flash 为 S25FL128S、JEDEC `012018`， +配置存储器条目 `s25fl128sxxxxxx0-spi-x1_x2_x4`。其他板须先识别实际 Flash。 + +## Windows 操作 + +1. PROG/UART 接数据 USB 线，JP1/MODE 两针装跳线帽，SW0=0。 +2. 安装 Vivado/Hardware Manager、Digilent/FTDI 驱动和 Python 3.10+； + 关闭其他串口客户端。本次使用 Vivado 2025.1。 +3. 在解压目录执行，替换串口、工具路径及已确认的 Flash 条目： + +```powershell +python -m pip install -r requirements.txt +python verify_bundle.py +.\run_flash.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' -FlashPart s25fl128sxxxxxx0-spi-x1_x2_x4 +``` + +脚本会备份全部 16 MiB 原内容到新的 `build/flash-program-*/flash-before.bin`， +然后擦写、校验 MCS，并要求从 Flash 重配置和进入 Linux。备份保持私有。 +一小时总超时，保留全部烧写和启动日志；擦写/校验期间保持供电。 + +配置从 `0x000000` 开始，软件从 `0x400000` 开始。Boot ROM 从 Flash 读取、 +解压并检查 CRC 后进入 DDR 中的 OpenSBI/Linux。此 `.bit` 必须配套软件， +只把 `.bit` 写进 Flash 不会完成软件固化。 + +## 冷启动核验与恢复 + +烧写成功后，先启动观察器： + +```powershell +python host/observe_flash_boot.py --port COM5 --require-disconnect --transcript build/cold-boot.log --timeout 600 +``` + +拔掉 USB 和其他所有供电，等至少 5 秒再接回。应出现 `PASS FLASH_PAYLOAD_CRC`、 +OpenSBI/Linux，五项 Linux 检查均通过，返回 0。本次上电启动约两分钟。 +需要临时加载软件时，可将 SW0=1 后按 BTN0，使用 UART 恢复入口。 + +本包已验证 Flash 烧写/读回、实际冷启动及五项系统检查；不继承临时包最新 +Gemmini 测试的软件验收结论。完整模型、全面浮点测试和长期稳定性仍未验收。 +证据见 `evidence/flash/`；源码与许可证见同一 Release 的 `arty-a7-toy-sources.zip`。 diff --git a/platforms/arty-a7-toy/distribution/SOURCES_README.md b/platforms/arty-a7-toy/distribution/SOURCES_README.md new file mode 100644 index 0000000..bb4f781 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/SOURCES_README.md @@ -0,0 +1,20 @@ +# 下载包对应源码与构建输入 + +`fpga/` 是 Release 标签所指提交的完整 Git 文件快照；构建说明、板级约束、 +Chisel 覆盖、软件准备流程、测试源码与实际执行输入/证据均保留。 +`SOURCE_COMMIT.txt` 记录该提交，`MANIFEST.json` 逐项绑定本源码包文件。 + +软件依赖的原始归档位于 +`fpga/platforms/arty-a7-toy/build/downloads/`，包括固定提交的 Linux、BusyBox、 +OpenSBI 与 bbkernel，原始许可证保留在各归档中。摘要与归档构建日志的 CACHE +记录一致。`actual-configs/` 保存最新 Linux/Gemmini 镜像使用的 Linux/BusyBox +配置及板级软件修改清单；实际 14 个 Gemmini C 输入另在仓库 evidence 中。 + +复现方法见 `fpga/platforms/arty-a7-toy/software/GEMMINI_LINUX.md`； +Flash 软件使用此前标准镜像，仅安装 `linux_system_check-linux`，流程见 +`FLASH_BOOT.md`、`software/build.sh`、`scripts/build_board_firmware.py`。 +硬件固定依赖由 `dependencies.json` 指定，Chisel 构建会按固定提交取回； +原许可证副本见 `notices/`。运行 Vivado 生成 IP 需要自己的合法工具安装。 + +本包未包含 Git 数据库、凭据、板上 Flash 原内容备份或与测试无关的运行记录。 +操作步骤与日志中的命令使用原文；源码遵循各组件自己的许可证。 diff --git a/platforms/arty-a7-toy/distribution/UART_README.md b/platforms/arty-a7-toy/distribution/UART_README.md new file mode 100644 index 0000000..adc27b7 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/UART_README.md @@ -0,0 +1,46 @@ +# Arty A7-100T：临时加载 Linux/Gemmini + +本包包含已在实物验证的 `toy_a7_uart.bit`、最新 `fw_payload.bin`、软件构建记录、 +烧录 Tcl、串口运行器及对应证据。无需重新综合或交叉编译。 + +目标为 **Digilent Arty A7-100T / xc7a100tcsg324-1**。CPU 25 MHz、DDR 256 MiB、 +Gemmini 8×8，串口 1 Mbps、8N1。采用官方 E.0 MIG；实测板的 PCB 修订号未知， +不能认定其他 PCB 修订号或其他 A7 板也已验证。此包是工程验证版本。 + +## Windows 操作 + +1. 使用数据 USB 线连接板上 **PROG/UART**，SW0=0，关闭其他串口客户端。 +2. 安装 Vivado/Hardware Manager 与 Digilent/FTDI 驱动；Python 3.10+。 + 本次使用 Vivado 2025.1；本机烧录无需重新安装 Artix 综合组件。 + FTDI D2XX 入口需要 `C:/Windows/System32/ftd2xx.dll`。 +3. 在解压目录打开 PowerShell，替换实际串口和 Vivado 路径： + +```powershell +python -m pip install -r requirements.txt +python verify_bundle.py +.\run_uart.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +脚本先核验所有文件摘要，临时配置 FPGA，完整写入并读回 25,797,640 字节， +启动 OpenSBI/Linux，再执行 15 个程序。总超时一小时；程序侧另有超时保护。 +本次完整传输/读回约 806 秒，复用已加载镜像的回归约 124 秒，均不是纯计算耗时。 +日志及结果保存在解压目录的 `build/hardware-gemmini-*/`。 + +通过条件包括 `PASS FULL_DDR_READBACK`、`PASS LINUX_BOOT`、五项 Linux 检查、 +`PASS GEMMINI_LINUX_CHECK cases=16`，以及原 13 项 Gemmini 测试返回 0。 +如需完整独立核验，运行： + +```powershell +python scripts/verify_linux_gemmini.py --build-record LINUX_GEMMINI_BUILD.json --hardware-result build/hardware-gemmini-实际目录/RESULT.json +``` + +## 断电行为与范围 + +本流程不改 Flash。配置和 DDR 软件在断电后丢失；此前 Flash 有镜像时，会回到 +那个固化版本。单独 JTAG 下载 `.bit` 只配置硬件，仍须把软件加载到 DDR。 + +已验证系统启动、CPU/虚存/FP64 检查和本包矩阵用例；尚未验证完整模型、全面 +浮点异常/舍入和长期稳定性。跨 K 分块由 CPU 累加，小矩阵不保证比 CPU 快。 + +源码、构建输入和原许可证见同一 Release 的 `arty-a7-toy-sources.zip`。 +本包 `notices/` 保留硬件依赖声明；Linux、BusyBox、OpenSBI 和其他组件遵循各自许可证。 diff --git a/platforms/arty-a7-toy/distribution/run_flash.ps1 b/platforms/arty-a7-toy/distribution/run_flash.ps1 new file mode 100644 index 0000000..3d71c96 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/run_flash.ps1 @@ -0,0 +1,23 @@ +# 固化配套 MCS：先备份 Flash，再擦写/校验，最后核验自主启动。 +param( + [Parameter(Mandatory = $true)][string]$Port, + [Parameter(Mandatory = $true)][string]$Vivado, + [Parameter(Mandatory = $true)] + [ValidateSet('s25fl128sxxxxxx0-spi-x1_x2_x4', + 's25fl128sxxxxxx1-spi-x1_x2_x4', + 'mt25ql128-spi-x1_x2_x4')][string]$FlashPart, + [string]$Python = 'python' +) +$ErrorActionPreference = 'Stop' +$env:PYTHONUTF8 = '1' +Push-Location -LiteralPath $PSScriptRoot +try { + & $Python verify_bundle.py + if ($LASTEXITCODE -ne 0) { throw '下载包校验失败，取消烧录' } + & $Python host/flash.py --bitstream toy_a7_flash.bit ` + --payload flash_payload.bin --mcs toy_flash.mcs --part $FlashPart ` + --vivado $Vivado --port $Port + if ($LASTEXITCODE -ne 0) { throw 'Flash 烧写或启动检查失败，请查看 build/ 中的记录' } +} finally { + Pop-Location +} diff --git a/platforms/arty-a7-toy/distribution/run_uart.ps1 b/platforms/arty-a7-toy/distribution/run_uart.ps1 new file mode 100644 index 0000000..50a8af3 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/run_uart.ps1 @@ -0,0 +1,19 @@ +# 临时配置 FPGA、完整 DDR 读回、Linux/Gemmini 回归；不写 Flash。 +param( + [Parameter(Mandatory = $true)][string]$Port, + [Parameter(Mandatory = $true)][string]$Vivado, + [string]$Python = 'python' +) +$ErrorActionPreference = 'Stop' +$env:PYTHONUTF8 = '1' +Push-Location -LiteralPath $PSScriptRoot +try { + & $Python verify_bundle.py + if ($LASTEXITCODE -ne 0) { throw '下载包校验失败，取消烧录' } + & $Python host/check_linux_gemmini.py --payload fw_payload.bin ` + --build-result LINUX_GEMMINI_BUILD.json --bitstream toy_a7_uart.bit ` + --vivado $Vivado --port $Port + if ($LASTEXITCODE -ne 0) { throw '临时加载或测试失败，请查看 build/ 中的记录' } +} finally { + Pop-Location +} diff --git a/platforms/arty-a7-toy/distribution/verify_bundle.py b/platforms/arty-a7-toy/distribution/verify_bundle.py new file mode 100644 index 0000000..61e2435 --- /dev/null +++ b/platforms/arty-a7-toy/distribution/verify_bundle.py @@ -0,0 +1,39 @@ +"""烧录前离线核验下载包中的全部文件；本入口不连接硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path + + +def digest(path): + result = hashlib.sha256() + with path.open("rb") as source: + for block in iter(lambda: source.read(1024 * 1024), b""): + result.update(block) + return result.hexdigest() + + +def verify(root): + root = root.resolve() + record = json.loads((root / "MANIFEST.json").read_text(encoding="utf-8")) + for name, expected in record["files"].items(): + path = (root / name).resolve() + if not path.is_relative_to(root) or not path.is_file(): + raise ValueError("下载包文件缺失或路径无效：" + name) + if path.stat().st_size != expected["bytes"] or digest(path) != expected["sha256"]: + raise ValueError("下载包摘要不匹配：" + name) + print(f"PASS BUNDLE {record['flow']} files={len(record['files'])}") + return record + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("directory", nargs="?", type=Path, + default=Path(__file__).resolve().parent) + args = parser.parse_args() + verify(args.directory) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/HARDWARE_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/HARDWARE_RESULT.json new file mode 100644 index 0000000..3315c22 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/HARDWARE_RESULT.json @@ -0,0 +1,47 @@ +{ + "result": "PASS_ROB_RAM_PHYSICAL_LINUX_AND_GEMMINI", + "date": "2026-10-12", + "timezone": "Asia/Shanghai", + "part": "xc7a100tcsg324-1", + "hardware_source_commit": "da07b0ab9fa9e8a59819f988eddacf2f3ba2552c", + "hardware_source_pr": "https://github.com/DangoSys/fpga/pull/11", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "ddr_readback_bytes": 25797640, + "ddr_transfer_seconds": 806.265, + "uart_port": "COM5", + "uart_baud": 1000000, + "uart_serial": "210319BCC5FCB", + "jtag_serial": "210319BCC5FCA", + "programming_tool": "Vivado 2025.1", + "full_regression_runs": 2, + "workloads_per_run": 15, + "linux_system_checks_per_run": 5, + "original_gemmini_tests_per_run": 13, + "matrix_cases_per_run": 16, + "watchdog_tested": true, + "post_test_shell_checked": true, + "flash_written": false, + "cold_boot_of_candidate_tested": false, + "published_release_files_replaced": false, + "model_end_to_end_tested": false, + "execution_sources": { + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "diagnostics/run_rob_hardware.py": "00877023c88828cbfa06ce6d5111fa6b13552f96be19984dd1cef68a201991d7", + "host/check_linux_gemmini.py": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", + "host/check_live_shell.py": "3b8b1c0a884a79c2255d45bbe53ce68587e2709ef53ea72aafa48f7475741e52", + "host/check_watchdog.py": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573", + "host/ftdi_transport.py": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7", + "host/load.py": "a62e48b779c9ce1d6f8f6669523e427cf48bd19be3bf50a554dc391b09b3e3b2", + "patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", + "program.tcl": "0ff928503cf00798dae132117435e34981a176c586d7aa16e587c47877ba031f", + "scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", + "software/build_gemmini_image.py": "949a59cbc4bd494cbe793b392aaccc237637c809667b6bd5dd211e2176e6fcbf", + "software/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "software/linux_system_check.c": "c1cedf2ce6e2583393c9e7f51fe20558c1402b8d81faf2152e8f6eeaf8058315", + "software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/MANIFEST.json new file mode 100644 index 0000000..11a6891 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/MANIFEST.json @@ -0,0 +1,270 @@ +{ + "flash_written": false, + "model_end_to_end_tested": false, + "files": { + "first-pass/linux-console.log": { + "bytes": 14499, + "sha256": "492038f8ed6f1ca9af22fe8d04e95bcde597b714fc5e61119a1ab030c9bf2c7f" + }, + "first-pass/PERFORMANCE.json": { + "bytes": 3751, + "sha256": "8a965e7d11aa0f8f579d35369757de8e52dd7675ab495b8c19c6ade423b438f9" + }, + "first-pass/program-console.log": { + "bytes": 3148, + "sha256": "a804aadc44522767d581be24b083ded876a27243c75cb673a674e3ded7692913" + }, + "first-pass/program.jou": { + "bytes": 1754, + "sha256": "4c9fb890a73372af4aa95cea71fbcd6b779fa43ff573654600b57182f97a4ddb" + }, + "first-pass/program.log": { + "bytes": 4353, + "sha256": "91bc5daf46b6ab3ad89e36cdac360250b55b3f104c5263b77c16287083c2fddb" + }, + "first-pass/RESULT.json": { + "bytes": 9709, + "sha256": "9a4439e54f79b35e8baa7b79251d223aa5d3c4a2a7bc6d5d227a4e400f15b816" + }, + "first-pass/transfer-console.log": { + "bytes": 9022, + "sha256": "87bc321513fb3603245b13c2a30be9e8c4bb8897795a8f8f4c0ca77e163d0a55" + }, + "HARDWARE_RESULT.json": { + "bytes": 2820, + "sha256": "82899cdb4f090927dc1a41864b604c8d02b7011997d2ffe9eea856a3f6e496cd" + }, + "implementation/cdc.rpt": { + "bytes": 18459, + "sha256": "135fb071ef679e297772e213428481193b604b70e122ae57df1b397c7a73c17f" + }, + "implementation/drc.rpt": { + "bytes": 258678, + "sha256": "e0c062aa6e13a01a4feed37ea85bff0a8f6ae05ca266d77967bcf432e2195769" + }, + "implementation/MEMORY_MANIFEST.json": { + "bytes": 5624, + "sha256": "35a43d93e5bde0cd6b0379dc2755497d660e179a5ed190cec3de259e427226b4" + }, + "implementation/OPTIN_RESULT.json": { + "bytes": 725, + "sha256": "bdb1d489c2d4e7d7fa4757d104bbc155f504f75ab75be26f79005b546f0c8b9b" + }, + "implementation/RESULT.json": { + "bytes": 2132, + "sha256": "c415cbbe90ff1ae4bd699c8312453847f025e0ece0bdbdc0722650e972ca8b1d" + }, + "implementation/route-status.rpt": { + "bytes": 651, + "sha256": "940f9a8a05963ffdc7ffc304e6f4226be99a07b3f5a83199d5bcd6e289897742" + }, + "implementation/routed-timing.rpt": { + "bytes": 602572, + "sha256": "3c02fb09120654dba434c5b438117228bf2965953a5fb23f82d162736904bafe" + }, + "implementation/routed-utilization.rpt": { + "bytes": 14179, + "sha256": "c5e97613245378c1cf377f5d464b93354ec980376e6a63c272d379d96db1bf5e" + }, + "implementation/RUN.json": { + "bytes": 4107, + "sha256": "905863a76131fcac84f7164b461f03186497c61753565b08209a0872a722bcaa" + }, + "implementation/ToyLinuxChip.profile.json": { + "bytes": 1255, + "sha256": "57e251b00a486f406e5e27f666f4416be730b4e08c8838584e4aac49ebb30f86" + }, + "post-check/post-console.log": { + "bytes": 315, + "sha256": "4d2effa33782000122133d05e2b351679e3e068fea45c397f730848e3d88460f" + }, + "post-check/RESULT.json": { + "bytes": 229, + "sha256": "6145883e9bd39a79dc52dc0188dbc828ed360ec3f41e8428915fc968be0be24e" + }, + "repeat-pass/boot-console.log": { + "bytes": 14499, + "sha256": "492038f8ed6f1ca9af22fe8d04e95bcde597b714fc5e61119a1ab030c9bf2c7f" + }, + "repeat-pass/linux-console.log": { + "bytes": 11628, + "sha256": "5fcf06aa8c9078e948ed2b66a7f1ebd9142c203b7d7d17d01ae96e1a9594822e" + }, + "repeat-pass/LOAD_RESULT.json": { + "bytes": 9709, + "sha256": "9a4439e54f79b35e8baa7b79251d223aa5d3c4a2a7bc6d5d227a4e400f15b816" + }, + "repeat-pass/PERFORMANCE.json": { + "bytes": 3748, + "sha256": "5dda26f0cb420b06213b92559c9a230084309a430c33de0074c2bf971b6d896a" + }, + "repeat-pass/program-console.log": { + "bytes": 3148, + "sha256": "a804aadc44522767d581be24b083ded876a27243c75cb673a674e3ded7692913" + }, + "repeat-pass/program.jou": { + "bytes": 1754, + "sha256": "4c9fb890a73372af4aa95cea71fbcd6b779fa43ff573654600b57182f97a4ddb" + }, + "repeat-pass/program.log": { + "bytes": 4353, + "sha256": "91bc5daf46b6ab3ad89e36cdac360250b55b3f104c5263b77c16287083c2fddb" + }, + "repeat-pass/RESULT.json": { + "bytes": 11734, + "sha256": "6ae9ce316eec352943e2622374c6158d3ab21200aeb8ddc85b6ab66c2eead964" + }, + "REPORT.md": { + "bytes": 5236, + "sha256": "daf3bb87edfb8a9926bce97fa20b3f6b80c185a38999cffcdb7196d0e248bf14" + }, + "SESSION.json": { + "bytes": 1195, + "sha256": "9a0ac867271f706695f853d48a5668d9377971acc73042a0bbd4fd9b465bf066" + }, + "software/generated-inputs/ballISA.h": { + "bytes": 1088, + "sha256": "8f74e9230c45bc270c99b4b31fde6db6ed61b01c0055c7c62855de11bb571606" + }, + "software/generated-inputs/CMakeLists.txt": { + "bytes": 3629, + "sha256": "4ea8d92e23c19d780fff7d6a2c1369ef3363dc1fe87acf1195656ce852684f4f" + }, + "software/generated-inputs/gemmini_linux_check.c": { + "bytes": 5145, + "sha256": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467" + }, + "software/generated-inputs/gemmini_os_cisc_atranspose_test.c": { + "bytes": 1513, + "sha256": "d4b44df5f004b4e1d4ada02c247e5f66a6596dfa80cf70a09c54d7448b572712" + }, + "software/generated-inputs/gemmini_os_cisc_basic_test.c": { + "bytes": 1384, + "sha256": "481733138780de0ef2ce7d867bc375cd22a64990f33b9eabd8a03a45c2e8861c" + }, + "software/generated-inputs/gemmini_os_cisc_btranspose_test.c": { + "bytes": 1513, + "sha256": "efdf1cefe9277fde1dce1d62eb7c3364ddbb27926e99ddce9800f1fb54be1fec" + }, + "software/generated-inputs/gemmini_os_cisc_shift_test.c": { + "bytes": 1507, + "sha256": "9676b4e45945de9cbe005be695ffd8d0f3a406fa0448875a8372cc1d1c20fb4c" + }, + "software/generated-inputs/gemmini_os_risc_abtranspose_test.c": { + "bytes": 1715, + "sha256": "641982f9adc4b898a27d23967807d9f350c3db717b7c276df42281b7c6ba3558" + }, + "software/generated-inputs/gemmini_os_risc_atranspose_test.c": { + "bytes": 1601, + "sha256": "4583e36cbea777a439e65fb4ca58e51574e2f7686217088922128c36fa8d74f9" + }, + "software/generated-inputs/gemmini_os_risc_basic_test.c": { + "bytes": 2121, + "sha256": "cd8102c88b58a2ea289212779bd2bf50f9e35806e9039f4cc5a6abf73eef131f" + }, + "software/generated-inputs/gemmini_os_risc_btranspose_test.c": { + "bytes": 1601, + "sha256": "01ee05bb7a92de708e1bac4041354d9f0363c70a4f5b898af784f47410f63798" + }, + "software/generated-inputs/gemmini_os_risc_shift_test.c": { + "bytes": 1595, + "sha256": "aae1a632fd3fabc1ae9fea89daf9dc0693880c718f100c86b946257935a4076d" + }, + "software/generated-inputs/gemmini_ws_cisc_conv_test.c": { + "bytes": 2717, + "sha256": "ab75719d036a6b61b4369514c6771ebac94a04e7448f2127b1be60bab2e8f28b" + }, + "software/generated-inputs/gemmini_ws_risc_basic_test.c": { + "bytes": 1713, + "sha256": "f5aab861cf0f764e6179e24c70c75d9f3c7e9a0364a4e3aa818784f7f309c03a" + }, + "software/generated-inputs/gemmini_ws_risc_btranspose_test.c": { + "bytes": 1811, + "sha256": "fff4938ea7c16864e3e1b91a2d30ef2d3eabeb3ed4a1153964f5d351d6980279" + }, + "software/generated-inputs/gemmini_ws_risc_shift_test.c": { + "bytes": 1805, + "sha256": "a22209c0c02cd5d5b258525dd6266bbe3a7447b410a082e8da19a268478b6307" + }, + "software/generated-inputs/params.h": { + "bytes": 126, + "sha256": "cc6bbe816a15f9a7bd133fbeb45d039733a22a6a6f94dace16eecea5eef61b24" + }, + "software/generated-inputs/PREPARED.json": { + "bytes": 879, + "sha256": "890d8a759be94610a16a5ac976f0775e99220a4e4de3e44abd3c3aeeff99819e" + }, + "software/LINUX_GEMMINI_BUILD.json": { + "bytes": 3119, + "sha256": "4d9229135d7f92b711c385628fcd96839ad0e667a6579f87d8f604ce8dd7cda3" + }, + "sources/board/program_arty.tcl": { + "bytes": 1064, + "sha256": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c" + }, + "sources/build.sbt": { + "bytes": 4345, + "sha256": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407" + }, + "sources/diagnostics/run_rob_hardware.py": { + "bytes": 1662, + "sha256": "00877023c88828cbfa06ce6d5111fa6b13552f96be19984dd1cef68a201991d7" + }, + "sources/host/check_linux_gemmini.py": { + "bytes": 10604, + "sha256": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268" + }, + "sources/host/check_live_shell.py": { + "bytes": 2672, + "sha256": "3b8b1c0a884a79c2255d45bbe53ce68587e2709ef53ea72aafa48f7475741e52" + }, + "sources/host/check_watchdog.py": { + "bytes": 2989, + "sha256": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573" + }, + "sources/host/ftdi_transport.py": { + "bytes": 4518, + "sha256": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7" + }, + "sources/host/load.py": { + "bytes": 4823, + "sha256": "a62e48b779c9ce1d6f8f6669523e427cf48bd19be3bf50a554dc391b09b3e3b2" + }, + "sources/patches/framework/GlobalROB.scala": { + "bytes": 26125, + "sha256": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d" + }, + "sources/program.tcl": { + "bytes": 360, + "sha256": "0ff928503cf00798dae132117435e34981a176c586d7aa16e587c47877ba031f" + }, + "sources/scripts/verify_linux_gemmini.py": { + "bytes": 6737, + "sha256": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b" + }, + "sources/software/build_gemmini_image.py": { + "bytes": 3483, + "sha256": "949a59cbc4bd494cbe793b392aaccc237637c809667b6bd5dd211e2176e6fcbf" + }, + "sources/software/gemmini_linux_check.c": { + "bytes": 5145, + "sha256": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467" + }, + "sources/software/linux_system_check.c": { + "bytes": 3890, + "sha256": "c1cedf2ce6e2583393c9e7f51fe20558c1402b8d81faf2152e8f6eeaf8058315" + }, + "sources/software/prepare_gemmini_linux.py": { + "bytes": 4792, + "sha256": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec" + }, + "watchdog/check.log": { + "bytes": 791, + "sha256": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303" + }, + "watchdog/RESULT.json": { + "bytes": 513, + "sha256": "0982a18bad6beda608ad5191b2380bbe03683ecf16a2152011ca0f1838d11bbc" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/REPORT.md new file mode 100644 index 0000000..5436b72 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/REPORT.md @@ -0,0 +1,82 @@ +# ROB RAM 候选实物复测 + +2026-10-12（Asia/Shanghai）在同一块 Arty A7-100T 上临时烧录 ROB RAM 候选， +沿用先前有效的加载与测试方式。完整镜像读回、Linux 启动和两轮回归通过。 +本记录追加到 PR #9；优化源码与完整实现资料来自 +[PR #11](https://github.com/DangoSys/fpga/pull/11)，硬件源码提交固定为 +`da07b0ab9fa9e8a59819f988eddacf2f3ba2552c`。 + +## 输入与部署 + +- 器件 `xc7a100tcsg324-1`，JTAG `210319BCC5FCA`，UART B `210319BCC5FCB` / COM5。 +- Vivado 2025.1 临时 JTAG 编程，25 MHz CPU、1 Mbps UART；沿用官方 E.0 MIG。 + 板卡 PCB 修订号仍未确认，DDR 接口与之前已实测版本相同。 +- 位流 SHA256：`dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c`。 +- 沿用标准 Linux/Gemmini 镜像，25,797,640 字节，SHA256： + `e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0`。 +- CPU 保持复位，按 256 字节分块写入 DDR，每块读回并核验 CRC、响应序号与全部数据； + 完整一致后才释放 CPU。没有写 Flash，现有 Release 七个附件保持原内容。 + +## 实测结果 + +| 检查 | 结果 | +|---|---| +| JTAG 编程、loader 容量/频率 | 通过 | +| 完整 25,797,640 字节镜像读回 | 全部一致，806.265 秒 | +| 首轮加载、启动、15 个程序 | 通过，总计 916.109 秒 | +| 第二轮板上程序摘要 | 15 个均与构建记录一致 | +| 第二轮 15 个程序 | 全部返回 0，123.937 秒 | +| Linux 五项系统检查 | 两轮均通过 | +| 原版 13 项 Gemmini | 两轮均通过 | +| 新增 OS/WS 矩阵逐元素比较 | 每轮 16 项，两轮共 32 项通过 | +| watchdog 正常/非零/刻意超时 | 返回 0 / 1 / 137，全部 watcher 已回收 | +| 回归后交互 shell | 可响应；MemTotal 245,888 KiB，MemAvailable 226,060 KiB | +| UART 延迟清理 | 每次关闭恢复到原 16 ms | + +Linux 检查包括写时复制、页面保护、FP64 进程上下文、定时器和总检查。 +页面保护用例故意让子进程触发 SIGSEGV；后续 `PASS VM_PAGE_PROTECTION` 和退出 0 +是正确结果。watchdog 的 1、137 是预设自检，未发生非预期 workload 失败或超时。 +外层实物会话设 3,600 秒期限；单程序板上 90 秒 watchdog、主机等待 120 秒。 + +第二轮复用首轮完整加载结果，先从真实 Linux 对 15 个文件逐个计算 `sha256sum`， +没有重新烧录或重新传镜像。原始串口日志和结构化返回码通过独立离线核验。 +第二轮第 13 项有命令回显交织，原文保留；正式 PASSED 行与返回码仍完整。 +不能据此宣称所有串口文本显示行为均已完善。 + +## 计时与资格边界 + +两轮 `PERFORMANCE.json` 保存全部 32 项端到端计时。采样有波动，部分小矩阵仍慢于 +CPU 参考；不能仅凭两轮计时宣称性能提高。此测试包括分块、DMA、配置、同步与 +CPU 跨 K 累加，不能替代硬件跨 K 累加或完整模型验收。 + +这次证明了 ROB RAM 候选在这块板上可以运行 Linux 和上述 Gemmini 用例。 +完整 ISA/FPU 穷举、长期稳定性、热/功耗测量及整模型仍未完成。 +它是 UART 临时配置；当前板上运行该候选，掉电后原 Flash 镜像仍负责自主启动。 +本轮没有验证候选的 Flash 冷启动，也没有替换旧发布位流。 + +## 复现与日志 + +从平台目录执行，位流须来自固定硬件源码的 opt-in 构建；软件可使用已有 UART 包。 +替换下列路径与本机串口。新候选必须显式指定摘要，不能使用旧位流的缺省摘要。 + +```powershell +$sha = 'dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c' +$bit = 'D:\实际实现目录\toy_a7.bit' +$payload = 'D:\实际软件目录\fw_payload.bin' +$buildRecord = 'D:\实际软件目录\LINUX_GEMMINI_BUILD.json' +$vivado = 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +python host/check_linux_gemmini.py --payload $payload --build-result $buildRecord --bitstream $bit --expected-bit-sha256 $sha --vivado $vivado --port COM5 +# 首轮完整成功后复跑；断电或复位后不能沿用 --loaded-run。 +$firstRun = 'D:\首轮日志目录' +python host/check_linux_gemmini.py --payload $payload --build-result $buildRecord --bitstream $bit --expected-bit-sha256 $sha --vivado $vivado --port COM5 --loaded-run $firstRun +python host/check_watchdog.py --port COM5 --output build/new-watchdog +python host/check_live_shell.py --port COM5 --output build/new-post +python scripts/verify_linux_gemmini.py --build-record $buildRecord --hardware-result "$firstRun\RESULT.json" --expected-bit-sha256 $sha --output build/new-PERFORMANCE.json +python scripts/verify_rob_hardware.py +``` + +`first-pass/` 为本次 JTAG/完整读回/启动/首轮原文，`repeat-pass/` 为第二轮与板上摘要； +`watchdog/`、`post-check/` 为清理及回归后状态；`sources/` 保存实际脚本、测试源码与 Tcl。 +`software/` 保存构建记录及适配后的 C 输入，`implementation/` 绑定原实现报告与摘要。 +其中实现记录的“未做实物验证”是当时的历史状态，本次结论在 `HARDWARE_RESULT.json`。 +`MANIFEST.json` 核验全部档案文件；旧测试记录保持原字节，另行追加本次证据。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/SESSION.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/SESSION.json new file mode 100644 index 0000000..6f3c269 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/SESSION.json @@ -0,0 +1,27 @@ +{ + "started_at": "2026-10-12T21:04:12.519359+08:00", + "deadline": "2026-10-12T22:04:12.519359+08:00", + "timeout_seconds": 3600, + "command": [ + "D:\\python\\python.exe", + "-u", + "D:\\Verilog_Dev\\fpga-arty-a7-gemmini-linux\\platforms\\arty-a7-toy\\host\\check_linux_gemmini.py", + "--payload", + "D:\\Verilog_Dev\\fpga-arty-a7-gemmini-linux\\platforms\\arty-a7-toy\\build\\linux-gemmini-20261012-e8e89f4c\\fw_payload.bin", + "--build-result", + "D:\\Verilog_Dev\\fpga-arty-a7-gemmini-linux\\platforms\\arty-a7-toy\\build\\linux-gemmini-20261012-e8e89f4c\\LINUX_GEMMINI_BUILD.json", + "--bitstream", + "D:\\Verilog_Dev\\fpga-arty-a7-gemmini-linux\\platforms\\arty-a7-toy\\build\\toy-a7-rob-ram-20261012-2ebcbc31\\board\\toy_a7.bit", + "--expected-bit-sha256", + "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "--vivado", + "D:/Xilinx/2025.1/Vivado/bin/vivado.bat", + "--port", + "COM5" + ], + "flash_written": false, + "script_sha256": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", + "uart_serial": "210319BCC5FCB", + "exit_code": 0, + "finished_at": "2026-10-12T21:19:28.986339+08:00" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/PERFORMANCE.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/PERFORMANCE.json new file mode 100644 index 0000000..b939595 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/PERFORMANCE.json @@ -0,0 +1,169 @@ +{ + "result": "PASS_OFFLINE_VERIFICATION", + "console_sha256": "492038f8ed6f1ca9af22fe8d04e95bcde597b714fc5e61119a1ab030c9bf2c7f", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "matrix_measurements": [ + { + "case": 1, + "mode": "OS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 2538000, + "accelerator_end_to_end_ns": 894000, + "cpu_over_accelerator": 2.8389 + }, + { + "case": 2, + "mode": "WS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 614000, + "accelerator_end_to_end_ns": 2600000, + "cpu_over_accelerator": 0.2362 + }, + { + "case": 3, + "mode": "OS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 5606000, + "accelerator_end_to_end_ns": 5658000, + "cpu_over_accelerator": 0.9908 + }, + { + "case": 4, + "mode": "WS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 11158000, + "accelerator_end_to_end_ns": 7596000, + "cpu_over_accelerator": 1.4689 + }, + { + "case": 5, + "mode": "OS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 4128000, + "accelerator_end_to_end_ns": 10132000, + "cpu_over_accelerator": 0.4074 + }, + { + "case": 6, + "mode": "WS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 3960000, + "accelerator_end_to_end_ns": 8644000, + "cpu_over_accelerator": 0.4581 + }, + { + "case": 7, + "mode": "OS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 1578000, + "accelerator_end_to_end_ns": 1754000, + "cpu_over_accelerator": 0.8997 + }, + { + "case": 8, + "mode": "WS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 3308000, + "accelerator_end_to_end_ns": 3742000, + "cpu_over_accelerator": 0.884 + }, + { + "case": 9, + "mode": "OS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 638000, + "accelerator_end_to_end_ns": 2802000, + "cpu_over_accelerator": 0.2277 + }, + { + "case": 10, + "mode": "WS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 628000, + "accelerator_end_to_end_ns": 878000, + "cpu_over_accelerator": 0.7153 + }, + { + "case": 11, + "mode": "OS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 7116000, + "accelerator_end_to_end_ns": 5728000, + "cpu_over_accelerator": 1.2423 + }, + { + "case": 12, + "mode": "WS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 5564000, + "accelerator_end_to_end_ns": 7472000, + "cpu_over_accelerator": 0.7446 + }, + { + "case": 13, + "mode": "OS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 4206000, + "accelerator_end_to_end_ns": 10058000, + "cpu_over_accelerator": 0.4182 + }, + { + "case": 14, + "mode": "WS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 3898000, + "accelerator_end_to_end_ns": 8544000, + "cpu_over_accelerator": 0.4562 + }, + { + "case": 15, + "mode": "OS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 3336000, + "accelerator_end_to_end_ns": 1660000, + "cpu_over_accelerator": 2.0096 + }, + { + "case": 16, + "mode": "WS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 1568000, + "accelerator_end_to_end_ns": 3632000, + "cpu_over_accelerator": 0.4317 + } + ], + "timing_scope": "分块、DMA、配置、同步和 CPU 跨 K 累加；不是纯 MAC 延迟", + "model_end_to_end_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/RESULT.json new file mode 100644 index 0000000..dfa4f4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/RESULT.json @@ -0,0 +1,90 @@ +{ + "result": "PASS_LINUX_AND_GEMMINI_HARDWARE", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "port": "COM5", + "timeout_seconds": 3600, + "flash_written": false, + "tests": [ + { + "name": "linux_system_check-linux", + "exit_code": 0, + "output": "/root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai\nt $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_0:%s\\\nn' $r\nBEGIN LINUX_SYSTEM_CHECK\nPASS VM_COPY_ON_WRITE\nlinux_system_ch[26]: unhandled signal 11 code 0x2 at 0x0000003f9030e000 in linux_system_check-linux[10000+7a000]\nCPU: 0 PID: 26 Comm: linux_system_ch Not tainted 6.6.0 #1\nHardware name: ucb-bar,buckyball (DT)\nepc : 00000000000105c6 ra : 000000000001041e sp : 0000003fca649b50\n gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000\n t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fca649bd0\n s1 : 0000003f9030d000 a0 : 0000000000000000 a1 : 0000000000000000\n a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000\n a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000\n s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f9030e000\n s5 : 0000003fca649d88 s6 : 0000000000000002 s7 : 00000000000106ba\n s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28\n s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000\n t5 : 0000000000000000 t6 : 0000000000000000\nstatus: 800000020001e020 badaddr: 0000003f9030e000 cause: 000000000000000d\nPASS VM_PAGE_PROTECTION\nPASS FP64_PROCESS_CONTEXT\nPASS LINUX_TIMER elapsed_ns=102926000\nPASS LINUX_SYSTEM_CHECK\n\nWB_TEST_RC_0:0\n" + }, + { + "name": "gemmini_linux_check-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa\nit $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_1:%s\n\\n' $r\nBEGIN GEMMINI_LINUX_CHECK pid=28 dimension=8 bank_width=64\nBEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=2538000 accelerator_end_to_end_ns=894000\nBEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=614000 accelerator_end_to_end_ns=2600000\nBEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5606000 accelerator_end_to_end_ns=5658000\nBEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=11158000 accelerator_end_to_end_ns=7596000\nBEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4128000 accelerator_end_to_end_ns=10132000\nBEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3960000 accelerator_end_to_end_ns=8644000\nBEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=1578000 accelerator_end_to_end_ns=1754000\nBEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3308000 accelerator_end_to_end_ns=3742000\nBEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=638000 accelerator_end_to_end_ns=2802000\nBEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=878000\nBEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=7116000 accelerator_end_to_end_ns=5728000\nBEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5564000 accelerator_end_to_end_ns=7472000\nBEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=4206000 accelerator_end_to_end_ns=10058000\nBEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=3898000 accelerator_end_to_end_ns=8544000\nBEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=3336000 accelerator_end_to_end_ns=1660000\nBEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=1568000 accelerator_end_to_end_ns=3632000\nPASS GEMMINI_LINUX_CHECK cases=16\n\nWB_TEST_RC_1:0\n" + }, + { + "name": "gemmini_os_cisc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_2:%s\\n' $r\n=== Gemmini OS CISC a_transpose Test ===\nGemmini OS CISC a_transpose Test PASSED\n\nWB_TEST_RC_2:0\n" + }, + { + "name": "gemmini_os_cisc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_3:%s\\n' $r\n=== Gemmini OS CISC Basic Test ===\nGemmini OS CISC Basic Test PASSED\n\nWB_TEST_RC_3:0\n" + }, + { + "name": "gemmini_os_cisc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_4:%s\\n' $r\n=== Gemmini OS CISC b_transpose Test ===\nGemmini OS CISC b_transpose Test PASSED\n\nWB_TEST_RC_4:0\n" + }, + { + "name": "gemmini_os_cisc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_5:%s\\n' $r\n=== Gemmini OS CISC in_shift Test ===\nGemmini OS CISC in_shift Test PASSED\n\nWB_TEST_RC_5:0\n" + }, + { + "name": "gemmini_os_risc_abtranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $\np) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB\n_TEST_RC_6:%s\\n' $r\n=== Gemmini OS RISC ab_transpose Test ===\nGemmini OS RISC ab_transpose Test PASSED\n\nWB_TEST_RC_6:0\n" + }, + { + "name": "gemmini_os_risc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_7:%s\\n' $r\n=== Gemmini OS RISC a_transpose Test ===\nGemmini OS RISC a_transpose Test PASSED\n\nWB_TEST_RC_7:0\n" + }, + { + "name": "gemmini_os_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_8:%s\\n' $r\n=== Gemmini OS RISC Basic Test ===\nGemmini OS RISC Basic Test PASSED\n\nWB_TEST_RC_8:0\n" + }, + { + "name": "gemmini_os_risc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_9:%s\\n' $r\n=== Gemmini OS RISC b_transpose Test ===\nGemmini OS RISC b_transpose Test PASSED\n\nWB_TEST_RC_9:0\n" + }, + { + "name": "gemmini_os_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_10:%s\\n' $r\n=== Gemmini OS RISC in_shift Test ===\nGemmini OS RISC in_shift Test PASSED\n\nWB_TEST_RC_10:0\n" + }, + { + "name": "gemmini_ws_cisc_conv_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w=\n$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_R\nC_11:%s\\n' $r\n=== Gemmini WS CISC Loop Conv Test ===\nGemmini WS CISC Loop Conv Test PASSED\n\nWB_TEST_RC_11:0\n" + }, + { + "name": "gemmini_ws_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_12:%s\\n' $r\n=== Gemmini WS RISC Basic Test ===\nGemmini WS RISC Basic Test PASSED\n\nWB_TEST_RC_12:0\n" + }, + { + "name": "gemmini_ws_risc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_13:%s\\n' $r\n=== Gemmini WS RISC b_transpose Test ===\nGemmini WS RISC b_transpose Test PASSED\n\nWB_TEST_RC_13:0\n" + }, + { + "name": "gemmini_ws_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_14:%s\\n' $r\n=== Gemmini WS RISC in_shift Test ===\nGemmini WS RISC in_shift Test PASSED\n\nWB_TEST_RC_14:0\n" + } + ], + "ddr_readback_bytes": 25797640, + "ddr_transfer_seconds": 806.265, + "test_count": 15, + "blocked_matmul_cases": 16, + "elapsed_seconds": 916.109 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/linux-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/linux-console.log new file mode 100644 index 0000000..7ec3dd4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/linux-console.log @@ -0,0 +1,297 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Mon Oct 12 12:10:02 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 233208K/262144K available (2126K kernel code, 4319K rwdata, 2048K rodata, 12681K init, 299K bss, 28936K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 12680K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # /root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai +t $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_0:%s\ +n' $r +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[26]: unhandled signal 11 code 0x2 at 0x0000003f9030e000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 26 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fca649b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fca649bd0 + s1 : 0000003f9030d000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f9030e000 + s5 : 0000003fca649d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f9030e000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=102926000 +PASS LINUX_SYSTEM_CHECK + +WB_TEST_RC_0:0 +~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa +it $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_1:%s +\n' $r +BEGIN GEMMINI_LINUX_CHECK pid=28 dimension=8 bank_width=64 +BEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=2538000 accelerator_end_to_end_ns=894000 +BEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=614000 accelerator_end_to_end_ns=2600000 +BEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5606000 accelerator_end_to_end_ns=5658000 +BEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=11158000 accelerator_end_to_end_ns=7596000 +BEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4128000 accelerator_end_to_end_ns=10132000 +BEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3960000 accelerator_end_to_end_ns=8644000 +BEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=1578000 accelerator_end_to_end_ns=1754000 +BEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3308000 accelerator_end_to_end_ns=3742000 +BEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=638000 accelerator_end_to_end_ns=2802000 +BEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=878000 +BEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=7116000 accelerator_end_to_end_ns=5728000 +BEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5564000 accelerator_end_to_end_ns=7472000 +BEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=4206000 accelerator_end_to_end_ns=10058000 +BEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=3898000 accelerator_end_to_end_ns=8544000 +BEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=3336000 accelerator_end_to_end_ns=1660000 +BEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=1568000 accelerator_end_to_end_ns=3632000 +PASS GEMMINI_LINUX_CHECK cases=16 + +WB_TEST_RC_1:0 +~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_2:%s\n' $r +=== Gemmini OS CISC a_transpose Test === +Gemmini OS CISC a_transpose Test PASSED + +WB_TEST_RC_2:0 +~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_3:%s\n' $r +=== Gemmini OS CISC Basic Test === +Gemmini OS CISC Basic Test PASSED + +WB_TEST_RC_3:0 +~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_4:%s\n' $r +=== Gemmini OS CISC b_transpose Test === +Gemmini OS CISC b_transpose Test PASSED + +WB_TEST_RC_4:0 +~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_5:%s\n' $r +=== Gemmini OS CISC in_shift Test === +Gemmini OS CISC in_shift Test PASSED + +WB_TEST_RC_5:0 +~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $ +p) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB +_TEST_RC_6:%s\n' $r +=== Gemmini OS RISC ab_transpose Test === +Gemmini OS RISC ab_transpose Test PASSED + +WB_TEST_RC_6:0 +~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_7:%s\n' $r +=== Gemmini OS RISC a_transpose Test === +Gemmini OS RISC a_transpose Test PASSED + +WB_TEST_RC_7:0 +~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_8:%s\n' $r +=== Gemmini OS RISC Basic Test === +Gemmini OS RISC Basic Test PASSED + +WB_TEST_RC_8:0 +~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_9:%s\n' $r +=== Gemmini OS RISC b_transpose Test === +Gemmini OS RISC b_transpose Test PASSED + +WB_TEST_RC_9:0 +~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_10:%s\n' $r +=== Gemmini OS RISC in_shift Test === +Gemmini OS RISC in_shift Test PASSED + +WB_TEST_RC_10:0 +~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w= +$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_R +C_11:%s\n' $r +=== Gemmini WS CISC Loop Conv Test === +Gemmini WS CISC Loop Conv Test PASSED + +WB_TEST_RC_11:0 +~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_12:%s\n' $r +=== Gemmini WS RISC Basic Test === +Gemmini WS RISC Basic Test PASSED + +WB_TEST_RC_12:0 +~ # /root/gemmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_13:%s\n' $r +=== Gemmini WS RISC b_transpose Test === +Gemmini WS RISC b_transpose Test PASSED + +WB_TEST_RC_13:0 +~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_14:%s\n' $r +=== Gemmini WS RISC in_shift Test === +Gemmini WS RISC in_shift Test PASSED + +WB_TEST_RC_14:0 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program-console.log new file mode 100644 index 0000000..0480a7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program-console.log @@ -0,0 +1,64 @@ + +****** Vivado v2025.1 (64-bit) + **** SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 + **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 + **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 + **** Start of session at: Mon Oct 12 21:04:14 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} +# set toy_program_script [file join [file dirname [file normalize [info script]]] board program_arty.tcl] +# source $toy_program_script +## if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +## set bitfile [file normalize [lindex $argv 0]] +## if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +## open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 494.426 ; gain = 215.547 +## connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 494.426 ; gain = 0.000 +## set targets [get_hw_targets -quiet] +## if {[llength $targets] != 1} { +## error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +## } +## open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +## if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +## set device [lindex $devices 0] +## current_hw_device $device +## set_property PROGRAM.FILE $bitfile $device +## program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +## refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +## puts "ARTY_JTAG_PROGRAMMED: $bitfile" +ARTY_JTAG_PROGRAMMED: D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7.bit +## close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## disconnect_hw_server +## close_hw_manager +## exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 21:04:45 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.jou b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.jou new file mode 100644 index 0000000..7f9ab6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 21:04:14 2026 +# Process ID : 87892 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl -log D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.log -journal D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\toy-a7-rob-ram-20261012-2ebcbc31\board\toy_a7.bit +# Log file : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/hardware-gemmini-20261012-bcff9cd0/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 68200 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.log new file mode 100644 index 0000000..807366d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/program.log @@ -0,0 +1,78 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 21:04:14 2026 +# Process ID : 87892 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl -log D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.log -journal D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\toy-a7-rob-ram-20261012-2ebcbc31\board\toy_a7.bit +# Log file : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/hardware-gemmini-20261012-bcff9cd0/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 68200 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} +# set toy_program_script [file join [file dirname [file normalize [info script]]] board program_arty.tcl] +# source $toy_program_script +## if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +## set bitfile [file normalize [lindex $argv 0]] +## if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +## open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 494.426 ; gain = 215.547 +## connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 494.426 ; gain = 0.000 +## set targets [get_hw_targets -quiet] +## if {[llength $targets] != 1} { +## error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +## } +## open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +## if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +## set device [lindex $devices 0] +## current_hw_device $device +## set_property PROGRAM.FILE $bitfile $device +## program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +## refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +## puts "ARTY_JTAG_PROGRAMMED: $bitfile" +ARTY_JTAG_PROGRAMMED: D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7.bit +## close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## disconnect_hw_server +## close_hw_manager +## exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 21:04:45 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/transfer-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/transfer-console.log new file mode 100644 index 0000000..1eee976 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/first-pass/transfer-console.log @@ -0,0 +1,218 @@ +PASS VOLATILE_JTAG_PROGRAM +D2XX UART B COM5: latency 16->2 ms +PASS LOADER_INFO DDR=256MiB CPU=25MHz +DDR_VERIFY 256/25797640 +DDR_VERIFY 1048832/25797640 +DDR_VERIFY 2097408/25797640 +DDR_VERIFY 3145984/25797640 +DDR_VERIFY 4194560/25797640 +DDR_VERIFY 5243136/25797640 +DDR_VERIFY 6291712/25797640 +DDR_VERIFY 7340288/25797640 +DDR_VERIFY 8388864/25797640 +DDR_VERIFY 9437440/25797640 +DDR_VERIFY 10486016/25797640 +DDR_VERIFY 11534592/25797640 +DDR_VERIFY 12583168/25797640 +DDR_VERIFY 13631744/25797640 +DDR_VERIFY 14680320/25797640 +DDR_VERIFY 15728896/25797640 +DDR_VERIFY 16777472/25797640 +DDR_VERIFY 17826048/25797640 +DDR_VERIFY 18874624/25797640 +DDR_VERIFY 19923200/25797640 +DDR_VERIFY 20971776/25797640 +DDR_VERIFY 22020352/25797640 +DDR_VERIFY 23068928/25797640 +DDR_VERIFY 24117504/25797640 +DDR_VERIFY 25166080/25797640 +PASS FULL_DDR_READBACK bytes=25797640 seconds=806.265 +PASS LINUX_BOOT +RUN linux_system_check-linux +/root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai +t $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_0:%s\ +n' $r +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[26]: unhandled signal 11 code 0x2 at 0x0000003f9030e000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 26 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fca649b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fca649bd0 + s1 : 0000003f9030d000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f9030e000 + s5 : 0000003fca649d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f9030e000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=102926000 +PASS LINUX_SYSTEM_CHECK + +WB_TEST_RC_0:0 + +RUN gemmini_linux_check-linux +~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa +it $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_1:%s +\n' $r +BEGIN GEMMINI_LINUX_CHECK pid=28 dimension=8 bank_width=64 +BEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=2538000 accelerator_end_to_end_ns=894000 +BEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=614000 accelerator_end_to_end_ns=2600000 +BEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5606000 accelerator_end_to_end_ns=5658000 +BEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=11158000 accelerator_end_to_end_ns=7596000 +BEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4128000 accelerator_end_to_end_ns=10132000 +BEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3960000 accelerator_end_to_end_ns=8644000 +BEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=1578000 accelerator_end_to_end_ns=1754000 +BEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3308000 accelerator_end_to_end_ns=3742000 +BEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=638000 accelerator_end_to_end_ns=2802000 +BEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=878000 +BEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=7116000 accelerator_end_to_end_ns=5728000 +BEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5564000 accelerator_end_to_end_ns=7472000 +BEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=4206000 accelerator_end_to_end_ns=10058000 +BEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=3898000 accelerator_end_to_end_ns=8544000 +BEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=3336000 accelerator_end_to_end_ns=1660000 +BEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=1568000 accelerator_end_to_end_ns=3632000 +PASS GEMMINI_LINUX_CHECK cases=16 + +WB_TEST_RC_1:0 + +RUN gemmini_os_cisc_atranspose_test-linux +~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_2:%s\n' $r +=== Gemmini OS CISC a_transpose Test === +Gemmini OS CISC a_transpose Test PASSED + +WB_TEST_RC_2:0 + +RUN gemmini_os_cisc_basic_test-linux +~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_3:%s\n' $r +=== Gemmini OS CISC Basic Test === +Gemmini OS CISC Basic Test PASSED + +WB_TEST_RC_3:0 + +RUN gemmini_os_cisc_btranspose_test-linux +~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_4:%s\n' $r +=== Gemmini OS CISC b_transpose Test === +Gemmini OS CISC b_transpose Test PASSED + +WB_TEST_RC_4:0 + +RUN gemmini_os_cisc_shift_test-linux +~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_5:%s\n' $r +=== Gemmini OS CISC in_shift Test === +Gemmini OS CISC in_shift Test PASSED + +WB_TEST_RC_5:0 + +RUN gemmini_os_risc_abtranspose_test-linux +~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $ +p) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB +_TEST_RC_6:%s\n' $r +=== Gemmini OS RISC ab_transpose Test === +Gemmini OS RISC ab_transpose Test PASSED + +WB_TEST_RC_6:0 + +RUN gemmini_os_risc_atranspose_test-linux +~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_7:%s\n' $r +=== Gemmini OS RISC a_transpose Test === +Gemmini OS RISC a_transpose Test PASSED + +WB_TEST_RC_7:0 + +RUN gemmini_os_risc_basic_test-linux +~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_8:%s\n' $r +=== Gemmini OS RISC Basic Test === +Gemmini OS RISC Basic Test PASSED + +WB_TEST_RC_8:0 + +RUN gemmini_os_risc_btranspose_test-linux +~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_9:%s\n' $r +=== Gemmini OS RISC b_transpose Test === +Gemmini OS RISC b_transpose Test PASSED + +WB_TEST_RC_9:0 + +RUN gemmini_os_risc_shift_test-linux +~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_10:%s\n' $r +=== Gemmini OS RISC in_shift Test === +Gemmini OS RISC in_shift Test PASSED + +WB_TEST_RC_10:0 + +RUN gemmini_ws_cisc_conv_test-linux +~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w= +$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_R +C_11:%s\n' $r +=== Gemmini WS CISC Loop Conv Test === +Gemmini WS CISC Loop Conv Test PASSED + +WB_TEST_RC_11:0 + +RUN gemmini_ws_risc_basic_test-linux +~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_12:%s\n' $r +=== Gemmini WS RISC Basic Test === +Gemmini WS RISC Basic Test PASSED + +WB_TEST_RC_12:0 + +RUN gemmini_ws_risc_btranspose_test-linux +~ # /root/gemmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_13:%s\n' $r +=== Gemmini WS RISC b_transpose Test === +Gemmini WS RISC b_transpose Test PASSED + +WB_TEST_RC_13:0 + +RUN gemmini_ws_risc_shift_test-linux +~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_14:%s\n' $r +=== Gemmini WS RISC in_shift Test === +Gemmini WS RISC in_shift Test PASSED + +WB_TEST_RC_14:0 + +D2XX closed; latency restored to 16 ms +RESULT D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\RESULT.json diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/MEMORY_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/MEMORY_MANIFEST.json new file mode 100644 index 0000000..649b3e8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/MEMORY_MANIFEST.json @@ -0,0 +1,140 @@ +{ + "emitted_sha256": "dc7d0cd8ab3d819b1a72b54d624a8462f21c02708983bc7d45457c8d382a228f", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": [ + { + "module_name": "tag_array_ext", + "depth": 32, + "width": 92, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 23, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.meta.tag_array.tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "array_0_0_ext", + "depth": 128, + "width": 128, + "masked": true, + "read": 1, + "write": 1, + "readwrite": 0, + "mask_granularity": 64, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_0.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_0.array_0_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "bbtile_icache_tag_array_ext", + "depth": 64, + "width": 42, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 21, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_tag_array.bbtile_icache_tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "bbtile_icache_data_arrays_0_ext", + "depth": 256, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 32, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_3.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_2.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_1.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_0.bbtile_icache_data_arrays_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ], + "ram_style": "block" + }, + { + "module_name": "sram_ext", + "depth": 8, + "width": 1269, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.subRob.sram.sram_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "mem_ext", + "depth": 1024, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 8, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_7.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_6.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_5.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_4.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_3.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_2.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_1.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_0.mem.mem_ext" + ], + "ram_style": "block" + } + ], + "baseline_core_rtl_sha256": "03155e51ef07fec698c4c75f459478d065ed41fb324f00109d18a7426f330c05", + "additional_memory_adapters": [ + { + "module": "regfile_32x65", + "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, + "write_ports": 2, + "read_latency": 0, + "same_address_write_priority": "W1", + "added_cycles": 0, + "adapter_sha256": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/OPTIN_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/OPTIN_RESULT.json new file mode 100644 index 0000000..7a58cff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/OPTIN_RESULT.json @@ -0,0 +1,14 @@ +{ + "rob-default-raw": { + "emitted_sha256": "05d53ac2a64ae89cfdb2861b3652b0e5b9a5bea401757c29a35f9a0654a3a2eb", + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580" + }, + "rob-optin-raw": { + "emitted_sha256": "9cf090b2ecdf1f59115c5f639151ef9c0037cf2531a619d3dab349f937ec5097", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" + }, + "result": "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY", + "source_switch": "sbt -Dfpga.robOperandRam=true" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RESULT.json new file mode 100644 index 0000000..be1eac0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RESULT.json @@ -0,0 +1,51 @@ +{ + "result": "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION", + "part": "xc7a100tcsg324-1", + "mode": "UART", + "core_clock_hz": 25000000, + "baseline_record": "evidence/2026-10-11/BOARD_RESULT.json", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "routed_resources": { + "LUT": 53929, + "FF": 33943, + "Slice": 15579, + "BRAM_tiles": 31, + "DSP": 117 + }, + "resource_delta": { + "LUT": -484, + "FF": -1657, + "Slice": -84, + "BRAM_tiles": 2, + "DSP": 0 + }, + "free_slices": 271, + "gemmini_mesh_dsp": 64, + "timing": { + "wns_ns": 1.276, + "whs_ns": 0.012, + "tns_ns": 0, + "ths_ns": 0, + "wpws_ns": 0.187 + }, + "route_errors": 0, + "architectural_profile_unchanged": true, + "regression_cycles_unchanged": true, + "linux_rtl_cycles": 273506752, + "physical_board_tested": false, + "flash_boot_tested": false, + "replaces_published_artifacts": false, + "integration_sources": { + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", + "scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", + "scripts/elaborate_rob_candidate.sh": "ce65656a3ae6c9fd49d651b9cef434cf8cf3bcfb393180d210f233741c6ffa0f", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RUN.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RUN.json new file mode 100644 index 0000000..aafc26b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/RUN.json @@ -0,0 +1,71 @@ +{ + "status": "COMPLETED", + "optimization": "ROB_OPERAND_BRAM", + "timeout_seconds": 3600, + "termination_grace_seconds": 15, + "part": "xc7a100tcsg324-1", + "core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "board_sources": { + "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "execution_script": "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "execution_script_sha256": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "core_clock_hz": 25000000, + "uart_baud": 1000000, + "architectural_profile_unchanged": true, + "flash_boot": false, + "physical_boot_tested": false, + "inherits_baseline_hardware_qualification": false, + "started_at": "2026-10-12T20:13:52.282668+08:00", + "deadline": "2026-10-12T21:13:52.282668+08:00", + "command": [ + "timeout", + "--signal=TERM", + "--kill-after=15s", + "3600s", + "/home/yys/bin/vivado", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352" + ], + "worker_pid": 19876, + "timeout_process_pid": 19881, + "exit_code": 0, + "elapsed_seconds": 1396.3394632509999, + "finished_at": "2026-10-12T20:37:08.622201+08:00", + "core_unchanged": false, + "bitstream_generated": true, + "candidate_core_unchanged": true, + "candidate_memory_unchanged": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/ToyLinuxChip.profile.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/ToyLinuxChip.profile.json new file mode 100644 index 0000000..8207768 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/ToyLinuxChip.profile.json @@ -0,0 +1,73 @@ +{ + "serial_fpga": true, + "gemmini_only_balls": true, + "ball_count": 1, + "ball_names": [ + "GemminiBall" + ], + "ball_ids": [ + 0 + ], + "ball_funct7": [ + 2, + 3, + 53, + 66, + 67, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105 + ], + "ball_read_ports": 2, + "ball_write_ports": 4, + "accelerator_mmio_scale_pool": false, + "compact_caches": true, + "btb_enabled": false, + "icache_bytes": 8192, + "icache_ways": 2, + "dcache_bytes": 8192, + "dcache_mshrs": 1, + "l2_ways": 0, + "coherence_manager": "broadcast", + "rob_entries": 16, + "sub_rob_depth": 8, + "dma_n_xacts": 2, + "dma_max_in_flight": 4, + "tma_read_channels": 1, + "tma_write_channels": 1, + "cpu_mul_unroll": 8, + "gemmini_rows": 8, + "gemmini_columns": 8, + "virtual_bank_count": 16, + "trimmed_optional_peripherals": true, + "scratchpad_bytes": 0, + "cpu_use_debug": false, + "cpu_breakpoints": 0, + "extra_hpm_counters": 0, + "basic_counters": true, + "use_vm": true, + "fpu_shared_fma": true, + "fpu_sfma_latency": 6, + "fpu_dfma_latency": 6, + "fpu_min_flen": 16, + "fpu_flen": 64, + "bank_count": 8, + "bank_rows": 1024, + "bank_width": 64, + "bank_channels": 7 +} \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/cdc.rpt new file mode 100644 index 0000000..0772732 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/cdc.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:23 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 17 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/drc.rpt new file mode 100644 index 0000000..38a39cd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:22 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/route-status.rpt new file mode 100644 index 0000000..d85abf0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 119398 : + # of nets not needing routing.......... : 25764 : + # of internally routed nets........ : 23639 : + # of nets with no loads............ : 2125 : + # of routable nets..................... : 93634 : + # of fully routed nets............. : 93634 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-timing.rpt new file mode 100644 index 0000000..71fe54f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-timing.rpt @@ -0,0 +1,6691 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:17 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 107738 0.012 0.000 0 107696 0.187 0.000 0 41738 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 8.550 0.000 0 92342 0.012 0.000 0 92342 18.750 0.000 0 35501 + fb 7.845 0.000 0 3 + ref_raw 1.756 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.974 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.843 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.245 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 2.912 0.000 0 14674 0.027 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.665 0.000 0 20 +clk_pll_i ref_raw 16.907 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 10.088 0.000 0 8 45.348 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 8.404 0.000 0 8 46.023 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.095 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.557 0.000 0 20 +ref_raw clk_pll_i 16.759 0.000 0 12 0.112 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.947 0.000 0 111 0.176 0.000 0 111 +**async_default** core_raw core_raw 20.362 0.000 0 116 0.154 0.000 0 116 +**default** clk_pll_i 1.977 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 8.550ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.012ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.550ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 31.373ns (logic 7.987ns (25.458%) route 23.386ns (74.542%)) + Logic Levels: 35 (CARRY4=3 LUT2=6 LUT3=4 LUT4=8 LUT5=7 LUT6=7) + Clock Path Skew: -0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.360ns = ( 38.640 - 40.000 ) + Source Clock Delay (SCD): -0.857ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.683 -0.857 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X74Y126 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y126 FDRE (Prop_fdre_C_Q) 0.478 -0.379 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/Q + net (fo=2, routed) 1.253 0.874 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0[63] + SLICE_X82Y128 LUT6 (Prop_lut6_I4_O) 0.296 1.170 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.513 1.683 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X81Y128 LUT5 (Prop_lut5_I4_O) 0.124 1.807 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 1.224 3.031 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X68Y129 LUT5 (Prop_lut5_I4_O) 0.124 3.155 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 0.910 4.065 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X59Y137 LUT4 (Prop_lut4_I3_O) 0.124 4.189 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 0.999 5.188 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X56Y134 LUT4 (Prop_lut4_I3_O) 0.150 5.338 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[47]_i_3/O + net (fo=2, routed) 1.169 6.507 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[47] + SLICE_X48Y156 LUT6 (Prop_lut6_I0_O) 0.348 6.855 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2/O + net (fo=1, routed) 1.171 8.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2_n_0 + SLICE_X44Y161 LUT3 (Prop_lut3_I0_O) 0.124 8.150 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_1/O + net (fo=7, routed) 1.244 9.394 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[47] + SLICE_X39Y179 LUT4 (Prop_lut4_I3_O) 0.118 9.512 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9/O + net (fo=2, routed) 0.611 10.123 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9_n_0 + SLICE_X39Y178 LUT3 (Prop_lut3_I1_O) 0.320 10.443 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10/O + net (fo=1, routed) 0.569 11.011 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10_n_0 + SLICE_X41Y178 LUT6 (Prop_lut6_I2_O) 0.326 11.337 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7/O + net (fo=11, routed) 0.982 12.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7_n_0 + SLICE_X45Y174 LUT4 (Prop_lut4_I3_O) 0.150 12.469 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217/O + net (fo=3, routed) 0.591 13.060 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I1_O) 0.332 13.392 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213/O + net (fo=5, routed) 0.590 13.982 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213_n_0 + SLICE_X43Y178 LUT3 (Prop_lut3_I0_O) 0.124 14.106 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.815 14.921 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I0_O) 0.150 15.071 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.564 15.635 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.332 15.967 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.277 16.244 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.124 16.368 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.666 17.034 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X46Y180 LUT3 (Prop_lut3_I0_O) 0.124 17.158 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.602 17.759 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.149 17.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.668 18.576 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.332 18.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.579 19.487 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X45Y177 LUT5 (Prop_lut5_I3_O) 0.124 19.611 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.604 20.215 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X45Y181 LUT6 (Prop_lut6_I0_O) 0.124 20.339 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.626 20.965 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X44Y181 CARRY4 (Prop_carry4_DI[0]_O[1]) + 0.407 21.372 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[1] + net (fo=1, routed) 0.424 21.797 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[62] + SLICE_X42Y181 LUT4 (Prop_lut4_I0_O) 0.303 22.100 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135/O + net (fo=3, routed) 0.824 22.924 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135_n_0 + SLICE_X41Y181 LUT4 (Prop_lut4_I0_O) 0.152 23.076 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100/O + net (fo=2, routed) 0.584 23.660 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100_n_0 + SLICE_X41Y180 LUT4 (Prop_lut4_I3_O) 0.326 23.986 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97/O + net (fo=2, routed) 0.583 24.569 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97_n_0 + SLICE_X40Y179 LUT6 (Prop_lut6_I5_O) 0.124 24.693 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60/O + net (fo=2, routed) 0.837 25.530 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I4_O) 0.118 25.648 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 26.099 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I3_O) 0.326 26.425 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.507 26.932 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X40Y171 LUT6 (Prop_lut6_I5_O) 0.124 27.056 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 27.056 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X40Y171 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 27.457 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 27.457 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X40Y172 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 27.685 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/CO[2] + net (fo=2, routed) 0.583 28.268 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[6] + SLICE_X43Y170 LUT4 (Prop_lut4_I3_O) 0.307 28.575 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13/O + net (fo=1, routed) 0.452 29.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13_n_0 + SLICE_X46Y170 LUT6 (Prop_lut6_I3_O) 0.326 29.352 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5/O + net (fo=1, routed) 0.423 29.775 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 29.899 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2/O + net (fo=1, routed) 0.493 30.392 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 30.516 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_1/O + net (fo=1, routed) 0.000 30.516 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[6] + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.660 38.640 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/C + clock pessimism 0.488 39.128 + clock uncertainty -0.091 39.037 + SLICE_X48Y169 FDRE (Setup_fdre_C_D) 0.029 39.066 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6] + ------------------------------------------------------------------- + required time 39.066 + arrival time -30.516 + ------------------------------------------------------------------- + slack 8.550 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.012ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.285ns (logic 0.128ns (44.914%) route 0.157ns (55.086%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): -0.604ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.560 -0.604 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/clk + SLICE_X51Y66 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y66 FDRE (Prop_fdre_C_Q) 0.128 -0.476 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/Q + net (fo=1, routed) 0.157 -0.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[63]_1[56] + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/clk + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/C + clock pessimism 0.504 -0.343 + SLICE_X52Y67 FDRE (Hold_fdre_C_D) 0.012 -0.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56] + ------------------------------------------------------------------- + required time 0.331 + arrival time -0.319 + ------------------------------------------------------------------- + slack 0.012 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y69 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.756ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.756ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.724ns (logic 0.716ns (26.281%) route 2.008ns (73.719%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.519ns = ( 3.481 - 5.000 ) + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.605 -0.935 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y125 FDRE (Prop_fdre_C_Q) 0.419 -0.516 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 0.876 0.360 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X32Y131 LUT2 (Prop_lut2_I0_O) 0.297 0.657 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/arty_ddr3mig_7s_LUT2_2/O + net (fo=11, routed) 1.132 1.789 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.502 3.481 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/C + clock pessimism 0.560 4.041 + clock uncertainty -0.067 3.974 + SLICE_X28Y138 FDRE (Setup_fdre_C_R) -0.429 3.545 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1] + ------------------------------------------------------------------- + required time 3.545 + arrival time -1.789 + ------------------------------------------------------------------- + slack 1.756 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.240ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r btn_ref_meta_reg/Q + net (fo=1, routed) 0.056 -0.412 btn_ref_meta + SLICE_X67Y74 FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_sync_reg/C + clock pessimism 0.240 -0.609 + SLICE_X67Y74 FDRE (Hold_fdre_C_D) 0.075 -0.534 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.534 + arrival time -0.412 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.974ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.974ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.061 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.061 + ------------------------------------------------------------------- + slack 9.974 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.843ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.843ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.117ns (logic 0.425ns (38.045%) route 0.692ns (61.955%)) + Logic Levels: 0 + Clock Path Skew: -0.465ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.112ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.465 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y89 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) + 0.425 2.537 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/Q4 + net (fo=1, routed) 0.692 3.229 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d2[0] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D2[0]) + -0.524 13.072 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.072 + arrival time -3.229 + ------------------------------------------------------------------- + slack 9.843 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.245ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.245ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.483ns (logic 0.674ns (45.456%) route 0.809ns (54.544%)) + Logic Levels: 0 + Clock Path Skew: 0.407ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.114ns = ( 8.114 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.809 3.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.407 8.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.826 + clock uncertainty -0.054 8.772 + OLOGIC_X1Y77 OSERDESE2 (Setup_oserdese2_CLKDIV_D2) + -0.625 8.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.147 + arrival time -3.902 + ------------------------------------------------------------------- + slack 4.245 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 2.912ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.027ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.912ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.395ns (logic 0.743ns (8.850%) route 7.652ns (91.150%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.213ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.672ns = ( 12.672 - 12.000 ) + Source Clock Delay (SCD): 1.534ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.712 1.534 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg_rep__0_0 + SLICE_X77Y88 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y88 FDRE (Prop_fdre_C_Q) 0.419 1.953 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/Q + net (fo=145, routed) 4.268 6.221 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axi_wready + SLICE_X89Y110 LUT4 (Prop_lut4_I3_O) 0.324 6.545 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/goreg_dm.dout_i[144]_i_1/O + net (fo=144, routed) 3.384 9.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[144]_1[0] + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 12.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/m_aclk + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/C + clock pessimism 0.649 13.322 + clock uncertainty -0.067 13.255 + SLICE_X71Y100 FDRE (Setup_fdre_C_CE) -0.413 12.842 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18] + ------------------------------------------------------------------- + required time 12.842 + arrival time -9.929 + ------------------------------------------------------------------- + slack 2.912 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.027ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.302ns (logic 0.128ns (42.423%) route 0.174ns (57.577%)) + Logic Levels: 0 + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.192ns + Source Clock Delay (SCD): 0.136ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X53Y60 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y60 FDRE (Prop_fdre_C_Q) 0.128 0.264 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/Q + net (fo=2, routed) 0.174 0.437 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0]_4[4] + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.831 0.192 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/C + clock pessimism 0.210 0.402 + SLICE_X50Y61 FDRE (Hold_fdre_C_D) 0.009 0.411 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4] + ------------------------------------------------------------------- + required time -0.411 + arrival time 0.437 + ------------------------------------------------------------------- + slack 0.027 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.665ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.665ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.065ns (logic 0.419ns (39.345%) route 0.646ns (60.655%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 1.065 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 11.730 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 11.730 + arrival time -1.065 + ------------------------------------------------------------------- + slack 10.665 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 16.907ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.907ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 3.012ns (logic 0.456ns (15.138%) route 2.556ns (84.862%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.556 3.012 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X32Y125 FDRE (Setup_fdre_C_D) -0.081 19.919 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.919 + arrival time -3.012 + ------------------------------------------------------------------- + slack 16.907 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.088ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.348ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.088ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 6.328ns (logic 3.867ns (61.105%) route 2.461ns (38.895%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.219ns = ( 2.719 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.461 4.443 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 7.039 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 7.039 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.854 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.854 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.412 17.719 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.327 + clock uncertainty -0.220 18.107 + ILOGIC_X1Y85 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.942 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.942 + arrival time -7.854 + ------------------------------------------------------------------- + slack 10.088 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.348ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.688ns (logic 1.068ns (63.257%) route 0.620ns (36.743%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.065ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.990ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.620 60.924 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.608 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.851 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.178 15.990 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.227 + clock uncertainty 0.220 16.447 + ILOGIC_X1Y77 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.503 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.503 + arrival time 61.851 + ------------------------------------------------------------------- + slack 45.348 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 8.404ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 46.023ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.404ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.019ns (logic 3.867ns (48.222%) route 4.152ns (51.778%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 4.152 6.133 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 8.729 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 8.729 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 9.544 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 9.544 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -9.544 + ------------------------------------------------------------------- + slack 8.404 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 46.023ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 2.362ns (logic 1.068ns (45.210%) route 1.294ns (54.790%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.064ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 1.294 61.598 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUFDISABLE + L6 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 62.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 62.282 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y88 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 62.525 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 62.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y88 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 62.525 + ------------------------------------------------------------------- + slack 46.023 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y6 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.557ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.557ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.165ns (logic 0.419ns (35.978%) route 0.746ns (64.022%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 1.165 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 39.722 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 39.722 + arrival time -1.165 + ------------------------------------------------------------------- + slack 38.557 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 16.759ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.944ns (logic 0.456ns (9.223%) route 4.488ns (90.777%)) + Logic Levels: 0 + Clock Path Skew: 1.995ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.667ns + Source Clock Delay (SCD): -0.933ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.607 -0.933 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y126 FDRE (Prop_fdre_C_Q) 0.456 -0.477 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/Q + net (fo=1, routed) 4.488 4.011 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[7] + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.495 20.667 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/C + clock pessimism 0.395 21.062 + clock uncertainty -0.245 20.817 + SLICE_X35Y129 FDRE (Setup_fdre_C_D) -0.047 20.770 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7] + ------------------------------------------------------------------- + required time 20.770 + arrival time -4.011 + ------------------------------------------------------------------- + slack 16.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.112ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.784ns (logic 0.141ns (7.901%) route 1.643ns (92.099%)) + Logic Levels: 0 + Clock Path Skew: 1.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.185ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.553 -0.611 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X33Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.470 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/Q + net (fo=1, routed) 1.643 1.173 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[4] + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.823 0.185 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/C + clock pessimism 0.557 0.741 + clock uncertainty 0.245 0.986 + SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.075 1.061 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4] + ------------------------------------------------------------------- + required time -1.061 + arrival time 1.173 + ------------------------------------------------------------------- + slack 0.112 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.947ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.947ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.717ns (logic 0.518ns (19.068%) route 2.199ns (80.932%)) + Logic Levels: 0 + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.763ns = ( 12.763 - 12.000 ) + Source Clock Delay (SCD): 1.442ns + Clock Pessimism Removal (CPR): 0.729ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.620 1.442 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X58Y66 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + SLICE_X58Y66 FDPE (Prop_fdpe_C_Q) 0.518 1.960 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=47, routed) 2.199 4.159 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + SLICE_X78Y66 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.590 12.763 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.729 13.492 + clock uncertainty -0.067 13.425 + SLICE_X78Y66 FDCE (Recov_fdce_C_CLR) -0.319 13.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 13.106 + arrival time -4.159 + ------------------------------------------------------------------- + slack 8.947 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.176ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.291ns (logic 0.128ns (43.969%) route 0.163ns (56.031%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.180ns + Source Clock Delay (SCD): 0.129ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.553 0.129 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.257 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.163 0.420 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + SLICE_X53Y77 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.819 0.180 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + SLICE_X53Y77 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.210 0.390 + SLICE_X53Y77 FDCE (Remov_fdce_C_CLR) -0.146 0.244 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time -0.244 + arrival time 0.420 + ------------------------------------------------------------------- + slack 0.176 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 20.362ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 20.362ns (required time - arrival time) + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 19.149ns (logic 1.308ns (6.831%) route 17.841ns (93.169%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.079ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.493ns = ( 38.507 - 40.000 ) + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.487ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.825 2.294 platform/normalizer/sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.153 2.447 f platform/normalizer/axi_fullwidth_LUT4_10/O + net (fo=899, routed) 3.798 6.246 platform/loader/cpu_run_reg_inv_20 + SLICE_X85Y102 LUT2 (Prop_lut2_I0_O) 0.327 6.573 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3764, routed) 11.649 18.222 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X10Y93 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.527 38.507 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X10Y93 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/C + clock pessimism 0.487 38.994 + clock uncertainty -0.091 38.903 + SLICE_X10Y93 FDCE (Recov_fdce_C_CLR) -0.319 38.584 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1] + ------------------------------------------------------------------- + required time 38.584 + arrival time -18.222 + ------------------------------------------------------------------- + slack 20.362 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.154ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.141ns (40.345%) route 0.208ns (59.655%)) + Logic Levels: 0 + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.557 -0.607 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X51Y80 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y80 FDPE (Prop_fdpe_C_Q) 0.141 -0.466 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.208 -0.258 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X54Y80 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.824 -0.849 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X54Y80 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.504 -0.345 + SLICE_X54Y80 FDCE (Remov_fdce_C_CLR) -0.067 -0.412 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time 0.412 + arrival time -0.258 + ------------------------------------------------------------------- + slack 0.154 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 1.977ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.977ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 3.023ns (logic 0.456ns (15.083%) route 2.567ns (84.917%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.567 3.023 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -3.023 + ------------------------------------------------------------------- + slack 1.977 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + (rising edge-triggered cell FDCE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.748ns (logic 2.163ns (37.622%) route 3.586ns (62.378%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.711 1.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y66 FDCE (Prop_fdce_C_Q) 0.518 2.051 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/Q + net (fo=1, routed) 0.961 3.012 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n + SLICE_X87Y66 LUT2 (Prop_lut2_I1_O) 0.124 3.136 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.625 5.761 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.282 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.376ns (logic 0.141ns (10.246%) route 1.235ns (89.754%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.235 1.510 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/loader/cpu_run_reg_inv/C + (rising edge-triggered cell FDSE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 12.328ns (logic 4.784ns (38.808%) route 7.544ns (61.192%)) + Logic Levels: 2 (LUT5=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.721 -0.819 platform/loader/clk + SLICE_X78Y96 FDSE r platform/loader/cpu_run_reg_inv/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y96 FDSE (Prop_fdse_C_Q) 0.478 -0.341 f platform/loader/cpu_run_reg_inv/Q + net (fo=264, routed) 3.176 2.835 platform/loader/rx_valid1 + SLICE_X69Y78 LUT5 (Prop_lut5_I4_O) 0.295 3.130 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 4.368 7.498 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.011 11.509 r led_OBUF[2]_inst/O + net (fo=0) 0.000 11.509 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/peripherals/exit_code_reg[19]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.331ns (logic 2.205ns (66.189%) route 1.126ns (33.811%)) + Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.559 -0.605 platform/peripherals/clk + SLICE_X54Y101 FDRE r platform/peripherals/exit_code_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.164 -0.441 r platform/peripherals/exit_code_reg[19]/Q + net (fo=2, routed) 0.094 -0.347 platform/peripherals/exit_code[19] + SLICE_X55Y101 LUT6 (Prop_lut6_I3_O) 0.045 -0.302 r platform/peripherals/led_OBUF[1]_inst_i_4/O + net (fo=1, routed) 0.082 -0.220 platform/peripherals/led_OBUF[1]_inst_i_4_n_0 + SLICE_X55Y101 LUT5 (Prop_lut5_I2_O) 0.045 -0.175 r platform/peripherals/led_OBUF[1]_inst_i_1/O + net (fo=1, routed) 0.950 0.775 led_OBUF[1] + J5 OBUF (Prop_obuf_I_O) 1.951 2.726 r led_OBUF[1]_inst/O + net (fo=0) 0.000 2.726 led[1] + J5 r led[1] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.076ns (logic 0.711ns (17.445%) route 3.365ns (82.555%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.670ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 5.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.744ns (logic 0.232ns (31.172%) route 0.512ns (68.828%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.049ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.181ns + Source Clock Delay (SCD): 0.132ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.556 0.132 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.260 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.086 0.345 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.104 0.449 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.876 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X51Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.820 0.181 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.211ns (logic 1.308ns (18.138%) route 5.903ns (81.862%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.693ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 6.285 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.586ns (logic 0.337ns (57.552%) route 0.249ns (42.448%)) + Logic Levels: 0 + Clock Path Skew: 2.961ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.453ns + Source Clock Delay (SCD): -1.508ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.337 -1.171 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.249 -0.923 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.631 1.453 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.754ns (logic 0.402ns (22.913%) route 1.352ns (77.087%)) + Logic Levels: 0 + Clock Path Skew: 0.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.758ns + Source Clock Delay (SCD): -0.189ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.213 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 1.352 1.566 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.758 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.546ns (logic 0.204ns (37.365%) route 0.342ns (62.635%)) + Logic Levels: 0 + Clock Path Skew: 0.574ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.223ns + Source Clock Delay (SCD): -0.351ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.204 -0.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.342 0.195 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.619ns (logic 0.779ns (11.769%) route 5.840ns (88.231%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.586ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.659ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.301 1.178 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 5.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.567ns (logic 0.247ns (15.765%) route 1.320ns (84.235%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.847ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.238ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.099 0.239 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.719 0.957 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X83Y97 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.877 0.238 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X83Y97 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.988ns (logic 1.487ns (18.620%) route 6.501ns (81.380%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.522ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.522ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.501 7.988 btn0_IBUF + SLICE_X67Y77 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 clk + SLICE_X67Y77 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: uart_txd_in + (input port) + Destination: platform/receiver/rx_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.930ns (logic 0.294ns (15.218%) route 1.637ns (84.782%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + A9 0.000 0.000 r uart_txd_in (IN) + net (fo=0) 0.000 0.000 uart_txd_in + A9 IBUF (Prop_ibuf_I_O) 0.294 0.294 r uart_txd_in_IBUF_inst/O + net (fo=1, routed) 1.637 1.930 platform/receiver/rx + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.835 -0.838 platform/receiver/clk + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 3.789ns (logic 0.711ns (18.764%) route 3.078ns (81.236%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.866ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.238ns (logic 0.128ns (53.830%) route 0.110ns (46.170%)) + Logic Levels: 0 + Clock Path Skew: -0.978ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): 0.131ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.555 0.131 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.128 0.259 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.110 0.369 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.925ns (logic 1.308ns (18.888%) route 5.617ns (81.112%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.503ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.998 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.285ns (logic 0.293ns (22.796%) route 0.992ns (77.204%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.245ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.851ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.558 -0.606 clk + SLICE_X63Y78 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y78 FDPE (Prop_fdpe_C_Q) 0.141 -0.465 f lock_sync_reg[2]/Q + net (fo=4, routed) 0.287 -0.179 lock_sync[2] + SLICE_X69Y78 LUT4 (Prop_lut4_I1_O) 0.043 -0.136 r memory_cdc_i_1/O + net (fo=1, routed) 0.279 0.143 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.109 0.252 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.679 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X50Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.822 -0.851 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X50Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.119ns (logic 1.487ns (18.320%) route 6.632ns (81.680%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.525ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.525ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.632 8.119 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.495 -1.525 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.179ns (logic 0.255ns (8.026%) route 2.924ns (91.974%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.849ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.924 3.179 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.213ns (logic 0.141ns (11.621%) route 1.072ns (88.379%)) + Logic Levels: 0 + Clock Path Skew: -0.987ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.853ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.072 1.347 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.820 -0.853 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.125ns (logic 0.808ns (19.586%) route 3.317ns (80.414%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.481ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.408ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.330 1.207 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.992 3.199 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y53 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.612 -1.408 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y53 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.482ns (logic 0.244ns (16.461%) route 1.238ns (83.539%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.184ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.793ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.096 0.236 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 0.637 0.873 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y50 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.880 -0.793 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y50 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.581ns (logic 0.124ns (1.884%) route 6.457ns (98.116%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 1.943 1.943 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X89Y75 LUT4 (Prop_lut4_I0_O) 0.124 2.067 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 6.581 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.723ns (logic 0.045ns (6.224%) route 0.678ns (93.776%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.317 0.317 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in_n_6 + SLICE_X89Y75 LUT2 (Prop_lut2_I0_O) 0.045 0.362 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.361 0.723 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-utilization.rpt new file mode 100644 index 0000000..a543491 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/implementation/routed-utilization.rpt @@ -0,0 +1,264 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:07 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 53929 | 0 | 0 | 63400 | 85.06 | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15579 | 0 | 0 | 15850 | 98.29 | +| SLICEL | 10888 | 0 | | | | +| SLICEM | 4691 | 0 | | | | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37318 | | | | | +| using O5 and O6 | 12658 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register driven from within the Slice | 15009 | | | | | +| Register driven from outside the Slice | 18934 | | | | | +| LUT in front of the register is unused | 4958 | | | | | +| LUT in front of the register is used | 13976 | | | | | +| Unique Control Sets | 1256 | | 0 | 15850 | 7.92 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/RESULT.json new file mode 100644 index 0000000..1bc1b0b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/RESULT.json @@ -0,0 +1,9 @@ +{ + "flash_written": false, + "configuration_changed": false, + "watchdog_alive_rc": 1, + "MemTotal_kib": 245888, + "MemAvailable_kib": 226060, + "uart_latency_restored_ms": 16, + "result": "PASS_POST_TEST_LIVE_SHELL" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/post-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/post-console.log new file mode 100644 index 0000000..c1a5f19 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/post-check/post-console.log @@ -0,0 +1,8 @@ +kill -0 "$w" 2>/dev/null; printf "\nWATCHDOG_ALIVE_RC:%s\n" "$?" + +WATCHDOG_ALIVE_RC:1 +~ # while read a b c; do case "$a" in MemTotal:|MemAvailable:) printf "%s %s %s\ +n" "$a" "$b" "$c";; esac; done < /proc/meminfo; printf "LIVE_MEM_DONE\n" +MemTotal: 245888 kB +MemAvailable: 226060 kB +LIVE_MEM_DONE diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/LOAD_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/LOAD_RESULT.json new file mode 100644 index 0000000..dfa4f4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/LOAD_RESULT.json @@ -0,0 +1,90 @@ +{ + "result": "PASS_LINUX_AND_GEMMINI_HARDWARE", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "port": "COM5", + "timeout_seconds": 3600, + "flash_written": false, + "tests": [ + { + "name": "linux_system_check-linux", + "exit_code": 0, + "output": "/root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai\nt $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_0:%s\\\nn' $r\nBEGIN LINUX_SYSTEM_CHECK\nPASS VM_COPY_ON_WRITE\nlinux_system_ch[26]: unhandled signal 11 code 0x2 at 0x0000003f9030e000 in linux_system_check-linux[10000+7a000]\nCPU: 0 PID: 26 Comm: linux_system_ch Not tainted 6.6.0 #1\nHardware name: ucb-bar,buckyball (DT)\nepc : 00000000000105c6 ra : 000000000001041e sp : 0000003fca649b50\n gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000\n t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fca649bd0\n s1 : 0000003f9030d000 a0 : 0000000000000000 a1 : 0000000000000000\n a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000\n a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000\n s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f9030e000\n s5 : 0000003fca649d88 s6 : 0000000000000002 s7 : 00000000000106ba\n s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28\n s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000\n t5 : 0000000000000000 t6 : 0000000000000000\nstatus: 800000020001e020 badaddr: 0000003f9030e000 cause: 000000000000000d\nPASS VM_PAGE_PROTECTION\nPASS FP64_PROCESS_CONTEXT\nPASS LINUX_TIMER elapsed_ns=102926000\nPASS LINUX_SYSTEM_CHECK\n\nWB_TEST_RC_0:0\n" + }, + { + "name": "gemmini_linux_check-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa\nit $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_1:%s\n\\n' $r\nBEGIN GEMMINI_LINUX_CHECK pid=28 dimension=8 bank_width=64\nBEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=2538000 accelerator_end_to_end_ns=894000\nBEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=614000 accelerator_end_to_end_ns=2600000\nBEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5606000 accelerator_end_to_end_ns=5658000\nBEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=11158000 accelerator_end_to_end_ns=7596000\nBEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4128000 accelerator_end_to_end_ns=10132000\nBEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3960000 accelerator_end_to_end_ns=8644000\nBEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=1578000 accelerator_end_to_end_ns=1754000\nBEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3308000 accelerator_end_to_end_ns=3742000\nBEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=638000 accelerator_end_to_end_ns=2802000\nBEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=878000\nBEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=7116000 accelerator_end_to_end_ns=5728000\nBEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5564000 accelerator_end_to_end_ns=7472000\nBEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=4206000 accelerator_end_to_end_ns=10058000\nBEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=3898000 accelerator_end_to_end_ns=8544000\nBEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=3336000 accelerator_end_to_end_ns=1660000\nBEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=1568000 accelerator_end_to_end_ns=3632000\nPASS GEMMINI_LINUX_CHECK cases=16\n\nWB_TEST_RC_1:0\n" + }, + { + "name": "gemmini_os_cisc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_2:%s\\n' $r\n=== Gemmini OS CISC a_transpose Test ===\nGemmini OS CISC a_transpose Test PASSED\n\nWB_TEST_RC_2:0\n" + }, + { + "name": "gemmini_os_cisc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_3:%s\\n' $r\n=== Gemmini OS CISC Basic Test ===\nGemmini OS CISC Basic Test PASSED\n\nWB_TEST_RC_3:0\n" + }, + { + "name": "gemmini_os_cisc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_4:%s\\n' $r\n=== Gemmini OS CISC b_transpose Test ===\nGemmini OS CISC b_transpose Test PASSED\n\nWB_TEST_RC_4:0\n" + }, + { + "name": "gemmini_os_cisc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_5:%s\\n' $r\n=== Gemmini OS CISC in_shift Test ===\nGemmini OS CISC in_shift Test PASSED\n\nWB_TEST_RC_5:0\n" + }, + { + "name": "gemmini_os_risc_abtranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $\np) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB\n_TEST_RC_6:%s\\n' $r\n=== Gemmini OS RISC ab_transpose Test ===\nGemmini OS RISC ab_transpose Test PASSED\n\nWB_TEST_RC_6:0\n" + }, + { + "name": "gemmini_os_risc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_7:%s\\n' $r\n=== Gemmini OS RISC a_transpose Test ===\nGemmini OS RISC a_transpose Test PASSED\n\nWB_TEST_RC_7:0\n" + }, + { + "name": "gemmini_os_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_8:%s\\n' $r\n=== Gemmini OS RISC Basic Test ===\nGemmini OS RISC Basic Test PASSED\n\nWB_TEST_RC_8:0\n" + }, + { + "name": "gemmini_os_risc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_9:%s\\n' $r\n=== Gemmini OS RISC b_transpose Test ===\nGemmini OS RISC b_transpose Test PASSED\n\nWB_TEST_RC_9:0\n" + }, + { + "name": "gemmini_os_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_10:%s\\n' $r\n=== Gemmini OS RISC in_shift Test ===\nGemmini OS RISC in_shift Test PASSED\n\nWB_TEST_RC_10:0\n" + }, + { + "name": "gemmini_ws_cisc_conv_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w=\n$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_R\nC_11:%s\\n' $r\n=== Gemmini WS CISC Loop Conv Test ===\nGemmini WS CISC Loop Conv Test PASSED\n\nWB_TEST_RC_11:0\n" + }, + { + "name": "gemmini_ws_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_12:%s\\n' $r\n=== Gemmini WS RISC Basic Test ===\nGemmini WS RISC Basic Test PASSED\n\nWB_TEST_RC_12:0\n" + }, + { + "name": "gemmini_ws_risc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_13:%s\\n' $r\n=== Gemmini WS RISC b_transpose Test ===\nGemmini WS RISC b_transpose Test PASSED\n\nWB_TEST_RC_13:0\n" + }, + { + "name": "gemmini_ws_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_14:%s\\n' $r\n=== Gemmini WS RISC in_shift Test ===\nGemmini WS RISC in_shift Test PASSED\n\nWB_TEST_RC_14:0\n" + } + ], + "ddr_readback_bytes": 25797640, + "ddr_transfer_seconds": 806.265, + "test_count": 15, + "blocked_matmul_cases": 16, + "elapsed_seconds": 916.109 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/PERFORMANCE.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/PERFORMANCE.json new file mode 100644 index 0000000..9f2b1e3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/PERFORMANCE.json @@ -0,0 +1,169 @@ +{ + "result": "PASS_OFFLINE_VERIFICATION", + "console_sha256": "5fcf06aa8c9078e948ed2b66a7f1ebd9142c203b7d7d17d01ae96e1a9594822e", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "matrix_measurements": [ + { + "case": 1, + "mode": "OS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 666000, + "accelerator_end_to_end_ns": 2658000, + "cpu_over_accelerator": 0.2506 + }, + { + "case": 2, + "mode": "WS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 610000, + "accelerator_end_to_end_ns": 864000, + "cpu_over_accelerator": 0.706 + }, + { + "case": 3, + "mode": "OS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 5588000, + "accelerator_end_to_end_ns": 7500000, + "cpu_over_accelerator": 0.7451 + }, + { + "case": 4, + "mode": "WS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 5458000, + "accelerator_end_to_end_ns": 7714000, + "cpu_over_accelerator": 0.7075 + }, + { + "case": 5, + "mode": "OS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 4196000, + "accelerator_end_to_end_ns": 10404000, + "cpu_over_accelerator": 0.4033 + }, + { + "case": 6, + "mode": "WS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 3962000, + "accelerator_end_to_end_ns": 12618000, + "cpu_over_accelerator": 0.314 + }, + { + "case": 7, + "mode": "OS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 3358000, + "accelerator_end_to_end_ns": 1700000, + "cpu_over_accelerator": 1.9753 + }, + { + "case": 8, + "mode": "WS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 3282000, + "accelerator_end_to_end_ns": 4452000, + "cpu_over_accelerator": 0.7372 + }, + { + "case": 9, + "mode": "OS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 628000, + "accelerator_end_to_end_ns": 2856000, + "cpu_over_accelerator": 0.2199 + }, + { + "case": 10, + "mode": "WS", + "m": 8, + "n": 8, + "k": 8, + "cpu_ns": 636000, + "accelerator_end_to_end_ns": 876000, + "cpu_over_accelerator": 0.726 + }, + { + "case": 11, + "mode": "OS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 11124000, + "accelerator_end_to_end_ns": 7766000, + "cpu_over_accelerator": 1.4324 + }, + { + "case": 12, + "mode": "WS", + "m": 16, + "n": 16, + "k": 16, + "cpu_ns": 5572000, + "accelerator_end_to_end_ns": 5668000, + "cpu_over_accelerator": 0.9831 + }, + { + "case": 13, + "mode": "OS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 7182000, + "accelerator_end_to_end_ns": 8750000, + "cpu_over_accelerator": 0.8208 + }, + { + "case": 14, + "mode": "WS", + "m": 13, + "n": 11, + "k": 17, + "cpu_ns": 5600000, + "accelerator_end_to_end_ns": 8488000, + "cpu_over_accelerator": 0.6598 + }, + { + "case": 15, + "mode": "OS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 1596000, + "accelerator_end_to_end_ns": 3422000, + "cpu_over_accelerator": 0.4664 + }, + { + "case": 16, + "mode": "WS", + "m": 8, + "n": 24, + "k": 8, + "cpu_ns": 3330000, + "accelerator_end_to_end_ns": 3666000, + "cpu_over_accelerator": 0.9083 + } + ], + "timing_scope": "分块、DMA、配置、同步和 CPU 跨 K 累加；不是纯 MAC 延迟", + "model_end_to_end_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/RESULT.json new file mode 100644 index 0000000..6cb32b0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/RESULT.json @@ -0,0 +1,109 @@ +{ + "result": "PASS_LINUX_AND_GEMMINI_HARDWARE", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "port": "COM5", + "timeout_seconds": 3600, + "flash_written": false, + "tests": [ + { + "name": "linux_system_check-linux", + "exit_code": 0, + "output": "~ # /root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai\nt $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_0:%s\\\nn' $r\nBEGIN LINUX_SYSTEM_CHECK\nPASS VM_COPY_ON_WRITE\nlinux_system_ch[74]: unhandled signal 11 code 0x2 at 0x0000003fad4a5000 in linux_system_check-linux[10000+7a000]\nCPU: 0 PID: 74 Comm: linux_system_ch Not tainted 6.6.0 #1\nHardware name: ucb-bar,buckyball (DT)\nepc : 00000000000105c6 ra : 000000000001041e sp : 0000003fc0983b50\n gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000\n t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fc0983bd0\n s1 : 0000003fad4a4000 a0 : 0000000000000000 a1 : 0000000000000000\n a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000\n a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000\n s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003fad4a5000\n s5 : 0000003fc0983d88 s6 : 0000000000000002 s7 : 00000000000106ba\n s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28\n s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000\n t5 : 0000000000000000 t6 : 0000000000000000\nstatus: 800000020001e020 badaddr: 0000003fad4a5000 cause: 000000000000000d\nPASS VM_PAGE_PROTECTION\nPASS FP64_PROCESS_CONTEXT\nPASS LINUX_TIMER elapsed_ns=103262000\nPASS LINUX_SYSTEM_CHECK\n\nWB_TEST_RC_0:0\n" + }, + { + "name": "gemmini_linux_check-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa\nit $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_RC_1:%s\n\\n' $r\nBEGIN GEMMINI_LINUX_CHECK pid=76 dimension=8 bank_width=64\nBEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=666000 accelerator_end_to_end_ns=2658000\nBEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=610000 accelerator_end_to_end_ns=864000\nBEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5588000 accelerator_end_to_end_ns=7500000\nBEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=5458000 accelerator_end_to_end_ns=7714000\nBEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4196000 accelerator_end_to_end_ns=10404000\nBEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3962000 accelerator_end_to_end_ns=12618000\nBEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=3358000 accelerator_end_to_end_ns=1700000\nBEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3282000 accelerator_end_to_end_ns=4452000\nBEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8\nPASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=2856000\nBEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8\nPASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=636000 accelerator_end_to_end_ns=876000\nBEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16\nPASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=11124000 accelerator_end_to_end_ns=7766000\nBEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16\nPASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5572000 accelerator_end_to_end_ns=5668000\nBEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17\nPASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=7182000 accelerator_end_to_end_ns=8750000\nBEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17\nPASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=5600000 accelerator_end_to_end_ns=8488000\nBEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8\nPASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=1596000 accelerator_end_to_end_ns=3422000\nBEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8\nPASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=3330000 accelerator_end_to_end_ns=3666000\nPASS GEMMINI_LINUX_CHECK cases=16\n\nWB_TEST_RC_1:0\n" + }, + { + "name": "gemmini_os_cisc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_2:%s\\n' $r\n=== Gemmini OS CISC a_transpose Test ===\nGemmini OS CISC a_transpose Test PASSED\n\nWB_TEST_RC_2:0\n" + }, + { + "name": "gemmini_os_cisc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_3:%s\\n' $r\n=== Gemmini OS CISC Basic Test ===\nGemmini OS CISC Basic Test PASSED\n\nWB_TEST_RC_3:0\n" + }, + { + "name": "gemmini_os_cisc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_4:%s\\n' $r\n=== Gemmini OS CISC b_transpose Test ===\nGemmini OS CISC b_transpose Test PASSED\n\nWB_TEST_RC_4:0\n" + }, + { + "name": "gemmini_os_cisc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_5:%s\\n' $r\n=== Gemmini OS CISC in_shift Test ===\nGemmini OS CISC in_shift Test PASSED\n\nWB_TEST_RC_5:0\n" + }, + { + "name": "gemmini_os_risc_abtranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $\np) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB\n_TEST_RC_6:%s\\n' $r\n=== Gemmini OS RISC ab_transpose Test ===\nGemmini OS RISC ab_transpose Test PASSED\n\nWB_TEST_RC_6:0\n" + }, + { + "name": "gemmini_os_risc_atranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_7:%s\\n' $r\n=== Gemmini OS RISC a_transpose Test ===\nGemmini OS RISC a_transpose Test PASSED\n\nWB_TEST_RC_7:0\n" + }, + { + "name": "gemmini_os_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_8:%s\\n' $r\n=== Gemmini OS RISC Basic Test ===\nGemmini OS RISC Basic Test PASSED\n\nWB_TEST_RC_8:0\n" + }, + { + "name": "gemmini_os_risc_btranspose_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_9:%s\\n' $r\n=== Gemmini OS RISC b_transpose Test ===\nGemmini OS RISC b_transpose Test PASSED\n\nWB_TEST_RC_9:0\n" + }, + { + "name": "gemmini_os_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_10:%s\\n' $r\n=== Gemmini OS RISC in_shift Test ===\nGemmini OS RISC in_shift Test PASSED\n\nWB_TEST_RC_10:0\n" + }, + { + "name": "gemmini_ws_cisc_conv_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w=\n$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_R\nC_11:%s\\n' $r\n=== Gemmini WS CISC Loop Conv Test ===\nGemmini WS CISC Loop Conv Test PASSED\n\nWB_TEST_RC_11:0\n" + }, + { + "name": "gemmini_ws_risc_basic_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_12:%s\\n' $r\n=== Gemmini WS RISC Basic Test ===\nGemmini WS RISC Basic Test PASSED\n\nWB_TEST_RC_12:0\n" + }, + { + "name": "gemmini_ws_risc_btranspose_test-linux", + "exit_code": 0, + "output": "/root/gemmini_ws_risc_btranspose~ # _test-linux & p=/$!; (sleep 90; krill -KILL $p) & ow=$!; wait $p; ro=$?; kill $w 2>/tdev/null; wait $/w 2>/dev/null; pgrintf '\\nWB_TESTe_RC_13:%s\\n' $rm\nmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p\n) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_\nTEST_RC_13:%s\\n' $r\n=== Gemmini WS RISC b_transpose Test ===\nGemmini WS RISC b_transpose Test PASSED\n\nWB_TEST_RC_13:0\n" + }, + { + "name": "gemmini_ws_risc_shift_test-linux", + "exit_code": 0, + "output": "~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w\n=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\\nWB_TEST_\nRC_14:%s\\n' $r\n=== Gemmini WS RISC in_shift Test ===\nGemmini WS RISC in_shift Test PASSED\n\nWB_TEST_RC_14:0\n" + } + ], + "loaded_run": "D:\\Verilog_Dev\\fpga-arty-a7-gemmini-linux\\platforms\\arty-a7-toy\\build\\hardware-gemmini-20261012-bcff9cd0", + "ddr_readback_bytes": 25797640, + "ddr_transfer_seconds": 806.265, + "configuration_reused": true, + "workload_hashes": { + "gemmini_linux_check-linux": "3d80717b1f0b593e22761e78626c38dec685c7a25c3d53ed42037357b652aa90", + "gemmini_os_cisc_atranspose_test-linux": "a2a79cc1d7bb333494ae14307685fb4b8891869a5d1eb037c004c176e0b98f6c", + "gemmini_os_cisc_basic_test-linux": "1215a8cafc2d6c11cfc8f01888f6bbecb8b2ca2201d5145f474bc852b68e4af4", + "gemmini_os_cisc_btranspose_test-linux": "18fe78a5f89ce0123f475df151d407cdb1b68c99dda7ef94b5255f376a667ec9", + "gemmini_os_cisc_shift_test-linux": "8b909fa200eeb000eb21cc71ca5ee2c960079fea2d57c62914e1ea3db4ba1651", + "gemmini_os_risc_abtranspose_test-linux": "443f12c0b2c6695c88592ac6c40b29ec56b09750d4e993c60b1bfceb5fdd1b5d", + "gemmini_os_risc_atranspose_test-linux": "40b99995cb6da30d2c3ba3a22b409033ddb2bd919b65b9eb1e0a3c19b67ff72e", + "gemmini_os_risc_basic_test-linux": "c789f91569d945db7c3d0b9d3441ab8938bc63354b0cabdfc003b634928664ba", + "gemmini_os_risc_btranspose_test-linux": "157bc4c831becf30652c60f62cbe65d33a60e8daa2eaa3ede2c8f8462f3a10b7", + "gemmini_os_risc_shift_test-linux": "be2b3cdaf1508650b374a36ac71b6a2bc05773366534ccd4cb1ce0a6ff524a76", + "gemmini_ws_cisc_conv_test-linux": "dd6d61b4f5d3a3058c6d2ca9a719c2a764533a01931a6e1c8d502f4793cdc9b4", + "gemmini_ws_risc_basic_test-linux": "b71942c93c3c6e2fc0ae9a2bfb07f7c061eef863e1282bf1c38a58d3864fa796", + "gemmini_ws_risc_btranspose_test-linux": "db3c5c781198f5c9f6d4df6c74ed640c1dc20e3964a32908b57b3e6264a584e7", + "gemmini_ws_risc_shift_test-linux": "14ef70b0c8a134ab12deb37bb6d0b245b19243cf556eb0da970d823e7032a822", + "linux_system_check-linux": "7fff55e3b560fd72482984f225b70a4a1154512452b96fc1467665b2acc32e00" + }, + "test_count": 15, + "blocked_matmul_cases": 16, + "elapsed_seconds": 123.937 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/boot-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/boot-console.log new file mode 100644 index 0000000..7ec3dd4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/boot-console.log @@ -0,0 +1,297 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Mon Oct 12 12:10:02 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 233208K/262144K available (2126K kernel code, 4319K rwdata, 2048K rodata, 12681K init, 299K bss, 28936K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 12680K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # /root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai +t $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_0:%s\ +n' $r +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[26]: unhandled signal 11 code 0x2 at 0x0000003f9030e000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 26 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fca649b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fca649bd0 + s1 : 0000003f9030d000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f9030e000 + s5 : 0000003fca649d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f9030e000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=102926000 +PASS LINUX_SYSTEM_CHECK + +WB_TEST_RC_0:0 +~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa +it $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_1:%s +\n' $r +BEGIN GEMMINI_LINUX_CHECK pid=28 dimension=8 bank_width=64 +BEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=2538000 accelerator_end_to_end_ns=894000 +BEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=614000 accelerator_end_to_end_ns=2600000 +BEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5606000 accelerator_end_to_end_ns=5658000 +BEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=11158000 accelerator_end_to_end_ns=7596000 +BEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4128000 accelerator_end_to_end_ns=10132000 +BEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3960000 accelerator_end_to_end_ns=8644000 +BEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=1578000 accelerator_end_to_end_ns=1754000 +BEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3308000 accelerator_end_to_end_ns=3742000 +BEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=638000 accelerator_end_to_end_ns=2802000 +BEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=878000 +BEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=7116000 accelerator_end_to_end_ns=5728000 +BEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5564000 accelerator_end_to_end_ns=7472000 +BEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=4206000 accelerator_end_to_end_ns=10058000 +BEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=3898000 accelerator_end_to_end_ns=8544000 +BEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=3336000 accelerator_end_to_end_ns=1660000 +BEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=1568000 accelerator_end_to_end_ns=3632000 +PASS GEMMINI_LINUX_CHECK cases=16 + +WB_TEST_RC_1:0 +~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_2:%s\n' $r +=== Gemmini OS CISC a_transpose Test === +Gemmini OS CISC a_transpose Test PASSED + +WB_TEST_RC_2:0 +~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_3:%s\n' $r +=== Gemmini OS CISC Basic Test === +Gemmini OS CISC Basic Test PASSED + +WB_TEST_RC_3:0 +~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_4:%s\n' $r +=== Gemmini OS CISC b_transpose Test === +Gemmini OS CISC b_transpose Test PASSED + +WB_TEST_RC_4:0 +~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_5:%s\n' $r +=== Gemmini OS CISC in_shift Test === +Gemmini OS CISC in_shift Test PASSED + +WB_TEST_RC_5:0 +~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $ +p) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB +_TEST_RC_6:%s\n' $r +=== Gemmini OS RISC ab_transpose Test === +Gemmini OS RISC ab_transpose Test PASSED + +WB_TEST_RC_6:0 +~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_7:%s\n' $r +=== Gemmini OS RISC a_transpose Test === +Gemmini OS RISC a_transpose Test PASSED + +WB_TEST_RC_7:0 +~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_8:%s\n' $r +=== Gemmini OS RISC Basic Test === +Gemmini OS RISC Basic Test PASSED + +WB_TEST_RC_8:0 +~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_9:%s\n' $r +=== Gemmini OS RISC b_transpose Test === +Gemmini OS RISC b_transpose Test PASSED + +WB_TEST_RC_9:0 +~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_10:%s\n' $r +=== Gemmini OS RISC in_shift Test === +Gemmini OS RISC in_shift Test PASSED + +WB_TEST_RC_10:0 +~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w= +$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_R +C_11:%s\n' $r +=== Gemmini WS CISC Loop Conv Test === +Gemmini WS CISC Loop Conv Test PASSED + +WB_TEST_RC_11:0 +~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_12:%s\n' $r +=== Gemmini WS RISC Basic Test === +Gemmini WS RISC Basic Test PASSED + +WB_TEST_RC_12:0 +~ # /root/gemmini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_13:%s\n' $r +=== Gemmini WS RISC b_transpose Test === +Gemmini WS RISC b_transpose Test PASSED + +WB_TEST_RC_13:0 +~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_14:%s\n' $r +=== Gemmini WS RISC in_shift Test === +Gemmini WS RISC in_shift Test PASSED + +WB_TEST_RC_14:0 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/linux-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/linux-console.log new file mode 100644 index 0000000..cb2529f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/linux-console.log @@ -0,0 +1,236 @@ + +~ # printf 'WB_RESUME_58f3a6f5\n' +WB_RESUME_58f3a6f5 +~ # /bin/busybox sha256sum /root/gemmini_linux_check-linux; printf '\nWB_HASH_0: +%s\n' "$?" +3d80717b1f0b593e22761e78626c38dec685c7a25c3d53ed42037357b652aa90 /root/gemmini_linux_check-linux + +WB_HASH_0:0 +~ # /bin/busybox sha256sum /root/gemmini_os_cisc_atranspose_test-linux; printf ' +\nWB_HASH_1:%s\n' "$?" +a2a79cc1d7bb333494ae14307685fb4b8891869a5d1eb037c004c176e0b98f6c /root/gemmini_os_cisc_atranspose_test-linux + +WB_HASH_1:0 +/bin/busybox sha256sum /root/gem~ # mini_os_cisc_bas/ic_test-linux; pbrintf '\nWB_HASHi_2:%s\n' "$?" +n/busybox sha256sum /root/gemmini_os_cisc_basic_test-linux; printf '\nWB_ +HASH_2:%s\n' "$?" +1215a8cafc2d6c11cfc8f01888f6bbecb8b2ca2201d5145f474bc852b68e4af4 /root/gemmini_os_cisc_basic_test-linux + +WB_HASH_2:0 +~ # /bin/busybox sha256sum /root/gemmini_os_cisc_btranspose_test-linux; printf ' +\nWB_HASH_3:%s\n' "$?" +18fe78a5f89ce0123f475df151d407cdb1b68c99dda7ef94b5255f376a667ec9 /root/gemmini_os_cisc_btranspose_test-linux + +WB_HASH_3:0 +~ # /bin/busybox sha256sum /root/gemmini_os_cisc_shift_test-linux; printf '\nWB_ +HASH_4:%s\n' "$?" +8b909fa200eeb000eb21cc71ca5ee2c960079fea2d57c62914e1ea3db4ba1651 /root/gemmini_os_cisc_shift_test-linux + +WB_HASH_4:0 +~ # /bin/busybox sha256sum /root/gemmini_os_risc_abtranspose_test-linux; printf +'\nWB_HASH_5:%s\n' "$?" +443f12c0b2c6695c88592ac6c40b29ec56b09750d4e993c60b1bfceb5fdd1b5d /root/gemmini_os_risc_abtranspose_test-linux + +WB_HASH_5:0 +~ # /bin/busybox sha256sum /root/gemmini_os_risc_atranspose_test-linux; printf ' +\nWB_HASH_6:%s\n' "$?" +40b99995cb6da30d2c3ba3a22b409033ddb2bd919b65b9eb1e0a3c19b67ff72e /root/gemmini_os_risc_atranspose_test-linux + +WB_HASH_6:0 +~ # /bin/busybox sha256sum /root/gemmini_os_risc_basic_test-linux; printf '\nWB_ +HASH_7:%s\n' "$?" +c789f91569d945db7c3d0b9d3441ab8938bc63354b0cabdfc003b634928664ba /root/gemmini_os_risc_basic_test-linux + +WB_HASH_7:0 +/bin/busybox sha256sum /root/gem~ # mini_os_risc_btr/anspose_test-linbux; printf '\nWBi_HASH_8:%s\n' "$n/busybox sha256sum /root/gemmini_os_risc_btranspose_test-linux; printf ' +\nWB_HASH_8:%s\n' "$?" +157bc4c831becf30652c60f62cbe65d33a60e8daa2eaa3ede2c8f8462f3a10b7 /root/gemmini_os_risc_btranspose_test-linux + +WB_HASH_8:0 +~ # /bin/busybox sha256sum /root/gemmini_os_risc_shift_test-linux; printf '\nWB_ +HASH_9:%s\n' "$?" +be2b3cdaf1508650b374a36ac71b6a2bc05773366534ccd4cb1ce0a6ff524a76 /root/gemmini_os_risc_shift_test-linux + +WB_HASH_9:0 +~ # /bin/busybox sha256sum /root/gemmini_ws_cisc_conv_test-linux; printf '\nWB_H +ASH_10:%s\n' "$?" +dd6d61b4f5d3a3058c6d2ca9a719c2a764533a01931a6e1c8d502f4793cdc9b4 /root/gemmini_ws_cisc_conv_test-linux + +WB_HASH_10:0 +~ # /bin/busybox sha256sum /root/gemmini_ws_risc_basic_test-linux; printf '\nWB_ +HASH_11:%s\n' "$?" +b71942c93c3c6e2fc0ae9a2bfb07f7c061eef863e1282bf1c38a58d3864fa796 /root/gemmini_ws_risc_basic_test-linux + +WB_HASH_11:0 +~ # /bin/busybox sha256sum /root/gemmini_ws_risc_btranspose_test-linux; printf ' +\nWB_HASH_12:%s\n' "$?" +db3c5c781198f5c9f6d4df6c74ed640c1dc20e3964a32908b57b3e6264a584e7 /root/gemmini_ws_risc_btranspose_test-linux + +WB_HASH_12:0 +~ # /bin/busybox sha256sum /root/gemmini_ws_risc_shift_test-linux; printf '\nWB_ +HASH_13:%s\n' "$?" +14ef70b0c8a134ab12deb37bb6d0b245b19243cf556eb0da970d823e7032a822 /root/gemmini_ws_risc_shift_test-linux + +WB_HASH_13:0 +~ # /bin/busybox sha256sum /root/linux_system_check-linux; printf '\nWB_HASH_14: +%s\n' "$?" +7fff55e3b560fd72482984f225b70a4a1154512452b96fc1467665b2acc32e00 /root/linux_system_check-linux + +WB_HASH_14:0 +~ # /root/linux_system_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wai +t $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_0:%s\ +n' $r +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[74]: unhandled signal 11 code 0x2 at 0x0000003fad4a5000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 74 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fc0983b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fc0983bd0 + s1 : 0000003fad4a4000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003fad4a5000 + s5 : 0000003fc0983d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003fad4a5000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=103262000 +PASS LINUX_SYSTEM_CHECK + +WB_TEST_RC_0:0 +~ # /root/gemmini_linux_check-linux & p=$!; (sleep 90; kill -KILL $p) & w=$!; wa +it $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_RC_1:%s +\n' $r +BEGIN GEMMINI_LINUX_CHECK pid=76 dimension=8 bank_width=64 +BEGIN GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=1 mode=OS m=8 n=8 k=8 cpu_ns=666000 accelerator_end_to_end_ns=2658000 +BEGIN GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=2 mode=WS m=8 n=8 k=8 cpu_ns=610000 accelerator_end_to_end_ns=864000 +BEGIN GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=3 mode=OS m=16 n=16 k=16 cpu_ns=5588000 accelerator_end_to_end_ns=7500000 +BEGIN GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=4 mode=WS m=16 n=16 k=16 cpu_ns=5458000 accelerator_end_to_end_ns=7714000 +BEGIN GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=5 mode=OS m=13 n=11 k=17 cpu_ns=4196000 accelerator_end_to_end_ns=10404000 +BEGIN GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=6 mode=WS m=13 n=11 k=17 cpu_ns=3962000 accelerator_end_to_end_ns=12618000 +BEGIN GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=7 mode=OS m=8 n=24 k=8 cpu_ns=3358000 accelerator_end_to_end_ns=1700000 +BEGIN GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=8 mode=WS m=8 n=24 k=8 cpu_ns=3282000 accelerator_end_to_end_ns=4452000 +BEGIN GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 +PASS GEMMINI_CASE id=9 mode=OS m=8 n=8 k=8 cpu_ns=628000 accelerator_end_to_end_ns=2856000 +BEGIN GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 +PASS GEMMINI_CASE id=10 mode=WS m=8 n=8 k=8 cpu_ns=636000 accelerator_end_to_end_ns=876000 +BEGIN GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 +PASS GEMMINI_CASE id=11 mode=OS m=16 n=16 k=16 cpu_ns=11124000 accelerator_end_to_end_ns=7766000 +BEGIN GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 +PASS GEMMINI_CASE id=12 mode=WS m=16 n=16 k=16 cpu_ns=5572000 accelerator_end_to_end_ns=5668000 +BEGIN GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 +PASS GEMMINI_CASE id=13 mode=OS m=13 n=11 k=17 cpu_ns=7182000 accelerator_end_to_end_ns=8750000 +BEGIN GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 +PASS GEMMINI_CASE id=14 mode=WS m=13 n=11 k=17 cpu_ns=5600000 accelerator_end_to_end_ns=8488000 +BEGIN GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 +PASS GEMMINI_CASE id=15 mode=OS m=8 n=24 k=8 cpu_ns=1596000 accelerator_end_to_end_ns=3422000 +BEGIN GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 +PASS GEMMINI_CASE id=16 mode=WS m=8 n=24 k=8 cpu_ns=3330000 accelerator_end_to_end_ns=3666000 +PASS GEMMINI_LINUX_CHECK cases=16 + +WB_TEST_RC_1:0 +~ # /root/gemmini_os_cisc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_2:%s\n' $r +=== Gemmini OS CISC a_transpose Test === +Gemmini OS CISC a_transpose Test PASSED + +WB_TEST_RC_2:0 +~ # /root/gemmini_os_cisc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_3:%s\n' $r +=== Gemmini OS CISC Basic Test === +Gemmini OS CISC Basic Test PASSED + +WB_TEST_RC_3:0 +~ # /root/gemmini_os_cisc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_4:%s\n' $r +=== Gemmini OS CISC b_transpose Test === +Gemmini OS CISC b_transpose Test PASSED + +WB_TEST_RC_4:0 +~ # /root/gemmini_os_cisc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_5:%s\n' $r +=== Gemmini OS CISC in_shift Test === +Gemmini OS CISC in_shift Test PASSED + +WB_TEST_RC_5:0 +~ # /root/gemmini_os_risc_abtranspose_test-linux & p=$!; (sleep 90; kill -KILL $ +p) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB +_TEST_RC_6:%s\n' $r +=== Gemmini OS RISC ab_transpose Test === +Gemmini OS RISC ab_transpose Test PASSED + +WB_TEST_RC_6:0 +~ # /root/gemmini_os_risc_atranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_7:%s\n' $r +=== Gemmini OS RISC a_transpose Test === +Gemmini OS RISC a_transpose Test PASSED + +WB_TEST_RC_7:0 +~ # /root/gemmini_os_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_8:%s\n' $r +=== Gemmini OS RISC Basic Test === +Gemmini OS RISC Basic Test PASSED + +WB_TEST_RC_8:0 +~ # /root/gemmini_os_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_9:%s\n' $r +=== Gemmini OS RISC b_transpose Test === +Gemmini OS RISC b_transpose Test PASSED + +WB_TEST_RC_9:0 +~ # /root/gemmini_os_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_10:%s\n' $r +=== Gemmini OS RISC in_shift Test === +Gemmini OS RISC in_shift Test PASSED + +WB_TEST_RC_10:0 +~ # /root/gemmini_ws_cisc_conv_test-linux & p=$!; (sleep 90; kill -KILL $p) & w= +$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_R +C_11:%s\n' $r +=== Gemmini WS CISC Loop Conv Test === +Gemmini WS CISC Loop Conv Test PASSED + +WB_TEST_RC_11:0 +~ # /root/gemmini_ws_risc_basic_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_12:%s\n' $r +=== Gemmini WS RISC Basic Test === +Gemmini WS RISC Basic Test PASSED + +WB_TEST_RC_12:0 +/root/gemmini_ws_risc_btranspose~ # _test-linux & p=/$!; (sleep 90; krill -KILL $p) & ow=$!; wait $p; ro=$?; kill $w 2>/tdev/null; wait $/w 2>/dev/null; pgrintf '\nWB_TESTe_RC_13:%s\n' $rm +mini_ws_risc_btranspose_test-linux & p=$!; (sleep 90; kill -KILL $p +) & w=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_ +TEST_RC_13:%s\n' $r +=== Gemmini WS RISC b_transpose Test === +Gemmini WS RISC b_transpose Test PASSED + +WB_TEST_RC_13:0 +~ # /root/gemmini_ws_risc_shift_test-linux & p=$!; (sleep 90; kill -KILL $p) & w +=$!; wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWB_TEST_ +RC_14:%s\n' $r +=== Gemmini WS RISC in_shift Test === +Gemmini WS RISC in_shift Test PASSED + +WB_TEST_RC_14:0 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program-console.log new file mode 100644 index 0000000..0480a7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program-console.log @@ -0,0 +1,64 @@ + +****** Vivado v2025.1 (64-bit) + **** SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 + **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 + **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 + **** Start of session at: Mon Oct 12 21:04:14 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} +# set toy_program_script [file join [file dirname [file normalize [info script]]] board program_arty.tcl] +# source $toy_program_script +## if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +## set bitfile [file normalize [lindex $argv 0]] +## if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +## open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 494.426 ; gain = 215.547 +## connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 494.426 ; gain = 0.000 +## set targets [get_hw_targets -quiet] +## if {[llength $targets] != 1} { +## error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +## } +## open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +## if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +## set device [lindex $devices 0] +## current_hw_device $device +## set_property PROGRAM.FILE $bitfile $device +## program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +## refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +## puts "ARTY_JTAG_PROGRAMMED: $bitfile" +ARTY_JTAG_PROGRAMMED: D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7.bit +## close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## disconnect_hw_server +## close_hw_manager +## exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 21:04:45 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.jou b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.jou new file mode 100644 index 0000000..7f9ab6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 21:04:14 2026 +# Process ID : 87892 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl -log D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.log -journal D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\toy-a7-rob-ram-20261012-2ebcbc31\board\toy_a7.bit +# Log file : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/hardware-gemmini-20261012-bcff9cd0/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 68200 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.log new file mode 100644 index 0000000..807366d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/repeat-pass/program.log @@ -0,0 +1,78 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 21:04:14 2026 +# Process ID : 87892 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl -log D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.log -journal D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\toy-a7-rob-ram-20261012-2ebcbc31\board\toy_a7.bit +# Log file : D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/hardware-gemmini-20261012-bcff9cd0/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\build\hardware-gemmini-20261012-bcff9cd0\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 68200 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-gemmini-linux\platforms\arty-a7-toy\program.tcl} +# set toy_program_script [file join [file dirname [file normalize [info script]]] board program_arty.tcl] +# source $toy_program_script +## if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +## set bitfile [file normalize [lindex $argv 0]] +## if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +## open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 494.426 ; gain = 215.547 +## connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 494.426 ; gain = 0.000 +## set targets [get_hw_targets -quiet] +## if {[llength $targets] != 1} { +## error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +## } +## open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +## if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +## set device [lindex $devices 0] +## current_hw_device $device +## set_property PROGRAM.FILE $bitfile $device +## program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +## refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +## puts "ARTY_JTAG_PROGRAMMED: $bitfile" +ARTY_JTAG_PROGRAMMED: D:/Verilog_Dev/fpga-arty-a7-gemmini-linux/platforms/arty-a7-toy/build/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7.bit +## close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +## disconnect_hw_server +## close_hw_manager +## exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 21:04:45 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/LINUX_GEMMINI_BUILD.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/LINUX_GEMMINI_BUILD.json new file mode 100644 index 0000000..ae04c82 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/LINUX_GEMMINI_BUILD.json @@ -0,0 +1,86 @@ +{ + "result": "PASS_BUILD_NOT_HARDWARE_TESTED", + "elapsed_seconds": 143.825, + "software_baseline": { + "bbkernel": "b80336ce647f6604713f1570e1e1355f705a4355", + "linux": "ffc253263a1375a65fa6c9f62a893e9767fbebfa", + "opensbi": "c0f87f10d1bfb9e72a84ddfafb5604ee1bfe9d04", + "busybox": "1a64f6a20aaf6ea4dbba68bbfa8cc1ab7e5c57c4" + }, + "profile": { + "gemmini_rows": 8, + "gemmini_columns": 8, + "bank_width": 64, + "bank_count": 8, + "virtual_bank_count": 16, + "bank_rows": 1024 + }, + "payload_bytes": 25797640, + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "workloads": { + "gemmini_linux_check-linux": { + "bytes": 630680, + "sha256": "3d80717b1f0b593e22761e78626c38dec685c7a25c3d53ed42037357b652aa90" + }, + "gemmini_os_cisc_atranspose_test-linux": { + "bytes": 604440, + "sha256": "a2a79cc1d7bb333494ae14307685fb4b8891869a5d1eb037c004c176e0b98f6c" + }, + "gemmini_os_cisc_basic_test-linux": { + "bytes": 604408, + "sha256": "1215a8cafc2d6c11cfc8f01888f6bbecb8b2ca2201d5145f474bc852b68e4af4" + }, + "gemmini_os_cisc_btranspose_test-linux": { + "bytes": 604440, + "sha256": "18fe78a5f89ce0123f475df151d407cdb1b68c99dda7ef94b5255f376a667ec9" + }, + "gemmini_os_cisc_shift_test-linux": { + "bytes": 604408, + "sha256": "8b909fa200eeb000eb21cc71ca5ee2c960079fea2d57c62914e1ea3db4ba1651" + }, + "gemmini_os_risc_abtranspose_test-linux": { + "bytes": 604960, + "sha256": "443f12c0b2c6695c88592ac6c40b29ec56b09750d4e993c60b1bfceb5fdd1b5d" + }, + "gemmini_os_risc_atranspose_test-linux": { + "bytes": 604928, + "sha256": "40b99995cb6da30d2c3ba3a22b409033ddb2bd919b65b9eb1e0a3c19b67ff72e" + }, + "gemmini_os_risc_basic_test-linux": { + "bytes": 604920, + "sha256": "c789f91569d945db7c3d0b9d3441ab8938bc63354b0cabdfc003b634928664ba" + }, + "gemmini_os_risc_btranspose_test-linux": { + "bytes": 604928, + "sha256": "157bc4c831becf30652c60f62cbe65d33a60e8daa2eaa3ede2c8f8462f3a10b7" + }, + "gemmini_os_risc_shift_test-linux": { + "bytes": 604888, + "sha256": "be2b3cdaf1508650b374a36ac71b6a2bc05773366534ccd4cb1ce0a6ff524a76" + }, + "gemmini_ws_cisc_conv_test-linux": { + "bytes": 604408, + "sha256": "dd6d61b4f5d3a3058c6d2ca9a719c2a764533a01931a6e1c8d502f4793cdc9b4" + }, + "gemmini_ws_risc_basic_test-linux": { + "bytes": 604920, + "sha256": "b71942c93c3c6e2fc0ae9a2bfb07f7c061eef863e1282bf1c38a58d3864fa796" + }, + "gemmini_ws_risc_btranspose_test-linux": { + "bytes": 604960, + "sha256": "db3c5c781198f5c9f6d4df6c74ed640c1dc20e3964a32908b57b3e6264a584e7" + }, + "gemmini_ws_risc_shift_test-linux": { + "bytes": 604920, + "sha256": "14ef70b0c8a134ab12deb37bb6d0b245b19243cf556eb0da970d823e7032a822" + }, + "linux_system_check-linux": { + "bytes": 616848, + "sha256": "7fff55e3b560fd72482984f225b70a4a1154512452b96fc1467665b2acc32e00" + } + }, + "rootfs_install_verified": true, + "flash_modified": false, + "hardware_gemmini_tested": false, + "model_end_to_end_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/CMakeLists.txt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/CMakeLists.txt new file mode 100644 index 0000000..a3931f9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/CMakeLists.txt @@ -0,0 +1,53 @@ +cmake_minimum_required(VERSION 3.22) +project(ToyLinuxGemmini C) +set(CMAKE_C_STANDARD 11) +add_compile_options(-march=rv64gc -mabi=lp64d -O2 -Wall -Wextra -Werror -ffp-contract=off) +add_link_options(-static) +include_directories(${CMAKE_CURRENT_SOURCE_DIR} + reference/bb-tests/workloads/lib reference/examples/balls/gemmini/workloads) +add_library(bb_reference STATIC reference/bb-tests/workloads/lib/buckyball.c + reference/bb-tests/workloads/lib/bbhw/mem/mem.c + reference/bb-tests/workloads/lib/bbhw/isa/isa.c) +set(workloads gemmini_linux_check-linux) +add_executable(gemmini_linux_check-linux gemmini_linux_check.c) +target_link_libraries(gemmini_linux_check-linux PRIVATE bb_reference m) +add_executable(gemmini_os_cisc_atranspose_test-linux gemmini_os_cisc_atranspose_test.c) +target_link_libraries(gemmini_os_cisc_atranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_cisc_atranspose_test-linux) +add_executable(gemmini_os_cisc_basic_test-linux gemmini_os_cisc_basic_test.c) +target_link_libraries(gemmini_os_cisc_basic_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_cisc_basic_test-linux) +add_executable(gemmini_os_cisc_btranspose_test-linux gemmini_os_cisc_btranspose_test.c) +target_link_libraries(gemmini_os_cisc_btranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_cisc_btranspose_test-linux) +add_executable(gemmini_os_cisc_shift_test-linux gemmini_os_cisc_shift_test.c) +target_link_libraries(gemmini_os_cisc_shift_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_cisc_shift_test-linux) +add_executable(gemmini_os_risc_abtranspose_test-linux gemmini_os_risc_abtranspose_test.c) +target_link_libraries(gemmini_os_risc_abtranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_risc_abtranspose_test-linux) +add_executable(gemmini_os_risc_atranspose_test-linux gemmini_os_risc_atranspose_test.c) +target_link_libraries(gemmini_os_risc_atranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_risc_atranspose_test-linux) +add_executable(gemmini_os_risc_basic_test-linux gemmini_os_risc_basic_test.c) +target_link_libraries(gemmini_os_risc_basic_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_risc_basic_test-linux) +add_executable(gemmini_os_risc_btranspose_test-linux gemmini_os_risc_btranspose_test.c) +target_link_libraries(gemmini_os_risc_btranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_risc_btranspose_test-linux) +add_executable(gemmini_os_risc_shift_test-linux gemmini_os_risc_shift_test.c) +target_link_libraries(gemmini_os_risc_shift_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_os_risc_shift_test-linux) +add_executable(gemmini_ws_cisc_conv_test-linux gemmini_ws_cisc_conv_test.c) +target_link_libraries(gemmini_ws_cisc_conv_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_ws_cisc_conv_test-linux) +add_executable(gemmini_ws_risc_basic_test-linux gemmini_ws_risc_basic_test.c) +target_link_libraries(gemmini_ws_risc_basic_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_ws_risc_basic_test-linux) +add_executable(gemmini_ws_risc_btranspose_test-linux gemmini_ws_risc_btranspose_test.c) +target_link_libraries(gemmini_ws_risc_btranspose_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_ws_risc_btranspose_test-linux) +add_executable(gemmini_ws_risc_shift_test-linux gemmini_ws_risc_shift_test.c) +target_link_libraries(gemmini_ws_risc_shift_test-linux PRIVATE bb_reference m) +list(APPEND workloads gemmini_ws_risc_shift_test-linux) +install(TARGETS ${workloads} RUNTIME DESTINATION .) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/PREPARED.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/PREPARED.json new file mode 100644 index 0000000..48d3b2d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/PREPARED.json @@ -0,0 +1,30 @@ +{ + "result": "PREPARED_NOT_BUILT", + "dimension": 8, + "reference_commit": "1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097", + "original_cases": [ + "gemmini_os_cisc_atranspose_test.c", + "gemmini_os_cisc_basic_test.c", + "gemmini_os_cisc_btranspose_test.c", + "gemmini_os_cisc_shift_test.c", + "gemmini_os_risc_abtranspose_test.c", + "gemmini_os_risc_atranspose_test.c", + "gemmini_os_risc_basic_test.c", + "gemmini_os_risc_btranspose_test.c", + "gemmini_os_risc_shift_test.c", + "gemmini_ws_cisc_conv_test.c", + "gemmini_ws_risc_basic_test.c", + "gemmini_ws_risc_btranspose_test.c", + "gemmini_ws_risc_shift_test.c" + ], + "new_blocked_matmul_cases": 16, + "profile": { + "gemmini_rows": 8, + "gemmini_columns": 8, + "bank_width": 64, + "bank_count": 8, + "virtual_bank_count": 16, + "bank_rows": 1024 + }, + "model_end_to_end_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/ballISA.h b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/ballISA.h new file mode 100644 index 0000000..3956da8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/ballISA.h @@ -0,0 +1,23 @@ +#define BB_FUNC7_GEMMINI_CONFIG 2 +#define BB_FUNC7_GEMMINI_FLUSH 3 +#define BB_FUNC7_GEMMINI_PRELOAD 53 +#define BB_FUNC7_GEMMINI_COMPUTE_PRELOADED 66 +#define BB_FUNC7_GEMMINI_COMPUTE_ACCUMULATED 67 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_BOUNDS 80 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_ADDR_A 81 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_ADDR_B 82 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_ADDR_D 83 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_ADDR_C 84 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB 85 +#define BB_FUNC7_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC 86 +#define BB_FUNC7_GEMMINI_LOOP_WS 87 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_1 96 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_2 97 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_3 98 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_4 99 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_5 100 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_6 101 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_7 102 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_8 103 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS_CONFIG_9 104 +#define BB_FUNC7_GEMMINI_LOOP_CONV_WS 105 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_linux_check.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_linux_check.c new file mode 100644 index 0000000..1f6fa7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_linux_check.c @@ -0,0 +1,132 @@ +// Linux workload for the actual 8x8 profile; use the pinned upstream ISA and DMA library. +#define _GNU_SOURCE +#include "buckyball.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if GEMMINI_DIM != 8 || BANK_WIDTH != 64 +#error This workload requires the emitted Toy FPGA 8x8 / 64-bit bank profile. +#endif + +enum { TILE = 8, MAX_DIM = 24 }; +static elem_t tile_a[TILE * TILE] __attribute__((aligned(64))); +static elem_t tile_b[TILE * TILE] __attribute__((aligned(64))); +static elem_t tile_zero[TILE * TILE] __attribute__((aligned(64))); +static result_t tile_c[TILE * TILE] __attribute__((aligned(64))); +static elem_t matrix_a[MAX_DIM * MAX_DIM], matrix_b[MAX_DIM * MAX_DIM]; +static result_t expected[MAX_DIM * MAX_DIM], observed[MAX_DIM * MAX_DIM]; + +static uint64_t nanoseconds(void) { + struct timespec value; + if (clock_gettime(CLOCK_MONOTONIC, &value)) { + perror("clock_gettime"); + exit(2); + } + return (uint64_t)value.tv_sec * 1000000000ULL + value.tv_nsec; +} + +static void gemmini_tile(unsigned ws) { + // 8-byte bank rows: INT8 uses one group, INT32 output uses four groups. + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 4); + bb_mem_alloc(3, 1, 1); + bb_mvin((uintptr_t)tile_a, 0, TILE, 1); + bb_mvin((uintptr_t)tile_b, 1, TILE, 1); + bb_mvin((uintptr_t)tile_zero, 3, TILE, 1); + bb_gemmini_config(ws, 0, 0, 0, 0); + bb_gemmini_preload(ws ? 1 : 3, 2, TILE, 0, 0); + bb_gemmini_compute_preloaded(0, ws ? 3 : 1, 2, TILE, 0, 0, 0); + bb_mvout((uintptr_t)tile_c, 2, TILE, 1); + bb_fence(); + for (unsigned bank = 0; bank < 4; ++bank) + bb_mem_release(bank); +} + +static void cpu_reference(unsigned m, unsigned n, unsigned k) { + for (unsigned row = 0; row < m; ++row) + for (unsigned col = 0; col < n; ++col) { + int32_t sum = 0; + for (unsigned inner = 0; inner < k; ++inner) + sum += (int32_t)matrix_a[row * k + inner] * matrix_b[inner * n + col]; + expected[row * n + col] = sum; + } +} + +static void blocked_matmul(unsigned m, unsigned n, unsigned k, unsigned ws) { + memset(observed, 0, sizeof(observed)); + for (unsigned row = 0; row < m; row += TILE) + for (unsigned col = 0; col < n; col += TILE) + for (unsigned inner = 0; inner < k; inner += TILE) { + memset(tile_a, 0, sizeof(tile_a)); + memset(tile_b, 0, sizeof(tile_b)); + memset(tile_zero, 0, sizeof(tile_zero)); + // Explicit writes give the DMA destination a private writable page. + memset(tile_c, 0, sizeof(tile_c)); + for (unsigned i = 0; i < TILE; ++i) + for (unsigned j = 0; j < TILE; ++j) { + if (row + i < m && inner + j < k) + tile_a[i * TILE + j] = matrix_a[(row + i) * k + inner + j]; + if (inner + i < k && col + j < n) + tile_b[i * TILE + j] = matrix_b[(inner + i) * n + col + j]; + } + gemmini_tile(ws); + for (unsigned i = 0; i < TILE && row + i < m; ++i) + for (unsigned j = 0; j < TILE && col + j < n; ++j) + observed[(row + i) * n + col + j] += tile_c[i * TILE + j]; + } +} + +static int check_case(unsigned id, unsigned m, unsigned n, unsigned k, unsigned ws) { + // Small bounded values keep the independent INT32 oracle free of overflow. + for (unsigned i = 0; i < m * k; ++i) + matrix_a[i] = (int)((i * 7 + id * 3) % 19) - 9; + for (unsigned i = 0; i < k * n; ++i) + matrix_b[i] = (int)((i * 11 + id * 5) % 23) - 11; + printf("BEGIN GEMMINI_CASE id=%u mode=%s m=%u n=%u k=%u\n", + id, ws ? "WS" : "OS", m, n, k); + alarm(60); + uint64_t start = nanoseconds(); + cpu_reference(m, n, k); + uint64_t cpu_ns = nanoseconds() - start; + start = nanoseconds(); + blocked_matmul(m, n, k, ws); + uint64_t accelerator_ns = nanoseconds() - start; + alarm(0); + for (unsigned i = 0; i < m * n; ++i) + if (observed[i] != expected[i]) { + printf("FAIL GEMMINI_CASE id=%u row=%u col=%u got=%d expected=%d\n", + id, i / n, i % n, observed[i], expected[i]); + return 1; + } + printf("PASS GEMMINI_CASE id=%u mode=%s m=%u n=%u k=%u cpu_ns=%llu " + "accelerator_end_to_end_ns=%llu\n", id, ws ? "WS" : "OS", m, n, k, + (unsigned long long)cpu_ns, (unsigned long long)accelerator_ns); + return 0; +} + +int main(void) { + setvbuf(stdout, NULL, _IONBF, 0); + printf("BEGIN GEMMINI_LINUX_CHECK pid=%ld dimension=%d bank_width=%d\n", + (long)getpid(), GEMMINI_DIM, BANK_WIDTH); + if (mlockall(MCL_CURRENT | MCL_FUTURE)) + printf("INFO MLOCKALL errno=%d; buffers are explicitly faulted in\n", errno); + unsigned id = 0; + const unsigned shapes[][3] = {{8, 8, 8}, {16, 16, 16}, {13, 11, 17}, {8, 24, 8}}; + for (unsigned repeat = 0; repeat < 2; ++repeat) + for (unsigned shape = 0; shape < sizeof(shapes) / sizeof(shapes[0]); ++shape) + for (unsigned ws = 0; ws < 2; ++ws) + if (check_case(++id, shapes[shape][0], shapes[shape][1], shapes[shape][2], ws)) + return 1; + printf("PASS GEMMINI_LINUX_CHECK cases=%u\n", id); + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_atranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_atranspose_test.c new file mode 100644 index 0000000..02a4d6c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_atranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_basic_test.c new file mode 100644 index 0000000..c8689ff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_basic_test.c @@ -0,0 +1,45 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC Basic Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_btranspose_test.c new file mode 100644 index 0000000..fd0fb1c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_btranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_shift_test.c new file mode 100644 index 0000000..bde5f70 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_cisc_shift_test.c @@ -0,0 +1,48 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_abtranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_abtranspose_test.c new file mode 100644 index 0000000..565b36f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_abtranspose_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC ab_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_at, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC ab_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC ab_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_atranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_atranspose_test.c new file mode 100644 index 0000000..32b9bb1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_atranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_basic_test.c new file mode 100644 index 0000000..b335b4f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_basic_test.c @@ -0,0 +1,71 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t zeros[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini OS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2, bank_d_zeros = 3; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mem_alloc(bank_d_zeros, 1, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_mvin((uintptr_t)zeros, bank_d_zeros, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, 0); + /* Preload D from zeros bank so C = A*B + D = A*B (not A*B + A) */ + bb_gemmini_preload(bank_d_zeros, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + bb_mem_release(bank_d_zeros); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC Basic Test PASSED\n"); + return 0; + } + + printf("got mat_c: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", mat_c[i]); + } + printf("\n"); + // for (int i = 0; i < DIM; i++) { + // for (int j = 0; j < DIM; j++) { + // printf("%d ", mat_c[i * DIM + j]); + // } + // printf("\n"); + // } + + printf("exp row0: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", expected[i]); + } + printf("\n"); + printf("Gemmini OS RISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_btranspose_test.c new file mode 100644 index 0000000..b8b6a40 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_btranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_shift_test.c new file mode 100644 index 0000000..d357012 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_os_risc_shift_test.c @@ -0,0 +1,52 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_cisc_conv_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_cisc_conv_test.c new file mode 100644 index 0000000..71f7653 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_cisc_conv_test.c @@ -0,0 +1,74 @@ +#include "buckyball.h" +#include +#include +#include +#include + +// Pointwise conv: batch=1, in_dim=1, in_channels=DIM, out_channels=DIM, +// kernel=1 Degenerates to a single DIM x DIM matmul (input[1x1xIC] * +// weight[1x1xICxOC]) +#define DIM 8 +#define BATCH 1 +#define IN_DIM 1 +#define OUT_DIM 1 +#define IN_CH DIM +#define OUT_CH DIM +#define KERNEL_DIM 1 + +// input layout: [batch, in_dim, in_dim, in_ch] = [1, 1, 1, 16] = 16 bytes +// weight layout: [krow, kcol, in_ch, out_ch] = [1, 1, 16, 16] = 256 bytes +// output layout: [batch, out_dim, out_dim, out_ch] = [1, 1, 1, 16] x 4 bytes = +// 64 bytes +static elem_t input[BATCH * IN_DIM * IN_DIM * IN_CH] + __attribute__((aligned(64))); +static elem_t weight[KERNEL_DIM * KERNEL_DIM * IN_CH * OUT_CH] + __attribute__((aligned(64))); +static result_t output[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); +static result_t expected[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS CISC Loop Conv Test ===\n"); + + for (int k = 0; k < IN_CH; ++k) { + input[k] = k % 7 - 3; + for (int out = 0; out < OUT_CH; ++out) + weight[k * OUT_CH + out] = (2 * k + 3 * out) % 5 - 2; + } + + // CPU reference: output[0..OUT_CH] = sum_k(input[k] * weight[k][j]) + // cpu_matmul(A[M×K], B[K×N], C[M×N]) — here A=input(1×IN_CH), + // B=weight(IN_CH×OUT_CH) + cpu_matmul(input, weight, expected, 1, OUT_CH, IN_CH); + + // Strides: + // input_stride = in_ch * elemSize = 16 * 1 = 16 (bytes per spatial step) + // weight_stride = in_ch * out_ch * elemSize = 16 * 16 * 1 = 256 (bytes per + // kernel step) output_stride = out_ch * accBytes = 16 * 4 = 64 + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_1(BATCH, IN_DIM, IN_CH); + bb_gemmini_loop_conv_ws_config_2(OUT_CH, OUT_DIM, 1, 0); + bb_gemmini_loop_conv_ws_config_3(KERNEL_DIM, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_4(0); // no bias + bb_gemmini_loop_conv_ws_config_5((uintptr_t)input); + bb_gemmini_loop_conv_ws_config_6((uintptr_t)weight); + bb_gemmini_loop_conv_ws_config_7((uintptr_t)output); + bb_gemmini_loop_conv_ws_config_8( + IN_CH, IN_CH * OUT_CH); // input_stride, weight_stride + bb_gemmini_loop_conv_ws_config_9(OUT_CH * 4); // output_stride (accBytes=4) + bb_gemmini_loop_conv_ws( + 0, 1, 2, 1); // bank_input=0, bank_weight=1, bank_output=2, no_bias=1 + bb_fence(); + + if (compare_u32_matrices(output, expected, 1, OUT_CH)) { + printf("Gemmini WS CISC Loop Conv Test PASSED\n"); + return 0; + } + printf("Gemmini WS CISC Loop Conv Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_basic_test.c new file mode 100644 index 0000000..fa62726 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_basic_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini WS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC Basic Test PASSED\n"); + return 0; + } + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_btranspose_test.c new file mode 100644 index 0000000..052d4bc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_btranspose_test.c @@ -0,0 +1,56 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 1, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_shift_test.c new file mode 100644 index 0000000..e645b9e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/gemmini_ws_risc_shift_test.c @@ -0,0 +1,57 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 8 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/params.h b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/params.h new file mode 100644 index 0000000..092a058 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/software/generated-inputs/params.h @@ -0,0 +1,5 @@ +#define BANK_WIDTH 64 +#define PHYSICAL_BANK_NUM 8 +#define VIRTUAL_BANK_NUM 16 +#define BANK_ENTRIES 1024 +#define GEMMINI_DIM 8 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/board/program_arty.tcl new file mode 100644 index 0000000..f70f054 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/board/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +program_hw_devices $device +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/build.sbt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/build.sbt new file mode 100644 index 0000000..79eb11f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/build.sbt @@ -0,0 +1,70 @@ +ThisBuild / scalaVersion := "2.13.16" +ThisBuild / organization := "srtp.fpga" +ThisBuild / version := "0.1.0" +ThisBuild / scalacOptions ++= Seq("-language:reflectiveCalls", "-Ymacro-annotations", "-deprecation", "-feature") + +lazy val chiselSettings = Seq( + scalaVersion := "2.13.16", + libraryDependencies += "org.chipsalliance" %% "chisel" % "6.7.0", + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.7.0" cross CrossVersion.full) +) +lazy val cde = project.in(file("thirdparty/cde")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "cde/src/chipsalliance" +) +lazy val diplomacy = project.in(file("thirdparty/diplomacy/diplomacy")).dependsOn(cde).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "src/diplomacy", + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.0" +) +lazy val hardfloat = project.in(file("thirdparty/hardfloat/hardfloat")).dependsOn(cde).settings(chiselSettings) +lazy val macros = project.in(file("thirdparty/rocket-chip/macros")).settings( + libraryDependencies += "org.scala-lang" % "scala-reflect" % "2.13.16" +) +lazy val rocket = project.in(file("thirdparty/rocket-chip")).dependsOn(cde, diplomacy, hardfloat, macros).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "src/main/scala") ** "*.scala").get + original.filterNot(f => f.getName == "FPU.scala") ++ + ((baseDirectory.value / "../../patches/rocket") ** "*.scala").get + }, + libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", + "org.json4s" %% "json4s-jackson" % "4.0.5", + "org.scala-graph" %% "graph-core" % "1.13.5" + ) +) +lazy val inclusive = project.in(file("thirdparty/inclusive-cache")).dependsOn(rocket).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "design/craft" +) +lazy val midas = project.in(file("thirdparty/firesim-compile")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "../firesim/sim/midas/targetutils/src/main/scala" +) +lazy val gemmini = project.in(file("thirdparty/gemmini-compile")).dependsOn(rocket, midas).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "../gemmini/src/main/scala") ** "*.scala").get + original.filterNot(f => Set("PE.scala", "Tile.scala", "Mesh.scala")(f.getName)) ++ + ((baseDirectory.value / "../../patches/gemmini") ** "*.scala").get + }, + Compile / unmanagedResourceDirectories += baseDirectory.value / "../gemmini/src/main/resources" +) +lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chiselSettings).settings( + name := "toy-arty-a7-linux", + libraryDependencies ++= Seq( + "com.lihaoyi" %% "upickle" % "3.3.1", + "tech.sparse" %% "toml-scala" % "0.2.2" + ), + Compile / unmanagedSources ++= { + val upstream = baseDirectory.value / "upstream" + val framework = upstream / "arch/src/main/scala/framework" + val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", + "system/core/rocket", "system/core/accelerator", "system/tile") + val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ + ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => + val ball = upstream / "examples/balls" / name + ((ball / "arch/src/main/scala") ** "*.scala").get.filterNot(f => + Set("GemminiExCtrl.scala", "GemminiExCtrlDefs.scala", + "GemminiExCtrlComputeFeedState.scala", "GemminiExCtrlStoreOps.scala", + "GemminiExCtrlPreloadStates.scala", "GemminiExCtrlCmdStates.scala", "GemminiBall.scala", "LoopMatmulUnroller.scala")(f.getName)) ++ ((ball / "configs") ** "*.scala").get + } + } +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/diagnostics/run_rob_hardware.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/diagnostics/run_rob_hardware.py new file mode 100644 index 0000000..76a5535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/diagnostics/run_rob_hardware.py @@ -0,0 +1,31 @@ +from datetime import datetime, timedelta, timezone +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +root = Path(__file__).resolve().parents[1] +out = root / 'build/rob-hardware-session-20261012' +out.mkdir(exist_ok=False) +bit = root / 'build/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7.bit' +payload = root / 'build/linux-gemmini-20261012-e8e89f4c/fw_payload.bin' +build = root / 'build/linux-gemmini-20261012-e8e89f4c/LINUX_GEMMINI_BUILD.json' +expected = 'dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c' +assert hashlib.sha256(bit.read_bytes()).hexdigest() == expected +start = datetime.now(timezone(timedelta(hours=8))) +command = [sys.executable, '-u', str(root/'host/check_linux_gemmini.py'), + '--payload', str(payload), '--build-result', str(build), '--bitstream', str(bit), + '--expected-bit-sha256', expected, + '--vivado', 'D:/Xilinx/2025.1/Vivado/bin/vivado.bat', '--port', 'COM5'] +record = {'started_at':start.isoformat(), 'deadline':(start+timedelta(seconds=3600)).isoformat(), + 'timeout_seconds':3600, 'command':command, 'flash_written':False, + 'script_sha256':hashlib.sha256((root/'host/check_linux_gemmini.py').read_bytes()).hexdigest(), + 'uart_serial':'210319BCC5FCB'} +(out/'SESSION.json').write_text(json.dumps(record,indent=2)+'\n',encoding='utf-8') +try: + result = subprocess.run(command,cwd=root,timeout=3600,check=True) + record['exit_code']=result.returncode +finally: + record['finished_at']=datetime.now(timezone(timedelta(hours=8))).isoformat() + (out/'SESSION.json').write_text(json.dumps(record,indent=2)+'\n',encoding='utf-8') diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_linux_gemmini.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_linux_gemmini.py new file mode 100644 index 0000000..01619cd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_linux_gemmini.py @@ -0,0 +1,186 @@ +"""临时烧录已验证位流、完整读回标准镜像，运行 Linux/Gemmini 测试并归档证据。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import shutil +import struct +import subprocess +import time +import uuid + +from ftdi_transport import D2xxPort +from load import Loader + +ROOT = Path(__file__).resolve().parents[1] +EXPECTED_BIT = "ccc33c511e613561fb9dd1e9c847bd3b84037da1d078c44cd3de197d55dffde1" + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def bounded_command(program, marker, seconds=90): + # $! and $? produce numeric values. Wait for both children so the watcher + # cannot retain a pending job/zombie after a successful workload. + command = (f"{program} & p=$!; (sleep {seconds}; kill -KILL $p) & w=$!; " + f"wait $p; r=$?; kill $w 2>/dev/null; wait $w 2>/dev/null; " + f"printf '\\n{marker}:%s\\n' $r\n") + if len(command.encode()) >= 220: + raise ValueError("Console command exceeds the RX FIFO budget") + return command + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--payload", type=Path, required=True) + parser.add_argument("--build-result", type=Path, required=True) + parser.add_argument("--bitstream", type=Path, required=True) + parser.add_argument("--vivado", type=Path, required=True) + parser.add_argument("--port", default="COM5") + parser.add_argument("--expected-bit-sha256", default=EXPECTED_BIT, + help="重建 UART 位流后，填写已通过实现检查的位流 SHA256") + parser.add_argument("--loaded-run", type=Path, + help="继续完整读回且已启动 Linux 的运行；逐个核验板上程序摘要") + args = parser.parse_args() + build = json.loads(args.build_result.read_text(encoding="utf-8")) + if build["result"] != "PASS_BUILD_NOT_HARDWARE_TESTED": + raise ValueError("Expected a verified standard-image build record") + expected_bit = args.expected_bit_sha256.lower() + if not re.fullmatch(r"[0-9a-f]{64}", expected_bit): + raise ValueError("Expected an explicit 64-digit bitstream SHA256") + if digest(args.payload) != build["payload_sha256"] or digest(args.bitstream) != expected_bit: + raise ValueError("Payload or previously validated UART bitstream hash mismatch") + out = ROOT / "build" / ("hardware-gemmini-" + time.strftime("%Y%m%d") + "-" + uuid.uuid4().hex[:8]) + out.mkdir(parents=True, exist_ok=False) + started = time.monotonic() + result = {"result": "RUNNING", "bitstream_sha256": expected_bit, + "payload_sha256": build["payload_sha256"], "port": args.port, + "timeout_seconds": 3600, "flash_written": False, "tests": []} + try: + if args.loaded_run: + previous = json.loads((args.loaded_run / "RESULT.json").read_text(encoding="utf-8")) + boot = (args.loaded_run / "linux-console.log").read_bytes() + if (previous["bitstream_sha256"] != expected_bit + or previous["payload_sha256"] != build["payload_sha256"] + or previous.get("ddr_readback_bytes") != build["payload_bytes"] + or b"Linux version 6.6.0" not in boot or b"~ # " not in boot + or b"Kernel panic" in boot or previous["flash_written"]): + raise ValueError("Loaded run lacks complete DDR/boot evidence") + shutil.copy2(args.loaded_run / "RESULT.json", out / "LOAD_RESULT.json") + shutil.copy2(args.loaded_run / "linux-console.log", out / "boot-console.log") + for name in ["program.log", "program.jou", "program-console.log"]: + shutil.copy2(args.loaded_run / name, out / name) + result["loaded_run"] = str(args.loaded_run.resolve()) + result["ddr_readback_bytes"] = previous["ddr_readback_bytes"] + result["ddr_transfer_seconds"] = previous["ddr_transfer_seconds"] + result["configuration_reused"] = True + print("REUSE COMPLETE_DDR_READBACK_AND_LINUX_BOOT", flush=True) + else: + with (out / "program-console.log").open("wb") as log: + subprocess.run([str(args.vivado), "-mode", "batch", "-source", + str(ROOT / "program.tcl"), "-log", str(out / "program.log"), + "-journal", str(out / "program.jou"), "-tclargs", str(args.bitstream.resolve())], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, timeout=120, check=True) + print("PASS VOLATILE_JTAG_PROGRAM", flush=True) + data = args.payload.read_bytes() + with D2xxPort(args.port, timeout_seconds=3500) as port: + if not args.loaded_run: + loader = Loader(port) + info = loader.request(4) + if info != b"TA7\x02" + struct.pack(" 3500: + raise TimeoutError("One-hour board verification timeout") + chunk = data[offset:offset + 256] + loader.request(1, 0x80000000 + offset, len(chunk), chunk) + if loader.request(2, 0x80000000 + offset, len(chunk)) != chunk: + raise RuntimeError(f"DDR readback mismatch at {offset:#x}; CPU remains reset") + if offset % 1048576 == 0: + print(f"DDR_VERIFY {offset + len(chunk)}/{len(data)}", flush=True) + result["ddr_readback_bytes"] = len(data) + result["ddr_transfer_seconds"] = round(time.monotonic() - transfer_start, 3) + print(f"PASS FULL_DDR_READBACK bytes={len(data)} seconds={result['ddr_transfer_seconds']}", flush=True) + loader.request(3, 0x80000000) + with (out / "linux-console.log").open("wb") as log: + console = bytearray() + + def read_until(pattern, seconds): + deadline = time.monotonic() + seconds + while time.monotonic() < deadline: + block = port.read(4096) + if block: + console.extend(block) + log.write(block) + log.flush() + if b"Kernel panic" in console: + raise RuntimeError("Kernel panic; inspect raw console") + match = re.search(pattern, console) + if match: + return match + raise TimeoutError("Linux console response timeout; inspect raw transcript") + + if args.loaded_run: + marker = "WB_RESUME_" + out.name.rsplit("-", 1)[-1] + port.write(f"\nprintf '{marker}\\n'\n".encode()) + read_until(rb"(?:^|\n)" + marker.encode() + rb"\r*\n", 15) + result["workload_hashes"] = {} + for index, (name, metadata) in enumerate(build["workloads"].items()): + console.clear() + marker = f"WB_HASH_{index}" + port.write((f"/bin/busybox sha256sum /root/{name}; " + f"printf '\\n{marker}:%s\\n' \"$?\"\n").encode()) + match = read_until(rb"(?:^|\n)" + marker.encode() + rb":(\d+)\r*\n", 60) + if int(match.group(1)) or not re.search( + rb"(?:^|\n)" + metadata["sha256"].encode() + rb"\s+/root/" + + re.escape(name.encode()) + rb"\r*\n", console): + raise RuntimeError("Live rootfs workload hash mismatch: " + name) + result["workload_hashes"][name] = metadata["sha256"] + print("PASS LIVE_WORKLOAD_SHA256 " + name, flush=True) + else: + read_until(rb"~ # ", 180) + if b"Linux version 6.6.0" not in console: + raise RuntimeError("Expected real Linux 6.6.0 boot") + print("PASS LINUX_BOOT", flush=True) + commands = ["linux_system_check-linux", "gemmini_linux_check-linux"] + commands += sorted(name for name in build["workloads"] + if name not in commands) + for index, name in enumerate(commands): + console.clear() + marker = f"WB_TEST_RC_{index}" + command = bounded_command("/root/" + name, marker) + print("RUN " + name, flush=True) + port.write(command.encode()) + match = read_until(rb"(?:^|\n)" + marker.encode() + rb":(\d+)\r*\n", 120) + code = int(match.group(1)) + output = bytes(console).replace(b"\r", b"").decode(errors="replace") + item = {"name": name, "exit_code": code, "output": output} + result["tests"].append(item) + print(output, flush=True) + if code or (name == "gemmini_linux_check-linux" and "PASS GEMMINI_LINUX_CHECK cases=16" not in output): + raise RuntimeError(f"Hardware workload failed: {name} rc={code}") + if name == "linux_system_check-linux": + for label in ["VM_COPY_ON_WRITE", "VM_PAGE_PROTECTION", + "FP64_PROCESS_CONTEXT", "LINUX_TIMER", "LINUX_SYSTEM_CHECK"]: + if "PASS " + label not in output: + raise RuntimeError("Missing Linux check: " + label) + result["result"] = "PASS_LINUX_AND_GEMMINI_HARDWARE" + result["test_count"] = len(result["tests"]) + result["blocked_matmul_cases"] = 16 + except BaseException as error: + result["result"] = "FAIL" + result["error"] = str(error) + raise + finally: + result["elapsed_seconds"] = round(time.monotonic() - started, 3) + (out / "RESULT.json").write_text(json.dumps(result, indent=2) + "\n", encoding="utf-8") + print("RESULT " + str(out / "RESULT.json"), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_live_shell.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_live_shell.py new file mode 100644 index 0000000..76337e0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_live_shell.py @@ -0,0 +1,61 @@ +"""回归后检查 Linux 控制台、空闲内存和已回收的 watchdog。""" +import argparse +import json +from pathlib import Path +import re +import sys +import time + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT / 'host')) +from ftdi_transport import D2xxPort + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument('--port', default='COM5') + parser.add_argument('--output', type=Path, required=True) + args = parser.parse_args() + args.output.mkdir(exist_ok=False, parents=True) + commands = [ + b'kill -0 "$w" 2>/dev/null; printf "\\nWATCHDOG_ALIVE_RC:%s\\n" "$?"\n', + b'while read a b c; do case "$a" in MemTotal:|MemAvailable:) printf "%s %s %s\\n" "$a" "$b" "$c";; esac; done < /proc/meminfo; printf "LIVE_MEM_DONE\\n"\n', + ] + result = {'flash_written': False, 'configuration_changed': False} + with D2xxPort(args.port, timeout_seconds=120) as port: + with (args.output / 'post-console.log').open('wb') as log: + for index, command in enumerate(commands): + port.write(command) + buffer = bytearray() + deadline = time.monotonic() + 30 + pattern = (rb'(?:^|\n)WATCHDOG_ALIVE_RC:(\d+)\r*\n' if index == 0 + else rb'(?:^|\n)LIVE_MEM_DONE\r*\n') + while time.monotonic() < deadline: + data = port.read(4096) + buffer.extend(data) + log.write(data) + log.flush() + match = re.search(pattern, buffer) + if match: + break + else: + raise TimeoutError('Post-test live console timeout') + print(buffer.decode(errors='replace')) + if index == 0: + result['watchdog_alive_rc'] = int(match[1]) + if int(match[1]) == 0: + raise ValueError('Last watchdog still running') + else: + for name in ['MemTotal', 'MemAvailable']: + match = re.search(name.encode() + rb':\s+(\d+) kB\r*\n', buffer) + if not match: + raise ValueError('Missing live memory field') + result[name + '_kib'] = int(match[1]) + result['uart_latency_restored_ms'] = port.original_latency.value + result['result'] = 'PASS_POST_TEST_LIVE_SHELL' + (args.output / 'RESULT.json').write_text(json.dumps(result, indent=2) + '\n', encoding='utf-8') + print(json.dumps(result, indent=2)) + + +if __name__ == '__main__': + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_watchdog.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_watchdog.py new file mode 100644 index 0000000..eaa947c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/check_watchdog.py @@ -0,0 +1,69 @@ +"""在已启动的 Linux 控制台验证正常退出、非零退出、超时及 watcher 回收。""" + +import argparse +import json +from pathlib import Path +import re +import time +import uuid + +from check_linux_gemmini import bounded_command +from ftdi_transport import D2xxPort + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--port", default="COM5") + parser.add_argument("--output", type=Path) + args = parser.parse_args() + out = args.output or ROOT / "build" / ( + "watchdog-" + time.strftime("%Y%m%d") + "-" + uuid.uuid4().hex[:8] + ) + out.mkdir(parents=True, exist_ok=False) + cases = [("/bin/busybox true", 0), ("/bin/busybox false", 1), + ("/bin/busybox sleep 5", 137)] + result = {"result": "RUNNING", "cases": [], "flash_written": False} + try: + with D2xxPort(args.port, timeout_seconds=120) as port: + with (out / "check.log").open("wb") as log: + def run(command, marker): + port.write(command.encode()) + buffer = bytearray() + deadline = time.monotonic() + 15 + while time.monotonic() < deadline: + block = port.read(4096) + buffer.extend(block) + log.write(block) + log.flush() + match = re.search(rb"(?:^|\n)" + marker.encode() + + rb":(\d+)\r*\n", buffer) + if match: + return int(match[1]) + raise TimeoutError("Watchdog check response timeout") + + for index, (program, expected) in enumerate(cases): + marker = f"WATCH_SELF_{index}" + code = run(bounded_command(program, marker, seconds=1), marker) + if code != expected: + raise RuntimeError(f"{program}: exit {code}, expected {expected}") + marker = f"WATCH_REAP_{index}" + alive = run(f"kill -0 $w 2>/dev/null; " + f"printf '\\n{marker}:%s\\n' $?\n", marker) + if alive == 0: + raise RuntimeError("Watcher remains after explicit wait") + result["cases"].append({"program": program, "exit_code": code, + "watcher_alive_rc": alive, "expected": True}) + print(f"PASS watchdog case={index} exit={code} watcher_reaped=True") + result["result"] = "PASS_WATCHDOG_SUCCESS_FAILURE_TIMEOUT_AND_REAP" + except BaseException as error: + result.update(result="FAIL", error=str(error)) + raise + finally: + (out / "RESULT.json").write_text(json.dumps(result, indent=2) + "\n", encoding="utf-8") + print("RESULT " + str(out / "RESULT.json")) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/ftdi_transport.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/ftdi_transport.py new file mode 100644 index 0000000..2439f49 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/ftdi_transport.py @@ -0,0 +1,105 @@ +"""Windows UART B 的 D2XX 运输适配；关闭时恢复原延迟，不访问 JTAG A。""" + +import ctypes as c +import time + + +class D2xxPort: + def __init__(self, port, baudrate=1000000, timeout_seconds=3600): + import serial.tools.list_ports + + matches = [item for item in serial.tools.list_ports.comports() if item.device == port] + if len(matches) != 1: + raise RuntimeError("Expected exactly one selected UART port") + device = matches[0] + if (device.vid, device.pid) != (0x0403, 0x6010) or not device.serial_number.endswith("B"): + raise RuntimeError("Expected FT2232 UART B; do not use JTAG A") + self.api = c.WinDLL("C:/Windows/System32/ftd2xx.dll") + signatures = { + "FT_OpenEx": [c.c_void_p, c.c_uint32, c.POINTER(c.c_void_p)], + "FT_Close": [c.c_void_p], + "FT_GetLatencyTimer": [c.c_void_p, c.POINTER(c.c_ubyte)], + "FT_SetLatencyTimer": [c.c_void_p, c.c_ubyte], + "FT_SetBaudRate": [c.c_void_p, c.c_uint32], + "FT_SetDataCharacteristics": [c.c_void_p, c.c_ubyte, c.c_ubyte, c.c_ubyte], + "FT_SetFlowControl": [c.c_void_p, c.c_ushort, c.c_ubyte, c.c_ubyte], + "FT_SetTimeouts": [c.c_void_p, c.c_uint32, c.c_uint32], + "FT_Purge": [c.c_void_p, c.c_uint32], + "FT_Read": [c.c_void_p, c.c_void_p, c.c_uint32, c.POINTER(c.c_uint32)], + "FT_Write": [c.c_void_p, c.c_void_p, c.c_uint32, c.POINTER(c.c_uint32)], + "FT_GetQueueStatus": [c.c_void_p, c.POINTER(c.c_uint32)], + } + for name, signature in signatures.items(): + method = getattr(self.api, name) + method.argtypes = signature + method.restype = c.c_uint32 + self.handle = c.c_void_p() + self.original_latency = c.c_ubyte() + self.closed = True + self.deadline = time.monotonic() + timeout_seconds + self.call("FT_OpenEx", c.cast(c.c_char_p(device.serial_number.encode()), c.c_void_p), + 1, c.byref(self.handle)) + self.closed = False + self.latency_known = False + try: + self.call("FT_GetLatencyTimer", self.handle, c.byref(self.original_latency)) + self.latency_known = True + self.call("FT_SetLatencyTimer", self.handle, 2) + self.call("FT_SetBaudRate", self.handle, baudrate) + self.call("FT_SetDataCharacteristics", self.handle, 8, 0, 0) + self.call("FT_SetFlowControl", self.handle, 0, 0, 0) + self.call("FT_SetTimeouts", self.handle, 100, 5000) + self.call("FT_Purge", self.handle, 3) + except BaseException: + self.close() + raise + print(f"D2XX UART B {port}: latency {self.original_latency.value}->2 ms", flush=True) + + def call(self, name, *args): + status = getattr(self.api, name)(*args) + if status: + raise OSError(f"{name}: FT_STATUS {status}") + + def check_deadline(self): + if time.monotonic() > self.deadline: + raise TimeoutError("One-hour hardware-session timeout") + + def read(self, count): + self.check_deadline() + if not count: + return b"" + available = c.c_uint32() + self.call("FT_GetQueueStatus", self.handle, c.byref(available)) + size = min(count, available.value) if available.value else 1 + buffer = c.create_string_buffer(size) + received = c.c_uint32() + self.call("FT_Read", self.handle, buffer, size, c.byref(received)) + return buffer.raw[:received.value] + + def write(self, data): + self.check_deadline() + buffer = c.create_string_buffer(data) + written = c.c_uint32() + self.call("FT_Write", self.handle, buffer, len(data), c.byref(written)) + if written.value != len(data): + raise TimeoutError("D2XX short write") + return written.value + + def flush(self): + pass # FT_Write completes its synchronous USB transfer before returning. + + def close(self): + if not self.closed: + try: + if self.latency_known: + self.call("FT_SetLatencyTimer", self.handle, self.original_latency.value) + finally: + self.call("FT_Close", self.handle) + self.closed = True + print(f"D2XX closed; latency restored to {self.original_latency.value} ms", flush=True) + + def __enter__(self): + return self + + def __exit__(self, *args): + self.close() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/load.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/load.py new file mode 100644 index 0000000..1f83575 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/host/load.py @@ -0,0 +1,103 @@ +"""Load and byte-verify a complete Toy/OpenSBI/Linux payload in DDR. + +Reset BTN0 and wait for LED0 (DDR calibration). Requires pyserial. +Example: python host/load.py --port COM5 build/board-software/fw_payload.bin +""" +import argparse +import binascii +import hashlib +from pathlib import Path +import struct +import sys +import time + + +def frame(op, sequence, address, length, data=b""): + body=struct.pack("256:raise ValueError("Invalid response size") + payload=self.read_exact(size) + checksum=struct.unpack("capacity:raise ValueError("Image exceeds reported DDR capacity") + print(f"DDR {capacity} bytes, core {clock} Hz, payload SHA256 {hashlib.sha256(data).hexdigest()}") + started=time.monotonic() + for offset in range(0,len(data),256): + chunk=data[offset:offset+256] + loader.request(1,0x80000000+offset,len(chunk),chunk) + if loader.request(2,0x80000000+offset,len(chunk))!=chunk: + raise RuntimeError(f"DDR readback mismatch at {offset:#x}; CPU remains reset") + if offset%65536==0:print(f"Verified {offset+len(chunk)}/{len(data)} bytes",flush=True) + loader.request(3,0x80000000) + print(f"Full readback passed; CPU started after {time.monotonic()-started:.1f}s. Console:") + deadline=time.monotonic()+args.console_seconds + console=bytearray() + command_sent=False + linux_passed=False + checks=(b"PASS VM_COPY_ON_WRITE",b"PASS VM_PAGE_PROTECTION",b"PASS FP64_PROCESS_CONTEXT", + b"PASS LINUX_TIMER",b"PASS LINUX_SYSTEM_CHECK") + with args.transcript.open("wb") as log: + while time.monotonic()= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} + +object GlobalROB { + def operandRamEnabled: Boolean = java.lang.Boolean.getBoolean("fpga.robOperandRam") +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/program.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/program.tcl new file mode 100644 index 0000000..9538500 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/program.tcl @@ -0,0 +1,5 @@ +# Arty A7-100T volatile JTAG entry point, usable from any working directory. +# vivado -mode batch -source /path/to/program.tcl -tclargs /path/to/toy_a7.bit +# Delegates to the exact board script used by the recorded hardware run. +set toy_program_script [file join [file dirname [file normalize [info script]]] board program_arty.tcl] +source $toy_program_script diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/scripts/verify_linux_gemmini.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/scripts/verify_linux_gemmini.py new file mode 100644 index 0000000..27aa87d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/scripts/verify_linux_gemmini.py @@ -0,0 +1,125 @@ +"""离线核验标准镜像与实物日志；仅从实际 PASS 行汇总计算耗时。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +SHAPES = [(8, 8, 8), (16, 16, 16), (13, 11, 17), (8, 24, 8)] +CHECKS = [ + "VM_COPY_ON_WRITE", + "VM_PAGE_PROTECTION", + "FP64_PROCESS_CONTEXT", + "LINUX_TIMER", + "LINUX_SYSTEM_CHECK", +] + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--build-record", type=Path, required=True) + parser.add_argument("--hardware-result", type=Path, required=True) + parser.add_argument("--output", type=Path) + parser.add_argument("--expected-bit-sha256", + help="核验重建位流的新运行；省略时使用历史实测位流摘要") + args = parser.parse_args() + build = read(args.build_record) + result = read(args.hardware_result) + original = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") + require(build["result"] == "PASS_BUILD_NOT_HARDWARE_TESTED", "Build did not pass") + require(result["result"] == "PASS_LINUX_AND_GEMMINI_HARDWARE", "Hardware did not pass") + expected_bit = args.expected_bit_sha256 or original["bitstream_sha256"] + require(re.fullmatch(r"[0-9a-f]{64}", expected_bit), "Invalid expected bitstream digest") + require(result["bitstream_sha256"] == expected_bit, "Wrong bitstream") + require(result["payload_sha256"] == build["payload_sha256"], "Payload mismatch") + require(result["ddr_readback_bytes"] == build["payload_bytes"], "Incomplete DDR readback") + require(not result["flash_written"], "Expected temporary deployment") + require(result["elapsed_seconds"] < result["timeout_seconds"] == 3600, "Invalid timeout") + require(len(result["tests"]) == result["test_count"] == 15, "Expected 15 workloads") + tests = {item["name"]: item for item in result["tests"]} + require(set(tests) == set(build["workloads"]), "Workload set mismatch") + raw = (args.hardware_result.parent / "linux-console.log").read_bytes() + console = raw.replace(b"\r", b"").decode(errors="replace") + boot_file = args.hardware_result.parent / "boot-console.log" + boot = boot_file.read_bytes().decode(errors="replace") if boot_file.is_file() else console + require("OpenSBI v1.9" in boot and "Linux version 6.6.0" in boot, "Wrong boot") + if result.get("configuration_reused"): + load = read(args.hardware_result.parent / "LOAD_RESULT.json") + require(load["payload_sha256"] == build["payload_sha256"] + and load["bitstream_sha256"] == result["bitstream_sha256"] + and load["ddr_readback_bytes"] == build["payload_bytes"], "Wrong prior load") + expected_hashes = {name: item["sha256"] for name, item in build["workloads"].items()} + require(result["workload_hashes"] == expected_hashes, "Live workload hash mismatch") + for name, expected in expected_hashes.items(): + require(re.search(rf"^{expected}\s+/root/{re.escape(name)}$", + console, re.MULTILINE), "Missing raw live hash: " + name) + require("Kernel panic" not in console, "Kernel panic in transcript") + for index, item in enumerate(result["tests"]): + require(item["exit_code"] == 0, "Failed workload: " + item["name"]) + require(item["output"] in console, "Structured output differs from raw transcript") + require(re.search(rf"^WB_TEST_RC_{index}:0$", console, re.MULTILINE), + "Missing raw process return code: " + item["name"]) + for label in CHECKS: + require("PASS " + label in tests["linux_system_check-linux"]["output"], label) + sources = ROOT / "tests/reference/examples/balls/gemmini/workloads/ctests" + for source in sources.glob("*.c"): + output = tests[source.stem + "-linux"]["output"] + markers = re.findall(r'printf\("([^"\n]* PASSED)\\n"\)', + source.read_text(encoding="utf-8")) + require(len(markers) == 1 and markers[0] in output, "Missing oracle: " + source.name) + require(markers[0] in console, "Missing raw oracle: " + source.name) + output = tests["gemmini_linux_check-linux"]["output"] + pattern = (r"^PASS GEMMINI_CASE id=(\d+) mode=(OS|WS) m=(\d+) n=(\d+) k=(\d+) " + r"cpu_ns=(\d+) accelerator_end_to_end_ns=(\d+)$") + rows = re.findall(pattern, output, re.MULTILINE) + require(len(rows) == result["blocked_matmul_cases"] == 16, "Missing matrix cases") + measurements = [] + for index, row in enumerate(rows): + case, mode, m, n, k, cpu, accelerator = row + shape = tuple(map(int, (m, n, k))) + require(int(case) == index + 1 and shape == SHAPES[(index % 8) // 2] + and mode == ("WS" if index % 2 else "OS"), "Wrong case order/shape") + require(int(cpu) > 0 and int(accelerator) > 0, "Unusable timing sample") + require("PASS GEMMINI_CASE " + " ".join([ + f"id={case}", f"mode={mode}", f"m={m}", f"n={n}", f"k={k}", + f"cpu_ns={cpu}", f"accelerator_end_to_end_ns={accelerator}", + ]) in console, "Missing raw matrix result") + measurements.append({ + "case": int(case), "mode": mode, "m": int(m), "n": int(n), "k": int(k), + "cpu_ns": int(cpu), "accelerator_end_to_end_ns": int(accelerator), + "cpu_over_accelerator": round(int(cpu) / int(accelerator), 4), + }) + require("PASS GEMMINI_LINUX_CHECK cases=16" in output, "Missing final oracle") + require("PASS GEMMINI_LINUX_CHECK cases=16" in console, "Missing raw final oracle") + summary = { + "result": "PASS_OFFLINE_VERIFICATION", + "console_sha256": hashlib.sha256(raw).hexdigest(), + "payload_sha256": build["payload_sha256"], + "matrix_measurements": measurements, + "timing_scope": "分块、DMA、配置、同步和 CPU 跨 K 累加；不是纯 MAC 延迟", + "model_end_to_end_tested": False, + } + if args.output: + args.output.write_text(json.dumps(summary, ensure_ascii=False, indent=2) + "\n", + encoding="utf-8") + print("PASS offline verification: 15 workloads, five Linux checks, 16 matrix cases") + for item in measurements: + print(f"CASE {item['case']:2} {item['mode']} {item['m']}x{item['n']}x{item['k']} " + f"CPU={item['cpu_ns'] / 1e6:.3f}ms " + f"accelerator={item['accelerator_end_to_end_ns'] / 1e6:.3f}ms " + f"CPU/accelerator={item['cpu_over_accelerator']:.4f}") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/build_gemmini_image.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/build_gemmini_image.py new file mode 100644 index 0000000..678e72a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/build_gemmini_image.py @@ -0,0 +1,82 @@ +"""在全新隔离目录按原 bbkernel 流程构建 Linux/Gemmini 测试镜像。""" + +import argparse +import hashlib +import json +import os +from pathlib import Path +import shutil +import subprocess +import time + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--cache-base", type=Path, required=True) + parser.add_argument("--sdk", type=Path, required=True) + args = parser.parse_args() + started = time.monotonic() + baseline = json.loads((ROOT / "SOFTWARE_BASELINE.json").read_text()) + cache = ROOT / "build/downloads" + cache.mkdir(parents=True, exist_ok=True) + for name, commit in baseline.items(): + filename = f"{name}-{commit}.tar.gz" + source = args.cache_base / "build/downloads" / filename + target = cache / filename + if source.is_file() and not target.exists(): + shutil.copy2(source, target) + print(f"CACHE {name} {digest(target)}", flush=True) + environment = os.environ.copy() + environment["PATH"] = str(args.sdk / "bin") + ":" + environment["PATH"] + + def run(command, timeout): + print("RUN " + " ".join(map(str, command)), flush=True) + subprocess.run(list(map(str, command)), cwd=ROOT, env=environment, + timeout=timeout, check=True) + + run(["python3", "software/prepare_gemmini_linux.py"], 60) + run(["cmake", "-S", "build/linux-gemmini", "-B", "build/linux-gemmini-build", + "-DCMAKE_C_COMPILER=riscv64-unknown-linux-gnu-gcc"], 60) + run(["cmake", "--build", "build/linux-gemmini-build", "-j8"], 180) + workloads = ROOT / "build/software/bb-tests/output/workloads" + run(["cmake", "--install", "build/linux-gemmini-build", "--prefix", workloads], 60) + # Existing entry installs the Linux system check, builds rootfs and Linux, + # and packages the original OpenSBI firmware. No alternate runtime uploader. + run(["bash", "software/build.sh"], 2400) + run(["python3", "scripts/build_board_firmware.py", + "--cross-compile", "riscv64-unknown-linux-gnu-"], 300) + payload = ROOT / "build/board-software/fw_payload.bin" + prepared = json.loads((ROOT / "build/linux-gemmini/PREPARED.json").read_text()) + installed = sorted(workloads.glob("*-linux")) + rootfs = ROOT / "build/software/kernel-build/rootfs/root" + if len(installed) != 15: + raise RuntimeError(f"Expected 15 workloads, got {len(installed)}") + for path in installed: + if digest(path) != digest(rootfs / path.name): + raise RuntimeError(f"Rootfs workload mismatch: {path.name}") + result = { + "result": "PASS_BUILD_NOT_HARDWARE_TESTED", + "elapsed_seconds": round(time.monotonic() - started, 3), + "software_baseline": baseline, + "profile": prepared["profile"], + "payload_bytes": payload.stat().st_size, + "payload_sha256": digest(payload), + "workloads": {path.name: {"bytes": path.stat().st_size, "sha256": digest(path)} + for path in installed}, + "rootfs_install_verified": True, + "flash_modified": False, + "hardware_gemmini_tested": False, + "model_end_to_end_tested": False, + } + (ROOT / "build/LINUX_GEMMINI_BUILD.json").write_text(json.dumps(result, indent=2) + "\n") + print(json.dumps(result, indent=2), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/gemmini_linux_check.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/gemmini_linux_check.c new file mode 100644 index 0000000..1f6fa7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/gemmini_linux_check.c @@ -0,0 +1,132 @@ +// Linux workload for the actual 8x8 profile; use the pinned upstream ISA and DMA library. +#define _GNU_SOURCE +#include "buckyball.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if GEMMINI_DIM != 8 || BANK_WIDTH != 64 +#error This workload requires the emitted Toy FPGA 8x8 / 64-bit bank profile. +#endif + +enum { TILE = 8, MAX_DIM = 24 }; +static elem_t tile_a[TILE * TILE] __attribute__((aligned(64))); +static elem_t tile_b[TILE * TILE] __attribute__((aligned(64))); +static elem_t tile_zero[TILE * TILE] __attribute__((aligned(64))); +static result_t tile_c[TILE * TILE] __attribute__((aligned(64))); +static elem_t matrix_a[MAX_DIM * MAX_DIM], matrix_b[MAX_DIM * MAX_DIM]; +static result_t expected[MAX_DIM * MAX_DIM], observed[MAX_DIM * MAX_DIM]; + +static uint64_t nanoseconds(void) { + struct timespec value; + if (clock_gettime(CLOCK_MONOTONIC, &value)) { + perror("clock_gettime"); + exit(2); + } + return (uint64_t)value.tv_sec * 1000000000ULL + value.tv_nsec; +} + +static void gemmini_tile(unsigned ws) { + // 8-byte bank rows: INT8 uses one group, INT32 output uses four groups. + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 4); + bb_mem_alloc(3, 1, 1); + bb_mvin((uintptr_t)tile_a, 0, TILE, 1); + bb_mvin((uintptr_t)tile_b, 1, TILE, 1); + bb_mvin((uintptr_t)tile_zero, 3, TILE, 1); + bb_gemmini_config(ws, 0, 0, 0, 0); + bb_gemmini_preload(ws ? 1 : 3, 2, TILE, 0, 0); + bb_gemmini_compute_preloaded(0, ws ? 3 : 1, 2, TILE, 0, 0, 0); + bb_mvout((uintptr_t)tile_c, 2, TILE, 1); + bb_fence(); + for (unsigned bank = 0; bank < 4; ++bank) + bb_mem_release(bank); +} + +static void cpu_reference(unsigned m, unsigned n, unsigned k) { + for (unsigned row = 0; row < m; ++row) + for (unsigned col = 0; col < n; ++col) { + int32_t sum = 0; + for (unsigned inner = 0; inner < k; ++inner) + sum += (int32_t)matrix_a[row * k + inner] * matrix_b[inner * n + col]; + expected[row * n + col] = sum; + } +} + +static void blocked_matmul(unsigned m, unsigned n, unsigned k, unsigned ws) { + memset(observed, 0, sizeof(observed)); + for (unsigned row = 0; row < m; row += TILE) + for (unsigned col = 0; col < n; col += TILE) + for (unsigned inner = 0; inner < k; inner += TILE) { + memset(tile_a, 0, sizeof(tile_a)); + memset(tile_b, 0, sizeof(tile_b)); + memset(tile_zero, 0, sizeof(tile_zero)); + // Explicit writes give the DMA destination a private writable page. + memset(tile_c, 0, sizeof(tile_c)); + for (unsigned i = 0; i < TILE; ++i) + for (unsigned j = 0; j < TILE; ++j) { + if (row + i < m && inner + j < k) + tile_a[i * TILE + j] = matrix_a[(row + i) * k + inner + j]; + if (inner + i < k && col + j < n) + tile_b[i * TILE + j] = matrix_b[(inner + i) * n + col + j]; + } + gemmini_tile(ws); + for (unsigned i = 0; i < TILE && row + i < m; ++i) + for (unsigned j = 0; j < TILE && col + j < n; ++j) + observed[(row + i) * n + col + j] += tile_c[i * TILE + j]; + } +} + +static int check_case(unsigned id, unsigned m, unsigned n, unsigned k, unsigned ws) { + // Small bounded values keep the independent INT32 oracle free of overflow. + for (unsigned i = 0; i < m * k; ++i) + matrix_a[i] = (int)((i * 7 + id * 3) % 19) - 9; + for (unsigned i = 0; i < k * n; ++i) + matrix_b[i] = (int)((i * 11 + id * 5) % 23) - 11; + printf("BEGIN GEMMINI_CASE id=%u mode=%s m=%u n=%u k=%u\n", + id, ws ? "WS" : "OS", m, n, k); + alarm(60); + uint64_t start = nanoseconds(); + cpu_reference(m, n, k); + uint64_t cpu_ns = nanoseconds() - start; + start = nanoseconds(); + blocked_matmul(m, n, k, ws); + uint64_t accelerator_ns = nanoseconds() - start; + alarm(0); + for (unsigned i = 0; i < m * n; ++i) + if (observed[i] != expected[i]) { + printf("FAIL GEMMINI_CASE id=%u row=%u col=%u got=%d expected=%d\n", + id, i / n, i % n, observed[i], expected[i]); + return 1; + } + printf("PASS GEMMINI_CASE id=%u mode=%s m=%u n=%u k=%u cpu_ns=%llu " + "accelerator_end_to_end_ns=%llu\n", id, ws ? "WS" : "OS", m, n, k, + (unsigned long long)cpu_ns, (unsigned long long)accelerator_ns); + return 0; +} + +int main(void) { + setvbuf(stdout, NULL, _IONBF, 0); + printf("BEGIN GEMMINI_LINUX_CHECK pid=%ld dimension=%d bank_width=%d\n", + (long)getpid(), GEMMINI_DIM, BANK_WIDTH); + if (mlockall(MCL_CURRENT | MCL_FUTURE)) + printf("INFO MLOCKALL errno=%d; buffers are explicitly faulted in\n", errno); + unsigned id = 0; + const unsigned shapes[][3] = {{8, 8, 8}, {16, 16, 16}, {13, 11, 17}, {8, 24, 8}}; + for (unsigned repeat = 0; repeat < 2; ++repeat) + for (unsigned shape = 0; shape < sizeof(shapes) / sizeof(shapes[0]); ++shape) + for (unsigned ws = 0; ws < 2; ++ws) + if (check_case(++id, shapes[shape][0], shapes[shape][1], shapes[shape][2], ws)) + return 1; + printf("PASS GEMMINI_LINUX_CHECK cases=%u\n", id); + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/linux_system_check.c b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/linux_system_check.c new file mode 100644 index 0000000..fa90a06 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/linux_system_check.c @@ -0,0 +1,135 @@ +// Linux acceptance workload: processes, Sv39-backed memory and floating point. +// A host run validates the test program only; the FPGA run is the acceptance. +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void fail(const char *message) { + fprintf(stderr, "FAIL %s\n", message); + exit(1); +} + +static int wait_child(pid_t pid) { + int status; + pid_t result; + do { + result = waitpid(pid, &status, 0); + } while (result < 0 && errno == EINTR); + if (result != pid) + fail("waitpid"); + return status; +} + +static void check_virtual_memory(void) { + long page_size = sysconf(_SC_PAGESIZE); + if (page_size <= 0) + fail("page size"); + volatile unsigned char *memory = mmap(NULL, (size_t)page_size * 2, + PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (memory == MAP_FAILED) + fail("mmap"); + memory[0] = 0x42; + memory[page_size] = 0x7b; + + pid_t child = fork(); + if (child < 0) + fail("fork for copy-on-write"); + if (child == 0) { + if (memory[0] != 0x42) + _exit(2); + memory[0] = 0xa5; + _exit(memory[0] == 0xa5 ? 0 : 3); + } + int status = wait_child(child); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0 || memory[0] != 0x42) + fail("process isolation / copy-on-write"); + puts("PASS VM_COPY_ON_WRITE"); + + if (mprotect((void *)(memory + page_size), (size_t)page_size, PROT_NONE)) + fail("mprotect"); + child = fork(); + if (child < 0) + fail("fork for page fault"); + if (child == 0) { + volatile unsigned char forbidden = memory[page_size]; + (void)forbidden; + _exit(4); + } + status = wait_child(child); + if (!WIFSIGNALED(status) || WTERMSIG(status) != SIGSEGV) + fail("protected page must deliver SIGSEGV"); + if (mprotect((void *)(memory + page_size), (size_t)page_size, PROT_READ)) + fail("restore page access"); + if (memory[page_size] != 0x7b) + fail("page contents after protection change"); + if (munmap((void *)memory, (size_t)page_size * 2)) + fail("munmap"); + puts("PASS VM_PAGE_PROTECTION"); +} + +static int float_work(double seed) { + volatile double scale = 1.5; + double value = seed; + for (int i = 0; i < 1000; ++i) { + value = value * scale + 0.25; + if (sched_yield()) + return 1; + value = (value - 0.25) / scale; + if (!isfinite(value) || fabs(value - seed) > 1e-10) + return 1; + } + return 0; +} + +static void check_float_context(void) { + pid_t child = fork(); + if (child < 0) + fail("fork for floating-point context"); + if (child == 0) + _exit(float_work(-3.125)); + int parent_result = float_work(7.25); + int status = wait_child(child); + if (parent_result || !WIFEXITED(status) || WEXITSTATUS(status)) + fail("floating-point arithmetic/context"); + puts("PASS FP64_PROCESS_CONTEXT"); +} + +static void check_timer(void) { + struct timespec before, after, remaining = {0, 100000000}; + if (clock_gettime(CLOCK_MONOTONIC, &before)) + fail("clock_gettime start"); + while (nanosleep(&remaining, &remaining)) { + if (errno != EINTR) + fail("nanosleep"); + } + if (clock_gettime(CLOCK_MONOTONIC, &after)) + fail("clock_gettime end"); + int64_t elapsed = (after.tv_sec - before.tv_sec) * INT64_C(1000000000) + + after.tv_nsec - before.tv_nsec; + if (elapsed < 100000000) + fail("monotonic timer / scheduled wakeup"); + printf("PASS LINUX_TIMER elapsed_ns=%lld\n", (long long)elapsed); +} + +int main(void) { + const struct rlimit no_core_dump = {0, 0}; + if (setrlimit(RLIMIT_CORE, &no_core_dump)) + fail("disable expected-fault core dumps"); + setvbuf(stdout, NULL, _IONBF, 0); + puts("BEGIN LINUX_SYSTEM_CHECK"); + check_virtual_memory(); + check_float_context(); + check_timer(); + puts("PASS LINUX_SYSTEM_CHECK"); + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/prepare_gemmini_linux.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/prepare_gemmini_linux.py new file mode 100644 index 0000000..267558b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/sources/software/prepare_gemmini_linux.py @@ -0,0 +1,91 @@ +"""生成匹配实际 8×8 核心的 Linux 测试构建输入，不执行编译。""" + +import argparse +import hashlib +import json +from pathlib import Path +import shutil + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--profile", type=Path, + default=ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json") + parser.add_argument("--output", type=Path, default=ROOT / "build/linux-gemmini") + args = parser.parse_args() + profile = json.loads(args.profile.read_text(encoding="utf-8")) + expected = {"gemmini_rows": 8, "gemmini_columns": 8, "bank_width": 64, + "bank_count": 8, "virtual_bank_count": 16, "bank_rows": 1024} + for key, value in expected.items(): + if profile[key] != value: + raise ValueError(f"Wrong hardware profile: {key}={profile[key]}, expected {value}") + reference = ROOT / "tests/reference" + manifest = json.loads((ROOT / "tests/REFERENCE_MANIFEST.json").read_text(encoding="utf-8")) + for name, digest in manifest["files"].items(): + if hashlib.sha256((reference / name).read_bytes()).hexdigest() != digest: + raise ValueError(f"Changed pinned reference: {name}") + out = args.output.resolve() + if out == ROOT or out in ROOT.parents: + raise ValueError("Output must not replace the source directory") + out.mkdir(parents=True, exist_ok=True) + shutil.copytree(reference, out / "reference", dirs_exist_ok=True) + shutil.copy2(ROOT / "software/gemmini_linux_check.c", out / "gemmini_linux_check.c") + (out / "params.h").write_text( + "#define BANK_WIDTH 64\n#define PHYSICAL_BANK_NUM 8\n" + "#define VIRTUAL_BANK_NUM 16\n#define BANK_ENTRIES 1024\n#define GEMMINI_DIM 8\n", + encoding="utf-8") + # Preserve the exact pinned Gemmini instruction encodings; do not use + # upstream Berkeley Gemmini binaries with this Buckyball instruction ABI. + names = {2: "CONFIG", 3: "FLUSH", 53: "PRELOAD", 66: "COMPUTE_PRELOADED", + 67: "COMPUTE_ACCUMULATED", 80: "LOOP_WS_CONFIG_BOUNDS", + 81: "LOOP_WS_CONFIG_ADDR_A", 82: "LOOP_WS_CONFIG_ADDR_B", + 83: "LOOP_WS_CONFIG_ADDR_D", 84: "LOOP_WS_CONFIG_ADDR_C", + 85: "LOOP_WS_CONFIG_STRIDES_AB", 86: "LOOP_WS_CONFIG_STRIDES_DC", + 87: "LOOP_WS"} + names.update({95 + index: f"LOOP_CONV_WS_CONFIG_{index}" for index in range(1, 10)}) + names[105] = "LOOP_CONV_WS" + if set(names) != set(profile["ball_funct7"]): + raise ValueError("Instruction definitions do not match the emitted profile") + (out / "ballISA.h").write_text("\n".join( + f"#define BB_FUNC7_GEMMINI_{name} {number}" for number, name in names.items()) + "\n", + encoding="utf-8") + sources = [] + for index, original in enumerate(sorted((reference / "examples/balls/gemmini/workloads/ctests").glob("*.c")), 1): + data = original.read_text(encoding="utf-8") + if data.count("#define DIM 16") != 1: + raise ValueError(f"Unexpected test dimension: {original}") + target = out / (original.stem + ".c") + target.write_text(data.replace("#define DIM 16", "#define DIM 8"), encoding="utf-8") + sources.append(target.name) + cmake = '''cmake_minimum_required(VERSION 3.22) +project(ToyLinuxGemmini C) +set(CMAKE_C_STANDARD 11) +add_compile_options(-march=rv64gc -mabi=lp64d -O2 -Wall -Wextra -Werror -ffp-contract=off) +add_link_options(-static) +include_directories(${CMAKE_CURRENT_SOURCE_DIR} + reference/bb-tests/workloads/lib reference/examples/balls/gemmini/workloads) +add_library(bb_reference STATIC reference/bb-tests/workloads/lib/buckyball.c + reference/bb-tests/workloads/lib/bbhw/mem/mem.c + reference/bb-tests/workloads/lib/bbhw/isa/isa.c) +set(workloads gemmini_linux_check-linux) +add_executable(gemmini_linux_check-linux gemmini_linux_check.c) +target_link_libraries(gemmini_linux_check-linux PRIVATE bb_reference m) +''' + for name in sources: + target = Path(name).stem + "-linux" + cmake += f"add_executable({target} {name})\ntarget_link_libraries({target} PRIVATE bb_reference m)\nlist(APPEND workloads {target})\n" + cmake += "install(TARGETS ${workloads} RUNTIME DESTINATION .)\n" + (out / "CMakeLists.txt").write_text(cmake, encoding="utf-8") + (out / "PREPARED.json").write_text(json.dumps({ + "result": "PREPARED_NOT_BUILT", "dimension": 8, + "reference_commit": manifest["commit"], "original_cases": sources, + "new_blocked_matmul_cases": 16, "profile": expected, + "model_end_to_end_tested": False, + }, indent=2) + "\n", encoding="utf-8") + print(f"Prepared {len(sources)} pinned cases and one blocked-matmul workload in {out}") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/RESULT.json new file mode 100644 index 0000000..50ee95f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/RESULT.json @@ -0,0 +1,24 @@ +{ + "result": "PASS_WATCHDOG_SUCCESS_FAILURE_TIMEOUT_AND_REAP", + "cases": [ + { + "program": "/bin/busybox true", + "exit_code": 0, + "watcher_alive_rc": 1, + "expected": true + }, + { + "program": "/bin/busybox false", + "exit_code": 1, + "watcher_alive_rc": 1, + "expected": true + }, + { + "program": "/bin/busybox sleep 5", + "exit_code": 137, + "watcher_alive_rc": 1, + "expected": true + } + ], + "flash_written": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/check.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/check.log new file mode 100644 index 0000000..8aa436b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram-hardware/watchdog/check.log @@ -0,0 +1,22 @@ +/bin/busybox true & p=$!; (sleep 1; kill -KILL $p) & w=$!; wait $p; r=$?; ki +ll $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWATCH_SELF_0:%s\n' $r + +WATCH_SELF_0:0 +~ # kill -0 $w 2>/dev/null; printf '\nWATCH_REAP_0:%s\n' $? + +WATCH_REAP_0:1 +~ # /bin/busybox false & p=$!; (sleep 1; kill -KILL $p) & w=$!; wait $p; r=$?; k +ill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWATCH_SELF_1:%s\n' $r + +WATCH_SELF_1:1 +~ # kill -0 $w 2>/dev/null; printf '\nWATCH_REAP_1:%s\n' $? + +WATCH_REAP_1:1 +~ # /bin/busybox sleep 5 & p=$!; (sleep 1; kill -KILL $p) & w=$!; wait $p; r=$?; + kill $w 2>/dev/null; wait $w 2>/dev/null; printf '\nWATCH_SELF_2:%s\n' $r +Killed + +WATCH_SELF_2:137 +~ # kill -0 $w 2>/dev/null; printf '\nWATCH_REAP_2:%s\n' $? + +WATCH_REAP_2:1 diff --git a/platforms/arty-a7-toy/host/check_live_shell.py b/platforms/arty-a7-toy/host/check_live_shell.py new file mode 100644 index 0000000..76337e0 --- /dev/null +++ b/platforms/arty-a7-toy/host/check_live_shell.py @@ -0,0 +1,61 @@ +"""回归后检查 Linux 控制台、空闲内存和已回收的 watchdog。""" +import argparse +import json +from pathlib import Path +import re +import sys +import time + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT / 'host')) +from ftdi_transport import D2xxPort + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument('--port', default='COM5') + parser.add_argument('--output', type=Path, required=True) + args = parser.parse_args() + args.output.mkdir(exist_ok=False, parents=True) + commands = [ + b'kill -0 "$w" 2>/dev/null; printf "\\nWATCHDOG_ALIVE_RC:%s\\n" "$?"\n', + b'while read a b c; do case "$a" in MemTotal:|MemAvailable:) printf "%s %s %s\\n" "$a" "$b" "$c";; esac; done < /proc/meminfo; printf "LIVE_MEM_DONE\\n"\n', + ] + result = {'flash_written': False, 'configuration_changed': False} + with D2xxPort(args.port, timeout_seconds=120) as port: + with (args.output / 'post-console.log').open('wb') as log: + for index, command in enumerate(commands): + port.write(command) + buffer = bytearray() + deadline = time.monotonic() + 30 + pattern = (rb'(?:^|\n)WATCHDOG_ALIVE_RC:(\d+)\r*\n' if index == 0 + else rb'(?:^|\n)LIVE_MEM_DONE\r*\n') + while time.monotonic() < deadline: + data = port.read(4096) + buffer.extend(data) + log.write(data) + log.flush() + match = re.search(pattern, buffer) + if match: + break + else: + raise TimeoutError('Post-test live console timeout') + print(buffer.decode(errors='replace')) + if index == 0: + result['watchdog_alive_rc'] = int(match[1]) + if int(match[1]) == 0: + raise ValueError('Last watchdog still running') + else: + for name in ['MemTotal', 'MemAvailable']: + match = re.search(name.encode() + rb':\s+(\d+) kB\r*\n', buffer) + if not match: + raise ValueError('Missing live memory field') + result[name + '_kib'] = int(match[1]) + result['uart_latency_restored_ms'] = port.original_latency.value + result['result'] = 'PASS_POST_TEST_LIVE_SHELL' + (args.output / 'RESULT.json').write_text(json.dumps(result, indent=2) + '\n', encoding='utf-8') + print(json.dumps(result, indent=2)) + + +if __name__ == '__main__': + main() diff --git a/platforms/arty-a7-toy/scripts/package_downloads.py b/platforms/arty-a7-toy/scripts/package_downloads.py new file mode 100644 index 0000000..6efca40 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/package_downloads.py @@ -0,0 +1,174 @@ +"""打包已归档且摘要固定的两套烧录产物，不构建、不连接或写入板卡。""" + +import argparse +import hashlib +import io +import json +from pathlib import Path +import re +import shutil +import subprocess +import zipfile + +ROOT = Path(__file__).resolve().parents[1] +TEMPLATES = ROOT / "distribution" +ARCHIVE = ROOT / "evidence/2026-10-12" +TAG = "arty-a7-toy-2026-10-12" + + +def digest(path): + value = hashlib.sha256() + with path.open("rb") as source: + for block in iter(lambda: source.read(1024 * 1024), b""): + value.update(block) + return value.hexdigest() + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def copy(source, root, relative): + destination = root / relative + destination.parent.mkdir(parents=True, exist_ok=True) + shutil.copy2(source, destination) + + +def bind_file(path): + return {"bytes": path.stat().st_size, "sha256": digest(path)} + + +def manifest(root, flow, commit): + files = {p.relative_to(root).as_posix(): bind_file(p) + for p in sorted(root.rglob("*")) if p.is_file()} + result = {"flow": flow, "source_commit": commit, + "target": "xc7a100tcsg324-1", "engineering_prerelease": True, + "files": files} + (root / "MANIFEST.json").write_text( + json.dumps(result, indent=2, ensure_ascii=False) + "\n", encoding="utf-8") + return result + + +def zip_directory(source, target): + with zipfile.ZipFile(target, "w", compression=zipfile.ZIP_DEFLATED, + compresslevel=6) as output: + for path in sorted(source.rglob("*")): + if path.is_file(): + # Upstream source .tar.gz files are already compressed. + method = zipfile.ZIP_STORED if path.name.endswith(".tar.gz") else zipfile.ZIP_DEFLATED + output.write(path, path.relative_to(source).as_posix(), compress_type=method) + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + for name in ["uart-bit", "uart-payload", "flash-bit", "flash-packed", "flash-mcs", "os-inputs", "output"]: + parser.add_argument("--" + name, required=True, type=Path) + args = parser.parse_args() + repo = Path(subprocess.check_output(["git", "rev-parse", "--show-toplevel"], + cwd=ROOT, text=True).strip()) + require(not subprocess.check_output(["git", "status", "--porcelain", "--untracked-files=no"], + cwd=repo), "先提交全部公开源码，拒绝打包未提交的修改") + commit = subprocess.check_output(["git", "rev-parse", "HEAD"], cwd=repo, text=True).strip() + build = read(ARCHIVE / "linux-gemmini/build/LINUX_GEMMINI_BUILD.json") + uart_record = read(ARCHIVE / "hardware/PROGRAM_RESULT.json") + flash_record = read(ARCHIVE / "flash/FLASH_RESULT.json") + flash_image = read(ARCHIVE / "flash/software/FLASH_IMAGE.json") + expected = [(args.uart_bit, uart_record["bitstream_sha256"]), + (args.uart_payload, build["payload_sha256"]), + (args.flash_bit, flash_record["bitstream_sha256"]), + (args.flash_packed, flash_image["packed_payload_sha256"]), + (args.flash_mcs, flash_image["flash_image_sha256"])] + for path, sha in expected: + require(digest(path) == sha, "烧录文件与已归档实物证据不符：" + path.name) + require(args.uart_payload.stat().st_size == build["payload_bytes"], "软件镜像长度错误") + baseline = read(ROOT / "SOFTWARE_BASELINE.json") + cache_log = (ARCHIVE / "linux-gemmini/build/build.log").read_text(encoding="utf-8") + cache_hashes = dict(re.findall(r"^CACHE (\S+) ([0-9a-f]{64})$", cache_log, re.MULTILINE)) + os_files = [] + for name, version in baseline.items(): + path = args.os_inputs / "build/downloads" / f"{name}-{version}.tar.gz" + require(digest(path) == cache_hashes[name], "依赖归档摘要不符：" + name) + os_files.append(path) + input_record = read(args.os_inputs / "INPUTS.json") + for name in ["build/software/kernel-build/linux/.config", + "build/software/kernel-build/busybox/.config", + "build/software/SOURCE_MANIFEST.json"]: + require(bind_file(args.os_inputs / name) == input_record[name], "实际软件配置摘要不符") + notices = args.os_inputs / "notices" + require((notices / "thirdparty/rocket-chip/LICENSE.Berkeley").is_file(), "缺少硬件依赖声明") + output = args.output.resolve() + output.mkdir(parents=True, exist_ok=False) + package_roots = {name: output / name for name in ["uart", "flash", "sources"]} + for name in ["uart", "flash"]: + root = package_roots[name] + root.mkdir() + copy(TEMPLATES / "verify_bundle.py", root, "verify_bundle.py") + copy(TEMPLATES / f"{name.upper()}_README.md", root, "README.md") + copy(TEMPLATES / f"run_{name}.ps1", root, f"run_{name}.ps1") + copy(repo / "LICENSE", root, "LICENSE") + shutil.copytree(notices, root / "notices") + (root / "requirements.txt").write_text("pyserial==3.5\n", encoding="utf-8") + + uart = package_roots["uart"] + copy(args.uart_bit, uart, "toy_a7_uart.bit") + copy(args.uart_payload, uart, "fw_payload.bin") + copy(ARCHIVE / "linux-gemmini/build/LINUX_GEMMINI_BUILD.json", uart, "LINUX_GEMMINI_BUILD.json") + for name in ["program.tcl", "board/program_arty.tcl", "host/check_linux_gemmini.py", + "host/ftdi_transport.py", "host/load.py", "scripts/verify_linux_gemmini.py"]: + copy(ROOT / name, uart, name) + shutil.copytree(ARCHIVE / "linux-gemmini", uart / "evidence/linux-gemmini") + copy(ARCHIVE / "hardware/PROGRAM_RESULT.json", uart, "evidence/PROGRAM_RESULT.json") + + flash = package_roots["flash"] + copy(args.flash_bit, flash, "toy_a7_flash.bit") + copy(args.flash_packed, flash, "flash_payload.bin") + copy(args.flash_mcs, flash, "toy_flash.mcs") + copy(ARCHIVE / "flash/software/FLASH_IMAGE.json", flash, "toy_flash.mcs.json") + for name in ["host/flash.py", "host/observe_flash_boot.py", "board/program_flash.tcl", + "board/make_flash_image.tcl"]: + copy(ROOT / name, flash, name) + shutil.copytree(ARCHIVE / "flash", flash / "evidence/flash") + + sources = package_roots["sources"] + sources.mkdir() + snapshot = subprocess.check_output(["git", "archive", "--format=zip", "--prefix=fpga/", commit], cwd=repo) + with zipfile.ZipFile(io.BytesIO(snapshot)) as archive: + archive.extractall(sources) + copy(TEMPLATES / "SOURCES_README.md", sources, "README.md") + copy(TEMPLATES / "verify_bundle.py", sources, "verify_bundle.py") + (sources / "SOURCE_COMMIT.txt").write_text(commit + "\n", encoding="utf-8") + shutil.copytree(notices, sources / "notices") + for path in os_files: + copy(path, sources, "fpga/platforms/arty-a7-toy/build/downloads/" + path.name) + for name, target in [("linux/.config", "linux.config"), ("busybox/.config", "busybox.config")]: + copy(args.os_inputs / "build/software/kernel-build" / name, sources, "actual-configs/" + target) + copy(args.os_inputs / "build/software/SOURCE_MANIFEST.json", sources, "actual-configs/SOURCE_MANIFEST.json") + + bundles = {} + for flow, root in package_roots.items(): + metadata = manifest(root, flow, commit) + filename = f"arty-a7-toy-{flow}.zip" + zip_directory(root, output / filename) + bundles[filename] = {**bind_file(output / filename), "files": len(metadata["files"])} + print(f"PACKED {filename} files={len(metadata['files'])}", flush=True) + # Also make the two .bit files directly downloadable, with explicit flow names. + for name, source in [("toy_a7_uart.bit", args.uart_bit), ("toy_a7_flash.bit", args.flash_bit)]: + copy(source, output, name) + bundles[name] = bind_file(output / name) + record = {"tag": TAG, "source_commit": commit, "engineering_prerelease": True, + "assets": bundles} + (output / "RELEASE_MANIFEST.json").write_text( + json.dumps(record, indent=2, ensure_ascii=False) + "\n", encoding="utf-8") + bundles["RELEASE_MANIFEST.json"] = bind_file(output / "RELEASE_MANIFEST.json") + (output / "SHA256SUMS.txt").write_text( + "".join(f"{metadata['sha256']} {name}\n" for name, metadata in bundles.items()), encoding="utf-8") + print("PASS DOWNLOAD_PACKAGING " + commit, flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_rob_hardware.py b/platforms/arty-a7-toy/scripts/verify_rob_hardware.py new file mode 100644 index 0000000..259113c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_rob_hardware.py @@ -0,0 +1,79 @@ +"""核验 ROB RAM 候选的两次实物回归、原始日志和输入摘要。""" + +import hashlib +import json +from pathlib import Path +import re +import subprocess +import sys + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/rob-ram-hardware" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + manifest = read(ARCHIVE / "MANIFEST.json") + for name, metadata in manifest["files"].items(): + path = (ARCHIVE / name).resolve() + assert path.is_relative_to(ARCHIVE.resolve()), name + assert path.stat().st_size == metadata["bytes"] and sha(path) == metadata["sha256"], name + summary = read(ARCHIVE / "HARDWARE_RESULT.json") + assert summary["result"] == "PASS_ROB_RAM_PHYSICAL_LINUX_AND_GEMMINI" + assert summary["flash_written"] is False and summary["model_end_to_end_tested"] is False + implementation = read(ARCHIVE / "implementation/RUN.json") + assert implementation["status"] == "COMPLETED" and implementation["exit_code"] == 0 + assert implementation["candidate_core_unchanged"] and implementation["candidate_memory_unchanged"] + assert implementation["core_sha256"] == summary["core_rtl_sha256"] + assert implementation["memory_sha256"] == summary["memory_rtl_sha256"] + assert implementation["part"] == summary["part"] == "xc7a100tcsg324-1" + first = read(ARCHIVE / "first-pass/RESULT.json") + build = read(ARCHIVE / "software/LINUX_GEMMINI_BUILD.json") + assert not first.get("configuration_reused", False) + assert first["ddr_readback_bytes"] == build["payload_bytes"] == summary["ddr_readback_bytes"] + transfer = (ARCHIVE / "first-pass/transfer-console.log").read_text(encoding="utf-8") + expected = f"PASS FULL_DDR_READBACK bytes={build['payload_bytes']} seconds={first['ddr_transfer_seconds']}" + assert expected in transfer and "PASS LINUX_BOOT" in transfer + program = (ARCHIVE / "first-pass/program.log").read_text(encoding="utf-8") + assert "ARTY_JTAG_PROGRAMMED:" in program and "xc7a100t" in program + session = read(ARCHIVE / "SESSION.json") + assert session["exit_code"] == 0 and session["timeout_seconds"] == 3600 + for directory in ["first-pass", "repeat-pass"]: + result = read(ARCHIVE / directory / "RESULT.json") + assert result["bitstream_sha256"] == summary["bitstream_sha256"] + assert result["payload_sha256"] == build["payload_sha256"] == summary["payload_sha256"] + subprocess.run([ + sys.executable, str(ROOT / "scripts/verify_linux_gemmini.py"), + "--build-record", str(ARCHIVE / "software/LINUX_GEMMINI_BUILD.json"), + "--hardware-result", str(ARCHIVE / directory / "RESULT.json"), + "--expected-bit-sha256", summary["bitstream_sha256"], + ], check=True, timeout=30, stdout=subprocess.DEVNULL) + assert read(ARCHIVE / "repeat-pass/LOAD_RESULT.json") == first + watchdog = read(ARCHIVE / "watchdog/RESULT.json") + assert watchdog["result"] == "PASS_WATCHDOG_SUCCESS_FAILURE_TIMEOUT_AND_REAP" + assert [case["exit_code"] for case in watchdog["cases"]] == [0, 1, 137] + raw = (ARCHIVE / "watchdog/check.log").read_bytes() + for index, case in enumerate(watchdog["cases"]): + assert case["watcher_alive_rc"] == 1 + assert re.search(rb"(?:^|\n)WATCH_SELF_" + str(index).encode() + rb":" + + str(case["exit_code"]).encode() + rb"\r*\n", raw) + assert re.search(rb"(?:^|\n)WATCH_REAP_" + str(index).encode() + rb":1\r*\n", raw) + live = read(ARCHIVE / "post-check/RESULT.json") + assert live["result"] == "PASS_POST_TEST_LIVE_SHELL" and live["watchdog_alive_rc"] == 1 + assert live["MemTotal_kib"] > 200000 and live["MemAvailable_kib"] > 0 + assert not live["flash_written"] and not live["configuration_changed"] + assert live["uart_latency_restored_ms"] == 16 + for name, expected in summary["execution_sources"].items(): + assert sha(ARCHIVE / "sources" / name) == expected, name + print(f"PASS ROB RAM physical archive: {len(manifest['files'])} files; full DDR readback; two 15-workload runs") + + +if __name__ == "__main__": + main()