From 36b0109321b696d6921dabea5fe099a91065169f Mon Sep 17 00:00:00 2001 From: Cody-ic <261693366+Cody-ic@users.noreply.github.com> Date: Mon, 12 Oct 2026 03:21:30 +0800 Subject: [PATCH] =?UTF-8?q?[fpga]=20feat:=20=E6=94=AF=E6=8C=81=20Toy=20Lin?= =?UTF-8?q?ux=20Flash=20=E5=9B=BA=E5=8C=96=E4=B8=8E=E6=96=AD=E7=94=B5?= =?UTF-8?q?=E8=87=AA=E4=B8=BB=E5=90=AF=E5=8A=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- platforms/arty-a7-toy/.gitignore | 1 + platforms/arty-a7-toy/FLASH_BOOT.md | 109 + platforms/arty-a7-toy/README.md | 7 + platforms/arty-a7-toy/SOURCE_LOCK.json | 531 +- platforms/arty-a7-toy/VALIDATION.md | 21 +- platforms/arty-a7-toy/board/axi_scu.sv | 29 +- platforms/arty-a7-toy/board/backup_flash.tcl | 32 + platforms/arty-a7-toy/board/build_board.tcl | 16 +- platforms/arty-a7-toy/board/flash_boot.xdc | 19 + platforms/arty-a7-toy/board/flash_spi_byte.sv | 33 + .../arty-a7-toy/board/make_flash_image.tcl | 18 + platforms/arty-a7-toy/board/program_flash.tcl | 51 + .../arty-a7-toy/board/toy_a7_platform.sv | 15 +- platforms/arty-a7-toy/board/toy_a7_top.sv | 23 +- platforms/arty-a7-toy/boot/build.sh | 12 + platforms/arty-a7-toy/boot/flash.ld | 11 + platforms/arty-a7-toy/boot/flash_boot.c | 114 + platforms/arty-a7-toy/boot/flash_start.S | 16 + platforms/arty-a7-toy/boot/requirements.txt | 1 + .../evidence/2026-10-11/sources/README.md | 10 + .../sources/board/SOURCE_MANIFEST.json | 18 + .../2026-10-11/sources/board/arty_a7.xdc | 27 + .../2026-10-11/sources/board/axi_fullwidth.sv | 115 + .../2026-10-11/sources/board/axi_scu.sv | 88 + .../2026-10-11/sources/board/build_board.tcl | 78 + .../sources/board/ddr_uart_loader.sv | 169 + .../2026-10-11/sources/board/loader_axi.sv | 53 + .../sources/board/toy_a7_platform.sv | 445 ++ .../2026-10-11/sources/board/toy_a7_top.sv | 288 + .../2026-10-11/sources/board/uart_rx.sv | 40 + .../2026-10-11/sources/board/uart_tx.sv | 37 + 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platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_header.log create mode 100644 platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_payload.log create mode 100644 platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/valid.log create mode 100644 platforms/arty-a7-toy/host/flash.py create mode 100644 platforms/arty-a7-toy/host/observe_flash_boot.py create mode 100644 platforms/arty-a7-toy/scripts/check_flash_boot.py create mode 100644 platforms/arty-a7-toy/scripts/make_flash_image.py create mode 100644 platforms/arty-a7-toy/scripts/prepare_flash_boot.py create mode 100644 platforms/arty-a7-toy/scripts/verify_flash_evidence.py create mode 100644 platforms/arty-a7-toy/tests/spi_flash_model.sv diff --git a/platforms/arty-a7-toy/.gitignore b/platforms/arty-a7-toy/.gitignore index c600d86..08f0be8 100644 --- a/platforms/arty-a7-toy/.gitignore +++ b/platforms/arty-a7-toy/.gitignore @@ -11,3 +11,4 @@ __pycache__/ *.jou !evidence/**/*.jou toy-console.log +/dfx_runtime.txt diff --git a/platforms/arty-a7-toy/FLASH_BOOT.md b/platforms/arty-a7-toy/FLASH_BOOT.md new file mode 100644 index 0000000..066102a --- /dev/null +++ b/platforms/arty-a7-toy/FLASH_BOOT.md @@ -0,0 +1,109 @@ +# Persistent Toy/Linux boot + +This target keeps the validated CPU, Sv39, FPU, Gemmini 8x8 and original Linux +payload. A new boot ROM reads the onboard SPI Flash, bounds-checks and decompresses +an LZ4 block into DDR, checks its CRC32, and enters the original OpenSBI image. +Runtime DDR and changes to the initramfs remain volatile; the stored boot image +survives power loss. The existing UART load/RUN path remains available for recovery. + +On 2026-10-12 the connected Arty A7-100T passed Flash programming/readback +verification, autonomous Linux startup, and a physical power cycle confirmed by +the operator. Both boots passed all five Linux system checks with exit status 0. +See [the recorded implementation and hardware evidence](evidence/2026-10-12/flash/README.md). + +## Layout and switches + +The Arty A7-100T has a 16 MiB Flash. Configuration starts at `0x000000`, with a +4 MiB reserved partition; a 32-byte header and compressed software start at +`0x400000`, with 12 MiB available. The original 17,409,032-byte payload compresses +to 3,636,031 bytes with the pinned LZ4 version. Packing fails on overlap/overflow. + +- JP1/MODE: install the shorting cap for SPI power-on configuration. +- SW0=0: automatic Flash boot after DDR calibration. +- SW0=1, then BTN0: UART recovery; load a payload using `host/load.py` as before. +- PROG reloads FPGA configuration; BTN0 resets DDR/CPU and repeats software boot. + +The SPI byte engine uses 3.125 MHz mode 0 and STARTUPE2 for the dedicated CCLK pin. +The CPU reads JEDEC ID before the software header. Invalid IDs, header CRC, lengths, +LZ4 offsets or payload CRC halt in ROM and print `FAIL FLASH_BOOT`. + +## Build + +From this platform directory in the isolated Linux toolchain, first produce the +normal validated `build/serial-bound/` core and original board software. Then: + +```bash +python3 -m pip install -r boot/requirements.txt +bash boot/build.sh +python3 scripts/prepare_flash_boot.py \ + --payload build/board-software/fw_payload.bin \ + --boot-bin build/flash-boot/boot.bin +VIVADO=/path/to/vivado python3 scripts/start_board_build.py --flash +``` + +The packer replaces only `TLROM` in a separate generated file. It preserves the +original device tree at `0x11000` and verifies every byte outside that module. +The ROM is an 8 KiB synchronous BRAM with a response held under TileLink stalls. +The FPGA build keeps the one-hour timeout and rejects timing, routing, critical +CDC and DRC failures. The historical October 11 results describe the archived +pre-Flash board sources, rather than certifying this changed target. + +## Program + +Identify the actual Flash part using the board marking/JEDEC ID and a compatible +Vivado configuration-memory entry. Do not infer the Flash variant from FPGA size. +For an identified S25FL128S with the corresponding sector variant, for example: + +```bash +vivado -mode batch -source board/make_flash_image.tcl -tclargs \ + build/board-/toy_a7.bit build/flash-boot/flash_payload.bin build/toy_flash.mcs +vivado -mode batch -source board/program_flash.tcl -tclargs \ + build/toy_flash.mcs s25fl128sxxxxxx0-spi-x1_x2_x4 build/flash-backup-.bin +``` + +Programming first reads all 16 MiB into a fresh backup, then erases/programs the +image addresses and verifies Flash. It finally requests configuration from Flash +using `boot_hw_device`; it does not download the application `.bit` at that step. + +`host/flash.py` wraps both Tcl steps with a one-hour timeout, records hashes and +captures UART while programming, then runs the Linux check. Example on Windows: + +```powershell +python host/flash.py --vivado D:/Xilinx/2025.1/Vivado/bin/vivado.bat ` + --bitstream build/board-/toy_a7.bit --payload build/flash-boot/flash_payload.bin ` + --part s25fl128sxxxxxx0-spi-x1_x2_x4 --port COM5 +``` + +If the programming machine has hardware support but lacks Artix-7 build files, +create the MCS on the build machine with `scripts/make_flash_image.py` and copy +both the MCS and its `.mcs.json` sidecar. Add `--mcs build/toy_flash.mcs` to the +host command. It verifies the bitstream, software and MCS hashes against the +sidecar before programming. Keep Flash backups private and outside Git. + +## Verify + +Capture UART at 1 Mbps, 8N1. Require `PASS FLASH_PAYLOAD_CRC`, OpenSBI, the Linux +shell, and all five checks from `/root/linux_system_check-linux` with exit status +0. Finally disconnect every power source, reconnect, and repeat these checks +without running JTAG programming or `host/load.py`. A JTAG PROGRAM restart alone +does not constitute the final cold-power-cycle test. + +Arm a reconnecting UART observer before disconnecting USB and any external +power supply: + +```bash +python host/observe_flash_boot.py --port COM5 --require-disconnect \ + --transcript build/cold-boot.log --timeout 600 +``` + +USB disappearance is recorded; the person performing the test must also confirm +that all board power was removed. The observer sends only the Linux system check, +never a payload or configuration file. + +Allow roughly two minutes for the boot-ROM decompression and Linux startup on +the measured 25 MHz target. Do not interrupt Flash erase/program/verify; begin +the power-cycle test only after the programming command completes successfully. + +`scripts/check_flash_boot.py` tests the real CPU/ROM/SPI path from empty DDR with +the original CPU oracle plus two corrupted images. Its DDR/Flash models do not +validate physical Flash or the DDR PHY. Hardware results are recorded separately. diff --git a/platforms/arty-a7-toy/README.md b/platforms/arty-a7-toy/README.md index 20019ea..377e902 100644 --- a/platforms/arty-a7-toy/README.md +++ b/platforms/arty-a7-toy/README.md @@ -8,6 +8,13 @@ This remains a **Rev E engineering target**: PCB revision is unconfirmed and physical Gemmini tests are pending. See [measured results](VALIDATION.md) and [the hardware logs](evidence/2026-10-12/README.md). +For stored configuration/software and autonomous power-on startup, see +[persistent Flash boot](FLASH_BOOT.md). The separate Flash target has passed +complete FPGA implementation, Flash verification and a physical power cycle: +it boots the original Linux image and passes all five system checks without +reloading from the host. See [Flash evidence](evidence/2026-10-12/flash/README.md). +Runtime DDR and changes to the initramfs remain volatile. + ## Architecture and scope - RV64IMAFDC with Zfh/Zba/Zbb/Zbs, M/S/U, PMP, Sv39, interrupts and 8 KiB I/D diff --git a/platforms/arty-a7-toy/SOURCE_LOCK.json b/platforms/arty-a7-toy/SOURCE_LOCK.json index 13149e9..d921035 100644 --- a/platforms/arty-a7-toy/SOURCE_LOCK.json +++ b/platforms/arty-a7-toy/SOURCE_LOCK.json @@ -1,211 +1,320 @@ -{ - "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", - "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", - "files": { - ".gitattributes": "8d9ebca04236fcd49c43562b5c6ca1d88ded1ff8c8d437fbdfe3822a5ec22d74", - ".gitignore": "2c2d881b7e4f197b4b0baf1df40f9f6885dbd3f0d7d0bd83a5e8cca7c908fec9", - ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", - "README.md": "8d957c96f6212498b7cf906a264ea6af6a1198b5615f3582f701854e41b35c81", - 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"tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h": "28d76de0a7cea15ad56857dc0bf96e66931a004d43531d57415fef9180060794", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h": "884721bb02de7c8e5ad5df6ce64a55eb1877de69ce1b5b82ddeed32615f59e21", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h": "bbab5fa3af8537b10dd9102008e4fac64553a6f265837aea7fa7ffa07d941fa3", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h": "c02b851181bbba2e3c562714dade47ef9fd37d94671827df9fca2da99b429265", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h": "9e57eb61e455a3296e3177c2f56a50ee4b85467e17db925ec959e83e9d469822", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h": "3111bf7ece22ff56a2a248c802dd5dc0cc5a7cb8323a427b916c2de98b306fe6", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h": "19530b9162e59cce3deb707312c2cfe4ec885fa73b54cc79bf3e6f52d45a73e0", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h": "a5ac4c839a9ec1c33e8a34a1ebc282c6470196b8c19d91a429df3afa24f4b85e", + "tests/serial_loop_stress.c": "7058ae7627cee616c69e42ecf905d6b1a57d23ea2aa66a20a8cfe6ee41166dc7", + "tests/spi_flash_model.sv": "904377bb59c15643203b991d8414493d2f4f593285ecad63dc01628cb41f28fc", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/tb_fpu_rf.sv": "6d2e61c50907fee0125a0be9acf35ff718fb8615554e6b5f064cfe1e88beaf25", + "tests/tb_group_query.sv": "3461eda9a029ef0259daff3d5f58f43894e20893dbc489a3e64c8eda83c3f921", + "tests/tb_round_shift.sv": "d6cad7539f59f5dcb5c572cfb983828e35665586be79fea55fdb7471f895ae4f", + "tests/tb_subrob.sv": "fdaa673650870895e823491e835f351372ec18a73cdd0a188107a956c3d336a4", + "tests/ws_round_edges.c": "4ba46cd06447f1c5d8fdbebf16cc3ef4780c1b0d0b74f4d8d2dc7598410d3d10", + "tests/ws_shift_edges.c": "9a3fa9f60a25e5f1d6f5922bbe1ec97c77ce98b573a38830b8d36542e1a7fd8f" + } +} diff --git a/platforms/arty-a7-toy/VALIDATION.md b/platforms/arty-a7-toy/VALIDATION.md index d51a3da..1483076 100644 --- a/platforms/arty-a7-toy/VALIDATION.md +++ b/platforms/arty-a7-toy/VALIDATION.md @@ -79,8 +79,8 @@ the connected Arty A7-100T; the October 11 records remain unchanged. PCB revision remains unknown; this exact official E.0 MIG image works on the connected board. Physical Gemmini operator regression, FP16/FP32 exhaustive checks, full 256 MiB DDR sweep, long-duration stability and power measurements -are still pending. Programming uses volatile SRAM; no configuration flash was -written. Treat the result as successful first bring-up, not full hardware release. +are still pending. This first run used volatile SRAM and did not write Flash. +Treat the result as successful first bring-up, not full hardware release. DRC retains 360 warnings; methodology retains 49 warnings and 16 advisories, including DSP pipeline recommendations, MIG clock/reset structure, control-set @@ -94,3 +94,20 @@ The corresponding 17,409,032-byte payload SHA256 is These binaries are not stored in Git. Rebuilt software may differ by compiler and build timestamps; a new core/board toolchain requires fresh functional and implementation checks rather than inheriting these measured results. + +## Persistent Flash target: 2026-10-12 + +The [separate Flash archive](evidence/2026-10-12/flash/README.md) binds the new +implementation to its exact input sources and keeps the earlier records intact. +It adds a synchronous boot ROM and SPI reader, preserving the CPU, MMU, FPU, +Gemmini and original Linux payload. Routed use is 53,944 LUTs, 15,618 Slice sites, +35,645 FFs, 31 BRAM tiles and 117 DSPs. WNS/WHS are +1.276/+0.015 ns, routing +errors are zero and critical CDC/DRC guards pass. Only 232 Slice sites remain. + +The identified S25FL128S was fully backed up before erase/program/verify; the +16 MiB backup stays private. Vivado reconfiguration from Flash and a subsequent +operator-confirmed loss of all power both boot OpenSBI/Linux without downloading +a bitstream or software. The cold-start observer records one USB disconnect and +five Linux checks with exit status 0. Runtime DDR/initramfs changes still vanish +on reset; the stored startup image persists. Hardware Gemmini qualification and +the other acceptance limits above remain pending. diff --git a/platforms/arty-a7-toy/board/axi_scu.sv b/platforms/arty-a7-toy/board/axi_scu.sv index 3b47454..71415b1 100644 --- a/platforms/arty-a7-toy/board/axi_scu.sv +++ b/platforms/arty-a7-toy/board/axi_scu.sv @@ -1,7 +1,7 @@ // Single-hart SCU console used by the pinned Buckyball OpenSBI platform. // EXIT 0x60000000, TX 0x60020000, RX 0x60020004, STATUS 0x60020005. // Reads use AXI lane positions; RX pops only after its R response is accepted. -module axi_scu ( +module axi_scu #(parameter FLASH_BOOT=0) ( input wire clk, reset, input wire [1:0] awid, arid, input wire [30:0] awaddr, araddr, @@ -15,7 +15,10 @@ module axi_scu ( output reg bvalid, rvalid, rlast, output reg [63:0] rdata, input wire rx_valid, rx_error, input wire [7:0] rx_data, output wire tx_valid, output wire [7:0] tx_data, input wire tx_ready, - output reg exited, output reg [31:0] exit_code, output wire interrupt + output reg exited, output reg [31:0] exit_code, output wire interrupt, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, + output reg flash_cs_n ); // SBI/HVC is polled. A paste may otherwise overflow a 16-byte FIFO before // Linux's next console poll; use RAM-backed 256-byte buffering. @@ -28,9 +31,20 @@ module axi_scu ( wire pop=rvalid && rready && pop_on_read; wire push=rx_valid && (count<256 || pop); wire wr_tx=wr_addr==31'h60020000 && !bad && wstrb[0]; + wire wr_spi=FLASH_BOOT && wr_addr==31'h60020008 && !bad && wstrb[0]; + wire wr_cs=FLASH_BOOT && wr_addr==31'h6002000c && !bad && wstrb[4]; + wire spi_busy; + wire [7:0] spi_rx; + generate if(FLASH_BOOT) begin : spi_enabled + flash_spi_byte flash (.clk(clk),.reset(reset),.start(wvalid && wready && wr_spi), + .tx_data(wdata[7:0]),.miso(flash_miso),.mosi(flash_mosi),.sck(flash_sck), + .busy(spi_busy),.rx_data(spi_rx)); + end else begin + assign spi_busy=0;assign spi_rx=0;assign flash_mosi=0;assign flash_sck=0; + end endgenerate assign awready=!reset && !wa && !bvalid; assign arready=!reset && !rvalid; - assign wready=!reset && wa && (!wr_tx || tx_ready); + assign wready=!reset && wa && (!wr_tx || tx_ready) && (!(wr_spi || wr_cs) || !spi_busy); assign tx_valid=!reset && wa && wvalid && wr_tx; assign tx_data=wdata[7:0]; assign interrupt=count!=0; @@ -40,15 +54,18 @@ module axi_scu ( wa<=0;bad<=0;wr_left<=0;rd_left<=0;wr_addr<=0; bid<=0;rid<=0;bresp<=0;rresp<=0;bvalid<=0;rvalid<=0;rlast<=0;rdata<=0; exited<=0;exit_code<=0; + flash_cs_n<=1; end else begin if(bvalid && bready) bvalid<=0; if(awvalid && awready) begin wa<=1;bid<=awid;wr_addr<=awaddr;wr_left<=awlen; bad<=awlen!=0 || awsize>3 || awburst>1 || (awaddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; end else rresp<=2; diff --git a/platforms/arty-a7-toy/board/backup_flash.tcl b/platforms/arty-a7-toy/board/backup_flash.tcl new file mode 100644 index 0000000..7c44264 --- /dev/null +++ b/platforms/arty-a7-toy/board/backup_flash.tcl @@ -0,0 +1,32 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/board/build_board.tcl b/platforms/arty-a7-toy/board/build_board.tcl index b92682e..93159c2 100644 --- a/platforms/arty-a7-toy/board/build_board.tcl +++ b/platforms/arty-a7-toy/board/build_board.tcl @@ -1,6 +1,11 @@ set root [file dirname [file dirname [file normalize [info script]]]] cd $root -if {[llength $argv]!=1} {error "Usage: build_board.tcl OUTPUT_DIRECTORY"} +if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +set flash 0 +if {[llength $argv]==2} { + if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} + set flash 1 +} set out [file normalize [lindex $argv 0]] file mkdir $out file mkdir $out/ip @@ -22,12 +27,15 @@ report_ip_status -file $out/ip-status.rpt phase SYNTH_IP synth_ip [get_ips] phase SYNTH_BOARD -read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { + read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +} read_verilog -sv $root/build/serial-bound/FpgaMemories.sv foreach f [glob $root/board/*.sv] {read_verilog -sv $f} set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] read_xdc $root/board/arty_a7.xdc -synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on +read_xdc $root/board/flash_boot.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash write_checkpoint -force $out/synthesized.dcp report_utilization -file $out/synth-utilization.rpt report_utilization -hierarchical -file $out/synth-hierarchy.rpt @@ -75,4 +83,4 @@ phase BITSTREAM set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] write_bitstream -force $out/toy_a7.bit phase COMPLETE -puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; hardware revision and Linux boot unverified" +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" diff --git a/platforms/arty-a7-toy/board/flash_boot.xdc b/platforms/arty-a7-toy/board/flash_boot.xdc new file mode 100644 index 0000000..902d6a7 --- /dev/null +++ b/platforms/arty-a7-toy/board/flash_boot.xdc @@ -0,0 +1,19 @@ +# Digilent Arty-A7-100-Master.xdc Rev D/E; CCLK is owned by STARTUPE2. +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports flash_cs_n] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports flash_mosi] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports flash_miso] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports flash_wp_n] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports flash_hold_n] +set_property DRIVE 8 [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property SLEW SLOW [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set switch_sync [get_pins -quiet -hier -filter {NAME =~ *sw_meta_reg/D}] +if {[llength $switch_sync]} {set_false_path -from [get_ports sw0] -to $switch_sync} +# Serial input sampled after two synchronizer stages. Mode-0 half bit is 160 ns; +# the external data settles before these stages, then is sampled on the next rise. +set flash_sync [get_pins -quiet -hier -filter {NAME =~ *miso_meta_reg/D}] +if {[llength $flash_sync]} {set_false_path -from [get_ports flash_miso] -to $flash_sync} +set_false_path -to [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] diff --git a/platforms/arty-a7-toy/board/flash_spi_byte.sv b/platforms/arty-a7-toy/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/board/make_flash_image.tcl b/platforms/arty-a7-toy/board/make_flash_image.tcl new file mode 100644 index 0000000..ad0a6d6 --- /dev/null +++ b/platforms/arty-a7-toy/board/make_flash_image.tcl @@ -0,0 +1,18 @@ +# Combine configuration and packed software without crossing partitions. +if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +lassign $argv bitfile payload output +set bitfile [file normalize $bitfile] +set payload [file normalize $payload] +set output [file normalize $output] +if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +set f [open $payload rb] +set magic [read $f 8] +close $f +if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +file mkdir [file dirname $output] +write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ + -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +exit diff --git a/platforms/arty-a7-toy/board/program_flash.tcl b/platforms/arty-a7-toy/board/program_flash.tcl new file mode 100644 index 0000000..82a6c4f --- /dev/null +++ b/platforms/arty-a7-toy/board/program_flash.tcl @@ -0,0 +1,51 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +program_hw_cfgmem $memory +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/board/toy_a7_platform.sv b/platforms/arty-a7-toy/board/toy_a7_platform.sv index 8757e24..e26d6dc 100644 --- a/platforms/arty-a7-toy/board/toy_a7_platform.sv +++ b/platforms/arty-a7-toy/board/toy_a7_platform.sv @@ -1,5 +1,5 @@ // Generated wiring; source CPU/accelerator RTL is byte-identical. -module toy_a7_platform #(parameter UART_DIVISOR=25) ( +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( input wire clk, reset, uart_rx_in, output wire uart_tx_out, cpu_run, exited, loader_error, output wire [31:0] exit_code, @@ -31,9 +31,13 @@ module toy_a7_platform #(parameter UART_DIVISOR=25) ( input wire [1:0] ddr_rresp, input wire ddr_rlast, input wire ddr_rvalid, - output wire ddr_rready + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n ); wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); wire irq; wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; wire [7:0] rx_data, loader_tx_data, mmio_tx_data; @@ -46,7 +50,7 @@ module toy_a7_platform #(parameter UART_DIVISOR=25) ( .ready(tx_ready),.tx(uart_tx_out)); ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), - .cpu_run(cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); wire memory_aw_ready; wire memory_aw_valid; @@ -400,7 +404,7 @@ module toy_a7_platform #(parameter UART_DIVISOR=25) ( assign ddr_rready=cpu_run ? c_rready : l_rready; wire [1:0] scu_bresp; assign peripherals_b_bits_resp=|scu_bresp; - axi_scu peripherals ( + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( .clk(clk), .reset(cpu_reset), .awid(peripherals_aw_bits_id), @@ -440,6 +444,7 @@ module toy_a7_platform #(parameter UART_DIVISOR=25) ( .tx_ready(tx_ready), .exited(exited), .exit_code(exit_code), - .interrupt(irq) + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) ); endmodule diff --git a/platforms/arty-a7-toy/board/toy_a7_top.sv b/platforms/arty-a7-toy/board/toy_a7_top.sv index 4d86921..397a262 100644 --- a/platforms/arty-a7-toy/board/toy_a7_top.sv +++ b/platforms/arty-a7-toy/board/toy_a7_top.sv @@ -1,9 +1,11 @@ -module toy_a7_top ( +module toy_a7_top #(parameter FLASH_BOOT=0) ( input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, - output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n ); wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); @@ -14,6 +16,19 @@ module toy_a7_top ( BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; @@ -93,7 +108,7 @@ module toy_a7_top ( wire ui_rlast; wire ui_rvalid; wire ui_rready; - toy_a7_platform platform ( + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( .clk(clk), .reset(reset), .uart_rx_in(uart_txd_in), @@ -102,6 +117,8 @@ module toy_a7_top ( .exited(exited), .loader_error(loader_error), .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), .ddr_awid(ddr_awid), .ddr_awaddr(ddr_awaddr), .ddr_awlen(ddr_awlen), diff --git a/platforms/arty-a7-toy/boot/build.sh b/platforms/arty-a7-toy/boot/build.sh new file mode 100644 index 0000000..a0f57a6 --- /dev/null +++ b/platforms/arty-a7-toy/boot/build.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +mkdir -p build/flash-boot +cross="${CROSS_COMPILE:-riscv64-linux-gnu-}" +"${cross}gcc" -march=rv64imac_zicsr_zifencei -mabi=lp64 -mcmodel=medany \ + -Os -ffreestanding -fno-builtin -fno-pic -fno-stack-protector -msmall-data-limit=0 \ + -nostdlib -static -Wl,--build-id=none -Wl,-T,boot/flash.ld \ + boot/flash_start.S boot/flash_boot.c -o build/flash-boot/boot.elf +"${cross}objcopy" -O binary build/flash-boot/boot.elf build/flash-boot/boot.bin +"${cross}objdump" -d build/flash-boot/boot.elf > build/flash-boot/boot.dis +"${cross}size" build/flash-boot/boot.elf diff --git a/platforms/arty-a7-toy/boot/flash.ld b/platforms/arty-a7-toy/boot/flash.ld new file mode 100644 index 0000000..c8c0942 --- /dev/null +++ b/platforms/arty-a7-toy/boot/flash.ld @@ -0,0 +1,11 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS { + . = 0x10000; + .text : { *(.text.start) *(.text*) *(.rodata*) } + ASSERT(. <= 0x11000, "Flash boot code exceeds 4 KiB") + .data : { *(.data*) *(.sdata*) } + .bss : { *(.bss*) *(.sbss*) *(COMMON) } + ASSERT(SIZEOF(.data) == 0 && SIZEOF(.bss) == 0, "Boot ROM must not have writable globals") + /DISCARD/ : { *(.comment) *(.eh_frame*) *(.riscv.attributes) } +} diff --git a/platforms/arty-a7-toy/boot/flash_boot.c b/platforms/arty-a7-toy/boot/flash_boot.c new file mode 100644 index 0000000..abba384 --- /dev/null +++ b/platforms/arty-a7-toy/boot/flash_boot.c @@ -0,0 +1,114 @@ +// LZ4 block reader, bounds checks and CRC before jumping to unchanged OpenSBI. +#include +#define REG8(a) (*(volatile uint8_t *)(uintptr_t)(a)) +#define FLASH_OFFSET 0x400000u +#define FLASH_AVAILABLE 0xc00000u +#define MAX_OUTPUT 0x0f000000u // Exclude the top DDR region used for this stack. + +static void text(const char *s) { + while (*s) REG8(0x60020000) = (uint8_t)*s++; +} +static void hex(unsigned value) { + static const char digits[]="0123456789abcdef"; + REG8(0x60020000)=digits[(value >> 4) & 15]; + REG8(0x60020000)=digits[value & 15]; +} +static void fail(void) { + REG8(0x6002000c) = 1; + text("FAIL FLASH_BOOT\n"); + *(volatile uint64_t *)0x60000000 = 0xbad0f101; + for (;;) __asm__ volatile("wfi"); +} +static uint8_t spi(uint8_t value) { + REG8(0x60020008) = value; + unsigned timeout = 100000; + while (REG8(0x60020009) & 1) if (!--timeout) fail(); + return REG8(0x60020008); +} +static uint32_t crc_byte(uint32_t crc, uint8_t value) { + // Nibble lookup saves time without a 1 KiB CRC table in the boot ROM. + static const uint32_t table[16] = { + 0x00000000,0x1db71064,0x3b6e20c8,0x26d930ac, + 0x76dc4190,0x6b6b51f4,0x4db26158,0x5005713c, + 0xedb88320,0xf00f9344,0xd6d6a3e8,0xcb61b38c, + 0x9b64c2b0,0x86d3d2d4,0xa00ae278,0xbdbdf21c + }; + crc ^= value; + crc = (crc >> 4) ^ table[crc & 15]; + return (crc >> 4) ^ table[crc & 15]; +} +static uint8_t get(unsigned *remaining) { + if (!*remaining) fail(); + --*remaining; + return spi(0xff); +} +static unsigned length(unsigned initial, unsigned *remaining) { + if (initial == 15) { + unsigned more; + do { + more = get(remaining); + if (initial > MAX_OUTPUT - more) fail(); + initial += more; + } while (more == 255); + } + return initial; +} +static void launch(void) __attribute__((noreturn)); +static void launch(void) { + __asm__ volatile( + "fence rw,rw\n fence.i\n csrr a0,mhartid\n li a1,0x11000\n" + "li t0,0x1800\n csrs mstatus,t0\n li t0,0x80000000\n csrw mepc,t0\n mret\n" + ::: "a0","a1","t0","memory"); + __builtin_unreachable(); +} +void flash_main(void) { + if (!REG8(0x6002000a)) launch(); // SW0 high: original UART load/RUN recovery. + text("TOY FLASH_BOOT\n"); + // Exercise STARTUPE2 CCLK takeover with CS high before sending commands. + REG8(0x6002000c) = 1; + spi(0xff); spi(0xff); + REG8(0x6002000c) = 0; + spi(0x9f); + unsigned manufacturer = spi(0xff), type = spi(0xff), capacity = spi(0xff); + text("FLASH_ID ");hex(manufacturer);hex(type);hex(capacity);text("\n"); + REG8(0x6002000c) = 1; + if (!((manufacturer == 0x01 && type == 0x20) || + (manufacturer == 0x20 && type == 0xba)) || capacity != 0x18) fail(); + REG8(0x6002000c) = 0; + spi(0x03); spi(FLASH_OFFSET >> 16); spi(0); spi(0); + uint32_t header[8]; + uint32_t hcrc = ~0u; + for (unsigned i = 0; i < 8; ++i) { + uint32_t word = 0; + for (unsigned b = 0; b < 4; ++b) { + uint8_t v = spi(0xff); + word |= (uint32_t)v << (b * 8); + if (i < 7) hcrc = crc_byte(hcrc, v); + } + header[i] = word; + } + if (header[0] != 0x46594f54 || header[1] != 0x00345a4c || header[2] != 1 || + !header[3] || header[3] > FLASH_AVAILABLE - 32 || !header[4] || + header[4] > MAX_OUTPUT || header[6] || header[7] != ~hcrc) fail(); + unsigned remaining = header[3], produced = 0; + uint8_t *out = (uint8_t *)(uintptr_t)0x80000000; + while (remaining) { + unsigned token = get(&remaining); + unsigned count = length(token >> 4, &remaining); + if (count > remaining || count > header[4] - produced) fail(); + while (count--) out[produced++] = get(&remaining); + if (!remaining) break; + unsigned offset = get(&remaining); + offset |= (unsigned)get(&remaining) << 8; + count = length(token & 15, &remaining) + 4; + if (!offset || offset > produced || count > header[4] - produced) fail(); + while (count--) { out[produced] = out[produced - offset]; ++produced; } + } + REG8(0x6002000c) = 1; + if (produced != header[4]) fail(); + uint32_t crc = ~0u; + for (unsigned i = 0; i < produced; ++i) crc = crc_byte(crc, out[i]); + if (~crc != header[5]) fail(); + text("PASS FLASH_PAYLOAD_CRC\n"); + launch(); +} diff --git a/platforms/arty-a7-toy/boot/flash_start.S b/platforms/arty-a7-toy/boot/flash_start.S new file mode 100644 index 0000000..da83474 --- /dev/null +++ b/platforms/arty-a7-toy/boot/flash_start.S @@ -0,0 +1,16 @@ +.option norelax +.section .text.start,"ax",@progbits +.globl _start +_start: + li sp, 0x8ffff000 + la t0, trap + csrw mtvec, t0 + csrw mie, zero + li t0, 8 + csrc mstatus, t0 + call flash_main +trap: + li t0, 0x60000000 + li t1, 0xbad0f100 + sd t1, 0(t0) +1: j 1b diff --git a/platforms/arty-a7-toy/boot/requirements.txt b/platforms/arty-a7-toy/boot/requirements.txt new file mode 100644 index 0000000..7eb4011 --- /dev/null +++ b/platforms/arty-a7-toy/boot/requirements.txt @@ -0,0 +1 @@ +lz4==4.4.5 diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/README.md b/platforms/arty-a7-toy/evidence/2026-10-11/sources/README.md new file mode 100644 index 0000000..742aa6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/README.md @@ -0,0 +1,10 @@ +# Original board source snapshots + +These files were recovered byte for byte from FPGA repository commit +`6e8554193a652992a9be28c8647839807ea92284`. Their SHA256 digests match the +non-document entries of `../BOARD_RESULT.json`. + +They keep the October 11 implementation evidence bound to its original inputs +after the maintained board sources add optional Flash boot. That implementation +record and its original reports remain unchanged. New Flash implementation and +physical boot evidence are recorded separately under `../../2026-10-12/flash/`. diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/arty_a7.xdc b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/build_board.tcl b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/build_board.tcl new file mode 100644 index 0000000..b92682e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/build_board.tcl @@ -0,0 +1,78 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]!=1} {error "Usage: build_board.tcl OUTPUT_DIRECTORY"} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; hardware revision and Linux boot unverified" diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..8757e24 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_platform.sv @@ -0,0 +1,445 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready +); + wire cpu_reset=reset || !cpu_run; + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..4d86921 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/toy_a7_top.sv @@ -0,0 +1,288 @@ +module toy_a7_top ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/board.xml b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/sources/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/platforms/arty-a7-toy/evidence/2026-10-12/flash/FLASH_RESULT.json @@ -0,0 +1,28 @@ +{ + "result": "PASS_FLASH_IMPLEMENTATION_AND_PHYSICAL_COLD_BOOT", + "part": "xc7a100tcsg324-1", + "physical_board_revision": "unknown", + "original_core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "flash_core_sha256": "67817bf756167acf063e0c65dc2c259d632c4646b43792205d25661bbed7575c", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "bitstream_sha256": "78d2e703372c13c5044674c8d4eea5b775d6b12771d21df37ba0f90617723c18", + "routed_resources": { + "LUT": 53944, + "FF": 35645, + "BRAM_tiles": 31, + "DSP": 117, + "Slice": 15618 + }, + "wns_ns": 1.276, + "whs_ns": 0.015, + "routing_errors": 0, + "physical_cold_boot_tested": true, + "operator_confirmed_all_power_removed": true, + "operator_confirmation": "已拔掉全部供电并重接", + "operator_action": "Remove USB and all other power, wait at least five seconds, reconnect", + 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"2b1155d8cad3c3a00d85e676b5bb17e252592054d2e3e0ef8e396012438dd8bf", + "tests/flash-regression/RESULT.json": "0e12af653bc651607b0701a5e562aedffda0e09d06d464398dc3ffa923dc064a", + "tests/flash-regression/valid.log": "beada20d15f8c8476c9849ed4c698bce487bc983bc12991cc0d7371a36a5c054" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/README.md b/platforms/arty-a7-toy/evidence/2026-10-12/flash/README.md new file mode 100644 index 0000000..777d406 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/README.md @@ -0,0 +1,48 @@ +# Persistent Flash boot evidence + +The connected **Arty A7-100T** passed autonomous Flash boot on **2026-10-12**. +The operator then confirmed removing all power and reconnecting it. The UART +observer recorded USB loss, a fresh software CRC check, OpenSBI/Linux and five +passing system checks with process exit status 0. No application bitstream or +software was downloaded during the cold-start test. + +| Measurement | Result | +|---|---:| +| FPGA / identified Flash | XC7A100T / S25FL128S, JEDEC `012018` | +| Routed LUT / occupied Slice sites | 53,944 / 15,618 (98.54% of sites) | +| FF / BRAM tiles / DSP | 35,645 / 31 / 117 | +| WNS / WHS / routing errors | +1.276 ns / +0.015 ns / 0 | +| Implementation / timeout | 1,391.1 / 3,600 seconds | +| Flash backup | All 16,777,216 bytes; not published | +| Flash program and verification | PASS, Vivado 2025.1 | +| Software image | Original 17,409,032 bytes; LZ4 3,636,031 bytes | +| Observed cold-start/check window | 135.172 seconds including operator action | +| Cold-start Linux checks | COW, protection, FP64 context, timer, overall PASS | + +`implementation/` preserves the Vivado 2024.1 routed reports and build record. +`sources/` snapshots the actual implementation inputs, boot firmware and initial +host procedure; `software/` records ROM/core/payload/image hashes. The October 11 +records refer to their separately preserved original sources and remain unchanged. +Only `TLROM` was replaced in the generated core; CPU, MMU, FPU, Gemmini and the +Linux payload were retained. New SPI and recovery simulations are under `tests/`. + +`hardware/program.log` records the complete backup, erase/program/verify and +`boot_hw_device` request. `linux-console.log` records the first automatic boot; +`cold-boot-1.log` and its JSON record preserve the power-cycle observation. +`AUTOMATIC_BOOT_RESULT.json` records an initial monitor formatting failure: +the raw console used CRCRLF and showed all checks passing, but the monitor waited +for single-CR line endings. Only the monitors were stopped after Vivado exited. +The corrected observer, archived as `cold-observer.py`, then completed the +physical cold-start test normally. Raw logs and the interrupted monitor record +are retained; no Flash rewrite was needed. + +After this measured run, the maintained Flash XDC added quiet guards for absent +synchronizers in the non-Flash configuration. The applied Flash-mode exceptions +are unchanged; the exact built XDC remains in `sources/board/flash_boot.xdc`. + +JP1 is shorted and SW0 is 0 for autonomous boot. See +[`../../../FLASH_BOOT.md`](../../../FLASH_BOOT.md) for the repeatable build, +program and recovery commands. Bitstream/MCS/payload binaries and private Flash +backups are excluded from Git; `MANIFEST.json` hashes all public evidence. +PCB revision remains unconfirmed, physical Gemmini operator tests and extended +hardware qualification remain pending, and runtime RAM/initramfs edits are volatile. diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/AUTOMATIC_BOOT_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/AUTOMATIC_BOOT_RESULT.json new file mode 100644 index 0000000..7ca2541 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/AUTOMATIC_BOOT_RESULT.json @@ -0,0 +1,41 @@ +{ + "result": "PASS_FLASH_PROGRAM_AND_AUTOMATIC_LINUX_BOOT", + "recorded_at": "2026-10-12T03:10:52.818431+08:00", + "physical_board": "Arty A7-100T", + "physical_board_revision": "unknown", + "part": "xc7a100tcsg324-1", + "flash_part": "s25fl128sxxxxxx0-spi-x1_x2_x4", + "flash_jedec": "012018", + "flash_bytes": 16777216, + "port": "COM5", + "uart_baud": 1000000, + "bitstream_sha256": "78d2e703372c13c5044674c8d4eea5b775d6b12771d21df37ba0f90617723c18", + "packed_payload_sha256": "73507c2176800c410699407766caf95f2f5185b4f3fc8c7e74e0d496101ca494", + "flash_image_sha256": "422b45a9af8d43645063c233b737d77a8fab480b687f316e4aaa8d3aace69630", + "backup_bytes": 16777216, + "backup_sha256": "064c2e4bb290cb26d92eab770b0824bac70b867377dc51741dd5ed2634a3280a", + "backup_published": false, + "flash_program_verify": "PASS", + "configuration_from_flash": "PASS", + "payload_crc": "PASS", + "original_payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "linux_checks": { + "VM_COPY_ON_WRITE": "PASS", + "VM_PAGE_PROTECTION": "PASS", + "FP64_PROCESS_CONTEXT": "PASS", + "LINUX_TIMER": "PASS", + "LINUX_SYSTEM_CHECK": "PASS" + }, + "system_check_process_exit_status": 0, + "cold_power_cycle_tested": false, + "board_release_ready": false, + "physical_gemmini_operator_tests_run": false, + "observer_note": "Initial monitor waited despite a passing system check because Linux emitted CRCRLF. Only the UART monitors were stopped after Vivado had exited successfully. Raw logs were checked independently; observer now accepts repeated CR and a separate cold-start test follows.", + "evidence_sha256": { + "program.log": "0dd1d38183ef4c82d0c0c7eec8b16fb1913037e070fe0095fb5624b4af610306", + "program.jou": "7db8abe5e3d98d3fec16adb503f13fb2df8e29c5dfcd97c65b2173a728ec5a52", + "command-1.log": "41dce217c172b02d32aeac2a377703b11d845d570f59e6f3afbfd53b65090334", + "linux-console.log": "df9e249f7257e97089a61c8a19ac6ce1b4815777ff4c4ddfcb81a4f7c6ac874c", + "RESULT-monitor-interrupted.json": "525848d5cdfe2944c0242dc3c31853a0f37dad085159d91f07d2a751b7284095" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/RESULT-monitor-interrupted.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/RESULT-monitor-interrupted.json new file mode 100644 index 0000000..544ffd9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/RESULT-monitor-interrupted.json @@ -0,0 +1,27 @@ +{ + "status": "RUNNING", + "timeout_seconds": 3600, + "bitstream_sha256": "78d2e703372c13c5044674c8d4eea5b775d6b12771d21df37ba0f90617723c18", + "packed_payload_sha256": "73507c2176800c410699407766caf95f2f5185b4f3fc8c7e74e0d496101ca494", + "part": "s25fl128sxxxxxx0-spi-x1_x2_x4", + "port": "COM5", + "started_at": "2026-10-12T03:02:05.422494+08:00", + "commands": [ + null, + [ + "D:/Xilinx/2025.1/Vivado/bin/vivado.bat", + "-mode", + "batch", + "-source", + "D:\\Verilog_Dev\\fpga-arty-a7-pr\\platforms\\arty-a7-toy\\board\\program_flash.tcl", + "-log", + "D:\\Verilog_Dev\\fpga-arty-a7-pr\\platforms\\arty-a7-toy\\build\\flash-program-20261012\\program.log", + "-journal", + "D:\\Verilog_Dev\\fpga-arty-a7-pr\\platforms\\arty-a7-toy\\build\\flash-program-20261012\\program.jou", + "-tclargs", + "D:\\Verilog_Dev\\fpga-arty-a7-pr\\platforms\\arty-a7-toy\\build\\flash-program-20261012\\toy_flash.mcs", + "s25fl128sxxxxxx0-spi-x1_x2_x4", + "D:\\Verilog_Dev\\fpga-arty-a7-pr\\platforms\\arty-a7-toy\\build\\flash-program-20261012\\flash-before.bin" + ] + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.json new file mode 100644 index 0000000..da53763 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.json @@ -0,0 +1,17 @@ +{ + "result": "PASS_FLASH_LINUX", + "checks": [ + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK" + ], + "exit_status": 0, + "usb_disconnections": 1, + "disconnect_required": true, + "elapsed_seconds": 135.172, + "recorded_at": "2026-10-11T19:11:36.626394+00:00", + "port": "COM5", + "transcript": "platforms\\arty-a7-toy\\build\\flash-program-20261012\\cold-boot-1.log" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.log new file mode 100644 index 0000000..76c61fe --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-boot-1.log @@ -0,0 +1,167 @@ + +OBSERVER_USB_DISCONNECTED +PASS FLASH_PAYLOAD_CRC + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Sat Oct 10 16:24:07 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 241400K/262144K available (2126K kernel code, 4423K rwdata, 2048K rodata, 4385K init, 299K bss, 20744K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 4384K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # /root/linux_system_check-linux; echo FLASH_LINUX_RC:$? +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003f8df4f000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fdb0eab50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fdb0eabd0 + s1 : 0000003f8df4e000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f8df4f000 + s5 : 0000003fdb0ead88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f8df4f000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=103884000 +PASS LINUX_SYSTEM_CHECK +FLASH_LINUX_RC:0 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-observer.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-observer.py new file mode 100644 index 0000000..0d562d7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/cold-observer.py @@ -0,0 +1,163 @@ +"""Observe autonomous Flash/Linux startup, including an optional USB power cycle.""" + +import argparse +from datetime import datetime, timezone +import json +from pathlib import Path +import re +import threading +import time + +CHECKS = ( + b"PASS VM_COPY_ON_WRITE", + b"PASS VM_PAGE_PROTECTION", + b"PASS FP64_PROCESS_CONTEXT", + b"PASS LINUX_TIMER", + b"PASS LINUX_SYSTEM_CHECK", +) + + +class Observer: + def __init__(self, port, transcript, timeout=600, require_disconnect=False): + self.port = port + self.transcript = Path(transcript) + self.timeout = timeout + self.require_disconnect = require_disconnect + self.result = None + self.disconnections = 0 + self.stop = threading.Event() + self.ready = threading.Event() + self.thread = threading.Thread(target=self.run, daemon=True) + + def run(self): + import serial + + deadline = time.monotonic() + self.timeout + started = time.monotonic() + active = not self.require_disconnect + data = bytearray() + sent = False + connection = None + self.transcript.parent.mkdir(parents=True, exist_ok=True) + with self.transcript.open("wb") as log: + try: + while time.monotonic() < deadline and not self.stop.is_set(): + try: + if connection is None: + connection = serial.Serial( + self.port, + 1000000, + timeout=0.1, + write_timeout=5, + rtscts=False, + dsrdtr=False, + ) + connection.reset_input_buffer() + self.ready.set() + chunk = connection.read(max(1, connection.in_waiting)) + if not chunk: + continue + log.write(chunk) + log.flush() + if not active: + continue + data.extend(chunk) + if b"FAIL FLASH_BOOT" in data or b"Kernel panic" in data: + raise RuntimeError( + "Flash startup or Linux failed; inspect the UART log" + ) + if ( + not sent + and b"PASS FLASH_PAYLOAD_CRC" in data + and b"OpenSBI" in data + and b"~ # " in data + ): + connection.write( + b"/root/linux_system_check-linux; echo FLASH_LINUX_RC:$?\n" + ) + connection.flush() + sent = True + print("FLASH_LINUX_CHECK_SENT", flush=True) + if ( + sent + and re.search(rb"(?:^|\n)FLASH_LINUX_RC:0\r*\n", data) + and all(m in data for m in CHECKS) + ): + self.result = dict( + result="PASS_FLASH_LINUX", + checks=[m.decode() for m in CHECKS], + exit_status=0, + usb_disconnections=self.disconnections, + disconnect_required=self.require_disconnect, + elapsed_seconds=round(time.monotonic() - started, 3), + recorded_at=datetime.now(timezone.utc).isoformat(), + port=self.port, + transcript=str(self.transcript), + ) + print("PASS FLASH_LINUX_UART_CHECKS", flush=True) + break + except (serial.SerialException, OSError): + if connection is not None: + connection.close() + connection = None + self.disconnections += 1 + active = True + data.clear() + sent = False + log.write(b"\nOBSERVER_USB_DISCONNECTED\n") + log.flush() + print("OBSERVER_USB_DISCONNECTED", flush=True) + self.stop.wait(0.2) + if self.result is None: + raise TimeoutError( + "No complete autonomous Flash/Linux pass before the timeout" + ) + except Exception as error: + self.result = dict( + result="FAILED", + error=str(error), + usb_disconnections=self.disconnections, + port=self.port, + ) + finally: + if connection is not None: + connection.close() + self.transcript.with_suffix(".json").write_text( + json.dumps(self.result, indent=2) + "\n" + ) + + def start(self): + self.thread.start() + if not self.ready.wait(timeout=5): + self.stop.set() + self.thread.join(timeout=6) + raise RuntimeError(f"Could not open UART {self.port}; observer not armed") + + def finish(self): + self.thread.join() + if not self.result or self.result["result"] != "PASS_FLASH_LINUX": + raise RuntimeError(self.result) + return self.result + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--port", required=True) + p.add_argument("--transcript", type=Path, required=True) + p.add_argument("--timeout", type=int, default=600) + p.add_argument( + "--require-disconnect", + action="store_true", + help="Ignore the current session; wait for USB removal and a new boot", + ) + args = p.parse_args() + watcher = Observer( + args.port, args.transcript, args.timeout, args.require_disconnect + ) + watcher.start() + print("OBSERVER_ARMED", flush=True) + print(json.dumps(watcher.finish(), indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/command-1.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/command-1.log new file mode 100644 index 0000000..79a0ee8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/command-1.log @@ -0,0 +1,105 @@ + +****** Vivado v2025.1 (64-bit) + **** SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 + **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 + **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 + **** Start of session at: Mon Oct 12 03:02:06 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +source {D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\board\program_flash.tcl} +# if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +# lassign $argv image part backup +# set image [file normalize $image] +# set backup [file normalize $backup] +# if {![file isfile $image]} {error "Missing Flash image"} +# if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +# if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { +# error "Select the exact supported 128-Mbit Arty Flash model" +# } +# open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 494.469 ; gain = 216.141 +# connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 494.469 ; gain = 0.000 +# set targets [get_hw_targets -quiet] +# if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +# open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +# set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +# if {[llength $devices]!=1} {error "Expected one XC7A100T"} +# set device [lindex $devices 0] +# current_hw_device $device +# set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +# if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +# create_hw_cfgmem -hw_device $device [lindex $choices 0] +# set memory [get_property PROGRAM.HW_CFGMEM $device] +# create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +# program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +# file mkdir [file dirname $backup] +# readback_hw_cfgmem -all -file $backup -format bin $memory +Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0 +Performing Readback Operation... +INFO: [Xicom 50-213] Readback file: D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/flash-before.bin +Readback Operation successful. +readback_hw_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:00:43 . Memory (MB): peak = 579.055 ; gain = 24.844 +# if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +# puts "PASS FLASH_BACKUP: $backup bytes=16777216" +PASS FLASH_BACKUP: D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/flash-before.bin bytes=16777216 +# set_property PROGRAM.ADDRESS_RANGE use_file $memory +# set_property PROGRAM.FILES [list $image] $memory +# set_property PROGRAM.BLANK_CHECK 0 $memory +# set_property PROGRAM.ERASE 1 $memory +# set_property PROGRAM.CFG_PROGRAM 1 $memory +# set_property PROGRAM.VERIFY 1 $memory +# set_property PROGRAM.CHECKSUM 0 $memory +# program_hw_cfgmem $memory +Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0 +Performing Erase Operation... +Erase Operation successful. +Performing Program and Verify Operations... +Program/Verify Operation successful. +INFO: [Labtoolstcl 44-377] Flash programming completed successfully +program_hw_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:02:21 . Memory (MB): peak = 579.055 ; gain = 0.000 +# puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +PASS FLASH_PROGRAM_VERIFY: s25fl128sxxxxxx0-spi-x1_x2_x4 D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/toy_flash.mcs +# boot_hw_device -timeout 60 $device +INFO: [Labtoolstcl 44-664] Will wait up to 60 seconds for booting to complete. +INFO: [Labtools 27-32] Done pin status: HIGH +# refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || +# [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || +# [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { +# error "FPGA did not successfully reconfigure from Flash" +# } +# puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +FLASH_BOOT_CONFIG_STATUS 01010000000100000111100111111100 +# close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +# disconnect_hw_server +# close_hw_manager +# exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 03:05:34 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/linux-console.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/linux-console.log new file mode 100644 index 0000000..4e3a706 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/linux-console.log @@ -0,0 +1,168 @@ +TOY FLASH_BOOT +FLASH_ID 012018 +PASS FLASH_PAYLOAD_CRC + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Sat Oct 10 16:24:07 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 241400K/262144K available (2126K kernel code, 4423K rwdata, 2048K rodata, 4385K init, 299K bss, 20744K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 4384K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # /root/linux_system_check-linux; echo FLASH_LINUX_RC:$? +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003fb1072000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fd659cb50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fd659cbd0 + s1 : 0000003fb1071000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003fb1072000 + s5 : 0000003fd659cd88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003fb1072000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=103440000 +PASS LINUX_SYSTEM_CHECK +FLASH_LINUX_RC:0 +~ # \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.jou b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.jou new file mode 100644 index 0000000..c5b8d07 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 03:02:06 2026 +# Process ID : 49956 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\board\program_flash.tcl -log D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.log -journal D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\toy_flash.mcs s25fl128sxxxxxx0-spi-x1_x2_x4 D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\flash-before.bin +# Log file : D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 73460 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\board\program_flash.tcl} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.log new file mode 100644 index 0000000..e5a6e6f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/hardware/program.log @@ -0,0 +1,119 @@ +#----------------------------------------------------------- +# Vivado v2025.1 (64-bit) +# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 +# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 +# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 +# Start of session at: Mon Oct 12 03:02:06 2026 +# Process ID : 49956 +# Current directory : D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy +# Command line : vivado.exe -mode batch -source D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\board\program_flash.tcl -log D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.log -journal D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.jou -tclargs D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\toy_flash.mcs s25fl128sxxxxxx0-spi-x1_x2_x4 D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\flash-before.bin +# Log file : D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/program.log +# Journal file : D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\build\flash-program-20261012\program.jou +# Running On : LAPTOP-IQGP9732 +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26200 +# Processor Detail : AMD Ryzen 9 8945HX with Radeon Graphics +# CPU Frequency : 2495 MHz +# CPU Physical cores : 16 +# CPU Logical cores : 32 +# Host memory : 33605 MB +# Swap memory : 66571 MB +# Total Virtual : 100177 MB +# Available Virtual : 73460 MB +#----------------------------------------------------------- +source {D:\Verilog_Dev\fpga-arty-a7-pr\platforms\arty-a7-toy\board\program_flash.tcl} +# if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +# lassign $argv image part backup +# set image [file normalize $image] +# set backup [file normalize $backup] +# if {![file isfile $image]} {error "Missing Flash image"} +# if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +# if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { +# error "Select the exact supported 128-Mbit Arty Flash model" +# } +# open_hw_manager +open_hw_manager: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 494.469 ; gain = 216.141 +# connect_hw_server -allow_non_jtag +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2025.1 + **** Build date : May 6 2025 at 09:15:36 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2025.1.0 + ****** Build date : May 14 2025-03:15:27 + **** Build number : 2025.1.1747163727 + ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. + + + +connect_hw_server: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 494.469 ; gain = 0.000 +# set targets [get_hw_targets -quiet] +# if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +# open_hw_target [lindex $targets 0] +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +# set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +# if {[llength $devices]!=1} {error "Expected one XC7A100T"} +# set device [lindex $devices 0] +# current_hw_device $device +# set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +# if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +# create_hw_cfgmem -hw_device $device [lindex $choices 0] +# set memory [get_property PROGRAM.HW_CFGMEM $device] +# create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +# program_hw_devices $device +INFO: [Labtools 27-3164] End of startup status: HIGH +# file mkdir [file dirname $backup] +# readback_hw_cfgmem -all -file $backup -format bin $memory +Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0 +Performing Readback Operation... +INFO: [Xicom 50-213] Readback file: D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/flash-before.bin +Readback Operation successful. +readback_hw_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:00:43 . Memory (MB): peak = 579.055 ; gain = 24.844 +# if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +# puts "PASS FLASH_BACKUP: $backup bytes=16777216" +PASS FLASH_BACKUP: D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/flash-before.bin bytes=16777216 +# set_property PROGRAM.ADDRESS_RANGE use_file $memory +# set_property PROGRAM.FILES [list $image] $memory +# set_property PROGRAM.BLANK_CHECK 0 $memory +# set_property PROGRAM.ERASE 1 $memory +# set_property PROGRAM.CFG_PROGRAM 1 $memory +# set_property PROGRAM.VERIFY 1 $memory +# set_property PROGRAM.CHECKSUM 0 $memory +# program_hw_cfgmem $memory +Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0 +Performing Erase Operation... +Erase Operation successful. +Performing Program and Verify Operations... +Program/Verify Operation successful. +INFO: [Labtoolstcl 44-377] Flash programming completed successfully +program_hw_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:02:21 . Memory (MB): peak = 579.055 ; gain = 0.000 +# puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +PASS FLASH_PROGRAM_VERIFY: s25fl128sxxxxxx0-spi-x1_x2_x4 D:/Verilog_Dev/fpga-arty-a7-pr/platforms/arty-a7-toy/build/flash-program-20261012/toy_flash.mcs +# boot_hw_device -timeout 60 $device +INFO: [Labtoolstcl 44-664] Will wait up to 60 seconds for booting to complete. +INFO: [Labtools 27-32] Done pin status: HIGH +# refresh_hw_device $device +INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || +# [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || +# [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { +# error "FPGA did not successfully reconfigure from Flash" +# } +# puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +FLASH_BOOT_CONFIG_STATUS 01010000000100000111100111111100 +# close_hw_target +INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319BCC5FCA +# disconnect_hw_server +# close_hw_manager +# exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 03:05:34 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/RUN.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/RUN.json new file mode 100644 index 0000000..4c1972c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/RUN.json @@ -0,0 +1,64 @@ +{ + "status": "COMPLETED", + "timeout_seconds": 3600, + "termination_grace_seconds": 15, + "output_directory": "/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749", + "part": "xc7a100tcsg324-1", + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "board_sources": { + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/flash_boot.xdc": "f95adc514f09056bad0e67c5ddc2da65352b4c75a8224791c6903dc841820806", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "core_clock_hz": 25000000, + "uart_baud": 1000000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "physical_boot_tested": false, + "flash_boot": true, + "started_at": "2026-10-12T02:37:50.035865+08:00", + "deadline": "2026-10-12T03:37:50.035865+08:00", + "command": [ + "timeout", + "--signal=TERM", + "--kill-after=15s", + "3600s", + "/home/yys/bin/vivado", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.log", + "-journal", + "/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749", + "flash" + ], + "worker_pid": 2988382, + "timeout_process_pid": 2988391, + "exit_code": 0, + "elapsed_seconds": 1391.0816919970093, + "finished_at": "2026-10-12T03:01:01.117619+08:00", + "core_unchanged": true, + "bitstream_generated": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/bus-skew.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/bus-skew.rpt new file mode 100644 index 0000000..9630ba4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/bus-skew.rpt @@ -0,0 +1,1380 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:18 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_bus_skew -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +Table of Contents +----------------- +1. Bus Skew Report Summary +2. Bus Skew Report Per Constraint + +1. Bus Skew Report Summary +-------------------------- + +Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns) +-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- +1 33 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.621 11.379 +2 35 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.847 11.153 +3 37 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.765 11.235 +4 39 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.696 11.304 +5 41 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.970 11.030 +6 43 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.891 11.109 +7 45 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.099 10.901 +8 47 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.874 11.126 +9 49 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.860 11.140 +10 51 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.660 11.340 + + +2. Bus Skew Report Per Constraint +--------------------------------- + +Id: 1 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.621 11.379 + + +Slack (MET) : 11.379ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.831ns + Reference Relative Delay: -1.992ns + Relative CRPR: 0.541ns + Actual Bus Skew: 0.621ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.628 -0.912 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y85 FDRE (Prop_fdre_C_Q) 0.419 -0.493 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.492 -0.001 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X67Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.504 0.677 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X67Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.072 + SLICE_X67Y85 FDRE (Setup_fdre_C_D) -0.242 0.830 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival -0.001 + clock arrival 0.830 + ------------------------------------------------------------------- + relative delay -0.831 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.507 -1.513 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y85 FDRE (Prop_fdre_C_Q) 0.367 -1.146 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.375 -0.771 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X68Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.051 + SLICE_X68Y84 FDRE (Hold_fdre_C_D) 0.170 1.221 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.771 + clock arrival 1.221 + ------------------------------------------------------------------- + relative delay -1.992 + + + +Id: 2 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.847 11.153 + + +Slack (MET) : 11.153ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.624ns + Reference Relative Delay: -2.010ns + Relative CRPR: 0.540ns + Actual Bus Skew: 0.847ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.626 -0.914 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X47Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y83 FDRE (Prop_fdre_C_Q) 0.419 -0.495 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.720 0.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X46Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.503 0.676 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X46Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.071 + SLICE_X46Y83 FDRE (Setup_fdre_C_D) -0.222 0.849 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.225 + clock arrival 0.849 + ------------------------------------------------------------------- + relative delay -0.624 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.509 -1.511 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X45Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y84 FDRE (Prop_fdre_C_Q) 0.367 -1.144 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.418 -0.726 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X46Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X46Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.051 + SLICE_X46Y83 FDRE (Hold_fdre_C_D) 0.233 1.284 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.726 + clock arrival 1.284 + ------------------------------------------------------------------- + relative delay -2.010 + + + +Id: 3 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.765 11.235 + + +Slack (MET) : 11.235ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.724ns + Reference Relative Delay: 2.443ns + Relative CRPR: 0.516ns + Actual Bus Skew: 0.765ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X48Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y83 FDRE (Prop_fdre_C_Q) 0.456 1.902 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.609 2.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X43Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.508 -1.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X43Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 -1.117 + SLICE_X43Y83 FDRE (Setup_fdre_C_D) -0.095 -1.212 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 2.512 + clock arrival -1.212 + ------------------------------------------------------------------- + relative delay 3.724 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.505 0.678 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X48Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y85 FDRE (Prop_fdre_C_Q) 0.367 1.045 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.259 1.304 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X48Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.627 -0.913 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X48Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.308 + SLICE_X48Y84 FDRE (Hold_fdre_C_D) 0.169 -1.139 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.304 + clock arrival -1.139 + ------------------------------------------------------------------- + relative delay 2.443 + + + +Id: 4 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.696 11.304 + + +Slack (MET) : 11.304ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.705ns + Reference Relative Delay: -1.955ns + Relative CRPR: 0.554ns + Actual Bus Skew: 0.696ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.715 -0.825 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X86Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y108 FDRE (Prop_fdre_C_Q) 0.456 -0.369 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.735 0.366 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X86Y110 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.597 0.769 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y110 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.164 + SLICE_X86Y110 FDRE (Setup_fdre_C_D) -0.093 1.071 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.366 + clock arrival 1.071 + ------------------------------------------------------------------- + relative delay -0.705 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.595 -1.426 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X86Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y108 FDRE (Prop_fdre_C_Q) 0.367 -1.059 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.438 -0.621 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.143 + SLICE_X87Y109 FDRE (Hold_fdre_C_D) 0.192 1.335 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.621 + clock arrival 1.335 + ------------------------------------------------------------------- + relative delay -1.955 + + + +Id: 5 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.970 11.030 + + +Slack (MET) : 11.030ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 4.064ns + Reference Relative Delay: 2.564ns + Relative CRPR: 0.529ns + Actual Bus Skew: 0.970ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X88Y110 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y110 FDRE (Prop_fdre_C_Q) 0.478 2.016 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.747 2.763 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X89Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.595 -1.426 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X89Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.031 + SLICE_X89Y107 FDRE (Setup_fdre_C_D) -0.270 -1.301 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.763 + clock arrival -1.301 + ------------------------------------------------------------------- + relative delay 4.064 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.597 0.769 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X86Y110 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y110 FDRE (Prop_fdre_C_Q) 0.367 1.136 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.377 1.513 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X86Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.715 -0.825 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X86Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.220 + SLICE_X86Y108 FDRE (Hold_fdre_C_D) 0.169 -1.051 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.513 + clock arrival -1.051 + ------------------------------------------------------------------- + relative delay 2.564 + + + +Id: 6 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.891 11.109 + + +Slack (MET) : 11.109ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.853ns + Reference Relative Delay: 2.429ns + Relative CRPR: 0.533ns + Actual Bus Skew: 0.891ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X40Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y79 FDRE (Prop_fdre_C_Q) 0.456 1.902 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.738 2.641 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X40Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.508 -1.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X40Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.117 + SLICE_X40Y81 FDRE (Setup_fdre_C_D) -0.095 -1.212 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.641 + clock arrival -1.212 + ------------------------------------------------------------------- + relative delay 3.853 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.504 0.677 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X39Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y80 FDRE (Prop_fdre_C_Q) 0.367 1.044 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.247 1.291 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X40Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.627 -0.913 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X40Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.308 + SLICE_X40Y80 FDRE (Hold_fdre_C_D) 0.170 -1.138 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.291 + clock arrival -1.138 + ------------------------------------------------------------------- + relative delay 2.429 + + + +Id: 7 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 1.099 10.901 + + +Slack (MET) : 10.901ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.510ns + Reference Relative Delay: -2.107ns + Relative CRPR: 0.499ns + Actual Bus Skew: 1.099ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.628 -0.912 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X34Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X34Y80 FDRE (Prop_fdre_C_Q) 0.518 -0.394 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.888 0.494 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X28Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.507 0.680 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X28Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 1.075 + SLICE_X28Y80 FDRE (Setup_fdre_C_D) -0.071 1.004 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 0.494 + clock arrival 1.004 + ------------------------------------------------------------------- + relative delay -0.510 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.507 -1.513 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X40Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y80 FDRE (Prop_fdre_C_Q) 0.367 -1.146 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.259 -0.887 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X40Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X40Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 1.051 + SLICE_X40Y79 FDRE (Hold_fdre_C_D) 0.169 1.220 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival -0.887 + clock arrival 1.220 + ------------------------------------------------------------------- + relative delay -2.107 + + + +Id: 8 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.874 11.126 + + +Slack (MET) : 11.126ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.825ns + Reference Relative Delay: -2.167ns + Relative CRPR: 0.468ns + Actual Bus Skew: 0.874ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.616 -0.924 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X52Y82 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X52Y82 FDRE (Prop_fdre_C_Q) 0.419 -0.505 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.480 -0.024 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.503 0.676 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X48Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.071 + SLICE_X48Y83 FDRE (Setup_fdre_C_D) -0.270 0.801 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival -0.024 + clock arrival 0.801 + ------------------------------------------------------------------- + relative delay -0.825 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.496 -1.524 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X52Y82 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X52Y82 FDRE (Prop_fdre_C_Q) 0.367 -1.157 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.263 -0.894 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X54Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.615 1.437 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X54Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.042 + SLICE_X54Y83 FDRE (Hold_fdre_C_D) 0.231 1.273 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.894 + clock arrival 1.273 + ------------------------------------------------------------------- + relative delay -2.167 + + + +Id: 9 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Slow 0.860 11.140 + + +Slack (MET) : 11.140ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.755ns + Reference Relative Delay: 2.540ns + Relative CRPR: 0.355ns + Actual Bus Skew: 0.860ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.615 1.437 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X54Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y83 FDRE (Prop_fdre_C_Q) 0.518 1.955 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.577 2.533 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X52Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.498 -1.522 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X52Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 -1.127 + SLICE_X52Y84 FDRE (Setup_fdre_C_D) -0.095 -1.222 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 2.533 + clock arrival -1.222 + ------------------------------------------------------------------- + relative delay 3.755 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.503 0.676 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X49Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y83 FDRE (Prop_fdre_C_Q) 0.337 1.013 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.249 1.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X49Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.627 -0.913 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X49Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism -0.395 -1.308 + SLICE_X49Y84 FDRE (Hold_fdre_C_D) 0.029 -1.279 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 1.262 + clock arrival -1.279 + ------------------------------------------------------------------- + relative delay 2.540 + + + +Id: 10 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Slow 0.660 11.340 + + +Slack (MET) : 11.340ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.708ns + Reference Relative Delay: 2.550ns + Relative CRPR: 0.499ns + Actual Bus Skew: 0.660ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.620 1.442 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X65Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y81 FDRE (Prop_fdre_C_Q) 0.456 1.898 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.620 2.518 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X64Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.502 -1.518 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X64Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 -1.123 + SLICE_X64Y81 FDRE (Setup_fdre_C_D) -0.067 -1.190 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 2.518 + clock arrival -1.190 + ------------------------------------------------------------------- + relative delay 3.708 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.503 0.676 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y84 FDRE (Prop_fdre_C_Q) 0.337 1.013 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.259 1.272 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X68Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.628 -0.912 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y85 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism -0.395 -1.307 + SLICE_X68Y85 FDRE (Hold_fdre_C_D) 0.029 -1.278 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 1.272 + clock arrival -1.278 + ------------------------------------------------------------------- + relative delay 2.550 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/cdc.rpt new file mode 100644 index 0000000..df355d5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/cdc.rpt @@ -0,0 +1,95 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:13 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 19 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[12]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[12]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[12]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[12]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[12]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path flash_miso platform/peripherals/spi_enabled.flash/miso_meta_reg/D + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path sw0 sw_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/check-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/check-timing.rpt new file mode 100644 index 0000000..38e3689 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/check-timing.rpt @@ -0,0 +1,112 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:32 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : check_timing -verbose -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/check-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (4) +6. checking no_output_delay (8) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (4) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +flash_miso +sw0 +uart_txd_in + + +6. checking no_output_delay (8) +------------------------------- + There are 0 ports with no output delay specified. + + There are 8 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +flash_cs_n +flash_mosi +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/clocks.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/clocks.rpt new file mode 100644 index 0000000..6d9adf4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/clocks.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:30 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_clocks -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/clocks.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +board_clk 10.000 {0.000 5.000} P {CLK100MHZ} +clk_pll_i 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} +core_raw 40.000 {0.000 20.000} P,G,A {clock_mmcm/CLKOUT0} +fb 10.000 {0.000 5.000} P,G,A {clock_mmcm/CLKFBOUT} +freq_refclk 1.500 {0.000 0.750} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} +iserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} +iserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} +mem_refclk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} +oserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} +oserdes_clk_1 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} +oserdes_clk_2 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} +oserdes_clk_3 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} +oserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} +oserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} +oserdes_clkdiv_2 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} +oserdes_clkdiv_3 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} +pll_clk3_out 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} +pll_clkfbout 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} +ref_raw 5.000 {0.000 2.500} P,G,A {clock_mmcm/CLKOUT2} +sync_pulse 48.000 {1.312 4.312} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} +sys_raw 6.000 {0.000 3.000} P,G,A {clock_mmcm/CLKOUT1} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clk_pll_i +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Master Clock : pll_clk3_out +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} + +Generated Clock : core_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 15.000 30.000} +Generated Sources : {clock_mmcm/CLKOUT0} + +Generated Clock : fb +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 1 +Generated Sources : {clock_mmcm/CLKFBOUT} + +Generated Clock : freq_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} + +Generated Clock : iserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : iserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : mem_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} + +Generated Clock : oserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} + +Generated Clock : oserdes_clk_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} + +Generated Clock : oserdes_clk_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} + +Generated Clock : oserdes_clk_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} + +Generated Clock : oserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK +Master Clock : oserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK +Master Clock : oserdes_clk_1 +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK +Master Clock : oserdes_clk_2 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK +Master Clock : oserdes_clk_3 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} + +Generated Clock : pll_clk3_out +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 3.000 6.000} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} + +Generated Clock : pll_clkfbout +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} + +Generated Clock : ref_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 2 +Generated Sources : {clock_mmcm/CLKOUT2} + +Generated Clock : sync_pulse +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {1.312 1.313 43.312} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} + +Generated Clock : sys_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -2.000 -4.000} +Generated Sources : {clock_mmcm/CLKOUT1} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/console.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/console.log new file mode 100644 index 0000000..a2ee546 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/console.log @@ -0,0 +1,5785 @@ + +****** Vivado v2024.1 (64-bit) + **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Oct 12 02:37:51 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-flash-20261012/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2215.965 ; gain = 268.445 ; free physical = 159065 ; free virtual = 545223 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 2988770 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2657.594 ; gain = 423.715 ; free physical = 158406 ; free virtual = 544576 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158173 ; free virtual = 544350 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158174 ; free virtual = 544351 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158174 ; free virtual = 544351 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2910.133 ; gain = 0.000 ; free physical = 158195 ; free virtual = 544372 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.977 ; gain = 0.000 ; free physical = 158227 ; free virtual = 544420 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3019.977 ; gain = 0.000 ; free physical = 158236 ; free virtual = 544429 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3019.977 ; gain = 786.098 ; free physical = 158359 ; free virtual = 544553 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158358 ; free virtual = 544552 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158371 ; free virtual = 544565 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158430 ; free virtual = 544636 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158467 ; free virtual = 544701 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:23 ; elapsed = 00:01:23 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158489 ; free virtual = 544731 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158494 ; free virtual = 544735 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:26 ; elapsed = 00:01:26 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158503 ; free virtual = 544744 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158557 ; free virtual = 544798 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158557 ; free virtual = 544798 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158548 ; free virtual = 544790 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158560 ; free virtual = 544802 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158563 ; free virtual = 544811 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:26 ; elapsed = 00:01:27 . Memory (MB): peak = 3299.543 ; gain = 955.820 ; free physical = 158565 ; free virtual = 544813 +Synthesis Optimization Complete : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.551 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3299.551 ; gain = 0.000 ; free physical = 158858 ; free virtual = 545110 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3355.570 ; gain = 0.000 ; free physical = 158873 ; free virtual = 545127 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:35 ; elapsed = 00:01:32 . Memory (MB): peak = 3355.570 ; gain = 1127.629 ; free physical = 158881 ; free virtual = 545135 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3023.344; main = 2722.250; forked = 446.556 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4341.133; main = 3355.574; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158789 ; free virtual = 545056 +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158799 ; free virtual = 545065 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158807 ; free virtual = 545074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158881 ; free virtual = 545148 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158881 ; free virtual = 545148 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158887 ; free virtual = 545154 +Write Physdb Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158887 ; free virtual = 545154 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158552 ; free virtual = 544832 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3418.586 ; gain = 0.000 ; free physical = 158542 ; free virtual = 544829 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3469.398 ; gain = 0.000 ; free physical = 158530 ; free virtual = 544817 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3469.398 ; gain = 0.000 ; free physical = 158530 ; free virtual = 544817 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158544 ; free virtual = 544831 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158544 ; free virtual = 544831 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544821 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158518 ; free virtual = 544807 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158409 ; free virtual = 544698 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158464 ; free virtual = 544753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158467 ; free virtual = 544756 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158469 ; free virtual = 544758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 15.000 ; free physical = 158535 ; free virtual = 544824 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.406 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544824 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3469.406 ; gain = 0.000 ; free physical = 158843 ; free virtual = 545132 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3469.406 ; gain = 0.000 ; free physical = 158854 ; free virtual = 545148 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3469.406 ; gain = 65.820 ; free physical = 158842 ; free virtual = 545136 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3078.561; main = 2773.062; forked = 447.628 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4511.992; main = 3469.402; forked = 1042.590 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3477.402 ; gain = 0.000 ; free physical = 158855 ; free virtual = 545149 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:09 ; elapsed = 00:02:05 . Memory (MB): peak = 3477.402 ; gain = 1261.438 ; free physical = 158843 ; free virtual = 545138 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3078.561; main = 2773.062; forked = 447.628 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4511.992; main = 3477.406; forked = 1042.590 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3477.523 ; gain = 0.000 ; free physical = 158499 ; free virtual = 544802 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 1 - type: integer +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:22] +INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137432] +INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137432] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 1 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103277] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:102029] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103736] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103736] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24349] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26100] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:27453] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68579] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68593] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68607] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:82862] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:82061] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:86947] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85200] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85208] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90518] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90550] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90582] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90614] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90646] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90678] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90710] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:98905] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:98927] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99546] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99552] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99558] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:100285] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:101280] +INFO: [Synth 8-3876] $readmem data file 'build/flash-boot/bootrom.hex' is read successfully [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:101970] + Parameter FLASH_BOOT bound to: 1 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76889] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76891] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76893] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76896] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76899] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76903] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76907] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76929] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76945] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76965] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77001] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77003] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77006] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77010] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77015] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77021] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77031] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77034] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77043] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77049] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76894] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76897] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76900] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76901] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76904] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76905] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76908] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76909] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76910] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76913] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76915] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76918] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76921] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76925] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76934] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76939] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76948] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:93717] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[7] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[6] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[5] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[4] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[3] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_corrupt in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[27] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[26] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[25] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[24] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[23] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[22] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[21] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[20] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[19] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[18] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[17] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3815.395 ; gain = 337.871 ; free physical = 158042 ; free virtual = 544370 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3830.238 ; gain = 352.715 ; free physical = 158048 ; free virtual = 544376 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3830.238 ; gain = 352.715 ; free physical = 158048 ; free virtual = 544376 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3833.379 ; gain = 0.000 ; free physical = 158097 ; free virtual = 544427 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4006.004 ; gain = 0.000 ; free physical = 157973 ; free virtual = 544304 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:84800] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:84798] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:86183] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_AC80CBA0 | 00 | 00 + P_AC57AB10 | 01 | 01 + P_AC775860 | 10 | 10 + P_AC7AE9F0 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:47 ; elapsed = 00:00:43 . Memory (MB): peak = 4009.922 ; gain = 532.398 ; free physical = 152969 ; free virtual = 539323 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 66 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 71 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 8 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 185 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 437 + 7 Bit Registers := 28 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 235 + 2 Bit Registers := 129 + 1 Bit Registers := 1669 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 ++---ROMs : + ROMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 307 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 371 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 197 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 258 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1291 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/serial-bound/FpgaMemories.sv:86] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79405] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79488] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79553] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79582] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79604] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79650] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79650] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79654] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79658] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79658] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79753] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79757] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85990] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\rowDelta_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\split_addr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memLoader/\pixel_bytes_reg_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (configer/\zeroLines/rowCount_reg[31] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/\reqReg_len_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_13/\bytesRequested_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_13/\bytesRequested_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\dma_addr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/\reqReg_pixel_bytes_reg[1] ) +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (writer/\reqReg_vaddr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\split_mask_reg[7] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__52 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:11:58 ; elapsed = 00:12:33 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157194 ; free virtual = 544592 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:04 ; elapsed = 00:12:39 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157162 ; free virtual = 544577 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------+-------------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------+-------------------+---------------+----------------+ +|TLROM | response_data_reg | 1024x64 | Block RAM | ++------------+-------------------+---------------+----------------+ + + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:11 ; elapsed = 00:12:46 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157314 ; free virtual = 544833 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:23 ; elapsed = 00:12:59 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157347 ; free virtual = 544869 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance systemi_20/bootrom_domain/bootrom/response_data_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance systemi_20/bootrom_domain/bootrom/response_data_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:42 ; elapsed = 00:13:17 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157468 ; free virtual = 545009 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/bootrom_domain/bootrom/response_data_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/bootrom_domain/bootrom/response_data_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:51 ; elapsed = 00:13:27 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157323 ; free virtual = 544946 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:51 ; elapsed = 00:13:27 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157322 ; free virtual = 544945 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157364 ; free virtual = 545006 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157364 ; free virtual = 545006 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157402 ; free virtual = 545044 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157410 ; free virtual = 545052 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4331| +|20 |LUT3 | 12207| +|21 |LUT4 | 10233| +|22 |LUT5 | 12403| +|23 |LUT6 | 18384| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 853| +|26 |MUXF8 | 221| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|39 |SRL16E | 225| +|40 |STARTUPE2 | 1| +|41 |FDCE | 8| +|42 |FDPE | 6| +|43 |FDRE | 29882| +|44 |FDSE | 459| +|45 |IBUF | 5| +|46 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157411 ; free virtual = 545053 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 512 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:53 ; elapsed = 00:13:34 . Memory (MB): peak = 6506.789 ; gain = 2849.582 ; free physical = 165324 ; free virtual = 552968 +Synthesis Optimization Complete : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 165344 ; free virtual = 552970 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165198 ; free virtual = 552965 +INFO: [Netlist 29-17] Analyzing 4423 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165045 ; free virtual = 552819 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165176 ; free virtual = 552950 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: e3d50df3 +INFO: [Common 17-83] Releasing license: Synthesis +612 Infos, 465 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:43 ; elapsed = 00:14:08 . Memory (MB): peak = 6506.789 ; gain = 3029.387 ; free physical = 165201 ; free virtual = 552975 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13724.044; main = 5807.853; forked = 8285.465 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19165.703; main = 6502.875; forked = 12662.832 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165216 ; free virtual = 552990 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165216 ; free virtual = 552990 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552991 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552991 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552992 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552992 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165210 ; free virtual = 552992 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 6526.879 ; gain = 20.090 ; free physical = 165012 ; free virtual = 552852 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 164960 ; free virtual = 552823 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6558.895 ; gain = 32.016 ; free physical = 164976 ; free virtual = 552841 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 +Phase 1 Initialization | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164973 ; free virtual = 552838 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164974 ; free virtual = 552839 +Phase 2 Timer Update And Timing Data Collection | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164974 ; free virtual = 552839 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2872 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 24d1b8c2b + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164995 ; free virtual = 552860 +Retarget | Checksum: 24d1b8c2b +INFO: [Opt 31-389] Phase Retarget created 95 cells and removed 601 cells +INFO: [Opt 31-1021] In phase Retarget, 54 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 1f9f2fa4a + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164999 ; free virtual = 552864 +Constant propagation | Checksum: 1f9f2fa4a +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 250c9c5d5 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165004 ; free virtual = 552869 +Sweep | Checksum: 250c9c5d5 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 330 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 1e2673890 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165012 ; free virtual = 552877 +BUFG optimization | Checksum: 1e2673890 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 1e2673890 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165011 ; free virtual = 552877 +Shift Register Optimization | Checksum: 1e2673890 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 103 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'flash_spi_byte'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_4x144_444'. +INFO: [Opt 31-75] Optimized module 'ram_4x281'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2240 inverters resulting in an inversion of 7773 pins +INFO: [Opt 31-138] Pushed 3 inverter(s) to 15 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 1c4622320 + +Time (s): cpu = 00:02:37 ; elapsed = 00:00:51 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 160966 ; free virtual = 548879 +Resynthesis | Checksum: 1c4622320 +INFO: [Opt 31-389] Phase Resynthesis created 18779 cells and removed 19516 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 1c4622320 + +Time (s): cpu = 00:02:37 ; elapsed = 00:00:51 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161043 ; free virtual = 548956 +Post Processing Netlist | Checksum: 1c4622320 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549075 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Phase 10 Finalization | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 95 | 601 | 54 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 330 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 18779 | 19516 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161228 ; free virtual = 549141 +Ending Netlist Obfuscation Task | Checksum: 1abb29775 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161228 ; free virtual = 549141 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:42 ; elapsed = 00:00:55 . Memory (MB): peak = 6558.895 ; gain = 32.016 ; free physical = 161228 ; free virtual = 549141 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549494 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549494 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161579 ; free virtual = 549504 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162747 ; free virtual = 550731 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1832c48e9 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e8838b6d + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 163162 ; free virtual = 551152 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163785 ; free virtual = 551794 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163795 ; free virtual = 551804 +Phase 1 Placer Initialization | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163814 ; free virtual = 551824 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 27b0407fd + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163965 ; free virtual = 551975 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2b26fc456 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 164112 ; free virtual = 552122 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2b26fc456 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 164113 ; free virtual = 552123 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 20cd516cb + +Time (s): cpu = 00:02:09 ; elapsed = 00:00:49 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154547 ; free virtual = 542720 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5057 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2158 nets or LUTs. Breaked 0 LUT, combined 2158 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 152603 ; free virtual = 542226 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2158 | 2158 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2158 | 2158 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 18eedb8ce + +Time (s): cpu = 00:02:20 ; elapsed = 00:00:55 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157047 ; free virtual = 542659 +Phase 2.4 Global Placement Core | Checksum: 24da91504 + +Time (s): cpu = 00:02:32 ; elapsed = 00:01:00 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157304 ; free virtual = 543107 +Phase 2 Global Placement | Checksum: 24da91504 + +Time (s): cpu = 00:02:33 ; elapsed = 00:01:00 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157247 ; free virtual = 543052 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 266f7d8f9 + +Time (s): cpu = 00:02:39 ; elapsed = 00:01:02 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 155839 ; free virtual = 541724 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a987373e + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153064 ; free virtual = 539052 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 14bd8cc79 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 152816 ; free virtual = 538813 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2282967f1 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 152734 ; free virtual = 538734 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2627c387e + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 146358 ; free virtual = 532915 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1c8d0f247 + +Time (s): cpu = 00:03:19 ; elapsed = 00:01:32 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154365 ; free virtual = 541003 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1f25e9ec5 + +Time (s): cpu = 00:03:19 ; elapsed = 00:01:33 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 156570 ; free virtual = 543229 +Phase 3 Detail Placement | Checksum: 1f25e9ec5 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:33 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 156341 ; free virtual = 543019 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 177f09b53 + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: b22e272a + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 155158 ; free virtual = 542278 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 11b632fca + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 154882 ; free virtual = 542046 +Phase 4.1.1.1 BUFG Insertion | Checksum: 177f09b53 + +Time (s): cpu = 00:03:50 ; elapsed = 00:01:44 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154664 ; free virtual = 541848 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1bd122984 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154474 ; free virtual = 541687 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154474 ; free virtual = 541687 +Phase 4.1 Post Commit Optimization | Checksum: 1bd122984 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154267 ; free virtual = 541498 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1bd122984 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154101 ; free virtual = 541356 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 4x4| 8x8| +|___________|___________________|___________________| +| South| 1x1| 4x4| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 2x2| 4x4| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1bd122984 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153908 ; free virtual = 541183 +Phase 4.3 Placer Reporting | Checksum: 1bd122984 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153827 ; free virtual = 541119 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 153825 ; free virtual = 541119 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153825 ; free virtual = 541119 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2549690c6 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153598 ; free virtual = 540910 +Ending Placer Task | Checksum: 18a614880 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:47 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153475 ; free virtual = 540803 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:03:59 ; elapsed = 00:01:49 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153473 ; free virtual = 540804 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.13 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 153328 ; free virtual = 540687 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149999 ; free virtual = 540240 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149999 ; free virtual = 540240 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149991 ; free virtual = 540232 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149941 ; free virtual = 540193 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149941 ; free virtual = 540193 +Write Physdb Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149924 ; free virtual = 540177 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 148331 ; free virtual = 538752 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:05 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 147231 ; free virtual = 537802 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 147233 ; free virtual = 537804 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: 3c76631f ConstDB: 0 ShapeSum: 9c1885cb RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 698097df | NumContArr: c52f5a13 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2b401e72c + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145822 ; free virtual = 536886 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2b401e72c + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145703 ; free virtual = 536783 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2b401e72c + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145678 ; free virtual = 536759 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 1f3dd5fe7 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:23 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 143307 ; free virtual = 534570 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.345 | THS=-659.163| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24899599d + +Time (s): cpu = 00:01:20 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142060 ; free virtual = 533390 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.298 | THS=-55.710| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 17add0eed + +Time (s): cpu = 00:01:21 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142056 ; free virtual = 533389 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 94828 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 94827 + Number of Partially Routed Nets = 1 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 1bddbf3bb + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142034 ; free virtual = 533368 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 1bddbf3bb + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142034 ; free virtual = 533368 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 1ba297ad2 + +Time (s): cpu = 00:01:37 ; elapsed = 00:00:33 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142178 ; free virtual = 533521 +Phase 4 Initial Routing | Checksum: 1ba297ad2 + +Time (s): cpu = 00:01:37 ; elapsed = 00:00:33 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142178 ; free virtual = 533522 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14987 + Number of Nodes with overlaps = 1443 + Number of Nodes with overlaps = 384 + Number of Nodes with overlaps = 139 + Number of Nodes with overlaps = 53 + Number of Nodes with overlaps = 15 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 32748357f + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:11 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161414 ; free virtual = 552787 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 17093f564 + +Time (s): cpu = 00:03:02 ; elapsed = 00:01:17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 +Phase 5 Rip-up And Reroute | Checksum: 17093f564 + +Time (s): cpu = 00:03:02 ; elapsed = 00:01:17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp +Phase 6.1 Delay CleanUp | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 +Phase 6 Delay and Skew Optimization | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.014 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:12 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161594 ; free virtual = 552982 +Phase 7 Post Hold Fix | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:13 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161594 ; free virtual = 552981 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 22.2778 % + Global Horizontal Routing Utilization = 27.5909 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:14 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161601 ; free virtual = 552988 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:14 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161612 ; free virtual = 552999 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 18b572001 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:24 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161772 ; free virtual = 553162 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 18b572001 + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:24 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161781 ; free virtual = 553171 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.015 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: eb1d40e0 + +Time (s): cpu = 00:03:48 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161811 ; free virtual = 553205 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 89.93 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: 123b2a607 + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161823 ; free virtual = 553217 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: 123b2a607 + +Time (s): cpu = 00:03:50 ; elapsed = 00:01:31 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161997 ; free virtual = 553392 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:03:56 ; elapsed = 00:01:34 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161931 ; free virtual = 553330 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161976 ; free virtual = 553394 +Wrote PlaceDB: Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553484 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553484 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553499 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162056 ; free virtual = 553543 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:06 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162101 ; free virtual = 553596 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162074 ; free virtual = 553579 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.25 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162059 ; free virtual = 553564 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7173120 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162196 ; free virtual = 553763 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=1; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 03:01:00 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/drc.rpt new file mode 100644 index 0000000..1313cbf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:12 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/io.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/io.rpt new file mode 100644 index 0000000..121f613 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/io.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:28 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_io -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/io.rpt +| Design : toy_a7_top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2012-07-17 +| Package Pin Delay Version : VERS. 2.0 2012-07-17 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 62 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | sw0 | High Range | IO_L12N_T1_MRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A9 | uart_txd_in | High Range | IO_L14N_T2_SRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | btn0 | High Range | IO_L6N_T0_VREF_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| D10 | uart_rxd_out | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | CLK100MHZ | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | led[0] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | led[1] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | ddr3_dq[2] | High Range | IO_L2P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| K5 | ddr3_dq[0] | High Range | IO_L5P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K6 | ddr3_reset_n | High Range | IO_0_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | flash_mosi | High Range | IO_L1P_T0_D00_MOSI_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| K18 | flash_miso | High Range | IO_L1N_T0_D01_DIN_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| L1 | ddr3_dm[0] | High Range | IO_L1P_T0_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | ddr3_dq[1] | High Range | IO_L2N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L4 | ddr3_dq[6] | High Range | IO_L5N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | ddr3_dq[3] | High Range | IO_L6P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | flash_cs_n | High Range | IO_L6P_T0_FCS_B_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L14 | flash_wp_n | High Range | IO_L2P_T0_D02_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | ddr3_dq[5] | High Range | IO_L1N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M2 | ddr3_dq[7] | High Range | IO_L4N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M3 | ddr3_dq[4] | High Range | IO_L4P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M4 | ddr3_cas_n | High Range | IO_L16P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | ddr3_addr[1] | High Range | IO_L18P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | flash_hold_n | High Range | IO_L2N_T0_D03_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | ddr3_dqs_n[0] | High Range | IO_L3N_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | ddr3_dqs_p[0] | High Range | IO_L3P_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| N4 | ddr3_addr[2] | High Range | IO_L16N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | ddr3_cke[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | ddr3_addr[4] | High Range | IO_L18N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | ddr3_ba[2] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P3 | ddr3_ras_n | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | ddr3_ba[1] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | ddr3_we_n | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | ddr3_ba[0] | High Range | IO_L17P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | ddr3_addr[0] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | ddr3_dq[15] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | ddr3_odt[0] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | ddr3_addr[10] | High Range | IO_L19P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | ddr3_addr[5] | High Range | IO_L23P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R8 | ddr3_addr[8] | High Range | IO_L24P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | ddr3_addr[3] | High Range | IO_L17N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| T3 | ddr3_dq[13] | High Range | IO_L11N_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | ddr3_dq[9] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T6 | ddr3_addr[12] | High Range | IO_L23N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | ddr3_addr[13] | High Range | IO_L24N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T9 | led[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T10 | led[3] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | ddr3_dm[1] | High Range | IO_L7P_T1_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U2 | ddr3_dqs_p[1] | High Range | IO_L9P_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | ddr3_dq[14] | High Range | IO_L8N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U4 | ddr3_dq[10] | High Range | IO_L8P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| U6 | ddr3_addr[11] | High Range | IO_L22N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U7 | ddr3_addr[7] | High Range | IO_L22P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | ddr3_cs_n[0] | High Range | IO_25_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | ddr3_ck_p[0] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | ddr3_dq[12] | High Range | IO_L7N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V2 | ddr3_dqs_n[1] | High Range | IO_L9N_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | ddr3_dq[8] | High Range | IO_L10N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V5 | ddr3_dq[11] | High Range | IO_L10P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V6 | ddr3_addr[6] | High Range | IO_L20N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V7 | ddr3_addr[9] | High Range | IO_L20P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| V9 | ddr3_ck_n[0] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/methodology.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/methodology.rpt new file mode 100644 index 0000000..a578e4e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/methodology.rpt @@ -0,0 +1,401 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:28 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_methodology -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/methodology.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 67 ++-----------+----------+-----------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 2 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 16 | +| SYNTH-9 | Warning | Small multiplier | 5 | +| SYNTH-10 | Warning | Wide multiplier | 21 | +| SYNTH-16 | Warning | Address collision | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +| XDCB-5 | Warning | Runtime inefficient way to find pin objects | 4 | +| REQP-1959 | Advisory | connects_SERDES_RST_driver_not_FF | 16 | ++-----------+----------+-----------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__7/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__9/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[0]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[10]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[11]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[1]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[3]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[4]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[5]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[6]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[7]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[8]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell platform/loader/in_pipe_v_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR, +platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR, +platform/chip/system/ibus_intsource/reg_0__0/reg_0_reg/CLR, +platform/chip/system/plic_domain/intsource/reg_0/reg_0_reg/CLR +platform/chip/system/plic_domain/intsource_1/reg_0/reg_0_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#9 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#10 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#11 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#12 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#13 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#14 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#15 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#16 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-9#1 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[11]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#2 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[15]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#3 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[19]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#4 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[3]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#5 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[7]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__0 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#5 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#6 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__2 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#7 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#8 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__4 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#9 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#10 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__6 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#11 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#12 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#13 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__9 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#14 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#15 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#16 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__1 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#17 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__2 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#18 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#19 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__4 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#20 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#21 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +ULMTCS-1#1 Warning +Control Sets use limits recommend reduction +This design uses 1263 control sets (vs. available limit of 15850, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. +Related violations: + +XDCB-5#1 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *miso_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '18' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc (Line: 13) +Related violations: + +XDCB-5#2 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '12' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc (Line: 18) +Related violations: + +XDCB-5#3 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *sw_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '17' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc (Line: 10) +Related violations: + +XDCB-5#4 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '6' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc (Line: 356) +Related violations: + +REQP-1959#1 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#2 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#3 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#4 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#5 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#6 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#7 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#8 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#9 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#10 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#11 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#12 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#13 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#14 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#15 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#16 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/route-status.rpt new file mode 100644 index 0000000..b2770c2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 121402 : + # of nets not needing routing.......... : 26541 : + # of internally routed nets........ : 24420 : + # of nets with no loads............ : 2121 : + # of routable nets..................... : 94861 : + # of fully routed nets............. : 94861 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-hierarchy.rpt new file mode 100644 index 0000000..cad49d0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-hierarchy.rpt @@ -0,0 +1,1150 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:00 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/routed-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 53944 | 50022 | 3644 | 278 | 35645 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 7 | 7 | 0 | 0 | 66 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 4576 | 3972 | 450 | 154 | 4081 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4360 | 3972 | 234 | 154 | 4081 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 38 | 38 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 6 | 6 | 0 | 0 | 32 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 1 | 1 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4317 | 3929 | 234 | 154 | 3912 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3348 | 3293 | 38 | 17 | 2828 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 2743 | 2697 | 30 | 16 | 2301 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2244 | 2230 | 0 | 14 | 1980 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 97 | 96 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 528 | 528 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 257 | 257 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 146 | 145 | 0 | 1 | 91 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 265 | 264 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 797 | 793 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 159 | 153 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 498 | 466 | 30 | 2 | 321 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 498 | 466 | 30 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 498 | 466 | 30 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 6 | 5 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 52 | 22 | 30 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 51 | 21 | 30 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 24 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 15 | 15 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 211 | 211 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 182 | 182 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 206 | 205 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 183 | 183 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 608 | 599 | 8 | 1 | 527 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 6 | 6 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 495 | 495 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 195 | 195 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 195 | 195 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 71 | 71 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 69 | 69 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 71 | 71 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 26 | 18 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 81 | 80 | 0 | 1 | 66 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 10 | 9 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 71 | 71 | 0 | 0 | 53 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 59 | 59 | 0 | 0 | 47 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 599 | 462 | 0 | 137 | 532 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 122 | 122 | 0 | 0 | 87 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 43 | 43 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 35 | 35 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 125 | 125 | 0 | 0 | 85 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 43 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 47 | 47 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 39 | 39 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 11 | 7 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 391 | 195 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 118 | 26 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 235 | 131 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 456 | 194 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 456 | 194 | 262 | 0 | 1212 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 455 | 193 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 455 | 193 | 262 | 0 | 1212 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 72 | 38 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 72 | 38 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 130 | 38 | 92 | 0 | 368 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 130 | 38 | 92 | 0 | 368 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 137 | 39 | 98 | 0 | 386 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 137 | 39 | 98 | 0 | 386 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 288 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 144 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 43 | 39 | 4 | 0 | 110 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 43 | 39 | 4 | 0 | 110 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 48909 | 45853 | 2932 | 124 | 30286 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 47910 | 44966 | 2820 | 124 | 29200 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 47910 | 44966 | 2820 | 124 | 29200 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 5 | 5 | 0 | 0 | 9 | 2 | 0 | 0 | +| bootrom | TLROM | 5 | 5 | 0 | 0 | 9 | 2 | 0 | 0 | +| cbus | PeripheryBus_cbus | 927 | 773 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 377 | 377 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 272 | 142 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 112 | 58 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 160 | 84 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 159 | 83 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 18 | 18 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 18 | 18 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 15 | 15 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 54 | 54 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 54 | 54 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 53 | 53 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 29 | 29 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 29 | 29 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 8 | 8 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 102 | 102 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 81 | 57 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 44 | 20 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 30 | 18 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 26 | 14 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 14 | 2 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 12 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 37 | 37 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 8 | 8 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 96 | 96 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 96 | 96 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 540 | 348 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 540 | 348 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 16 | 16 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 380 | 284 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 360 | 264 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 99 | 99 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 261 | 165 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 147 | 51 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 115 | 19 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 293 | 293 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 207 | 207 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 30 | 30 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 30 | 30 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 25 | 25 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1381 | 1047 | 334 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 753 | 419 | 334 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 217 | 79 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 73 | 41 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 68 | 36 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 46 | 14 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 40 | 8 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 276 | 116 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 77 | 41 | 36 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 11 | 5 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 9 | 3 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 86 | 86 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 31 | 31 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 488 | 488 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 44216 | 42209 | 1884 | 123 | 27556 | 25 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1207 | 623 | 584 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 100 | 4 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 158 | 62 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 156 | 60 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 644 | 518 | 126 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 641 | 515 | 126 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 127 | 15 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 43012 | 41589 | 1300 | 123 | 27535 | 25 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 23115 | 22482 | 510 | 123 | 16689 | 16 | 0 | 95 | +| ballDomain | BallDomain | 13140 | 12827 | 190 | 123 | 10877 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 141 | 45 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 12997 | 12780 | 94 | 123 | 10872 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 12997 | 12780 | 94 | 123 | 10862 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 476 | 476 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 33 | 33 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 445 | 445 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 11893 | 11676 | 94 | 123 | 9715 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1309 | 1309 | 0 | 0 | 2442 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 10208 | 10079 | 6 | 123 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 529 | 406 | 0 | 123 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9035 | 9035 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 95 | 95 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 106 | 106 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 30 | 24 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 25 | 19 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 511 | 511 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 305 | 261 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 83 | 39 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 627 | 627 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 32 | 16 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 26 | 10 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 34 | 18 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 29 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5609 | 5413 | 196 | 0 | 3863 | 0 | 0 | 0 | +| boot | BootRom | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5600 | 5404 | 196 | 0 | 3856 | 0 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 5076 | 5076 | 0 | 0 | 3325 | 0 | 0 | 0 | +| (rob) | GlobalROB | 3779 | 3779 | 0 | 0 | 3133 | 0 | 0 | 0 | +| bat | BankAliasTable | 875 | 875 | 0 | 0 | 176 | 0 | 0 | 0 | +| scoreboard | BankScoreboard | 433 | 433 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 492 | 300 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 299 | 299 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 194 | 2 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 194 | 2 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4305 | 4213 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2150 | 2150 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2150 | 2150 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 201 | 201 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 285 | 285 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 265 | 265 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 282 | 282 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 324 | 324 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 508 | 508 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 228 | 228 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2119 | 2027 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 573 | 573 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 133 | 133 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 95 | 95 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 8 | 8 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 379 | 379 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 544 | 544 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 142 | 142 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 142 | 142 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 38 | 38 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 127 | 49 | 78 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 93 | 41 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 34 | 8 | 26 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 31 | 5 | 26 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 111 | 41 | 70 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 107 | 37 | 70 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 104 | 34 | 70 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 237 | 105 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 56 | 4 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 53 | 1 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 181 | 101 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 180 | 100 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 5874 | 5786 | 88 | 0 | 1895 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2299 | 2299 | 0 | 0 | 753 | 0 | 0 | 0 | +| csr | CSRFile | 1828 | 1828 | 0 | 0 | 869 | 0 | 0 | 0 | +| div | MulDiv | 1532 | 1532 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 2958 | 2866 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 513 | 513 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 192 | 192 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1148 | 1148 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 633 | 633 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 262 | 262 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 296 | 296 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 116 | 116 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 72 | 72 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 109 | 109 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 78 | 78 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 78 | 78 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 260 | 260 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 7779 | 7515 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 26 | 26 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 315 | 315 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 311 | 311 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 311 | 311 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 842 | 842 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 833 | 833 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 833 | 833 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1019 | 1019 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 969 | 969 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 417 | 417 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 82 | 82 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 124 | 124 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 124 | 124 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1516 | 1516 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 776 | 776 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 750 | 750 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 343 | 343 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 316 | 316 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 342 | 342 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 301 | 301 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1065 | 801 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2440 | 2440 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 14 | 14 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2426 | 2426 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2037 | 1995 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 743 | 743 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 544 | 502 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 264 | 264 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 751 | 751 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 676 | 676 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 42 | 42 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 78 | 78 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 77 | 77 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 61 | 61 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 440 | 376 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 334 | 334 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 144 | 96 | 48 | 0 | 196 | 0 | 0 | 0 | +| (peripherals) | axi_scu | 108 | 60 | 48 | 0 | 163 | 0 | 0 | 0 | +| spi_enabled.flash | flash_spi_byte | 37 | 37 | 0 | 0 | 33 | 0 | 0 | 0 | +| receiver | uart_rx | 37 | 37 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-timing.rpt new file mode 100644 index 0000000..6fe3c8c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-timing.rpt @@ -0,0 +1,6694 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 03:00:07 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (4) +6. checking no_output_delay (8) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (4) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +flash_miso +sw0 +uart_txd_in + + +6. checking no_output_delay (8) +------------------------------- + There are 0 ports with no output delay specified. + + There are 8 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +flash_cs_n +flash_mosi +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 112551 0.015 0.000 0 112509 0.187 0.000 0 43438 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 7.537 0.000 0 97155 0.015 0.000 0 97155 18.750 0.000 0 37201 + fb 7.845 0.000 0 3 + ref_raw 1.909 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.811 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.957 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.564 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 3.155 0.000 0 14674 0.018 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.505 0.000 0 20 +clk_pll_i ref_raw 15.991 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 10.471 0.000 0 8 45.025 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 8.779 0.000 0 8 45.721 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.078 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.523 0.000 0 20 +ref_raw clk_pll_i 16.220 0.000 0 12 0.116 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.969 0.000 0 111 0.320 0.000 0 111 +**async_default** core_raw core_raw 27.439 0.000 0 116 0.167 0.000 0 116 +**default** clk_pll_i 1.426 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 7.537ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.015ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 7.537ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_2_0_reg[63]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 32.429ns (logic 8.075ns (24.900%) route 24.354ns (75.100%)) + Logic Levels: 35 (CARRY4=3 LUT2=6 LUT3=4 LUT4=7 LUT5=9 LUT6=6) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.365ns = ( 38.635 - 40.000 ) + Source Clock Delay (SCD): -0.853ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.687 -0.853 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X73Y119 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_2_0_reg[63]/C + ------------------------------------------------------------------- ------------------- + SLICE_X73Y119 FDRE (Prop_fdre_C_Q) 0.419 -0.434 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_2_0_reg[63]/Q + net (fo=2, routed) 1.433 0.999 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_2_0[63] + SLICE_X85Y124 LUT6 (Prop_lut6_I3_O) 0.299 1.298 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.154 1.452 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X85Y124 LUT5 (Prop_lut5_I4_O) 0.124 1.576 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 0.898 2.475 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X76Y126 LUT5 (Prop_lut5_I4_O) 0.124 2.599 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 1.115 3.714 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X69Y139 LUT4 (Prop_lut4_I3_O) 0.124 3.838 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 0.892 4.729 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X66Y141 LUT4 (Prop_lut4_I3_O) 0.124 4.853 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[49]_i_3/O + net (fo=2, routed) 1.593 6.446 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[49] + SLICE_X41Y160 LUT5 (Prop_lut5_I0_O) 0.124 6.570 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[49]_i_2/O + net (fo=1, routed) 0.580 7.150 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[49]_i_2_n_0 + SLICE_X43Y160 LUT3 (Prop_lut3_I0_O) 0.124 7.274 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[49]_i_1/O + net (fo=7, routed) 1.392 8.665 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[49] + SLICE_X39Y175 LUT4 (Prop_lut4_I0_O) 0.153 8.818 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9/O + net (fo=2, routed) 0.284 9.102 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9_n_0 + SLICE_X39Y175 LUT3 (Prop_lut3_I1_O) 0.322 9.424 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10/O + net (fo=1, routed) 0.588 10.012 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10_n_0 + SLICE_X41Y175 LUT6 (Prop_lut6_I2_O) 0.332 10.344 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7/O + net (fo=11, routed) 1.210 11.554 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7_n_0 + SLICE_X52Y174 LUT4 (Prop_lut4_I3_O) 0.152 11.706 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217/O + net (fo=3, routed) 0.904 12.610 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217_n_0 + SLICE_X52Y179 LUT2 (Prop_lut2_I1_O) 0.326 12.936 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213/O + net (fo=5, routed) 0.531 13.467 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213_n_0 + SLICE_X53Y179 LUT3 (Prop_lut3_I0_O) 0.124 13.591 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.518 14.109 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X52Y179 LUT2 (Prop_lut2_I0_O) 0.149 14.258 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.817 15.075 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X52Y177 LUT2 (Prop_lut2_I0_O) 0.357 15.432 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.753 16.184 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X52Y175 LUT2 (Prop_lut2_I0_O) 0.361 16.545 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.849 17.395 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X52Y181 LUT3 (Prop_lut3_I0_O) 0.327 17.722 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.716 18.438 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X52Y181 LUT2 (Prop_lut2_I0_O) 0.153 18.591 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.656 19.247 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X52Y181 LUT2 (Prop_lut2_I0_O) 0.327 19.574 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.621 20.195 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X52Y178 LUT5 (Prop_lut5_I3_O) 0.124 20.319 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.463 20.782 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X53Y182 LUT6 (Prop_lut6_I0_O) 0.124 20.906 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.465 21.371 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X54Y182 CARRY4 (Prop_carry4_DI[0]_O[1]) + 0.422 21.793 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[1] + net (fo=1, routed) 0.407 22.200 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[62] + SLICE_X55Y181 LUT4 (Prop_lut4_I0_O) 0.306 22.506 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135/O + net (fo=3, routed) 1.111 23.616 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135_n_0 + SLICE_X62Y181 LUT4 (Prop_lut4_I3_O) 0.124 23.740 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115/O + net (fo=4, routed) 0.689 24.430 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115_n_0 + SLICE_X62Y179 LUT4 (Prop_lut4_I1_O) 0.124 24.554 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_66/O + net (fo=2, routed) 0.883 25.436 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_66_n_0 + SLICE_X61Y172 LUT5 (Prop_lut5_I4_O) 0.119 25.555 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_61/O + net (fo=2, routed) 0.685 26.240 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_61_n_0 + SLICE_X61Y172 LUT5 (Prop_lut5_I3_O) 0.360 26.600 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 27.050 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X61Y172 LUT5 (Prop_lut5_I3_O) 0.326 27.376 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.538 27.914 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X60Y172 LUT6 (Prop_lut6_I5_O) 0.124 28.038 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 28.038 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X60Y172 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 28.414 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 28.414 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X60Y173 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 28.737 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/O[1] + net (fo=2, routed) 0.656 29.394 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[5] + SLICE_X57Y168 LUT6 (Prop_lut6_I5_O) 0.306 29.700 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_14/O + net (fo=1, routed) 0.578 30.278 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_14_n_0 + SLICE_X55Y168 LUT6 (Prop_lut6_I5_O) 0.124 30.402 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_5/O + net (fo=1, routed) 0.575 30.977 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_5_n_0 + SLICE_X55Y166 LUT5 (Prop_lut5_I0_O) 0.124 31.101 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_2/O + net (fo=1, routed) 0.351 31.452 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_2_n_0 + SLICE_X54Y166 LUT5 (Prop_lut5_I0_O) 0.124 31.576 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_1/O + net (fo=1, routed) 0.000 31.576 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[5] + SLICE_X54Y166 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=37217, routed) 1.655 38.635 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X54Y166 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/C + clock pessimism 0.488 39.123 + clock uncertainty -0.091 39.032 + SLICE_X54Y166 FDRE (Setup_fdre_C_D) 0.081 39.113 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5] + ------------------------------------------------------------------- + required time 39.113 + arrival time -31.576 + ------------------------------------------------------------------- + slack 7.537 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.015ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/respData_reg[63]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/latData_reg[63]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.384ns (logic 0.185ns (48.124%) route 0.199ns (51.876%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37217, routed) 0.557 -0.607 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/clk + SLICE_X51Y69 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/respData_reg[63]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y69 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/respData_reg[63]/Q + net (fo=1, routed) 0.199 -0.267 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/respData_reg_n_0_[63] + SLICE_X52Y69 LUT3 (Prop_lut3_I0_O) 0.044 -0.223 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/latData[63]_i_2/O + net (fo=1, routed) 0.000 -0.223 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/latData_reg[63]_1[63] + SLICE_X52Y69 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/latData_reg[63]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37217, routed) 0.824 -0.849 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/clk + SLICE_X52Y69 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/latData_reg[63]/C + clock pessimism 0.504 -0.345 + SLICE_X52Y69 FDRE (Hold_fdre_C_D) 0.107 -0.238 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memLoader/latData_reg[63] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.015 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y69 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y78 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y78 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.909ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.909ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[10]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.560ns (logic 0.773ns (30.201%) route 1.787ns (69.799%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.522ns = ( 3.478 - 5.000 ) + Source Clock Delay (SCD): -0.926ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.614 -0.926 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X42Y136 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y136 FDRE (Prop_fdre_C_Q) 0.478 -0.448 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 1.005 0.557 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X39Y137 LUT2 (Prop_lut2_I0_O) 0.295 0.852 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/arty_ddr3mig_7s_LUT2_2/O + net (fo=11, routed) 0.781 1.633 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + SLICE_X39Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[10]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.499 3.478 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X39Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[10]/C + clock pessimism 0.560 4.038 + clock uncertainty -0.067 3.971 + SLICE_X39Y138 FDRE (Setup_fdre_C_R) -0.429 3.542 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[10] + ------------------------------------------------------------------- + required time 3.542 + arrival time -1.633 + ------------------------------------------------------------------- + slack 1.909 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.811ns + Source Clock Delay (SCD): -0.573ns + Clock Pessimism Removal (CPR): -0.238ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.591 -0.573 ref_clk + SLICE_X75Y82 FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y82 FDRE (Prop_fdre_C_Q) 0.141 -0.432 r btn_ref_meta_reg/Q + net (fo=1, routed) 0.056 -0.376 btn_ref_meta + SLICE_X75Y82 FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.862 -0.811 ref_clk + SLICE_X75Y82 FDRE r btn_ref_sync_reg/C + clock pessimism 0.238 -0.573 + SLICE_X75Y82 FDRE (Hold_fdre_C_D) 0.075 -0.498 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.498 + arrival time -0.376 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X75Y82 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X75Y82 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.811ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.811ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[0] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.117ns (logic 0.425ns (38.045%) route 0.692ns (61.955%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q4 + net (fo=1, routed) 0.692 3.224 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[0] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[0] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[0]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.224 + ------------------------------------------------------------------- + slack 9.811 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.957ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.957ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.467ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.114ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.467 2.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y88 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.539 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.068 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d1[3] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.025 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.025 + arrival time -3.068 + ------------------------------------------------------------------- + slack 9.957 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.564ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.564ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.674ns (57.945%) route 0.489ns (42.055%)) + Logic Levels: 0 + Clock Path Skew: 0.407ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.114ns = ( 8.114 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[0]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[0] + net (fo=1, routed) 0.489 3.583 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[4] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.407 8.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.826 + clock uncertainty -0.054 8.772 + OLOGIC_X1Y77 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.147 + arrival time -3.583 + ------------------------------------------------------------------- + slack 4.564 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 3.155ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.018ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.155ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[11]/CE + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.224ns (logic 0.744ns (9.047%) route 7.480ns (90.953%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.660ns = ( 12.660 - 12.000 ) + Source Clock Delay (SCD): 1.450ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.628 1.450 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg_rep__0_0 + SLICE_X71Y88 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y88 FDRE (Prop_fdre_C_Q) 0.419 1.869 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/Q + net (fo=145, routed) 3.119 4.989 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axi_wready + SLICE_X89Y109 LUT4 (Prop_lut4_I3_O) 0.325 5.314 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/goreg_dm.dout_i[144]_i_1/O + net (fo=144, routed) 4.361 9.674 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[144]_1[0] + SLICE_X51Y118 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[11]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.488 12.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/m_aclk + SLICE_X51Y118 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[11]/C + clock pessimism 0.649 13.310 + clock uncertainty -0.067 13.243 + SLICE_X51Y118 FDRE (Setup_fdre_C_CE) -0.413 12.830 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[11] + ------------------------------------------------------------------- + required time 12.830 + arrival time -9.674 + ------------------------------------------------------------------- + slack 3.155 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.018ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[50]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[50]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.908%) route 0.212ns (60.092%)) + Logic Levels: 0 + Clock Path Skew: 0.260ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.184ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/m_aclk + SLICE_X53Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[50]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y84 FDRE (Prop_fdre_C_Q) 0.141 0.275 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[50]/Q + net (fo=1, routed) 0.212 0.487 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm_n_10 + SLICE_X51Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[50]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.823 0.184 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/m_aclk + SLICE_X51Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[50]/C + clock pessimism 0.210 0.394 + SLICE_X51Y80 FDRE (Hold_fdre_C_D) 0.075 0.469 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[50] + ------------------------------------------------------------------- + required time -0.469 + arrival time 0.487 + ------------------------------------------------------------------- + slack 0.018 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.505ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.505ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.225ns (logic 0.478ns (39.009%) route 0.747ns (60.991%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X88Y110 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X88Y110 FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.747 1.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X89Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X89Y107 FDRE (Setup_fdre_C_D) -0.270 11.730 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 11.730 + arrival time -1.225 + ------------------------------------------------------------------- + slack 10.505 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 15.991ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 15.991ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 3.962ns (logic 0.456ns (11.510%) route 3.506ns (88.490%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 3.506 3.962 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X42Y136 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X42Y136 FDRE (Setup_fdre_C_D) -0.047 19.953 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.953 + arrival time -3.962 + ------------------------------------------------------------------- + slack 15.991 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.471ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.025ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.471ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 5.941ns (logic 3.867ns (65.094%) route 2.074ns (34.906%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.296ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.219ns = ( 2.719 - 1.500 ) + Source Clock Delay (SCD): 1.530ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.708 1.530 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X82Y75 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y75 FDRE (Prop_fdre_C_Q) 0.456 1.986 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.074 4.060 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 6.656 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 6.656 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.471 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.471 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.412 17.719 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.327 + clock uncertainty -0.220 18.107 + ILOGIC_X1Y85 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.942 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.942 + arrival time -7.471 + ------------------------------------------------------------------- + slack 10.471 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.025ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.361ns (logic 1.068ns (78.454%) route 0.293ns (21.546%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.061ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.990ns + Source Clock Delay (SCD): 0.167ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.591 60.167 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X82Y75 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y75 FDRE (Prop_fdre_C_Q) 0.141 60.308 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.293 60.601 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq/IBUFDISABLE + T5 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.285 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.285 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y76 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.528 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.528 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.178 15.990 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.227 + clock uncertainty 0.220 16.447 + ILOGIC_X1Y76 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.503 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.503 + arrival time 61.528 + ------------------------------------------------------------------- + slack 45.025 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 8.779ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.721ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.779ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 7.640ns (logic 3.867ns (50.618%) route 3.773ns (49.382%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.303ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.530ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.708 1.530 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X82Y75 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y75 FDRE (Prop_fdre_C_Q) 0.456 1.986 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 3.773 5.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 8.355 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 8.355 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 9.170 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 9.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -9.170 + ------------------------------------------------------------------- + slack 8.779 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.721ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 2.057ns (logic 1.068ns (51.922%) route 0.989ns (48.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.060ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.167ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.591 60.167 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X82Y75 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y75 FDRE (Prop_fdre_C_Q) 0.141 60.308 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.989 61.297 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUFDISABLE + L6 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.981 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y88 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 62.224 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 62.224 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y88 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 62.224 + ------------------------------------------------------------------- + slack 45.721 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.078ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.078ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.902ns (logic 0.272ns (30.165%) route 0.630ns (69.835%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 2.013 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST + net (fo=10, routed) 0.630 2.643 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.168 2.006 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.565 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.565 + arrival time 2.643 + ------------------------------------------------------------------- + slack 0.078 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.523ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.523ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.406ns (logic 0.518ns (36.846%) route 0.888ns (63.154%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X34Y80 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X34Y80 FDRE (Prop_fdre_C_Q) 0.518 0.518 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.888 1.406 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X28Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X28Y80 FDRE (Setup_fdre_C_D) -0.071 39.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 39.929 + arrival time -1.406 + ------------------------------------------------------------------- + slack 38.523 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 16.220ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.116ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.220ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[8]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[8]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 5.307ns (logic 0.478ns (9.006%) route 4.829ns (90.994%)) + Logic Levels: 0 + Clock Path Skew: 1.991ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.672ns + Source Clock Delay (SCD): -0.924ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.616 -0.924 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X38Y134 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y134 FDRE (Prop_fdre_C_Q) 0.478 -0.446 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[8]/Q + net (fo=1, routed) 4.829 4.383 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[8] + SLICE_X45Y140 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 20.672 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X45Y140 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[8]/C + clock pessimism 0.395 21.067 + clock uncertainty -0.245 20.822 + SLICE_X45Y140 FDRE (Setup_fdre_C_D) -0.219 20.603 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[8] + ------------------------------------------------------------------- + required time 20.603 + arrival time -4.383 + ------------------------------------------------------------------- + slack 16.220 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.116ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[6]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[6]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.736ns (logic 0.148ns (8.525%) route 1.588ns (91.475%)) + Logic Levels: 0 + Clock Path Skew: 1.354ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.191ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.558 -0.606 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X38Y134 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y134 FDRE (Prop_fdre_C_Q) 0.148 -0.458 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[6]/Q + net (fo=1, routed) 1.588 1.130 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[6] + SLICE_X45Y137 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.829 0.191 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X45Y137 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[6]/C + clock pessimism 0.557 0.747 + clock uncertainty 0.245 0.992 + SLICE_X45Y137 FDRE (Hold_fdre_C_D) 0.022 1.014 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[6] + ------------------------------------------------------------------- + required time -1.014 + arrival time 1.130 + ------------------------------------------------------------------- + slack 0.116 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.969ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.320ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.969ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.704ns (logic 0.456ns (16.865%) route 2.248ns (83.135%)) + Logic Levels: 0 + Clock Path Skew: 0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.771ns = ( 12.771 - 12.000 ) + Source Clock Delay (SCD): 1.441ns + Clock Pessimism Removal (CPR): 0.729ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.619 1.441 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X71Y69 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.456 1.897 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/Q + net (fo=41, routed) 2.248 4.145 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/SR[0] + SLICE_X78Y51 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.598 12.771 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/my_full_reg[4] + SLICE_X78Y51 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/C + clock pessimism 0.729 13.500 + clock uncertainty -0.067 13.433 + SLICE_X78Y51 FDCE (Recov_fdce_C_CLR) -0.319 13.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg + ------------------------------------------------------------------- + required time 13.114 + arrival time -4.145 + ------------------------------------------------------------------- + slack 8.969 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.320ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.287ns (logic 0.141ns (49.210%) route 0.146ns (50.790%)) + Logic Levels: 0 + Clock Path Skew: 0.034ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.188ns + Source Clock Delay (SCD): 0.135ns + Clock Pessimism Removal (CPR): 0.019ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X37Y79 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y79 FDPE (Prop_fdpe_C_Q) 0.141 0.276 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.146 0.421 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X38Y79 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.827 0.188 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X38Y79 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism -0.019 0.169 + SLICE_X38Y79 FDCE (Remov_fdce_C_CLR) -0.067 0.102 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time -0.102 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.320 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 27.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 27.439ns (required time - arrival time) + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 12.008ns (logic 1.076ns (8.961%) route 10.932ns (91.039%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.057ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.448ns = ( 38.552 - 40.000 ) + Source Clock Delay (SCD): -0.911ns + Clock Pessimism Removal (CPR): 0.480ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.629 -0.911 clk + SLICE_X64Y87 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y87 FDRE (Prop_fdre_C_Q) 0.456 -0.455 r reset_count_reg[12]/Q + net (fo=2, routed) 0.705 0.250 platform/normalizer/reset_count_reg[12] + SLICE_X65Y86 LUT4 (Prop_lut4_I3_O) 0.124 0.374 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, routed) 0.446 0.821 platform/normalizer/reset_count[0]_i_7_n_0 + SLICE_X65Y85 LUT5 (Prop_lut5_I4_O) 0.124 0.945 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, routed) 0.263 1.208 platform/normalizer/reset_count[0]_i_5_n_0 + SLICE_X65Y85 LUT6 (Prop_lut6_I5_O) 0.124 1.332 f platform/normalizer/reset_count[0]_i_2/O + net (fo=22, routed) 0.664 1.996 platform/normalizer/sel + SLICE_X67Y86 LUT4 (Prop_lut4_I3_O) 0.124 2.120 f platform/normalizer/FSM_sequential_state[2]_i_1/O + net (fo=900, routed) 2.181 4.301 platform/loader/cpu_run_reg_inv_2 + SLICE_X69Y104 LUT2 (Prop_lut2_I0_O) 0.124 4.425 f platform/loader/in_pipe_v_i_1__0/O + net (fo=5332, routed) 6.672 11.097 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X72Y134 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=37217, routed) 1.573 38.552 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X72Y134 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.480 39.033 + clock uncertainty -0.091 38.942 + SLICE_X72Y134 FDCE (Recov_fdce_C_CLR) -0.405 38.537 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 38.537 + arrival time -11.097 + ------------------------------------------------------------------- + slack 27.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.167ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.282ns (logic 0.128ns (45.315%) route 0.154ns (54.685%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.850ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37217, routed) 0.557 -0.607 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X47Y79 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y79 FDPE (Prop_fdpe_C_Q) 0.128 -0.479 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.154 -0.325 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.rst_wr_reg2 + SLICE_X53Y79 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37217, routed) 0.823 -0.850 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X53Y79 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/C + clock pessimism 0.504 -0.346 + SLICE_X53Y79 FDCE (Remov_fdce_C_CLR) -0.146 -0.492 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] + ------------------------------------------------------------------- + required time 0.492 + arrival time -0.325 + ------------------------------------------------------------------- + slack 0.167 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 1.426ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.426ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 3.574ns (logic 0.456ns (12.758%) route 3.118ns (87.242%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 3.118 3.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -3.574 + ------------------------------------------------------------------- + slack 1.426 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg_rep__3/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.203ns (logic 2.101ns (33.867%) route 4.102ns (66.133%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.727 1.549 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/wrcal_pat_resume_reg + SLICE_X87Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg_rep__3/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y61 FDRE (Prop_fdre_C_Q) 0.456 2.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg_rep__3/Q + net (fo=47, routed) 1.380 3.385 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_ctl_wd_i1_reg[22] + SLICE_X88Y64 LUT2 (Prop_lut2_I0_O) 0.124 3.509 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.723 6.231 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.752 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.752 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.642ns (logic 0.141ns (8.586%) route 1.501ns (91.414%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X71Y69 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.501 1.776 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 7 Endpoints +Min Delay 7 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: flash_recovery_reg/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 13.462ns (logic 5.171ns (38.414%) route 8.291ns (61.586%)) + Logic Levels: 3 (LUT2=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.629 -0.911 clk + SLICE_X67Y87 FDRE r flash_recovery_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDRE (Prop_fdre_C_Q) 0.456 -0.455 f flash_recovery_reg/Q + net (fo=4, routed) 1.326 0.871 platform/loader/flash_recovery + SLICE_X70Y97 LUT2 (Prop_lut2_I1_O) 0.146 1.017 r platform/loader/led_OBUF[2]_inst_i_2/O + net (fo=119, routed) 2.493 3.510 platform/loader/cpu_run + SLICE_X67Y86 LUT5 (Prop_lut5_I4_O) 0.356 3.866 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 4.472 8.338 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.213 12.551 r led_OBUF[2]_inst/O + net (fo=0) 0.000 12.551 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: calib_sync_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.931ns (logic 2.152ns (73.407%) route 0.779ns (26.593%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37217, routed) 0.595 -0.569 clk + SLICE_X79Y83 FDRE r calib_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y83 FDRE (Prop_fdre_C_Q) 0.128 -0.441 r calib_sync_reg[1]/Q + net (fo=6, routed) 0.779 0.338 calib_sync[1] + H5 OBUF (Prop_obuf_I_O) 2.024 2.362 r led_OBUF[0]_inst/O + net (fo=0) 0.000 2.362 led[0] + H5 r led[0] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.091ns (logic 0.741ns (18.111%) route 3.350ns (81.889%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.675ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): 1.441ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.619 1.441 ui_clk + SLICE_X71Y80 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y80 FDPE (Prop_fdpe_C_Q) 0.419 1.860 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.796 2.656 memory_cdc/inst/m_axi_aresetn + SLICE_X69Y80 LUT2 (Prop_lut2_I1_O) 0.322 2.978 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.554 5.533 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y114 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y114 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ui_reset_pipe_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.776ns (logic 0.141ns (18.173%) route 0.635ns (81.827%)) + Logic Levels: 0 + Clock Path Skew: 0.055ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.189ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X71Y69 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.141 0.275 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 0.635 0.910 ui_rst + SLICE_X71Y80 FDPE f ui_reset_pipe_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.828 0.189 ui_clk + SLICE_X71Y80 FDPE r ui_reset_pipe_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.140ns (logic 1.337ns (18.725%) route 5.803ns (81.275%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.677ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): -0.911ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.629 -0.911 clk + SLICE_X64Y87 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y87 FDRE (Prop_fdre_C_Q) 0.456 -0.455 r reset_count_reg[12]/Q + net (fo=2, routed) 0.705 0.250 platform/normalizer/reset_count_reg[12] + SLICE_X65Y86 LUT4 (Prop_lut4_I3_O) 0.124 0.374 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, routed) 0.446 0.821 platform/normalizer/reset_count[0]_i_7_n_0 + SLICE_X65Y85 LUT5 (Prop_lut5_I4_O) 0.124 0.945 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, routed) 0.263 1.208 platform/normalizer/reset_count[0]_i_5_n_0 + SLICE_X65Y85 LUT6 (Prop_lut6_I5_O) 0.124 1.332 f platform/normalizer/reset_count[0]_i_2/O + net (fo=22, routed) 0.664 1.996 sel + SLICE_X67Y86 LUT4 (Prop_lut4_I3_O) 0.152 2.148 r memory_cdc_i_1/O + net (fo=1, routed) 1.170 3.318 memory_cdc/inst/s_axi_aresetn + SLICE_X69Y80 LUT2 (Prop_lut2_I0_O) 0.357 3.675 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.554 6.229 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y114 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y114 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.593ns (logic 0.337ns (56.825%) route 0.256ns (43.175%)) + Logic Levels: 0 + Clock Path Skew: 2.959ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.446ns + Source Clock Delay (SCD): -1.513ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.507 -1.513 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X40Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y80 FDRE (Prop_fdre_C_Q) 0.337 -1.176 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.256 -0.920 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X39Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.624 1.446 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X39Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.814ns (logic 0.402ns (22.164%) route 1.412ns (77.836%)) + Logic Levels: 0 + Clock Path Skew: 0.960ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.771ns + Source Clock Delay (SCD): -0.189ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.213 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 1.412 1.625 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X86Y79 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.598 0.771 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X86Y79 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.613ns (logic 0.204ns (33.281%) route 0.409ns (66.719%)) + Logic Levels: 0 + Clock Path Skew: 0.577ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.226ns + Source Clock Delay (SCD): -0.351ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.204 -0.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.409 0.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X87Y71 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.865 0.226 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X87Y71 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.385ns (logic 0.715ns (13.277%) route 4.670ns (86.723%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.506ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.672ns + Source Clock Delay (SCD): -0.834ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.706 -0.834 ref_clk + SLICE_X77Y81 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y81 FDCE (Prop_fdce_C_Q) 0.419 -0.415 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.269 0.855 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X88Y79 LUT4 (Prop_lut4_I2_O) 0.296 1.151 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 3.401 4.552 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X48Y103 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 0.672 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X48Y103 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__1/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.336ns (logic 0.226ns (16.914%) route 1.110ns (83.086%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.789ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.215ns + Source Clock Delay (SCD): -0.574ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.590 -0.574 ref_clk + SLICE_X77Y81 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y81 FDCE (Prop_fdce_C_Q) 0.128 -0.446 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.525 0.079 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X88Y79 LUT4 (Prop_lut4_I2_O) 0.098 0.177 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.585 0.762 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X73Y70 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__1/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.854 0.215 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X73Y70 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__1/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 4 Endpoints +Min Delay 4 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.443ns (logic 1.487ns (19.983%) route 5.956ns (80.017%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.512ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.512ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 5.956 7.443 btn0_IBUF + SLICE_X67Y87 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.508 -1.512 clk + SLICE_X67Y87 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: flash_miso + (input port) + Destination: platform/peripherals/spi_enabled.flash/miso_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.152ns (logic 0.257ns (22.291%) route 0.895ns (77.709%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.830ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.830ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K18 0.000 0.000 r flash_miso (IN) + net (fo=0) 0.000 0.000 flash_miso + K18 IBUF (Prop_ibuf_I_O) 0.257 0.257 r flash_miso_IBUF_inst/O + net (fo=1, routed) 0.895 1.152 platform/peripherals/spi_enabled.flash/flash_miso + SLICE_X28Y99 FDRE r platform/peripherals/spi_enabled.flash/miso_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37217, routed) 0.843 -0.830 platform/peripherals/spi_enabled.flash/clk + SLICE_X28Y99 FDRE r platform/peripherals/spi_enabled.flash/miso_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 3.858ns (logic 0.741ns (19.204%) route 3.117ns (80.796%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.871ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): 1.441ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.619 1.441 ui_clk + SLICE_X71Y80 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y80 FDPE (Prop_fdpe_C_Q) 0.419 1.860 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.796 2.656 memory_cdc/inst/m_axi_aresetn + SLICE_X69Y80 LUT2 (Prop_lut2_I1_O) 0.322 2.978 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.322 5.300 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.238ns (logic 0.128ns (53.830%) route 0.110ns (46.170%)) + Logic Levels: 0 + Clock Path Skew: -0.977ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.842ns + Source Clock Delay (SCD): 0.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X49Y83 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y83 FDRE (Prop_fdre_C_Q) 0.128 0.263 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.110 0.373 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X49Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37217, routed) 0.831 -0.842 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X49Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.907ns (logic 1.337ns (19.357%) route 5.570ns (80.643%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.519ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): -0.911ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37217, routed) 1.629 -0.911 clk + SLICE_X64Y87 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y87 FDRE (Prop_fdre_C_Q) 0.456 -0.455 r reset_count_reg[12]/Q + net (fo=2, routed) 0.705 0.250 platform/normalizer/reset_count_reg[12] + SLICE_X65Y86 LUT4 (Prop_lut4_I3_O) 0.124 0.374 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, routed) 0.446 0.821 platform/normalizer/reset_count[0]_i_7_n_0 + SLICE_X65Y85 LUT5 (Prop_lut5_I4_O) 0.124 0.945 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, routed) 0.263 1.208 platform/normalizer/reset_count[0]_i_5_n_0 + SLICE_X65Y85 LUT6 (Prop_lut6_I5_O) 0.124 1.332 f platform/normalizer/reset_count[0]_i_2/O + net (fo=22, routed) 0.664 1.996 sel + SLICE_X67Y86 LUT4 (Prop_lut4_I3_O) 0.152 2.148 r memory_cdc_i_1/O + net (fo=1, routed) 1.170 3.318 memory_cdc/inst/s_axi_aresetn + SLICE_X69Y80 LUT2 (Prop_lut2_I0_O) 0.357 3.675 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.322 5.996 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37217, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.325ns (logic 0.341ns (25.740%) route 0.984ns (74.260%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.241ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.841ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37217, routed) 0.564 -0.600 clk + SLICE_X69Y86 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y86 FDPE (Prop_fdpe_C_Q) 0.128 -0.472 f lock_sync_reg[2]/Q + net (fo=5, routed) 0.255 -0.217 lock_sync[2] + SLICE_X67Y86 LUT4 (Prop_lut4_I1_O) 0.102 -0.115 r memory_cdc_i_1/O + net (fo=1, routed) 0.429 0.314 memory_cdc/inst/s_axi_aresetn + SLICE_X69Y80 LUT2 (Prop_lut2_I0_O) 0.111 0.425 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.299 0.725 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X64Y82 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37217, routed) 0.832 -0.841 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X64Y82 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.041ns (logic 1.487ns (18.496%) route 6.554ns (81.504%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.431ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.431ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.554 8.041 btn0_IBUF + SLICE_X75Y82 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.589 -1.431 ref_clk + SLICE_X75Y82 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.159ns (logic 0.255ns (8.076%) route 2.904ns (91.924%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.811ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.811ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.904 3.159 btn0_IBUF + SLICE_X75Y82 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.862 -0.811 ref_clk + SLICE_X75Y82 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.798ns (logic 0.141ns (7.842%) route 1.657ns (92.158%)) + Logic Levels: 0 + Clock Path Skew: -0.980ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.846ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X71Y69 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y69 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.657 1.932 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X42Y136 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.826 -0.846 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X42Y136 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.738ns (logic 0.743ns (15.683%) route 3.995ns (84.317%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.465ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.299ns + Source Clock Delay (SCD): -0.834ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.706 -0.834 ref_clk + SLICE_X77Y81 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y81 FDCE (Prop_fdce_C_Q) 0.419 -0.415 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.269 0.855 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X88Y79 LUT1 (Prop_lut1_I0_O) 0.324 1.179 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 2.725 3.904 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X81Y36 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.722 -1.299 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X81Y36 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][13]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.806ns (logic 0.226ns (12.517%) route 1.580ns (87.483%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.170ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.744ns + Source Clock Delay (SCD): -0.574ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.590 -0.574 ref_clk + SLICE_X77Y81 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y81 FDCE (Prop_fdce_C_Q) 0.128 -0.446 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.525 0.079 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X88Y79 LUT1 (Prop_lut1_I0_O) 0.098 0.177 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.054 1.231 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X78Y39 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][13]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.929 -0.744 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X78Y39 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][13]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.915ns (logic 0.124ns (2.097%) route 5.791ns (97.904%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 2.390 2.390 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X88Y79 LUT4 (Prop_lut4_I0_O) 0.124 2.514 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 3.401 5.915 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X48Y103 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 0.672 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X48Y103 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.848ns (logic 0.045ns (5.305%) route 0.803ns (94.695%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.270 0.270 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in_n_6 + SLICE_X88Y77 LUT2 (Prop_lut2_I0_O) 0.045 0.315 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.533 0.848 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X73Y68 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.856 0.217 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X73Y68 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-utilization.rpt new file mode 100644 index 0000000..900b3d2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/routed-utilization.rpt @@ -0,0 +1,265 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 02:59:57 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 53944 | 0 | 0 | 63400 | 85.09 | +| LUT as Logic | 50022 | 0 | 0 | 63400 | 78.90 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 35645 | 0 | 0 | 126800 | 28.11 | +| Register as Flip Flop | 35645 | 0 | 0 | 126800 | 28.11 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 913 | 0 | 0 | 31700 | 2.88 | +| F8 Muxes | 221 | 0 | 0 | 15850 | 1.39 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 564 | Yes | Set | - | +| 34778 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15618 | 0 | 0 | 15850 | 98.54 | +| SLICEL | 10912 | 0 | | | | +| SLICEM | 4706 | 0 | | | | +| LUT as Logic | 50022 | 0 | 0 | 63400 | 78.90 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37337 | | | | | +| using O5 and O6 | 12654 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 35645 | 0 | 0 | 126800 | 28.11 | +| Register driven from within the Slice | 15192 | | | | | +| Register driven from outside the Slice | 20453 | | | | | +| LUT in front of the register is unused | 5424 | | | | | +| LUT in front of the register is used | 15029 | | | | | +| Unique Control Sets | 1263 | | 0 | 15850 | 7.97 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 62 | 62 | 0 | 210 | 29.52 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 30 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 1 | 0 | 0 | 1 | 100.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 34778 | Flop & Latch | +| LUT6 | 20347 | LUT | +| LUT3 | 13518 | LUT | +| LUT5 | 12657 | LUT | +| LUT4 | 10492 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4851 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| MUXF7 | 913 | MuxFx | +| LUT1 | 811 | LUT | +| FDSE | 564 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| MUXF8 | 221 | MuxFx | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| IBUF | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| STARTUPE2 | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.jou b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.jou new file mode 100644 index 0000000..22b2279 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 02:37:51 2026 +# Process ID: 2988461 +# Current directory: /home/yys/codex-builds/toy-a7-flash-20261012 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.log -journal /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749 flash +# Log file: /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :3565.568 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :571493 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.log new file mode 100644 index 0000000..2bce24a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/implementation/vivado.log @@ -0,0 +1,5915 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 02:37:51 2026 +# Process ID: 2988461 +# Current directory: /home/yys/codex-builds/toy-a7-flash-20261012 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.log -journal /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749 flash +# Log file: /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :3565.568 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :571493 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-flash-20261012/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-flash-20261012/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2215.965 ; gain = 268.445 ; free physical = 159065 ; free virtual = 545223 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 2988770 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2657.594 ; gain = 423.715 ; free physical = 158406 ; free virtual = 544576 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158173 ; free virtual = 544350 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158174 ; free virtual = 544351 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.133 ; gain = 676.254 ; free physical = 158174 ; free virtual = 544351 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2910.133 ; gain = 0.000 ; free physical = 158195 ; free virtual = 544372 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.977 ; gain = 0.000 ; free physical = 158227 ; free virtual = 544420 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3019.977 ; gain = 0.000 ; free physical = 158236 ; free virtual = 544429 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3019.977 ; gain = 786.098 ; free physical = 158359 ; free virtual = 544553 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158358 ; free virtual = 544552 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158371 ; free virtual = 544565 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.980 ; gain = 794.102 ; free physical = 158430 ; free virtual = 544636 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158467 ; free virtual = 544701 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:23 ; elapsed = 00:01:23 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158489 ; free virtual = 544731 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158494 ; free virtual = 544735 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:26 ; elapsed = 00:01:26 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158503 ; free virtual = 544744 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158557 ; free virtual = 544798 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158557 ; free virtual = 544798 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158548 ; free virtual = 544790 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158560 ; free virtual = 544802 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158563 ; free virtual = 544811 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.543 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:26 ; elapsed = 00:01:27 . Memory (MB): peak = 3299.543 ; gain = 955.820 ; free physical = 158565 ; free virtual = 544813 +Synthesis Optimization Complete : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 3299.551 ; gain = 1065.664 ; free physical = 158565 ; free virtual = 544813 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3299.551 ; gain = 0.000 ; free physical = 158858 ; free virtual = 545110 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3355.570 ; gain = 0.000 ; free physical = 158873 ; free virtual = 545127 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:35 ; elapsed = 00:01:32 . Memory (MB): peak = 3355.570 ; gain = 1127.629 ; free physical = 158881 ; free virtual = 545135 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3023.344; main = 2722.250; forked = 446.556 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4341.133; main = 3355.574; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158789 ; free virtual = 545056 +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158799 ; free virtual = 545065 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158807 ; free virtual = 545074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158881 ; free virtual = 545148 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158881 ; free virtual = 545148 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158887 ; free virtual = 545154 +Write Physdb Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158887 ; free virtual = 545154 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3403.586 ; gain = 0.000 ; free physical = 158552 ; free virtual = 544832 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3418.586 ; gain = 15.000 ; free physical = 158541 ; free virtual = 544828 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3418.586 ; gain = 0.000 ; free physical = 158542 ; free virtual = 544829 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3469.398 ; gain = 0.000 ; free physical = 158530 ; free virtual = 544817 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3469.398 ; gain = 0.000 ; free physical = 158530 ; free virtual = 544817 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158544 ; free virtual = 544831 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158544 ; free virtual = 544831 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544821 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158518 ; free virtual = 544807 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158409 ; free virtual = 544698 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158464 ; free virtual = 544753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158467 ; free virtual = 544756 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158469 ; free virtual = 544758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158534 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544823 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.398 ; gain = 15.000 ; free physical = 158535 ; free virtual = 544824 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3469.406 ; gain = 65.812 ; free physical = 158535 ; free virtual = 544824 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3469.406 ; gain = 0.000 ; free physical = 158843 ; free virtual = 545132 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3469.406 ; gain = 0.000 ; free physical = 158854 ; free virtual = 545148 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3469.406 ; gain = 65.820 ; free physical = 158842 ; free virtual = 545136 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3078.561; main = 2773.062; forked = 447.628 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4511.992; main = 3469.402; forked = 1042.590 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3477.402 ; gain = 0.000 ; free physical = 158855 ; free virtual = 545149 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:09 ; elapsed = 00:02:05 . Memory (MB): peak = 3477.402 ; gain = 1261.438 ; free physical = 158843 ; free virtual = 545138 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3078.561; main = 2773.062; forked = 447.628 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4511.992; main = 3477.406; forked = 1042.590 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3477.523 ; gain = 0.000 ; free physical = 158499 ; free virtual = 544802 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 1 - type: integer +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:22] +INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137432] +INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137432] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-flash-20261012/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 1 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103277] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:102029] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103736] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:103736] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24349] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:26100] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:27453] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68579] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68593] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:68607] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:82862] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:82061] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:86947] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85200] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85208] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90518] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90550] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90582] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90614] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90646] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90678] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:90710] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:98905] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:98927] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99546] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99552] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:99558] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:100285] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:101280] +INFO: [Synth 8-3876] $readmem data file 'build/flash-boot/bootrom.hex' is read successfully [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:101970] + Parameter FLASH_BOOT bound to: 1 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76889] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76891] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76893] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76896] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76899] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76903] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76907] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76929] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76945] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76965] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77001] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77003] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77006] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77010] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77015] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77021] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77031] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77034] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77043] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:77049] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76894] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76897] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76900] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76901] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76904] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76905] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76908] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76909] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76910] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76913] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76915] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76918] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76921] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76925] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76934] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76939] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:76948] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:93717] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_opcode[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_param[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[7] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[6] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[5] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[4] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[3] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[2] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[1] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_mask[0] in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port auto_in_a_bits_corrupt in module TLROM is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[27] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[26] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[25] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[24] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[23] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[22] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[21] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[20] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[19] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[18] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[17] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3815.395 ; gain = 337.871 ; free physical = 158042 ; free virtual = 544370 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3830.238 ; gain = 352.715 ; free physical = 158048 ; free virtual = 544376 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3830.238 ; gain = 352.715 ; free physical = 158048 ; free virtual = 544376 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3833.379 ; gain = 0.000 ; free physical = 158097 ; free virtual = 544427 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4006.004 ; gain = 0.000 ; free physical = 157973 ; free virtual = 544304 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4009.922 ; gain = 0.000 ; free physical = 157977 ; free virtual = 544307 +WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'memory_cdc' at clock pin 'm_axi_aclk' is different from the actual clock period '12.000', this can lead to different synthesis results. +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 4009.922 ; gain = 532.398 ; free physical = 156748 ; free virtual = 543089 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 4009.922 ; gain = 532.398 ; free physical = 156748 ; free virtual = 543089 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 2). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 3). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 4). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 5). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 6). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 7). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 8). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 9). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 10). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 11). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 12). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 13). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 14). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 15). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 16). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 17). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 18). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 19). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 20). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 21). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 22). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 23). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 24). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 25). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 26). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 28). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 29). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 30). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 31). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 32). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 33). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 34). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 35). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 36). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 37). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 38). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 39). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 40). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 41). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 42). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 43). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 44). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 45). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 46). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 47). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 48). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 49). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 50). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 51). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 52). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 53). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 54). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 55). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 56). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 57). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 58). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 59). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 60). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 61). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 62). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 63). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 64). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 65). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 66). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 67). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 68). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 69). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 70). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 71). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 72). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 73). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 74). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 75). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 76). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 77). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 78). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 79). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 80). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 81). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 82). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 83). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 84). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 85). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 86). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 87). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 88). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 89). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 90). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 91). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 92). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 93). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 94). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 95). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 96). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 97). +Applied set_property KEEP_HIERARCHY = SOFT for ddr_controller. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for memory_cdc. (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 4009.922 ; gain = 532.398 ; free physical = 156710 ; free virtual = 543050 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:84800] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:84798] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:86183] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_AC80CBA0 | 00 | 00 + P_AC57AB10 | 01 | 01 + P_AC775860 | 10 | 10 + P_AC7AE9F0 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:47 ; elapsed = 00:00:43 . Memory (MB): peak = 4009.922 ; gain = 532.398 ; free physical = 152969 ; free virtual = 539323 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 66 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 71 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 8 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 185 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 437 + 7 Bit Registers := 28 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 235 + 2 Bit Registers := 129 + 1 Bit Registers := 1669 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 ++---ROMs : + ROMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 307 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 371 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 197 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 258 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1291 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/serial-bound/FpgaMemories.sv:86] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79405] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79488] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79553] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79582] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79604] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79650] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79650] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79654] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79658] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79658] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79753] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:79757] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:85990] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\rowDelta_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\split_addr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memLoader/\pixel_bytes_reg_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (configer/\zeroLines/rowCount_reg[31] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/\reqReg_len_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_19/\bytesReceived_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_13/\bytesRequested_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/i_13/\bytesRequested_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\dma_addr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (reader/\reqReg_pixel_bytes_reg[1] ) +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (writer/\reqReg_vaddr_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (memStorer/\split_mask_reg[7] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__52 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:11:58 ; elapsed = 00:12:33 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157194 ; free virtual = 544592 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:04 ; elapsed = 00:12:39 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157162 ; free virtual = 544577 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------+-------------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------+-------------------+---------------+----------------+ +|TLROM | response_data_reg | 1024x64 | Block RAM | ++------------+-------------------+---------------+----------------+ + + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:11 ; elapsed = 00:12:46 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157314 ; free virtual = 544833 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:23 ; elapsed = 00:12:59 . Memory (MB): peak = 6494.863 ; gain = 3017.340 ; free physical = 157347 ; free virtual = 544869 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance systemi_20/bootrom_domain/bootrom/response_data_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance systemi_20/bootrom_domain/bootrom/response_data_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:42 ; elapsed = 00:13:17 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157468 ; free virtual = 545009 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/bootrom_domain/bootrom/response_data_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/bootrom_domain/bootrom/response_data_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:51 ; elapsed = 00:13:27 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157323 ; free virtual = 544946 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:51 ; elapsed = 00:13:27 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157322 ; free virtual = 544945 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157364 ; free virtual = 545006 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157364 ; free virtual = 545006 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157402 ; free virtual = 545044 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157410 ; free virtual = 545052 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4331| +|20 |LUT3 | 12207| +|21 |LUT4 | 10233| +|22 |LUT5 | 12403| +|23 |LUT6 | 18384| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 853| +|26 |MUXF8 | 221| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|39 |SRL16E | 225| +|40 |STARTUPE2 | 1| +|41 |FDCE | 8| +|42 |FDPE | 6| +|43 |FDRE | 29882| +|44 |FDSE | 459| +|45 |IBUF | 5| +|46 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:07 ; elapsed = 00:13:43 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 157411 ; free virtual = 545053 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 512 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:53 ; elapsed = 00:13:34 . Memory (MB): peak = 6506.789 ; gain = 2849.582 ; free physical = 165324 ; free virtual = 552968 +Synthesis Optimization Complete : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6506.789 ; gain = 3029.266 ; free physical = 165344 ; free virtual = 552970 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165198 ; free virtual = 552965 +INFO: [Netlist 29-17] Analyzing 4423 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165045 ; free virtual = 552819 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6506.789 ; gain = 0.000 ; free physical = 165176 ; free virtual = 552950 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: e3d50df3 +INFO: [Common 17-83] Releasing license: Synthesis +612 Infos, 465 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:43 ; elapsed = 00:14:08 . Memory (MB): peak = 6506.789 ; gain = 3029.387 ; free physical = 165201 ; free virtual = 552975 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13724.044; main = 5807.853; forked = 8285.465 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19165.703; main = 6502.875; forked = 12662.832 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165216 ; free virtual = 552990 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165216 ; free virtual = 552990 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552991 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552991 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552992 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165217 ; free virtual = 552992 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 165210 ; free virtual = 552992 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 6526.879 ; gain = 20.090 ; free physical = 165012 ; free virtual = 552852 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 6526.879 ; gain = 0.000 ; free physical = 164960 ; free virtual = 552823 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6558.895 ; gain = 32.016 ; free physical = 164976 ; free virtual = 552841 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 +Phase 1 Initialization | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164969 ; free virtual = 552834 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164973 ; free virtual = 552838 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164974 ; free virtual = 552839 +Phase 2 Timer Update And Timing Data Collection | Checksum: 27fd6c8c0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164974 ; free virtual = 552839 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2872 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 24d1b8c2b + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164995 ; free virtual = 552860 +Retarget | Checksum: 24d1b8c2b +INFO: [Opt 31-389] Phase Retarget created 95 cells and removed 601 cells +INFO: [Opt 31-1021] In phase Retarget, 54 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 1f9f2fa4a + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 164999 ; free virtual = 552864 +Constant propagation | Checksum: 1f9f2fa4a +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 250c9c5d5 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165004 ; free virtual = 552869 +Sweep | Checksum: 250c9c5d5 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 330 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 1e2673890 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165012 ; free virtual = 552877 +BUFG optimization | Checksum: 1e2673890 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 1e2673890 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 165011 ; free virtual = 552877 +Shift Register Optimization | Checksum: 1e2673890 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 103 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'flash_spi_byte'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_4x144_444'. +INFO: [Opt 31-75] Optimized module 'ram_4x281'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2240 inverters resulting in an inversion of 7773 pins +INFO: [Opt 31-138] Pushed 3 inverter(s) to 15 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 1c4622320 + +Time (s): cpu = 00:02:37 ; elapsed = 00:00:51 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 160966 ; free virtual = 548879 +Resynthesis | Checksum: 1c4622320 +INFO: [Opt 31-389] Phase Resynthesis created 18779 cells and removed 19516 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 1c4622320 + +Time (s): cpu = 00:02:37 ; elapsed = 00:00:51 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161043 ; free virtual = 548956 +Post Processing Netlist | Checksum: 1c4622320 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549075 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Phase 10 Finalization | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 95 | 601 | 54 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 330 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 18779 | 19516 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1abb29775 + +Time (s): cpu = 00:02:38 ; elapsed = 00:00:52 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161162 ; free virtual = 549076 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161228 ; free virtual = 549141 +Ending Netlist Obfuscation Task | Checksum: 1abb29775 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161228 ; free virtual = 549141 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:42 ; elapsed = 00:00:55 . Memory (MB): peak = 6558.895 ; gain = 32.016 ; free physical = 161228 ; free virtual = 549141 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549493 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549494 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161580 ; free virtual = 549494 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 161579 ; free virtual = 549504 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162747 ; free virtual = 550731 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1832c48e9 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 162910 ; free virtual = 550895 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e8838b6d + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6558.895 ; gain = 0.000 ; free physical = 163162 ; free virtual = 551152 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163785 ; free virtual = 551794 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163795 ; free virtual = 551804 +Phase 1 Placer Initialization | Checksum: 1f844bbe5 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163814 ; free virtual = 551824 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 27b0407fd + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 163965 ; free virtual = 551975 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2b26fc456 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 164112 ; free virtual = 552122 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2b26fc456 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 164113 ; free virtual = 552123 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 20cd516cb + +Time (s): cpu = 00:02:09 ; elapsed = 00:00:49 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154547 ; free virtual = 542720 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5057 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2158 nets or LUTs. Breaked 0 LUT, combined 2158 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 152603 ; free virtual = 542226 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2158 | 2158 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2158 | 2158 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 18eedb8ce + +Time (s): cpu = 00:02:20 ; elapsed = 00:00:55 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157047 ; free virtual = 542659 +Phase 2.4 Global Placement Core | Checksum: 24da91504 + +Time (s): cpu = 00:02:32 ; elapsed = 00:01:00 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157304 ; free virtual = 543107 +Phase 2 Global Placement | Checksum: 24da91504 + +Time (s): cpu = 00:02:33 ; elapsed = 00:01:00 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 157247 ; free virtual = 543052 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 266f7d8f9 + +Time (s): cpu = 00:02:39 ; elapsed = 00:01:02 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 155839 ; free virtual = 541724 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a987373e + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153064 ; free virtual = 539052 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 14bd8cc79 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 152816 ; free virtual = 538813 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2282967f1 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:07 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 152734 ; free virtual = 538734 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2627c387e + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 146358 ; free virtual = 532915 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1c8d0f247 + +Time (s): cpu = 00:03:19 ; elapsed = 00:01:32 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154365 ; free virtual = 541003 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1f25e9ec5 + +Time (s): cpu = 00:03:19 ; elapsed = 00:01:33 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 156570 ; free virtual = 543229 +Phase 3 Detail Placement | Checksum: 1f25e9ec5 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:33 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 156341 ; free virtual = 543019 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 177f09b53 + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: b22e272a + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 155158 ; free virtual = 542278 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 11b632fca + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 154882 ; free virtual = 542046 +Phase 4.1.1.1 BUFG Insertion | Checksum: 177f09b53 + +Time (s): cpu = 00:03:50 ; elapsed = 00:01:44 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154664 ; free virtual = 541848 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1bd122984 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154474 ; free virtual = 541687 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154474 ; free virtual = 541687 +Phase 4.1 Post Commit Optimization | Checksum: 1bd122984 + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154267 ; free virtual = 541498 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1bd122984 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 154101 ; free virtual = 541356 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 4x4| 8x8| +|___________|___________________|___________________| +| South| 1x1| 4x4| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 2x2| 4x4| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1bd122984 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153908 ; free virtual = 541183 +Phase 4.3 Placer Reporting | Checksum: 1bd122984 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153827 ; free virtual = 541119 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 153825 ; free virtual = 541119 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:46 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153825 ; free virtual = 541119 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2549690c6 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153598 ; free virtual = 540910 +Ending Placer Task | Checksum: 18a614880 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:47 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153475 ; free virtual = 540803 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:03:59 ; elapsed = 00:01:49 . Memory (MB): peak = 6565.922 ; gain = 7.027 ; free physical = 153473 ; free virtual = 540804 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.13 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 153328 ; free virtual = 540687 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149999 ; free virtual = 540240 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149999 ; free virtual = 540240 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149991 ; free virtual = 540232 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149941 ; free virtual = 540193 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149941 ; free virtual = 540193 +Write Physdb Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 149924 ; free virtual = 540177 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 148331 ; free virtual = 538752 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:05 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 147231 ; free virtual = 537802 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 147233 ; free virtual = 537804 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: 3c76631f ConstDB: 0 ShapeSum: 9c1885cb RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 698097df | NumContArr: c52f5a13 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2b401e72c + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145822 ; free virtual = 536886 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2b401e72c + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145703 ; free virtual = 536783 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2b401e72c + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 145678 ; free virtual = 536759 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 1f3dd5fe7 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:23 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 143307 ; free virtual = 534570 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.345 | THS=-659.163| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24899599d + +Time (s): cpu = 00:01:20 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142060 ; free virtual = 533390 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.298 | THS=-55.710| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 17add0eed + +Time (s): cpu = 00:01:21 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142056 ; free virtual = 533389 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 94828 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 94827 + Number of Partially Routed Nets = 1 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 1bddbf3bb + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142034 ; free virtual = 533368 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 1bddbf3bb + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142034 ; free virtual = 533368 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 1ba297ad2 + +Time (s): cpu = 00:01:37 ; elapsed = 00:00:33 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142178 ; free virtual = 533521 +Phase 4 Initial Routing | Checksum: 1ba297ad2 + +Time (s): cpu = 00:01:37 ; elapsed = 00:00:33 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 142178 ; free virtual = 533522 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14987 + Number of Nodes with overlaps = 1443 + Number of Nodes with overlaps = 384 + Number of Nodes with overlaps = 139 + Number of Nodes with overlaps = 53 + Number of Nodes with overlaps = 15 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 32748357f + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:11 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161414 ; free virtual = 552787 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 17093f564 + +Time (s): cpu = 00:03:02 ; elapsed = 00:01:17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 +Phase 5 Rip-up And Reroute | Checksum: 17093f564 + +Time (s): cpu = 00:03:02 ; elapsed = 00:01:17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp +Phase 6.1 Delay CleanUp | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 +Phase 6 Delay and Skew Optimization | Checksum: 17093f564 + +Time (s): cpu = 00:03:03 ; elapsed = 00:01:18 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161514 ; free virtual = 552900 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.014 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:12 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161594 ; free virtual = 552982 +Phase 7 Post Hold Fix | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:13 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161594 ; free virtual = 552981 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 22.2778 % + Global Horizontal Routing Utilization = 27.5909 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:14 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161601 ; free virtual = 552988 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 1ff8dc939 + +Time (s): cpu = 00:03:14 ; elapsed = 00:01:20 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161612 ; free virtual = 552999 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 18b572001 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:24 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161772 ; free virtual = 553162 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 18b572001 + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:24 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161781 ; free virtual = 553171 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.015 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: eb1d40e0 + +Time (s): cpu = 00:03:48 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161811 ; free virtual = 553205 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 89.93 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: 123b2a607 + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:30 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161823 ; free virtual = 553217 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: 123b2a607 + +Time (s): cpu = 00:03:50 ; elapsed = 00:01:31 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161997 ; free virtual = 553392 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:03:56 ; elapsed = 00:01:34 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161931 ; free virtual = 553330 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161976 ; free virtual = 553394 +Wrote PlaceDB: Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553484 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553484 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161980 ; free virtual = 553499 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 161979 ; free virtual = 553508 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162056 ; free virtual = 553543 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:06 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162101 ; free virtual = 553596 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162074 ; free virtual = 553579 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.25 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162059 ; free virtual = 553564 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7173120 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 6565.922 ; gain = 0.000 ; free physical = 162196 ; free virtual = 553763 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=1; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 03:01:00 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/FLASH_IMAGE.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/FLASH_IMAGE.json new file mode 100644 index 0000000..a1bcb1f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/FLASH_IMAGE.json @@ -0,0 +1,9 @@ +{ + "result": "PASS_VIVADO_FLASH_PACK", + "bitstream_sha256": "78d2e703372c13c5044674c8d4eea5b775d6b12771d21df37ba0f90617723c18", + "packed_payload_sha256": "73507c2176800c410699407766caf95f2f5185b4f3fc8c7e74e0d496101ca494", + "flash_image_sha256": "422b45a9af8d43645063c233b737d77a8fab480b687f316e4aaa8d3aace69630", + "configuration_offset": 0, + "software_offset": 4194304, + "flash_bytes": 16777216 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/MANIFEST.json new file mode 100644 index 0000000..a164c4f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/MANIFEST.json @@ -0,0 +1,18 @@ +{ + "payload_bytes": 17409032, + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "lz4_bytes": 3636031, + "flash_image_bytes": 3636063, + "flash_offset": 4194304, + "flash_bytes": 16777216, + "lz4_version": "4.4.5", + "boot_code_bytes": 1256, + "boot_sha256": "267cfb97380f858cafc649356f2514066267822f4f0a1de27e2de3b1a1b979af", + "original_core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "adapted_core_sha256": "67817bf756167acf063e0c65dc2c259d632c4646b43792205d25661bbed7575c", + "only_module_replaced": "TLROM", + "dtb_sha256": "0a19eba1b8112f854f892b3932eb31d25467cc5edb7cee58a132f5d5b4f7ae76", + "dtb_address": "0x11000", + "rom_bytes": 8192, + "payload_crc32": "de4616e3" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/toy_flash.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/toy_flash.log new file mode 100644 index 0000000..4d3e53e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/software/toy_flash.log @@ -0,0 +1,65 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 03:01:08 2026 +# Process ID: 3073685 +# Current directory: /home/yys/codex-builds/toy-a7-flash-20261012 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-flash-20261012/board/make_flash_image.tcl -log /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.log -journal /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.jou -tclargs /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/flash_payload.bin /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.mcs +# Log file: /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.log +# Journal file: /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :897.901 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :586168 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-flash-20261012/board/make_flash_image.tcl +# if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +# lassign $argv bitfile payload output +# set bitfile [file normalize $bitfile] +# set payload [file normalize $payload] +# set output [file normalize $output] +# if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +# if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +# if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +# set f [open $payload rb] +# set magic [read $f 8] +# close $f +# if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +# file mkdir [file dirname $output] +# write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ +# -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +Command: write_cfgmem -force -format mcs -interface SPIx1 -size 16 -loadbit {up 0x00000000 /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit} -loaddata {up 0x00400000 /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/flash_payload.bin} -file /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.mcs +Creating config memory files... +Creating bitstream load up from address 0x00000000 +Loading bitfile /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit +Creating bitstream load up from address 0x00400000 +Loading datafile /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/flash_payload.bin +Writing file /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.mcs +Writing log file /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/toy_flash.prm +=================================== +Configuration Memory information +=================================== +File Format MCS +Interface SPIX1 +Size 16M +Start Address 0x00000000 +End Address 0x00FFFFFF + +Addr1 Addr2 Date File(s) +0x00000000 0x002CB1F7 Oct 12 03:00:59 2026 /home/yys/codex-builds/toy-a7-flash-20261012/build/board-20261012-023749/toy_a7.bit +0x00400000 0x00777B5E Oct 12 02:36:05 2026 /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-boot/flash_payload.bin +0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_cfgmem completed successfully +# puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB +# exit +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 03:01:12 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/README.md b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/README.md new file mode 100644 index 0000000..af10a48 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/README.md @@ -0,0 +1,27 @@ +# Board integration + +Build and programming commands are in [the platform guide](../README.md). +This directory targets Arty A7-100T `xc7a100tcsg324-1` with official Digilent +Rev E.0 DDR parameters. The recorded hardware run passes full payload DDR +readback and Linux checks; physical PCB revision remains unconfirmed. + +- `toy_a7_top.sv`: 100 MHz input, MMCM/BUFG clocks, per-domain reset sequencing, + physical UART/LED/DDR pins, actual MIG and AXI Clock Converter instances. +- `toy_a7_platform.sv`: validated Chisel core, loader/CPU DDR arbitration, + fullwidth memory adapter and SCU console. CPU remains reset until verified RUN. +- `axi_fullwidth.sv`: preserves lanes, strobes, IDs and backpressure while + translating narrow INCR/FIXED beats into aligned 128-bit DDR accesses. +- `ddr_uart_loader.sv` / `loader_axi.sv`: CRC-framed load, readback and release; + acknowledgements wait for DDR responses. INFO bytes preserve LUTRAM inference. +- `axi_scu.sv`: UART/exit MMIO and 256-byte RX FIFO, with accepted-response pops. +- `arty_a7.xdc`: actual pins and targeted asynchronous I/O/reset exceptions; + DDR data/address/control and internal CPU timing remain checked. +- `build_board.tcl`: complete IP generation, synthesis, placement, routing and + bitstream. Setup/hold, CDC Critical, bus skew, routing errors and DRC errors + stop the build. No warning severity downgrade or CDC waiver is applied. +- `program_arty.tcl`: explicit volatile JTAG programming; exactly one target + and one XC7A100T required. The platform's `../program.tcl` entry delegates here. + The exact script used for first bring-up is also archived with the hardware logs. + +`vendor/` contains unmodified pinned Digilent MIG/board inputs and their license. +Vivado generates proprietary vendor IP into ignored build directories locally. diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/arty_a7.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/backup_flash.tcl new file mode 100644 index 0000000..7c44264 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/backup_flash.tcl @@ -0,0 +1,32 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/build_board.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/build_board.tcl new file mode 100644 index 0000000..93159c2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/build_board.tcl @@ -0,0 +1,86 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +set flash 0 +if {[llength $argv]==2} { + if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} + set flash 1 +} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { + read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +} +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +read_xdc $root/board/flash_boot.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_boot.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_boot.xdc new file mode 100644 index 0000000..51827b7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_boot.xdc @@ -0,0 +1,17 @@ +# Digilent Arty-A7-100-Master.xdc Rev D/E; CCLK is owned by STARTUPE2. +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports flash_cs_n] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports flash_mosi] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports flash_miso] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports flash_wp_n] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports flash_hold_n] +set_property DRIVE 8 [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property SLEW SLOW [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_false_path -from [get_ports sw0] -to [get_pins -hier -filter {NAME =~ *sw_meta_reg/D}] +# Serial input sampled after two synchronizer stages. Mode-0 half bit is 160 ns; +# the external data settles before these stages, then is sampled on the next rise. +set_false_path -from [get_ports flash_miso] -to [get_pins -hier -filter {NAME =~ *miso_meta_reg/D}] +set_false_path -to [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/make_flash_image.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/make_flash_image.tcl new file mode 100644 index 0000000..ad0a6d6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/make_flash_image.tcl @@ -0,0 +1,18 @@ +# Combine configuration and packed software without crossing partitions. +if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +lassign $argv bitfile payload output +set bitfile [file normalize $bitfile] +set payload [file normalize $payload] +set output [file normalize $output] +if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +set f [open $payload rb] +set magic [read $f 8] +close $f +if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +file mkdir [file dirname $output] +write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ + -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_arty.tcl new file mode 100644 index 0000000..f70f054 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +program_hw_devices $device +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_flash.tcl new file mode 100644 index 0000000..82a6c4f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/program_flash.tcl @@ -0,0 +1,51 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +program_hw_cfgmem $memory +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..e26d6dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/License.txt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/License.txt new file mode 100644 index 0000000..b76cf0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/License.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Digilent, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/board.xml b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Pullups to enable shield I2C + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 4 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 256 MB DDR3L memory SODIMM + + + + + + + DIP Switches 3 to 0 + + + PHY Ethernet on the board + + + + + + + + + + + Shield i2c + + + Shield i2c pullups, must pull high if using the shield I2C on J3 + + + LEDs 3 to 0 + + + Push buttons 3 to 0 + + + 16 MB of nonvolatile storage that can be used for configuration or data storage + + + CPU Reset Push Button, active low + + + RGB leds 12 to 0 (3 per LED) + + + Shield pins 0 through 19 + + + Shield pins 26 through 41 + + + Shield SPI + + + 3.3V Single-Ended 100MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/mig.prj b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/mig.prj new file mode 100644 index 0000000..1bff709 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a100t-csg324/-1 + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/part0_pins.xml b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/part0_pins.xml new file mode 100644 index 0000000..dc32e54 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/part0_pins.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/preset.xml b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/preset.xml new file mode 100644 index 0000000..ec20fb4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/board/vendor/preset.xml @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/build.sh b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/build.sh new file mode 100644 index 0000000..a0f57a6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/build.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +mkdir -p build/flash-boot +cross="${CROSS_COMPILE:-riscv64-linux-gnu-}" +"${cross}gcc" -march=rv64imac_zicsr_zifencei -mabi=lp64 -mcmodel=medany \ + -Os -ffreestanding -fno-builtin -fno-pic -fno-stack-protector -msmall-data-limit=0 \ + -nostdlib -static -Wl,--build-id=none -Wl,-T,boot/flash.ld \ + boot/flash_start.S boot/flash_boot.c -o build/flash-boot/boot.elf +"${cross}objcopy" -O binary build/flash-boot/boot.elf build/flash-boot/boot.bin +"${cross}objdump" -d build/flash-boot/boot.elf > build/flash-boot/boot.dis +"${cross}size" build/flash-boot/boot.elf diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash.ld b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash.ld new file mode 100644 index 0000000..c8c0942 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash.ld @@ -0,0 +1,11 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS { + . = 0x10000; + .text : { *(.text.start) *(.text*) *(.rodata*) } + ASSERT(. <= 0x11000, "Flash boot code exceeds 4 KiB") + .data : { *(.data*) *(.sdata*) } + .bss : { *(.bss*) *(.sbss*) *(COMMON) } + ASSERT(SIZEOF(.data) == 0 && SIZEOF(.bss) == 0, "Boot ROM must not have writable globals") + /DISCARD/ : { *(.comment) *(.eh_frame*) *(.riscv.attributes) } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_boot.c b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_boot.c new file mode 100644 index 0000000..abba384 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_boot.c @@ -0,0 +1,114 @@ +// LZ4 block reader, bounds checks and CRC before jumping to unchanged OpenSBI. +#include +#define REG8(a) (*(volatile uint8_t *)(uintptr_t)(a)) +#define FLASH_OFFSET 0x400000u +#define FLASH_AVAILABLE 0xc00000u +#define MAX_OUTPUT 0x0f000000u // Exclude the top DDR region used for this stack. + +static void text(const char *s) { + while (*s) REG8(0x60020000) = (uint8_t)*s++; +} +static void hex(unsigned value) { + static const char digits[]="0123456789abcdef"; + REG8(0x60020000)=digits[(value >> 4) & 15]; + REG8(0x60020000)=digits[value & 15]; +} +static void fail(void) { + REG8(0x6002000c) = 1; + text("FAIL FLASH_BOOT\n"); + *(volatile uint64_t *)0x60000000 = 0xbad0f101; + for (;;) __asm__ volatile("wfi"); +} +static uint8_t spi(uint8_t value) { + REG8(0x60020008) = value; + unsigned timeout = 100000; + while (REG8(0x60020009) & 1) if (!--timeout) fail(); + return REG8(0x60020008); +} +static uint32_t crc_byte(uint32_t crc, uint8_t value) { + // Nibble lookup saves time without a 1 KiB CRC table in the boot ROM. + static const uint32_t table[16] = { + 0x00000000,0x1db71064,0x3b6e20c8,0x26d930ac, + 0x76dc4190,0x6b6b51f4,0x4db26158,0x5005713c, + 0xedb88320,0xf00f9344,0xd6d6a3e8,0xcb61b38c, + 0x9b64c2b0,0x86d3d2d4,0xa00ae278,0xbdbdf21c + }; + crc ^= value; + crc = (crc >> 4) ^ table[crc & 15]; + return (crc >> 4) ^ table[crc & 15]; +} +static uint8_t get(unsigned *remaining) { + if (!*remaining) fail(); + --*remaining; + return spi(0xff); +} +static unsigned length(unsigned initial, unsigned *remaining) { + if (initial == 15) { + unsigned more; + do { + more = get(remaining); + if (initial > MAX_OUTPUT - more) fail(); + initial += more; + } while (more == 255); + } + return initial; +} +static void launch(void) __attribute__((noreturn)); +static void launch(void) { + __asm__ volatile( + "fence rw,rw\n fence.i\n csrr a0,mhartid\n li a1,0x11000\n" + "li t0,0x1800\n csrs mstatus,t0\n li t0,0x80000000\n csrw mepc,t0\n mret\n" + ::: "a0","a1","t0","memory"); + __builtin_unreachable(); +} +void flash_main(void) { + if (!REG8(0x6002000a)) launch(); // SW0 high: original UART load/RUN recovery. + text("TOY FLASH_BOOT\n"); + // Exercise STARTUPE2 CCLK takeover with CS high before sending commands. + REG8(0x6002000c) = 1; + spi(0xff); spi(0xff); + REG8(0x6002000c) = 0; + spi(0x9f); + unsigned manufacturer = spi(0xff), type = spi(0xff), capacity = spi(0xff); + text("FLASH_ID ");hex(manufacturer);hex(type);hex(capacity);text("\n"); + REG8(0x6002000c) = 1; + if (!((manufacturer == 0x01 && type == 0x20) || + (manufacturer == 0x20 && type == 0xba)) || capacity != 0x18) fail(); + REG8(0x6002000c) = 0; + spi(0x03); spi(FLASH_OFFSET >> 16); spi(0); spi(0); + uint32_t header[8]; + uint32_t hcrc = ~0u; + for (unsigned i = 0; i < 8; ++i) { + uint32_t word = 0; + for (unsigned b = 0; b < 4; ++b) { + uint8_t v = spi(0xff); + word |= (uint32_t)v << (b * 8); + if (i < 7) hcrc = crc_byte(hcrc, v); + } + header[i] = word; + } + if (header[0] != 0x46594f54 || header[1] != 0x00345a4c || header[2] != 1 || + !header[3] || header[3] > FLASH_AVAILABLE - 32 || !header[4] || + header[4] > MAX_OUTPUT || header[6] || header[7] != ~hcrc) fail(); + unsigned remaining = header[3], produced = 0; + uint8_t *out = (uint8_t *)(uintptr_t)0x80000000; + while (remaining) { + unsigned token = get(&remaining); + unsigned count = length(token >> 4, &remaining); + if (count > remaining || count > header[4] - produced) fail(); + while (count--) out[produced++] = get(&remaining); + if (!remaining) break; + unsigned offset = get(&remaining); + offset |= (unsigned)get(&remaining) << 8; + count = length(token & 15, &remaining) + 4; + if (!offset || offset > produced || count > header[4] - produced) fail(); + while (count--) { out[produced] = out[produced - offset]; ++produced; } + } + REG8(0x6002000c) = 1; + if (produced != header[4]) fail(); + uint32_t crc = ~0u; + for (unsigned i = 0; i < produced; ++i) crc = crc_byte(crc, out[i]); + if (~crc != header[5]) fail(); + text("PASS FLASH_PAYLOAD_CRC\n"); + launch(); +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_start.S b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_start.S new file mode 100644 index 0000000..da83474 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/flash_start.S @@ -0,0 +1,16 @@ +.option norelax +.section .text.start,"ax",@progbits +.globl _start +_start: + li sp, 0x8ffff000 + la t0, trap + csrw mtvec, t0 + csrw mie, zero + li t0, 8 + csrc mstatus, t0 + call flash_main +trap: + li t0, 0x60000000 + li t1, 0xbad0f100 + sd t1, 0(t0) +1: j 1b diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/requirements.txt b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/requirements.txt new file mode 100644 index 0000000..7eb4011 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/boot/requirements.txt @@ -0,0 +1 @@ +lz4==4.4.5 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/flash.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/flash.py new file mode 100644 index 0000000..421e163 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/flash.py @@ -0,0 +1,164 @@ +"""Back up/program/verify Flash and check automatic Linux startup, within 1 hour.""" + +import argparse +from datetime import datetime +import hashlib +import json +from pathlib import Path +import subprocess +import shutil +import time + +from observe_flash_boot import Observer + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", type=Path, required=True) + p.add_argument( + "--payload", + type=Path, + required=True, + help="Packed TOYFLZ4 software, not the raw image", + ) + p.add_argument("--part", required=True) + p.add_argument( + "--mcs", + type=Path, + help="Existing Vivado-packed image if the programming host lacks Artix build support", + ) + p.add_argument("--port", required=True) + p.add_argument("--out", type=Path) + args = p.parse_args() + bit = args.bitstream.resolve() + payload = args.payload.resolve() + out = args.out or ROOT / "build" / ( + "flash-program-" + datetime.now().strftime("%Y%m%d-%H%M%S") + ) + out = out.resolve() + out.mkdir(parents=True, exist_ok=False) + image = out / "toy_flash.mcs" + backup = out / "flash-before.bin" + commands = [ + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out / "image.log"), + "-journal", + str(out / "image.jou"), + "-tclargs", + str(bit), + str(payload), + str(image), + ], + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/program_flash.tcl"), + "-log", + str(out / "program.log"), + "-journal", + str(out / "program.jou"), + "-tclargs", + str(image), + args.part, + str(backup), + ], + ] + if args.mcs: + packed_record = json.loads( + args.mcs.with_suffix(args.mcs.suffix + ".json").read_text() + ) + assert packed_record["result"] == "PASS_VIVADO_FLASH_PACK" + assert packed_record["bitstream_sha256"] == sha(bit) + assert packed_record["packed_payload_sha256"] == sha(payload) + assert packed_record["flash_image_sha256"] == sha(args.mcs) + shutil.copy2(args.mcs.resolve(), image) + commands[0] = None + record = dict( + status="RUNNING", + timeout_seconds=3600, + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + part=args.part, + port=args.port, + started_at=datetime.now().astimezone().isoformat(), + commands=commands, + ) + result = out / "RESULT.json" + result.write_text(json.dumps(record, indent=2) + "\n") + started = time.monotonic() + watcher = None + try: + for i, command in enumerate(commands): + if command is None: + print("USING_PREPACKED_FLASH_IMAGE", sha(image), flush=True) + continue + if i == 1: + watcher = Observer(args.port, out / "linux-console.log", timeout=3600) + watcher.start() + with (out / f"command-{i}.log").open("w") as log: + proc = subprocess.Popen( + command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT + ) + try: + code = proc.wait( + timeout=max(1, 3600 - (time.monotonic() - started)) + ) + except subprocess.TimeoutExpired: + if __import__("os").name == "nt": + subprocess.run( + ["taskkill", "/PID", str(proc.pid), "/T", "/F"], + capture_output=True, + ) + else: + proc.kill() + proc.wait() + raise + if code: + raise RuntimeError( + f"Vivado command {i} failed with {code}; inspect {out}" + ) + print("PASS FLASH_STAGE", i, flush=True) + # Program completion may precede CPU decompression; cap the remaining wait. + watcher.thread.join(timeout=max(1, 3600 - (time.monotonic() - started))) + if watcher.thread.is_alive(): + raise TimeoutError("One-hour Flash/Linux timeout") + hardware = watcher.finish() + record.update( + status="PASS", + hardware=hardware, + backup_sha256=sha(backup), + backup_bytes=backup.stat().st_size, + flash_image_sha256=sha(image), + ) + except Exception as error: + record.update(status="FAILED", error=str(error)) + raise + finally: + if watcher is not None: + watcher.stop.set() + watcher.thread.join(timeout=6) + record.update( + elapsed_seconds=round(time.monotonic() - started, 3), + finished_at=datetime.now().astimezone().isoformat(), + ) + result.write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/observe_flash_boot.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/observe_flash_boot.py new file mode 100644 index 0000000..3473bb5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/host/observe_flash_boot.py @@ -0,0 +1,157 @@ +"""Observe autonomous Flash/Linux startup, including an optional USB power cycle.""" + +import argparse +from datetime import datetime, timezone +import json +from pathlib import Path +import re +import threading +import time + +CHECKS = ( + b"PASS VM_COPY_ON_WRITE", + b"PASS VM_PAGE_PROTECTION", + b"PASS FP64_PROCESS_CONTEXT", + b"PASS LINUX_TIMER", + b"PASS LINUX_SYSTEM_CHECK", +) + + +class Observer: + def __init__(self, port, transcript, timeout=600, require_disconnect=False): + self.port = port + self.transcript = Path(transcript) + self.timeout = timeout + self.require_disconnect = require_disconnect + self.result = None + self.disconnections = 0 + self.stop = threading.Event() + self.thread = threading.Thread(target=self.run, daemon=True) + + def run(self): + import serial + + deadline = time.monotonic() + self.timeout + started = time.monotonic() + active = not self.require_disconnect + data = bytearray() + sent = False + connection = None + self.transcript.parent.mkdir(parents=True, exist_ok=True) + with self.transcript.open("wb") as log: + try: + while time.monotonic() < deadline and not self.stop.is_set(): + try: + if connection is None: + connection = serial.Serial( + self.port, + 1000000, + timeout=0.1, + write_timeout=5, + rtscts=False, + dsrdtr=False, + ) + connection.reset_input_buffer() + chunk = connection.read(max(1, connection.in_waiting)) + if not chunk: + continue + log.write(chunk) + log.flush() + if not active: + continue + data.extend(chunk) + if b"FAIL FLASH_BOOT" in data or b"Kernel panic" in data: + raise RuntimeError( + "Flash startup or Linux failed; inspect the UART log" + ) + if ( + not sent + and b"PASS FLASH_PAYLOAD_CRC" in data + and b"OpenSBI" in data + and b"~ # " in data + ): + connection.write( + b"/root/linux_system_check-linux; echo FLASH_LINUX_RC:$?\n" + ) + connection.flush() + sent = True + print("FLASH_LINUX_CHECK_SENT", flush=True) + if ( + sent + and re.search(rb"(?:^|\n)FLASH_LINUX_RC:0\r?\n", data) + and all(m in data for m in CHECKS) + ): + self.result = dict( + result="PASS_FLASH_LINUX", + checks=[m.decode() for m in CHECKS], + exit_status=0, + usb_disconnections=self.disconnections, + disconnect_required=self.require_disconnect, + elapsed_seconds=round(time.monotonic() - started, 3), + recorded_at=datetime.now(timezone.utc).isoformat(), + port=self.port, + transcript=str(self.transcript), + ) + print("PASS FLASH_LINUX_UART_CHECKS", flush=True) + break + except (serial.SerialException, OSError): + if connection is not None: + connection.close() + connection = None + self.disconnections += 1 + active = True + data.clear() + sent = False + log.write(b"\nOBSERVER_USB_DISCONNECTED\n") + log.flush() + print("OBSERVER_USB_DISCONNECTED", flush=True) + self.stop.wait(0.2) + if self.result is None: + raise TimeoutError( + "No complete autonomous Flash/Linux pass before the timeout" + ) + except Exception as error: + self.result = dict( + result="FAILED", + error=str(error), + usb_disconnections=self.disconnections, + port=self.port, + ) + finally: + if connection is not None: + connection.close() + self.transcript.with_suffix(".json").write_text( + json.dumps(self.result, indent=2) + "\n" + ) + + def start(self): + self.thread.start() + + def finish(self): + self.thread.join() + if not self.result or self.result["result"] != "PASS_FLASH_LINUX": + raise RuntimeError(self.result) + return self.result + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--port", required=True) + p.add_argument("--transcript", type=Path, required=True) + p.add_argument("--timeout", type=int, default=600) + p.add_argument( + "--require-disconnect", + action="store_true", + help="Ignore the current session; wait for USB removal and a new boot", + ) + args = p.parse_args() + watcher = Observer( + args.port, args.transcript, args.timeout, args.require_disconnect + ) + watcher.start() + print("OBSERVER_ARMED", flush=True) + print(json.dumps(watcher.finish(), indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_board_uart_boot.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_board_uart_boot.py new file mode 100644 index 0000000..92be1b1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_board_uart_boot.py @@ -0,0 +1,162 @@ +"""Load, byte-verify and boot the original CPU oracle through actual UART RTL. + +Only the external DDR PHY is replaced with the stalled AXI memory model. No +testbench override releases the CPU and no initial image is put into DDR. +""" +import hashlib +import argparse +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/board-uart-boot" + +UART = r''' + reg [7:0] firmware[0:PROGRAM_BYTES-1]; + reg [7:0] reply_bytes[0:511]; + integer received=0; + reg run_requested=0; + initial $readmemh("program.hex",firmware); + // Independent receiver observes real TX transitions, not tx_valid/data. + always begin : receiver + reg [7:0] value; + @(negedge uart_tx_out); + repeat(37) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + value[bit_index]=uart_tx_out;repeat(25) @(negedge clk); + end + if(uart_tx_out!==1) $fatal(1,"UART TX framing error"); + if(!cpu_run) begin + if(received>=512) $fatal(1,"UART reply overflow"); + reply_bytes[received]=value;received=received+1; + end + end + always @(posedge clk) if(!reset && cpu_run && !run_requested) + $fatal(1,"CPU released before verified RUN request"); + function automatic [15:0] crc_step(input [15:0] previous,input [7:0] value); + reg [15:0] crc; + begin + crc=previous; + for(integer bit_index=7;bit_index>=0;bit_index=bit_index-1) + crc=(crc<<1)^((crc[15]^value[bit_index]) ? 16'h1021 : 16'd0); + crc_step=crc; + end + endfunction + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + uart_rx_in=value[bit_index];repeat(25) @(negedge clk); + end + uart_rx_in=1;repeat(25) @(negedge clk); + endtask + task automatic request(input [7:0] op,input integer offset,length,input bit corrupt); + reg [15:0] crc;reg [31:0] address;reg [7:0] value; + begin + received=0;crc=16'hffff;address=32'h80000000+offset; + send_byte(8'ha5);send_byte(8'h5a); + send_byte(op);crc=crc_step(crc,op); + send_byte(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(8*n);send_byte(value);crc=crc_step(crc,value); + end + value=length&255;send_byte(value);crc=crc_step(crc,value); + value=(length>>8)&255;send_byte(value);crc=crc_step(crc,value); + if(op==1) for(integer n=0;n=length+9); + if(reply_bytes[0]!==8'h5a || reply_bytes[1]!==8'ha5 || reply_bytes[2]!==(op|8'h80) || + reply_bytes[3]!==8'h37 || reply_bytes[4]!==status || {reply_bytes[6],reply_bytes[5]}!==length) + $fatal(1,"UART reply header/status op=%h status=%h count=%0d",op,reply_bytes[4],received); + crc=16'hffff; + for(integer n=2;n256) count=256; + request(1,offset,count,0);reply(1,0,0); + request(2,offset,count,0);reply(2,0,count); + for(integer n=0;n4000000", "cycles>120000000") + bench = bench.replace("endmodule", f" localparam PROGRAM_BYTES={len(data)};\n" + UART + "\nendmodule") + path = OUT / "tb_board_uart_boot.sv" + path.write_text(bench) + core=ROOT/("build/flash-boot/ToyLinuxChip.sv" if args.flash_recovery else "build/serial-bound/ToyLinuxChip.sv") + files = [core, ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", path] + files += [p for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run(["verilator", "--binary", "--timing", "-j", "8", "-Wno-fatal", "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_board_uart_boot", "--Mdir", str(OUT / "obj")] + + [str(p) for p in files], stdout=log, stderr=log, check=True, timeout=900,cwd=ROOT) + if args.flash_recovery: + # The bound ROM's readmemh path is relative to the platform directory. + import shutil + (OUT/"build/flash-boot").mkdir(parents=True,exist_ok=True) + shutil.copy2(ROOT/"build/flash-boot/bootrom.hex",OUT/"build/flash-boot/bootrom.hex") + with (OUT / "simulation.log").open("w") as log: + result = subprocess.run([str(OUT / "obj/Vtb_board_uart_boot")], cwd=OUT, + stdout=log, stderr=log, timeout=1200) + result.check_returncode() + transcript = (OUT / "simulation.log").read_text() + for marker in ("PASS UART_PAYLOAD_READBACK", "PASS UART_VERIFIED_RUN", "PASS CPU Sv39/FPU/AMO/cache/interrupt"): + assert marker in transcript, marker + record = dict(result="PASS_UART_LOAD_VERIFY_BOOT", binary_sha256=hashlib.sha256(data).hexdigest(), + bytes_verified=len(data), testbench_cpu_release_override=False, preloaded_ddr_image=False, + physical_mig_simulated=False, physical_board_tested=False, + flash_rom_recovery=args.flash_recovery, + cycles=int(re.search(r"through board AXI/SCU cycles=(\d+)", transcript)[1])) + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_flash_boot.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_flash_boot.py new file mode 100644 index 0000000..fbfa17f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/check_flash_boot.py @@ -0,0 +1,182 @@ +"""Real CPU executes ROM -> serial Flash -> decompression -> original oracle. + +DDR starts empty; no forced RUN or CPU reset bypass. SPI Flash and DDR PHY are +simulation models. Two corrupted images must halt in ROM without launching. +""" + +import argparse +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/flash-regression" + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument( + "--image", type=Path, required=True, help="Packed original CPU smoke image" + ) + p.add_argument("--skip-build", action="store_true") + args = p.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + image = args.image.read_bytes() + (OUT / "flash.hex").write_text("\n".join(f"{b:02x}" for b in image) + "\n") + text = (ROOT / "board/toy_a7_platform.sv").read_text() + header = text.split(") (", 1)[1].split(");", 1)[0] + signals = [] + direction, width = None, "" + for part in header.split(","): + m = re.fullmatch( + r"\s*(?:(input|output)\s+wire\s+)?(\[[^]]+\]\s*)?(\w+)\s*", part + ) + assert m, part + if m[1]: + direction, width = m[1], m[2] or "" + signals.append((direction, width, m[3])) + lines = [ + "`timescale 1ns/1ps", + "module tb_flash_boot;", + " reg clk=0;always #20 clk=~clk;", + " reg reset=1;", + " wire uart_rx_in=1,flash_recovery=0;", + ] + for _, width, name in signals: + if name not in ("clk", "reset", "uart_rx_in", "flash_recovery"): + lines.append(f" wire {width}{name};") + lines += [ + " toy_a7_platform #(.FLASH_BOOT(1)) platform(.*);", + " initial begin repeat(10) @(negedge clk);reset=0;end", + f' spi_flash_model #(.BYTES({len(image)}),.IMAGE("{OUT}/flash.hex")) flash', + " (.sck(flash_sck),.cs_n(flash_cs_n),.mosi(flash_mosi),.miso(flash_miso));", + " integer cycles=0;reg [255:0] tail=0;reg verified=0;", + " always @(posedge clk) if(!reset) begin", + " cycles<=cycles+1;", + " if(platform.mmio_tx_valid && platform.tx_ready) begin", + ' $write("%c",platform.mmio_tx_data);$fflush();', + " tail={tail[247:0],platform.mmio_tx_data};", + ' if(tail[175:0]=="PASS FLASH_PAYLOAD_CRC") verified=1;', + " end", + " if(exited && exit_code==32'h600d600d) begin", + ' if(!verified) $fatal(1,"Oracle ran before verified Flash payload");', + ' if($test$plusargs("bad_header") || $test$plusargs("bad_payload")) $fatal(1,"Corrupted image launched");', + ' $display("PASS FLASH_CPU_ORACLE cycles=%0d",cycles);$finish;end', + " if(exited && exit_code==32'hbad0f101) begin", + ' if(!$test$plusargs("bad_header") && !$test$plusargs("bad_payload")) $fatal(1,"Valid image rejected");', + ' if(verified) $fatal(1,"Corrupt image reported verified");', + ' $display("PASS FLASH_CORRUPTION_REJECTED cycles=%0d",cycles);$finish;end', + " if(exited && (exit_code & 32'hffff0000)==32'hbad00000 && exit_code!=32'hbad0f101)", + ' $fatal(1,"CPU/ROM trap %h",exit_code);', + ' if(cycles>40000000) $fatal(1,"Flash boot watchdog");', + " end", + ] + mapping = { + "awid": "aw_bits_id", + "awaddr": "aw_bits_addr", + "awlen": "aw_bits_len", + "awsize": "aw_bits_size", + "awburst": "aw_bits_burst", + "wdata": "w_bits_data", + "wstrb": "w_bits_strb", + "wlast": "w_bits_last", + "bid": "b_bits_id", + "bresp": "b_bits_resp", + "arid": "ar_bits_id", + "araddr": "ar_bits_addr", + "arlen": "ar_bits_len", + "arsize": "ar_bits_size", + "arburst": "ar_bits_burst", + "rid": "r_bits_id", + "rdata": "r_bits_data", + "rresp": "r_bits_resp", + "rlast": "r_bits_last", + } + connections = [".clock(clk)", ".reset(reset)"] + for _, _, name in signals: + if name.startswith("ddr_"): + s = name[4:] + connections.append( + f".{mapping.get(s,s.replace('ready','_ready').replace('valid','_valid'))}({name})" + ) + lines += [ + " axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(268435456)) memory (", + " " + ",\n ".join(connections) + "\n );", + "endmodule", + ] + bench = OUT / "tb_flash_boot.sv" + bench.write_text("\n".join(lines) + "\n") + if not args.skip_build: + files = [ + ROOT / "build/flash-boot/ToyLinuxChip.sv", + ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", + ROOT / "tests/spi_flash_model.sv", + bench, + ] + files += [f for f in (ROOT / "board").glob("*.sv") if f.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "-j", + "8", + "-Wno-fatal", + "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", + "--top-module", + "tb_flash_boot", + "--Mdir", + str(OUT / "obj"), + ] + + [str(f) for f in files], + stdout=log, + stderr=log, + check=True, + timeout=900, + cwd=ROOT, + ) + results = {} + for case in ("valid", "bad_header", "bad_payload"): + command = [str(OUT / "obj/Vtb_flash_boot")] + if case != "valid": + command.append("+" + case) + with (OUT / (case + ".log")).open("w") as log: + subprocess.run( + command, + cwd=ROOT, + stdout=log, + stderr=subprocess.STDOUT, + check=True, + timeout=300, + ) + output = (OUT / (case + ".log")).read_text() + print(output) + marker = ( + "PASS FLASH_CPU_ORACLE" + if case == "valid" + else "PASS FLASH_CORRUPTION_REJECTED" + ) + assert marker in output + results[case] = int(re.search(r"cycles=(\d+)", output)[1]) + (OUT / "RESULT.json").write_text( + json.dumps( + dict( + result="PASS", + cycles=results, + empty_ddr=True, + original_cpu_oracle=True, + forced_run=False, + physical_flash_tested=False, + ), + indent=2, + ) + + "\n" + ) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/prepare_flash_boot.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/prepare_flash_boot.py new file mode 100644 index 0000000..0fed787 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/prepare_flash_boot.py @@ -0,0 +1,123 @@ +"""Pack an unchanged payload as LZ4 and bind only the boot-ROM module. + +The 4 MiB configuration partition and 12 MiB software partition cannot overlap. +Dependencies: lz4==4.4.5. Compile boot/flash_boot.c and flash_start.S separately. +""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import struct +import zlib + +ROOT = Path(__file__).resolve().parents[1] +CORE_SHA = "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(data): + return hashlib.sha256(data).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--payload", type=Path, required=True) + p.add_argument("--boot-bin", type=Path, required=True) + p.add_argument( + "--core", type=Path, default=ROOT / "build/serial-bound/ToyLinuxChip.sv" + ) + p.add_argument("--out", type=Path, default=ROOT / "build/flash-boot") + args = p.parse_args() + import lz4 + import lz4.block + + raw = args.payload.read_bytes() + if not 0 < len(raw) <= 0x0F000000: + raise ValueError("Payload overlaps the boot stack reservation") + packed = lz4.block.compress( + raw, mode="high_compression", compression=12, store_size=False + ) + assert lz4.block.decompress(packed, uncompressed_size=len(raw)) == raw + head = struct.pack( + "<8s5I", b"TOYFLZ4\0", 1, len(packed), len(raw), zlib.crc32(raw), 0 + ) + image = head + struct.pack(" 0xC00000: + raise ValueError("Compressed software exceeds the 12 MiB partition") + original_bytes = args.core.read_bytes() + assert ( + sha(original_bytes) == CORE_SHA + ), "Unexpected core: use the pinned validated generation" + original = original_bytes.decode() + matches = list(re.finditer(r"^module TLROM\(.*?^endmodule", original, re.M | re.S)) + assert len(matches) == 1 + m = matches[0] + original_rom = m.group() + words = re.findall(r"64'h([0-9A-Fa-f]+)", original_rom.split("TLMonitor")[0]) + rom_bytes = b"".join(int(w, 16).to_bytes(8, "little") for w in words[::-1]) + dtb_start = rom_bytes.index(bytes.fromhex("d00dfeed")) + dtb_size = int.from_bytes(rom_bytes[dtb_start + 4 : dtb_start + 8], "big") + dtb = rom_bytes[dtb_start : dtb_start + dtb_size] + assert len(dtb) == dtb_size and dtb_size <= 4096 + boot = args.boot_bin.read_bytes() + assert 0 < len(boot) <= 4096 + rom = boot.ljust(4096, b"\0") + dtb.ljust(4096, b"\0") + replacement = original_rom.split(");", 1)[0] + """ +); + (* rom_style="block" *) reg [63:0] contents [0:1023]; + initial $readmemh("build/flash-boot/bootrom.hex", contents); + reg valid; + reg [1:0] response_size; + reg [6:0] response_source; + reg [63:0] response_data; + assign auto_in_a_ready=!valid || auto_in_d_ready; + assign auto_in_d_valid=valid; + assign auto_in_d_bits_size=response_size; + assign auto_in_d_bits_source=response_source; + assign auto_in_d_bits_data=response_data; + always @(posedge clock) begin + if(reset) valid<=0; + else if(auto_in_a_ready) valid<=auto_in_a_valid; + if(auto_in_a_ready && auto_in_a_valid) begin + response_size<=auto_in_a_bits_size;response_source<=auto_in_a_bits_source; + response_data<=|auto_in_a_bits_address[15:13] ? 64'd0 : contents[auto_in_a_bits_address[12:3]]; + end + end +endmodule""" + adapted = original[: m.start()] + replacement + original[m.end() :] + assert adapted.replace(replacement, original_rom, 1) == original + args.out.mkdir(parents=True, exist_ok=True) + (args.out / "flash_payload.bin").write_bytes(image) + (args.out / "bootrom.hex").write_text( + "\n".join( + f"{int.from_bytes(rom[i:i+8], 'little'):016x}" + for i in range(0, len(rom), 8) + ) + + "\n" + ) + (args.out / "ToyLinuxChip.sv").write_text(adapted, encoding="utf-8", newline="\n") + record = dict( + payload_bytes=len(raw), + payload_sha256=sha(raw), + lz4_bytes=len(packed), + flash_image_bytes=len(image), + flash_offset=0x400000, + flash_bytes=0x1000000, + lz4_version=lz4.__version__, + boot_code_bytes=len(boot), + boot_sha256=sha(boot), + original_core_sha256=sha(original_bytes), + adapted_core_sha256=sha(adapted.encode()), + only_module_replaced="TLROM", + dtb_sha256=sha(dtb), + dtb_address="0x11000", + rom_bytes=len(rom), + payload_crc32=f"{zlib.crc32(raw):08x}", + ) + (args.out / "MANIFEST.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/start_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/start_board_build.py new file mode 100644 index 0000000..a8c7b7a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/scripts/start_board_build.py @@ -0,0 +1,92 @@ +"""Run the complete board flow in isolation with a one-hour hard timeout.""" +from datetime import datetime, timedelta, timezone +import argparse +import hashlib +import json +import os +from pathlib import Path +import subprocess +import sys +import time + +ROOT=Path(__file__).resolve().parents[1] +TZ=timezone(timedelta(hours=8)) +EXPECTED="4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def save(path, record): + temp=path.with_suffix(".tmp") + temp.write_text(json.dumps(record,indent=2)+"\n",encoding="utf-8") + temp.replace(path) + + +def worker(out): + manifest=out/"RUN.json" + record=json.loads(manifest.read_text()) + now=datetime.now(TZ) + script=Path(record.get("execution_script",str(ROOT/"board/build_board.tcl"))) + if "execution_script_sha256" in record: + assert sha(script)==record["execution_script_sha256"] + command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), + "-mode","batch","-source",str(script), + "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + if record.get("flash_boot"): + command.append("flash") + record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), + command=command,worker_pid=os.getpid()) + started=time.monotonic() + try: + with (out/"console.log").open("w") as log: + p=subprocess.Popen(command,cwd=ROOT,stdin=subprocess.DEVNULL,stdout=log, + stderr=subprocess.STDOUT,start_new_session=True) + record["timeout_process_pid"]=p.pid + save(manifest,record) + code=p.wait() + record.update(exit_code=code,status="TIMED_OUT" if code in (124,137) else "COMPLETED" if code==0 else "FAILED") + except Exception as e: + record.update(status="LAUNCH_FAILED",error=str(e)) + record.update(elapsed_seconds=time.monotonic()-started,finished_at=datetime.now(TZ).isoformat(), + core_unchanged=sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED, + bitstream_generated=(out/"toy_a7.bit").is_file()) + save(manifest,record) + + +def main(): + p=argparse.ArgumentParser(description=__doc__) + p.add_argument("--worker",type=Path) + p.add_argument("--flash",action="store_true",help="Use the validated Flash boot ROM and SPI port") + args=p.parse_args() + if args.worker: + worker(args.worker.resolve());return + assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + if args.flash: + flash_manifest=json.loads((ROOT/"build/flash-boot/MANIFEST.json").read_text()) + assert flash_manifest["original_core_sha256"]==EXPECTED + assert sha(ROOT/"build/flash-boot/ToyLinuxChip.sv")==flash_manifest["adapted_core_sha256"] + for path in (ROOT/"build").glob("board-*/RUN.json"): + assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" + out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + # Snapshot the exact board sources used by this attempt, including failures. + import shutil + shutil.copytree(ROOT/"board",out/"inputs/board") + files={str(p.relative_to(ROOT)):sha(p) for p in (ROOT/"board").rglob("*") if p.is_file()} + record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, + output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, + board_sources=files,core_clock_hz=25000000,uart_baud=1000000, + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False, + flash_boot=args.flash) + save(out/"RUN.json",record) + with (out/"launcher.log").open("w") as log: + p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], + cwd=ROOT,stdout=log,stderr=subprocess.STDOUT,stdin=subprocess.DEVNULL, + start_new_session=True,close_fds=True) + print(json.dumps({"output_directory":str(out),"worker_pid":p.pid,"timeout_seconds":3600})) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/tests/spi_flash_model.sv b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/tests/spi_flash_model.sv new file mode 100644 index 0000000..477b37f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/sources/tests/spi_flash_model.sv @@ -0,0 +1,42 @@ +// Simulation-only standard 03h read / 9fh JEDEC model, no Flash writes. +module spi_flash_model #(parameter BYTES=1024, parameter IMAGE="flash.hex") ( + input wire sck, cs_n, mosi, output reg miso=1 +); + reg [7:0] contents [0:BYTES-1]; + reg [7:0] received; + integer bit_count=0, state=0, address_bytes=0, address=0, id_index=0; + reg [7:0] command; + reg [7:0] response; + initial begin + $readmemh(IMAGE,contents); + if($test$plusargs("bad_header")) contents[0]=contents[0]^1; + if($test$plusargs("bad_payload")) contents[BYTES-1]=contents[BYTES-1]^1; + end + always @(posedge sck or posedge cs_n) begin + if(cs_n) begin state=0;bit_count=0;address=0;address_bytes=0;id_index=0;received=0;command=0;end + else begin + received={received[6:0],mosi}; + if(bit_count==7) begin + if(state==0) begin + command=received; + if(received==8'h03) state=1; + else if(received==8'h9f) begin state=2;response=8'h01;end + else state=3; + end else if(state==1) begin + address=(address<<8)|received;address_bytes=address_bytes+1; + if(address_bytes==3) begin state=2;response=contents[0];end + end else if(state==2) begin + if(command==8'h9f) begin + id_index=id_index+1; + response=id_index==1 ? 8'h20 : id_index==2 ? 8'h18 : 8'hff; + end else begin + address=address+1; + response=(address-32'h400000)>(addr[2:0]*8) & 255)!==expected) + $fatal(1,"SCU read addr=%h data=%h resp=%h",addr,rdata,rresp); + @(negedge clk); + end + rready=1;@(negedge clk);rready=0; + end + endtask + initial begin + repeat(4) @(negedge clk);reset=0; + @(negedge clk);rx_data=8'h71;rx_valid=1;@(negedge clk);rx_valid=0; + read_byte(31'h60020005,1,0); + if(!interrupt) $fatal(1,"RX IRQ missing"); + read_byte(31'h60020004,8'h71,0); + if(interrupt) $fatal(1,"RX not popped exactly once"); + read_byte(31'h60020005,0,0); + // A whole pasted command must survive a long interval between SBI polls. + for(integer j=0;j<200;j=j+1) begin + @(negedge clk);rx_data=j;rx_valid=1;@(negedge clk);rx_valid=0; + end + if(dut.overflow) $fatal(1,"FIFO overflow on a 200-byte paste"); + for(integer j=0;j<200;j=j+1) read_byte(31'h60020004,j[7:0],0); + if(interrupt) $fatal(1,"FIFO not drained after paste"); + read_byte(31'h60030000,0,2); + @(negedge clk);awaddr=31'h60020000;awid=3;awvalid=1; + @(negedge clk);awvalid=0;wdata=64'h53;wstrb=1;wvalid=1; + repeat(10) begin @(negedge clk);if(wready || bvalid) $fatal(1,"SCU lost TX backpressure");end + tx_ready=1;@(negedge clk);wvalid=0; + repeat(4) @(negedge clk); + if(!bvalid || bid!==3 || bresp!==0 || tx_count!=1) $fatal(1,"SCU TX response/count"); + bready=1;@(negedge clk);bready=0; + awaddr=31'h60000000;awsize=2;awvalid=1;@(negedge clk);awvalid=0; + wdata=64'h12345678;wstrb=15;wvalid=1;@(negedge clk);wvalid=0; + if(!exited || exit_code!==32'h12345678) $fatal(1,"SCU EXIT decode"); + $display("PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT");$finish; + end + initial begin #100000;$fatal(1,"SCU watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/RESULT.json new file mode 100644 index 0000000..44624a9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/RESULT.json @@ -0,0 +1,11 @@ +{ + "result": "PASS_UART_LOAD_VERIFY_BOOT", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "bytes_verified": 110592, + "testbench_cpu_release_override": false, + "preloaded_ddr_image": false, + "physical_mig_simulated": false, + "physical_board_tested": false, + "flash_rom_recovery": true, + "cycles": 61853714 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/simulation.log new file mode 100644 index 0000000..2ba6a81 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-uart-flash-recovery/simulation.log @@ -0,0 +1,7 @@ +PASS UART_PAYLOAD_READBACK bytes=110592 cycles=61134003 +PASS UART_VERIFIED_RUN cycles=61144580 +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=61853714 +- /home/yys/codex-builds/toy-a7-flash-20261012/build/board-uart-flash-recovery/tb_board_uart_boot.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2s; walltime 429.844 s; speed 5.756 ms/s +- Verilator: cpu 429.660 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-unit/RESULT.json new file mode 100644 index 0000000..62b7f31 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/board-unit/RESULT.json @@ -0,0 +1,18 @@ +{ + "result": "PASS", + "tests": 3, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/RESULT.json new file mode 100644 index 0000000..31d4b81 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/RESULT.json @@ -0,0 +1,12 @@ +{ + "result": "PASS", + "cycles": { + "valid": 8841590, + "bad_header": 17918, + "bad_payload": 8130742 + }, + "empty_ddr": true, + "original_cpu_oracle": true, + "forced_run": false, + "physical_flash_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_header.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_header.log new file mode 100644 index 0000000..26e4d0b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_header.log @@ -0,0 +1,8 @@ +TOY FLASH_BOOT +FLASH_ID 012018 +FAIL FLASH_BOOT +PASS FLASH_CORRUPTION_REJECTED cycles=17918 +- /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-regression/tb_flash_boot.sv:63: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 717us; walltime 0.356 s; speed 2.012 ms/s +- Verilator: cpu 0.356 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_payload.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_payload.log new file mode 100644 index 0000000..024e1f8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/bad_payload.log @@ -0,0 +1,8 @@ +TOY FLASH_BOOT +FLASH_ID 012018 +FAIL FLASH_BOOT +PASS FLASH_CORRUPTION_REJECTED cycles=8130742 +- /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-regression/tb_flash_boot.sv:63: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 325ms; walltime 62.414 s; speed 5.211 ms/s +- Verilator: cpu 62.401 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/valid.log b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/valid.log new file mode 100644 index 0000000..6a9a6ef --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/flash/tests/flash-regression/valid.log @@ -0,0 +1,8 @@ +TOY FLASH_BOOT +FLASH_ID 012018 +PASS FLASH_PAYLOAD_CRC +PASS FLASH_CPU_ORACLE cycles=8841590 +- /home/yys/codex-builds/toy-a7-flash-20261012/build/flash-regression/tb_flash_boot.sv:59: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 354ms; walltime 67.969 s; speed 5.203 ms/s +- Verilator: cpu 67.956 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/host/flash.py b/platforms/arty-a7-toy/host/flash.py new file mode 100644 index 0000000..421e163 --- /dev/null +++ b/platforms/arty-a7-toy/host/flash.py @@ -0,0 +1,164 @@ +"""Back up/program/verify Flash and check automatic Linux startup, within 1 hour.""" + +import argparse +from datetime import datetime +import hashlib +import json +from pathlib import Path +import subprocess +import shutil +import time + +from observe_flash_boot import Observer + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", type=Path, required=True) + p.add_argument( + "--payload", + type=Path, + required=True, + help="Packed TOYFLZ4 software, not the raw image", + ) + p.add_argument("--part", required=True) + p.add_argument( + "--mcs", + type=Path, + help="Existing Vivado-packed image if the programming host lacks Artix build support", + ) + p.add_argument("--port", required=True) + p.add_argument("--out", type=Path) + args = p.parse_args() + bit = args.bitstream.resolve() + payload = args.payload.resolve() + out = args.out or ROOT / "build" / ( + "flash-program-" + datetime.now().strftime("%Y%m%d-%H%M%S") + ) + out = out.resolve() + out.mkdir(parents=True, exist_ok=False) + image = out / "toy_flash.mcs" + backup = out / "flash-before.bin" + commands = [ + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out / "image.log"), + "-journal", + str(out / "image.jou"), + "-tclargs", + str(bit), + str(payload), + str(image), + ], + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/program_flash.tcl"), + "-log", + str(out / "program.log"), + "-journal", + str(out / "program.jou"), + "-tclargs", + str(image), + args.part, + str(backup), + ], + ] + if args.mcs: + packed_record = json.loads( + args.mcs.with_suffix(args.mcs.suffix + ".json").read_text() + ) + assert packed_record["result"] == "PASS_VIVADO_FLASH_PACK" + assert packed_record["bitstream_sha256"] == sha(bit) + assert packed_record["packed_payload_sha256"] == sha(payload) + assert packed_record["flash_image_sha256"] == sha(args.mcs) + shutil.copy2(args.mcs.resolve(), image) + commands[0] = None + record = dict( + status="RUNNING", + timeout_seconds=3600, + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + part=args.part, + port=args.port, + started_at=datetime.now().astimezone().isoformat(), + commands=commands, + ) + result = out / "RESULT.json" + result.write_text(json.dumps(record, indent=2) + "\n") + started = time.monotonic() + watcher = None + try: + for i, command in enumerate(commands): + if command is None: + print("USING_PREPACKED_FLASH_IMAGE", sha(image), flush=True) + continue + if i == 1: + watcher = Observer(args.port, out / "linux-console.log", timeout=3600) + watcher.start() + with (out / f"command-{i}.log").open("w") as log: + proc = subprocess.Popen( + command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT + ) + try: + code = proc.wait( + timeout=max(1, 3600 - (time.monotonic() - started)) + ) + except subprocess.TimeoutExpired: + if __import__("os").name == "nt": + subprocess.run( + ["taskkill", "/PID", str(proc.pid), "/T", "/F"], + capture_output=True, + ) + else: + proc.kill() + proc.wait() + raise + if code: + raise RuntimeError( + f"Vivado command {i} failed with {code}; inspect {out}" + ) + print("PASS FLASH_STAGE", i, flush=True) + # Program completion may precede CPU decompression; cap the remaining wait. + watcher.thread.join(timeout=max(1, 3600 - (time.monotonic() - started))) + if watcher.thread.is_alive(): + raise TimeoutError("One-hour Flash/Linux timeout") + hardware = watcher.finish() + record.update( + status="PASS", + hardware=hardware, + backup_sha256=sha(backup), + backup_bytes=backup.stat().st_size, + flash_image_sha256=sha(image), + ) + except Exception as error: + record.update(status="FAILED", error=str(error)) + raise + finally: + if watcher is not None: + watcher.stop.set() + watcher.thread.join(timeout=6) + record.update( + elapsed_seconds=round(time.monotonic() - started, 3), + finished_at=datetime.now().astimezone().isoformat(), + ) + result.write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/host/observe_flash_boot.py b/platforms/arty-a7-toy/host/observe_flash_boot.py new file mode 100644 index 0000000..0d562d7 --- /dev/null +++ b/platforms/arty-a7-toy/host/observe_flash_boot.py @@ -0,0 +1,163 @@ +"""Observe autonomous Flash/Linux startup, including an optional USB power cycle.""" + +import argparse +from datetime import datetime, timezone +import json +from pathlib import Path +import re +import threading +import time + +CHECKS = ( + b"PASS VM_COPY_ON_WRITE", + b"PASS VM_PAGE_PROTECTION", + b"PASS FP64_PROCESS_CONTEXT", + b"PASS LINUX_TIMER", + b"PASS LINUX_SYSTEM_CHECK", +) + + +class Observer: + def __init__(self, port, transcript, timeout=600, require_disconnect=False): + self.port = port + self.transcript = Path(transcript) + self.timeout = timeout + self.require_disconnect = require_disconnect + self.result = None + self.disconnections = 0 + self.stop = threading.Event() + self.ready = threading.Event() + self.thread = threading.Thread(target=self.run, daemon=True) + + def run(self): + import serial + + deadline = time.monotonic() + self.timeout + started = time.monotonic() + active = not self.require_disconnect + data = bytearray() + sent = False + connection = None + self.transcript.parent.mkdir(parents=True, exist_ok=True) + with self.transcript.open("wb") as log: + try: + while time.monotonic() < deadline and not self.stop.is_set(): + try: + if connection is None: + connection = serial.Serial( + self.port, + 1000000, + timeout=0.1, + write_timeout=5, + rtscts=False, + dsrdtr=False, + ) + connection.reset_input_buffer() + self.ready.set() + chunk = connection.read(max(1, connection.in_waiting)) + if not chunk: + continue + log.write(chunk) + log.flush() + if not active: + continue + data.extend(chunk) + if b"FAIL FLASH_BOOT" in data or b"Kernel panic" in data: + raise RuntimeError( + "Flash startup or Linux failed; inspect the UART log" + ) + if ( + not sent + and b"PASS FLASH_PAYLOAD_CRC" in data + and b"OpenSBI" in data + and b"~ # " in data + ): + connection.write( + b"/root/linux_system_check-linux; echo FLASH_LINUX_RC:$?\n" + ) + connection.flush() + sent = True + print("FLASH_LINUX_CHECK_SENT", flush=True) + if ( + sent + and re.search(rb"(?:^|\n)FLASH_LINUX_RC:0\r*\n", data) + and all(m in data for m in CHECKS) + ): + self.result = dict( + result="PASS_FLASH_LINUX", + checks=[m.decode() for m in CHECKS], + exit_status=0, + usb_disconnections=self.disconnections, + disconnect_required=self.require_disconnect, + elapsed_seconds=round(time.monotonic() - started, 3), + recorded_at=datetime.now(timezone.utc).isoformat(), + port=self.port, + transcript=str(self.transcript), + ) + print("PASS FLASH_LINUX_UART_CHECKS", flush=True) + break + except (serial.SerialException, OSError): + if connection is not None: + connection.close() + connection = None + self.disconnections += 1 + active = True + data.clear() + sent = False + log.write(b"\nOBSERVER_USB_DISCONNECTED\n") + log.flush() + print("OBSERVER_USB_DISCONNECTED", flush=True) + self.stop.wait(0.2) + if self.result is None: + raise TimeoutError( + "No complete autonomous Flash/Linux pass before the timeout" + ) + except Exception as error: + self.result = dict( + result="FAILED", + error=str(error), + usb_disconnections=self.disconnections, + port=self.port, + ) + finally: + if connection is not None: + connection.close() + self.transcript.with_suffix(".json").write_text( + json.dumps(self.result, indent=2) + "\n" + ) + + def start(self): + self.thread.start() + if not self.ready.wait(timeout=5): + self.stop.set() + self.thread.join(timeout=6) + raise RuntimeError(f"Could not open UART {self.port}; observer not armed") + + def finish(self): + self.thread.join() + if not self.result or self.result["result"] != "PASS_FLASH_LINUX": + raise RuntimeError(self.result) + return self.result + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--port", required=True) + p.add_argument("--transcript", type=Path, required=True) + p.add_argument("--timeout", type=int, default=600) + p.add_argument( + "--require-disconnect", + action="store_true", + help="Ignore the current session; wait for USB removal and a new boot", + ) + args = p.parse_args() + watcher = Observer( + args.port, args.transcript, args.timeout, args.require_disconnect + ) + watcher.start() + print("OBSERVER_ARMED", flush=True) + print(json.dumps(watcher.finish(), indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/check_board_cdc.py b/platforms/arty-a7-toy/scripts/check_board_cdc.py index 4a5c443..0b22eb4 100644 --- a/platforms/arty-a7-toy/scripts/check_board_cdc.py +++ b/platforms/arty-a7-toy/scripts/check_board_cdc.py @@ -34,7 +34,7 @@ def main(): bench = bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;\n reg ui_clk=0; initial begin #3; forever #6 ui_clk=~ui_clk; end") # Reuse exactly the board's converter instance and port tie-offs. top = (ROOT / "board/toy_a7_top.sv").read_text() - declarations = top[top.index(" wire [3:0] ui_awid;"):top.index(" toy_a7_platform platform")] + declarations = top[top.index(" wire [3:0] ui_awid;"):top.index(" toy_a7_platform")] instance = top[top.index(" toy_axi_cdc memory_cdc"):top.index(" arty_ddr3 ddr_controller")] instance = instance.replace("ddr_", "m_").replace("ui_aresetn", "!reset") bench = bench.replace(" axi_fullwidth dut(.*);", declarations + instance + " axi_fullwidth dut(.*);") diff --git a/platforms/arty-a7-toy/scripts/check_board_uart_boot.py b/platforms/arty-a7-toy/scripts/check_board_uart_boot.py index 7aafa66..92be1b1 100644 --- a/platforms/arty-a7-toy/scripts/check_board_uart_boot.py +++ b/platforms/arty-a7-toy/scripts/check_board_uart_boot.py @@ -4,6 +4,7 @@ testbench override releases the CPU and no initial image is put into DDR. """ import hashlib +import argparse import json from pathlib import Path import re @@ -104,6 +105,12 @@ def main(): + global OUT + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--flash-recovery",action="store_true",help="Use the new ROM with SW0 recovery selected") + args=parser.parse_args() + if args.flash_recovery: + OUT=ROOT/"build/board-uart-flash-recovery" OUT.mkdir(parents=True, exist_ok=True) binary = ROOT / "build/cpu-smoke/smoke.bin" data = binary.read_bytes() @@ -112,18 +119,29 @@ def main(): bench = bench.replace("tb_board_cpu", "tb_board_uart_boot") bench = bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;") bench = bench.replace("force platform.loader.cpu_run=1;", "") + if args.flash_recovery: + bench=bench.replace("toy_a7_platform platform(.*);", "toy_a7_platform #(.FLASH_BOOT(1)) platform(.*);") + bench=bench.replace("wire flash_recovery;", "wire flash_recovery=1;") + bench=bench.replace("wire flash_miso;", "wire flash_miso=0;") + bench=bench.replace(".CAPACITY(262144)", ".CAPACITY(268435456)") bench = bench.replace('.IMAGE("smoke.hex")', '.IMAGE("")') bench = bench.replace("cycles>4000000", "cycles>120000000") bench = bench.replace("endmodule", f" localparam PROGRAM_BYTES={len(data)};\n" + UART + "\nendmodule") path = OUT / "tb_board_uart_boot.sv" path.write_text(bench) - files = [ROOT / "build/serial-bound/ToyLinuxChip.sv", ROOT / "build/serial-bound/FpgaMemories.sv", + core=ROOT/("build/flash-boot/ToyLinuxChip.sv" if args.flash_recovery else "build/serial-bound/ToyLinuxChip.sv") + files = [core, ROOT / "build/serial-bound/FpgaMemories.sv", ROOT / "tests/axi_smoke_memory.sv", path] files += [p for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] with (OUT / "compile.log").open("w") as log: subprocess.run(["verilator", "--binary", "--timing", "-j", "8", "-Wno-fatal", "-DSYNTHESIS", "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_board_uart_boot", "--Mdir", str(OUT / "obj")] - + [str(p) for p in files], stdout=log, stderr=log, check=True, timeout=900) + + [str(p) for p in files], stdout=log, stderr=log, check=True, timeout=900,cwd=ROOT) + if args.flash_recovery: + # The bound ROM's readmemh path is relative to the platform directory. + import shutil + (OUT/"build/flash-boot").mkdir(parents=True,exist_ok=True) + shutil.copy2(ROOT/"build/flash-boot/bootrom.hex",OUT/"build/flash-boot/bootrom.hex") with (OUT / "simulation.log").open("w") as log: result = subprocess.run([str(OUT / "obj/Vtb_board_uart_boot")], cwd=OUT, stdout=log, stderr=log, timeout=1200) @@ -134,6 +152,7 @@ def main(): record = dict(result="PASS_UART_LOAD_VERIFY_BOOT", binary_sha256=hashlib.sha256(data).hexdigest(), bytes_verified=len(data), testbench_cpu_release_override=False, preloaded_ddr_image=False, physical_mig_simulated=False, physical_board_tested=False, + flash_rom_recovery=args.flash_recovery, cycles=int(re.search(r"through board AXI/SCU cycles=(\d+)", transcript)[1])) (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") print(transcript) diff --git a/platforms/arty-a7-toy/scripts/check_flash_boot.py b/platforms/arty-a7-toy/scripts/check_flash_boot.py new file mode 100644 index 0000000..fbfa17f --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_flash_boot.py @@ -0,0 +1,182 @@ +"""Real CPU executes ROM -> serial Flash -> decompression -> original oracle. + +DDR starts empty; no forced RUN or CPU reset bypass. SPI Flash and DDR PHY are +simulation models. Two corrupted images must halt in ROM without launching. +""" + +import argparse +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/flash-regression" + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument( + "--image", type=Path, required=True, help="Packed original CPU smoke image" + ) + p.add_argument("--skip-build", action="store_true") + args = p.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + image = args.image.read_bytes() + (OUT / "flash.hex").write_text("\n".join(f"{b:02x}" for b in image) + "\n") + text = (ROOT / "board/toy_a7_platform.sv").read_text() + header = text.split(") (", 1)[1].split(");", 1)[0] + signals = [] + direction, width = None, "" + for part in header.split(","): + m = re.fullmatch( + r"\s*(?:(input|output)\s+wire\s+)?(\[[^]]+\]\s*)?(\w+)\s*", part + ) + assert m, part + if m[1]: + direction, width = m[1], m[2] or "" + signals.append((direction, width, m[3])) + lines = [ + "`timescale 1ns/1ps", + "module tb_flash_boot;", + " reg clk=0;always #20 clk=~clk;", + " reg reset=1;", + " wire uart_rx_in=1,flash_recovery=0;", + ] + for _, width, name in signals: + if name not in ("clk", "reset", "uart_rx_in", "flash_recovery"): + lines.append(f" wire {width}{name};") + lines += [ + " toy_a7_platform #(.FLASH_BOOT(1)) platform(.*);", + " initial begin repeat(10) @(negedge clk);reset=0;end", + f' spi_flash_model #(.BYTES({len(image)}),.IMAGE("{OUT}/flash.hex")) flash', + " (.sck(flash_sck),.cs_n(flash_cs_n),.mosi(flash_mosi),.miso(flash_miso));", + " integer cycles=0;reg [255:0] tail=0;reg verified=0;", + " always @(posedge clk) if(!reset) begin", + " cycles<=cycles+1;", + " if(platform.mmio_tx_valid && platform.tx_ready) begin", + ' $write("%c",platform.mmio_tx_data);$fflush();', + " tail={tail[247:0],platform.mmio_tx_data};", + ' if(tail[175:0]=="PASS FLASH_PAYLOAD_CRC") verified=1;', + " end", + " if(exited && exit_code==32'h600d600d) begin", + ' if(!verified) $fatal(1,"Oracle ran before verified Flash payload");', + ' if($test$plusargs("bad_header") || $test$plusargs("bad_payload")) $fatal(1,"Corrupted image launched");', + ' $display("PASS FLASH_CPU_ORACLE cycles=%0d",cycles);$finish;end', + " if(exited && exit_code==32'hbad0f101) begin", + ' if(!$test$plusargs("bad_header") && !$test$plusargs("bad_payload")) $fatal(1,"Valid image rejected");', + ' if(verified) $fatal(1,"Corrupt image reported verified");', + ' $display("PASS FLASH_CORRUPTION_REJECTED cycles=%0d",cycles);$finish;end', + " if(exited && (exit_code & 32'hffff0000)==32'hbad00000 && exit_code!=32'hbad0f101)", + ' $fatal(1,"CPU/ROM trap %h",exit_code);', + ' if(cycles>40000000) $fatal(1,"Flash boot watchdog");', + " end", + ] + mapping = { + "awid": "aw_bits_id", + "awaddr": "aw_bits_addr", + "awlen": "aw_bits_len", + "awsize": "aw_bits_size", + "awburst": "aw_bits_burst", + "wdata": "w_bits_data", + "wstrb": "w_bits_strb", + "wlast": "w_bits_last", + "bid": "b_bits_id", + "bresp": "b_bits_resp", + "arid": "ar_bits_id", + "araddr": "ar_bits_addr", + "arlen": "ar_bits_len", + "arsize": "ar_bits_size", + "arburst": "ar_bits_burst", + "rid": "r_bits_id", + "rdata": "r_bits_data", + "rresp": "r_bits_resp", + "rlast": "r_bits_last", + } + connections = [".clock(clk)", ".reset(reset)"] + for _, _, name in signals: + if name.startswith("ddr_"): + s = name[4:] + connections.append( + f".{mapping.get(s,s.replace('ready','_ready').replace('valid','_valid'))}({name})" + ) + lines += [ + " axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(268435456)) memory (", + " " + ",\n ".join(connections) + "\n );", + "endmodule", + ] + bench = OUT / "tb_flash_boot.sv" + bench.write_text("\n".join(lines) + "\n") + if not args.skip_build: + files = [ + ROOT / "build/flash-boot/ToyLinuxChip.sv", + ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", + ROOT / "tests/spi_flash_model.sv", + bench, + ] + files += [f for f in (ROOT / "board").glob("*.sv") if f.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "-j", + "8", + "-Wno-fatal", + "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", + "--top-module", + "tb_flash_boot", + "--Mdir", + str(OUT / "obj"), + ] + + [str(f) for f in files], + stdout=log, + stderr=log, + check=True, + timeout=900, + cwd=ROOT, + ) + results = {} + for case in ("valid", "bad_header", "bad_payload"): + command = [str(OUT / "obj/Vtb_flash_boot")] + if case != "valid": + command.append("+" + case) + with (OUT / (case + ".log")).open("w") as log: + subprocess.run( + command, + cwd=ROOT, + stdout=log, + stderr=subprocess.STDOUT, + check=True, + timeout=300, + ) + output = (OUT / (case + ".log")).read_text() + print(output) + marker = ( + "PASS FLASH_CPU_ORACLE" + if case == "valid" + else "PASS FLASH_CORRUPTION_REJECTED" + ) + assert marker in output + results[case] = int(re.search(r"cycles=(\d+)", output)[1]) + (OUT / "RESULT.json").write_text( + json.dumps( + dict( + result="PASS", + cycles=results, + empty_ddr=True, + original_cpu_oracle=True, + forced_run=False, + physical_flash_tested=False, + ), + indent=2, + ) + + "\n" + ) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/make_flash_image.py b/platforms/arty-a7-toy/scripts/make_flash_image.py new file mode 100644 index 0000000..58fcd3d --- /dev/null +++ b/platforms/arty-a7-toy/scripts/make_flash_image.py @@ -0,0 +1,69 @@ +"""Use Vivado to pack Flash, then record hashes for a separate programming host.""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", required=True, type=Path) + p.add_argument("--payload", required=True, type=Path) + p.add_argument("--out", required=True, type=Path) + args = p.parse_args() + bit, payload, out = ( + args.bitstream.resolve(), + args.payload.resolve(), + args.out.resolve(), + ) + out.parent.mkdir(parents=True, exist_ok=True) + command = [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out.with_suffix(".log")), + "-journal", + str(out.with_suffix(".jou")), + "-tclargs", + str(bit), + str(payload), + str(out), + ] + with out.with_suffix(".console.log").open("w") as log: + subprocess.run( + command, + cwd=ROOT, + stdout=log, + stderr=subprocess.STDOUT, + check=True, + timeout=180, + ) + record = dict( + result="PASS_VIVADO_FLASH_PACK", + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + flash_image_sha256=sha(out), + configuration_offset=0, + software_offset=0x400000, + flash_bytes=0x1000000, + ) + out.with_suffix(out.suffix + ".json").write_text( + json.dumps(record, indent=2) + "\n" + ) + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/prepare_flash_boot.py b/platforms/arty-a7-toy/scripts/prepare_flash_boot.py new file mode 100644 index 0000000..0fed787 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/prepare_flash_boot.py @@ -0,0 +1,123 @@ +"""Pack an unchanged payload as LZ4 and bind only the boot-ROM module. + +The 4 MiB configuration partition and 12 MiB software partition cannot overlap. +Dependencies: lz4==4.4.5. Compile boot/flash_boot.c and flash_start.S separately. +""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import struct +import zlib + +ROOT = Path(__file__).resolve().parents[1] +CORE_SHA = "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(data): + return hashlib.sha256(data).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--payload", type=Path, required=True) + p.add_argument("--boot-bin", type=Path, required=True) + p.add_argument( + "--core", type=Path, default=ROOT / "build/serial-bound/ToyLinuxChip.sv" + ) + p.add_argument("--out", type=Path, default=ROOT / "build/flash-boot") + args = p.parse_args() + import lz4 + import lz4.block + + raw = args.payload.read_bytes() + if not 0 < len(raw) <= 0x0F000000: + raise ValueError("Payload overlaps the boot stack reservation") + packed = lz4.block.compress( + raw, mode="high_compression", compression=12, store_size=False + ) + assert lz4.block.decompress(packed, uncompressed_size=len(raw)) == raw + head = struct.pack( + "<8s5I", b"TOYFLZ4\0", 1, len(packed), len(raw), zlib.crc32(raw), 0 + ) + image = head + struct.pack(" 0xC00000: + raise ValueError("Compressed software exceeds the 12 MiB partition") + original_bytes = args.core.read_bytes() + assert ( + sha(original_bytes) == CORE_SHA + ), "Unexpected core: use the pinned validated generation" + original = original_bytes.decode() + matches = list(re.finditer(r"^module TLROM\(.*?^endmodule", original, re.M | re.S)) + assert len(matches) == 1 + m = matches[0] + original_rom = m.group() + words = re.findall(r"64'h([0-9A-Fa-f]+)", original_rom.split("TLMonitor")[0]) + rom_bytes = b"".join(int(w, 16).to_bytes(8, "little") for w in words[::-1]) + dtb_start = rom_bytes.index(bytes.fromhex("d00dfeed")) + dtb_size = int.from_bytes(rom_bytes[dtb_start + 4 : dtb_start + 8], "big") + dtb = rom_bytes[dtb_start : dtb_start + dtb_size] + assert len(dtb) == dtb_size and dtb_size <= 4096 + boot = args.boot_bin.read_bytes() + assert 0 < len(boot) <= 4096 + rom = boot.ljust(4096, b"\0") + dtb.ljust(4096, b"\0") + replacement = original_rom.split(");", 1)[0] + """ +); + (* rom_style="block" *) reg [63:0] contents [0:1023]; + initial $readmemh("build/flash-boot/bootrom.hex", contents); + reg valid; + reg [1:0] response_size; + reg [6:0] response_source; + reg [63:0] response_data; + assign auto_in_a_ready=!valid || auto_in_d_ready; + assign auto_in_d_valid=valid; + assign auto_in_d_bits_size=response_size; + assign auto_in_d_bits_source=response_source; + assign auto_in_d_bits_data=response_data; + always @(posedge clock) begin + if(reset) valid<=0; + else if(auto_in_a_ready) valid<=auto_in_a_valid; + if(auto_in_a_ready && auto_in_a_valid) begin + response_size<=auto_in_a_bits_size;response_source<=auto_in_a_bits_source; + response_data<=|auto_in_a_bits_address[15:13] ? 64'd0 : contents[auto_in_a_bits_address[12:3]]; + end + end +endmodule""" + adapted = original[: m.start()] + replacement + original[m.end() :] + assert adapted.replace(replacement, original_rom, 1) == original + args.out.mkdir(parents=True, exist_ok=True) + (args.out / "flash_payload.bin").write_bytes(image) + (args.out / "bootrom.hex").write_text( + "\n".join( + f"{int.from_bytes(rom[i:i+8], 'little'):016x}" + for i in range(0, len(rom), 8) + ) + + "\n" + ) + (args.out / "ToyLinuxChip.sv").write_text(adapted, encoding="utf-8", newline="\n") + record = dict( + payload_bytes=len(raw), + payload_sha256=sha(raw), + lz4_bytes=len(packed), + flash_image_bytes=len(image), + flash_offset=0x400000, + flash_bytes=0x1000000, + lz4_version=lz4.__version__, + boot_code_bytes=len(boot), + boot_sha256=sha(boot), + original_core_sha256=sha(original_bytes), + adapted_core_sha256=sha(adapted.encode()), + only_module_replaced="TLROM", + dtb_sha256=sha(dtb), + dtb_address="0x11000", + rom_bytes=len(rom), + payload_crc32=f"{zlib.crc32(raw):08x}", + ) + (args.out / "MANIFEST.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/start_board_build.py b/platforms/arty-a7-toy/scripts/start_board_build.py index f2b5ee0..a8c7b7a 100644 --- a/platforms/arty-a7-toy/scripts/start_board_build.py +++ b/platforms/arty-a7-toy/scripts/start_board_build.py @@ -34,6 +34,8 @@ def worker(out): command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), "-mode","batch","-source",str(script), "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + if record.get("flash_boot"): + command.append("flash") record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), command=command,worker_pid=os.getpid()) started=time.monotonic() @@ -56,10 +58,15 @@ def worker(out): def main(): p=argparse.ArgumentParser(description=__doc__) p.add_argument("--worker",type=Path) + p.add_argument("--flash",action="store_true",help="Use the validated Flash boot ROM and SPI port") args=p.parse_args() if args.worker: worker(args.worker.resolve());return assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + if args.flash: + flash_manifest=json.loads((ROOT/"build/flash-boot/MANIFEST.json").read_text()) + assert flash_manifest["original_core_sha256"]==EXPECTED + assert sha(ROOT/"build/flash-boot/ToyLinuxChip.sv")==flash_manifest["adapted_core_sha256"] for path in (ROOT/"build").glob("board-*/RUN.json"): assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) @@ -71,7 +78,8 @@ def main(): record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, board_sources=files,core_clock_hz=25000000,uart_baud=1000000, - vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False) + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False, + flash_boot=args.flash) save(out/"RUN.json",record) with (out/"launcher.log").open("w") as log: p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], diff --git a/platforms/arty-a7-toy/scripts/verify_flash_evidence.py b/platforms/arty-a7-toy/scripts/verify_flash_evidence.py new file mode 100644 index 0000000..6ea4096 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_flash_evidence.py @@ -0,0 +1,126 @@ +"""Check the preserved Flash implementation and physical cold-start evidence.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/flash" +CHECKS = { + "VM_COPY_ON_WRITE", + "VM_PAGE_PROTECTION", + "FP64_PROCESS_CONTEXT", + "LINUX_TIMER", + "LINUX_SYSTEM_CHECK", +} + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def verify(): + manifest = read(ARCHIVE / "MANIFEST.json") + for name, expected in manifest["files"].items(): + assert sha(ARCHIVE / name) == expected, name + record = read(ARCHIVE / "FLASH_RESULT.json") + run = read(ARCHIVE / "implementation/RUN.json") + software = read(ARCHIVE / "software/MANIFEST.json") + packed = read(ARCHIVE / "software/FLASH_IMAGE.json") + assert run["status"] == "COMPLETED" and run["exit_code"] == 0 + assert run["flash_boot"] and run["bitstream_generated"] + assert run["timeout_seconds"] == 3600 and run["elapsed_seconds"] < 3600 + for name, expected in run["board_sources"].items(): + assert sha(ARCHIVE / "sources" / name) == expected, name + assert record["part"] == run["part"] == "xc7a100tcsg324-1" + assert run["core_sha256"] == software["original_core_sha256"] + assert software["only_module_replaced"] == "TLROM" + assert software["dtb_address"] == "0x11000" and software["rom_bytes"] == 8192 + assert record["payload_sha256"] == software["payload_sha256"] + assert record["bitstream_sha256"] == packed["bitstream_sha256"] + previous = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") + assert record["payload_sha256"] == previous["linux"]["payload_sha256"] + + labels = { + "Slice LUTs": "LUT", + "Slice Registers": "FF", + "Block RAM Tile": "BRAM_tiles", + "DSPs": "DSP", + "Slice": "Slice", + } + area = {} + for line in ( + (ARCHIVE / "implementation/routed-utilization.rpt").read_text().splitlines() + ): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + area[labels[fields[1]]] = float(fields[2]) + assert area == record["routed_resources"] + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + match = re.search( + r"WNS\(ns\).*?\n\s*-+[^\n]*\n\s*([\d.-]+)\s+([\d.-]+)\s+(\d+)\s+(\d+)\s+([\d.-]+)\s+([\d.-]+)", + timing, + ) + assert match and float(match[1]) == record["wns_ns"] >= 0 + assert float(match[2]) == float(match[6]) == 0 + assert float(match[5]) == record["whs_ns"] >= 0 + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + assert re.search(r"nets with routing errors\.*\s*:\s+0", route) + assert "checking unconstrained_internal_endpoints (0)" in timing + cdc = (ARCHIVE / "implementation/cdc.rpt").read_text() + assert not re.search(r"^CDC-\d+\s+Critical\s+\d+", cdc, re.MULTILINE) + drc = (ARCHIVE / "implementation/drc.rpt").read_text() + assert not re.search( + r"^\|[^|\n]+\|\s*(?:Error|Critical Warning)\s*\|", drc, re.MULTILINE + ) + + hardware = read(ARCHIVE / "hardware/AUTOMATIC_BOOT_RESULT.json") + assert hardware["result"] == "PASS_FLASH_PROGRAM_AND_AUTOMATIC_LINUX_BOOT" + assert hardware["bitstream_sha256"] == record["bitstream_sha256"] + assert hardware["packed_payload_sha256"] == packed["packed_payload_sha256"] + assert hardware["flash_image_sha256"] == packed["flash_image_sha256"] + assert hardware["backup_bytes"] == 16777216 and not hardware["backup_published"] + for name, expected in hardware["evidence_sha256"].items(): + assert sha(ARCHIVE / "hardware" / name) == expected, name + program = (ARCHIVE / "hardware/program.log").read_bytes() + assert b"Program/Verify Operation successful." in program + assert b"FLASH_BOOT_CONFIG_STATUS 01010000000100000111100111111100" in program + + cold = read(ARCHIVE / "hardware/cold-boot-1.json") + assert cold["result"] == "PASS_FLASH_LINUX" and cold["exit_status"] == 0 + assert cold["disconnect_required"] and cold["usb_disconnections"] >= 1 + assert record["operator_confirmed_all_power_removed"] + assert record["physical_cold_boot_tested"] and not record["board_release_ready"] + assert set(cold["checks"]) == {"PASS " + check for check in CHECKS} + for name in ("linux-console.log", "cold-boot-1.log"): + data = (ARCHIVE / "hardware" / name).read_bytes() + assert b"PASS FLASH_PAYLOAD_CRC" in data and b"OpenSBI v1.9" in data + assert b"Linux version 6.6.0" in data and b"Kernel panic" not in data + assert re.search(rb"(?:^|\n)FLASH_LINUX_RC:0\r*\n", data) + for check in CHECKS: + assert ("PASS " + check).encode() in data + assert ( + b"OBSERVER_USB_DISCONNECTED" + in (ARCHIVE / "hardware/cold-boot-1.log").read_bytes() + ) + assert read(ARCHIVE / "tests/flash-regression/RESULT.json")["result"] == "PASS" + recovery = read(ARCHIVE / "tests/board-uart-flash-recovery/RESULT.json") + assert recovery["result"] == "PASS_UART_LOAD_VERIFY_BOOT" + assert recovery["flash_rom_recovery"] and recovery["bytes_verified"] == 110592 + assert ( + not recovery["preloaded_ddr_image"] + and not recovery["testbench_cpu_release_override"] + ) + assert read(ARCHIVE / "tests/board-unit/RESULT.json")["result"] == "PASS" + print( + "PASS Flash evidence: implementation, program/verify and physical cold-start Linux checks" + ) + + +if __name__ == "__main__": + verify() diff --git a/platforms/arty-a7-toy/scripts/verify_target.py b/platforms/arty-a7-toy/scripts/verify_target.py index 900827c..8c52af8 100644 --- a/platforms/arty-a7-toy/scripts/verify_target.py +++ b/platforms/arty-a7-toy/scripts/verify_target.py @@ -5,6 +5,7 @@ from pathlib import Path import re from verify_hardware_evidence import verify as verify_hardware +from verify_flash_evidence import verify as verify_flash ROOT = Path(__file__).resolve().parents[1] EVIDENCE = ROOT / "evidence/2026-10-11" @@ -40,7 +41,9 @@ def main(): assert not record["physical_linux_boot_tested"] and not record["board_release_ready"] for name, expected in record["board_sources"].items(): if not name.endswith(".md"): - assert sha(ROOT / name) == expected, name + # Keep the October 11 proof attached to its original board sources; + # later Flash-boot changes require their own implementation evidence. + assert sha(EVIDENCE / "sources" / name) == expected, name area = {} labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Block RAM Tile": "BRAM_tiles", "DSPs": "DSP", "Slice": "Slice"} @@ -61,6 +64,7 @@ def main(): assert re.search(r"PASS BOARD_LINUX_USERSPACE cycles=273506752", transcript) assert read(EVIDENCE / "tests/uart-boot/RESULT.json")["result"] == "PASS_UART_LOAD_VERIFY_BOOT" verify_hardware() + verify_flash() if args.core: assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == lock["core_rtl_sha256"] assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == lock["memory_rtl_sha256"] diff --git a/platforms/arty-a7-toy/tests/spi_flash_model.sv b/platforms/arty-a7-toy/tests/spi_flash_model.sv new file mode 100644 index 0000000..477b37f --- /dev/null +++ b/platforms/arty-a7-toy/tests/spi_flash_model.sv @@ -0,0 +1,42 @@ +// Simulation-only standard 03h read / 9fh JEDEC model, no Flash writes. +module spi_flash_model #(parameter BYTES=1024, parameter IMAGE="flash.hex") ( + input wire sck, cs_n, mosi, output reg miso=1 +); + reg [7:0] contents [0:BYTES-1]; + reg [7:0] received; + integer bit_count=0, state=0, address_bytes=0, address=0, id_index=0; + reg [7:0] command; + reg [7:0] response; + initial begin + $readmemh(IMAGE,contents); + if($test$plusargs("bad_header")) contents[0]=contents[0]^1; + if($test$plusargs("bad_payload")) contents[BYTES-1]=contents[BYTES-1]^1; + end + always @(posedge sck or posedge cs_n) begin + if(cs_n) begin state=0;bit_count=0;address=0;address_bytes=0;id_index=0;received=0;command=0;end + else begin + received={received[6:0],mosi}; + if(bit_count==7) begin + if(state==0) begin + command=received; + if(received==8'h03) state=1; + else if(received==8'h9f) begin state=2;response=8'h01;end + else state=3; + end else if(state==1) begin + address=(address<<8)|received;address_bytes=address_bytes+1; + if(address_bytes==3) begin state=2;response=contents[0];end + end else if(state==2) begin + if(command==8'h9f) begin + id_index=id_index+1; + response=id_index==1 ? 8'h20 : id_index==2 ? 8'h18 : 8'hff; + end else begin + address=address+1; + response=(address-32'h400000)