From b815147a66978f32b4ad6d46db7da9a62c1e9751 Mon Sep 17 00:00:00 2001 From: Cody-ic <261693366+Cody-ic@users.noreply.github.com> Date: Sun, 11 Oct 2026 19:31:12 +0800 Subject: [PATCH] [fpga] feat: add Arty A7 Toy Linux engineering target --- .github/workflows/arty-a7-toy.yml | 35 + README.md | 7 +- platforms/arty-a7-toy/.gitattributes | 7 + platforms/arty-a7-toy/.gitignore | 12 + platforms/arty-a7-toy/.jvmopts | 4 + platforms/arty-a7-toy/README.md | 102 + platforms/arty-a7-toy/SOFTWARE_BASELINE.json | 6 + platforms/arty-a7-toy/SOURCE_LOCK.json | 193 + platforms/arty-a7-toy/THIRDPARTY.md | 19 + platforms/arty-a7-toy/UPSTREAM_MANIFEST.json | 1014 +++ platforms/arty-a7-toy/VALIDATION.md | 78 + platforms/arty-a7-toy/board/README.md | 25 + .../arty-a7-toy/board/SOURCE_MANIFEST.json | 18 + platforms/arty-a7-toy/board/arty_a7.xdc | 27 + platforms/arty-a7-toy/board/axi_fullwidth.sv | 115 + platforms/arty-a7-toy/board/axi_scu.sv | 88 + platforms/arty-a7-toy/board/build_board.tcl | 78 + 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mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c create mode 100644 platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c create mode 100644 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100644 platforms/arty-a7-toy/tests/ws_round_edges.c create mode 100644 platforms/arty-a7-toy/tests/ws_shift_edges.c diff --git a/.github/workflows/arty-a7-toy.yml b/.github/workflows/arty-a7-toy.yml new file mode 100644 index 0000000..f006645 --- /dev/null +++ b/.github/workflows/arty-a7-toy.yml @@ -0,0 +1,35 @@ +name: Arty A7 Toy source and interface checks + +on: + pull_request: + paths: + - 'platforms/arty-a7-toy/**' + - '.github/workflows/arty-a7-toy.yml' + push: + branches: [main] + paths: + - 'platforms/arty-a7-toy/**' + - '.github/workflows/arty-a7-toy.yml' + +permissions: + contents: read + +jobs: + source-and-interfaces: + runs-on: ubuntu-24.04 + timeout-minutes: 10 + steps: + - uses: actions/checkout@11d5960a326750d5838078e36cf38b85af677262 # v4 + with: + persist-credentials: false + - name: Verify pinned sources and recorded evidence + working-directory: platforms/arty-a7-toy + run: | + python3 scripts/verify_target.py + python3 -m compileall -q scripts tests host software + bash -n scripts/elaborate.sh scripts/build_test_programs.sh software/build.sh + - name: Install interface simulator + run: sudo apt-get update && sudo apt-get install -y iverilog + - name: AXI, UART/SCU and DDR loader interface tests + working-directory: platforms/arty-a7-toy + run: timeout --signal=TERM --kill-after=15s 180s python3 scripts/check_board.py diff --git a/README.md b/README.md index ff74e87..f033fc5 100644 --- a/README.md +++ b/README.md @@ -8,11 +8,16 @@ This repo is where we put [Buckyball](https://github.com/DangoSys/buckyball) ont |---|---|---| | Kintex-7 | `xc7k160tffg676-2` | [Existing P2E flow](platforms/xc7k160t/README.md) | | Digilent Arty A7-100T | `xc7a100tcsg324-1` | [Standalone CPU/BRAM/UART platform](platforms/arty-a7/README.md) | +| Digilent Arty A7-100T, Toy/Linux | `xc7a100tcsg324-1` | [CPU/Sv39/FPU/Gemmini 8×8 with DDR](platforms/arty-a7-toy/README.md) | -The Arty A7 platform has its own pinned Chisel build, serial loader, firmware, +The Arty A7 platforms have their own pinned Chisel build, serial loader, firmware, constraints and verification record. Follow its guide directly; the setup and demo below describe the existing Kintex-7 flow. +The Toy/Linux target passes complete board implementation and Linux RTL checks. +Its current Rev E DDR engineering target still requires physical DDR calibration +and Linux boot acceptance; see its guide before programming. + ## Kintex-7 setup First, build the repository with these steps: diff --git a/platforms/arty-a7-toy/.gitattributes b/platforms/arty-a7-toy/.gitattributes new file mode 100644 index 0000000..4203d69 --- /dev/null +++ b/platforms/arty-a7-toy/.gitattributes @@ -0,0 +1,7 @@ +# Preserve original source, vendor and measured-evidence bytes for hash checks. +* -text +* whitespace=trailing-space,space-before-tab,cr-at-eol +# Do not rewrite whitespace in upstream snapshots or raw tool output. +board/vendor/** -whitespace +tests/reference/** -whitespace +evidence/** -whitespace diff --git a/platforms/arty-a7-toy/.gitignore b/platforms/arty-a7-toy/.gitignore new file mode 100644 index 0000000..838bb3f --- /dev/null +++ b/platforms/arty-a7-toy/.gitignore @@ -0,0 +1,12 @@ +/upstream/ +/thirdparty/ +/build/ +/target/ +/project/target/ +/project/project/ +__pycache__/ +.Xil/ +*.log +!evidence/**/*.log +*.jou +toy-console.log diff --git a/platforms/arty-a7-toy/.jvmopts b/platforms/arty-a7-toy/.jvmopts new file mode 100644 index 0000000..1484c7b --- /dev/null +++ b/platforms/arty-a7-toy/.jvmopts @@ -0,0 +1,4 @@ +-Xmx12G +-Xss8M +-XX:ActiveProcessorCount=8 +-Dsbt.supershell=false diff --git a/platforms/arty-a7-toy/README.md b/platforms/arty-a7-toy/README.md new file mode 100644 index 0000000..9bb4d2e --- /dev/null +++ b/platforms/arty-a7-toy/README.md @@ -0,0 +1,102 @@ +# Toy/Linux on Arty A7-100T + +A Chisel-generated Toy platform for `xc7a100tcsg324-1`, with CPU, Sv39, full +FP16/32/64 support and Gemmini 8×8. Complete board implementation, timing, CDC +checks and Linux RTL tests pass. The physical board revision is unconfirmed: +this is a **Rev E engineering bring-up target**, awaiting hardware DDR and Linux +acceptance. See [measured results](VALIDATION.md) before programming. + +## Architecture and scope + +- RV64IMAFDC with Zfh/Zba/Zbb/Zbs, M/S/U, PMP, Sv39, interrupts and 8 KiB I/D + caches. FP16/32/64 share the FMA; the register file uses validated LUTRAM. +- Gemmini 8×8 OS/WS, 64 DSP PE MACs, 64 KiB accelerator SRAM and 23 opcodes. + Group-query ownership, simultaneous SubROB enqueue/retirement, WS bias and + rounding fixes are included as Chisel overrides. +- 256 MiB DDR3L at `0x80000000`, official Digilent Rev E MIG, real Xilinx AXI + Clock Converter and a byte-strobe preserving fullwidth DDR adapter. +- 100 MHz oscillator, 25 MHz CPU, 83.33 MHz MIG UI, 500 kHz CLINT; UART 1 Mbps + 8N1. SCU exit/TX/RX/status: `0x60000000`, `0x60020000/04/05`. + +This is the previously evaluated FPGA profile, not the default full-size Toy: +other Balls, L2, BTB, debug, extra performance counters and the separate TL +scratchpad are absent; broadcast coherence and basic counters remain. Accelerator +SRAM is distinct from that removed TL scratchpad. No software emulation is +silently substituted. The current PR adds no further core cuts. + +Pinned upstream files are restored into ignored `upstream/`; dependencies into +ignored `thirdparty/`. `patches/` contains the hardware overrides, `src/` the +top/configuration, `rtl/` memory/RF adapters, `board/` physical integration, +`software/` pinned Linux/OpenSBI preparation, and `tests/` independent oracles. + +## Build + +Run from this directory on Linux with Python 3.12+, Git, curl, JDK 17, sbt, +firtool 1.62.1, RV64 bare-metal and Linux GCC/binutils, Verilator, Icarus Verilog, +and Vivado with Artix-7 support. Kernel builds also need CMake, Make, flex, +bison and the standard kernel development libraries. The tested tool versions +and byte hashes are recorded in `evidence/2026-10-11/`. + +```bash +cd platforms/arty-a7-toy +# Optional --repository reuses pinned Git objects without changing that checkout. +bash scripts/elaborate.sh --repository ../../thirdparty/buckyball +bash scripts/build_test_programs.sh +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/run_board_regression.py +python3 scripts/start_board_build.py +``` + +Omit `--repository` to fetch a private pinned Git cache. Chisel 6.7.0 and Scala +2.13.16 are set by `build.sbt`; sbt is pinned in `project/build.properties`. +Set `CHISEL_FIRTOOL_PATH` to the directory containing firtool when required. +`scripts/verify_target.py --core` rejects a regenerated core or SRAM/RF binding +whose bytes differ from the validated version. + +The board launcher returns immediately with a fresh output directory. Inspect +its `RUN.json`, `phase.txt` and `vivado.log` until status is `COMPLETED`, exit code +0 and `bitstream_generated` true. The entire Vivado process group has a +3,600-second timeout plus 15-second termination grace. Timing, CDC, bus-skew, +routing and DRC failures prevent bitstream generation. `VIVADO` may point to an +installed compatibility wrapper; otherwise `vivado` is resolved on PATH. + +```bash +bash software/build.sh +python3 scripts/build_board_firmware.py +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_board_linux.py +timeout --signal=TERM --kill-after=15s 1800s python3 scripts/check_board_uart_boot.py +python3 scripts/check_board_cdc.py board-YYYYMMDD-HHMMSS --output-name board-cdc-new +``` + +Use the actual board run name for CDC testing and a fresh simulation output +name. OpenSBI rebuild defaults to `riscv64-linux-gnu-`; `--cross-compile` selects +another compatible GNU prefix. `--software-base` can reuse another isolated root +containing `build/software` produced by the same pinned software flow. + +Generated RTL, firmware, dependencies, checkpoints and bitstreams are build +products and are not committed. A successful fresh board run produces +`build/board-/toy_a7.bit`; the Linux payload is +`build/board-software/fw_payload.bin`. + +## First hardware boot + +1. Confirm the physical DDR/revision matches the official Rev E parameters; + connect PROG/UART USB and select the single XC7A100T in Hardware Manager. +2. Program the selected `.bit` into volatile FPGA SRAM. On Windows: + `./program.ps1 -Bitstream -VivadoBin `. + The script does not write flash and is not run automatically. +3. Press BTN0, wait for LED0 (DDR calibrated), and close other serial clients. +4. Install `pyserial`, then load and byte-verify the image before releasing CPU: + +```bash +python host/load.py --port COM5 --check-linux build/board-software/fw_payload.bin +``` + +Use the actual serial port. Expect OpenSBI, Linux, BusyBox and five PASS markers +for COW, page protection, FP64 process context, the timer and the total Linux +system check. A 17 MiB transfer with full readback takes several minutes at +1 Mbps. After the script closes the port, an interactive console is available +with `python -m serial.tools.miniterm COM5 1000000 --eol LF`. + +LED1 indicates loader error or nonzero exit, LED2 CPU released, LED3 heartbeat. +LEDs alone do not establish software success. Preserve the console transcript +and DDR calibration result; operator acceptance additionally needs Gemmini tests. diff --git a/platforms/arty-a7-toy/SOFTWARE_BASELINE.json b/platforms/arty-a7-toy/SOFTWARE_BASELINE.json new file mode 100644 index 0000000..c76935c --- /dev/null +++ b/platforms/arty-a7-toy/SOFTWARE_BASELINE.json @@ -0,0 +1,6 @@ +{ + "bbkernel": "b80336ce647f6604713f1570e1e1355f705a4355", + "linux": "ffc253263a1375a65fa6c9f62a893e9767fbebfa", + "opensbi": "c0f87f10d1bfb9e72a84ddfafb5604ee1bfe9d04", + "busybox": "1a64f6a20aaf6ea4dbba68bbfa8cc1ab7e5c57c4" +} diff --git a/platforms/arty-a7-toy/SOURCE_LOCK.json b/platforms/arty-a7-toy/SOURCE_LOCK.json new file mode 100644 index 0000000..ba5ec44 --- /dev/null +++ b/platforms/arty-a7-toy/SOURCE_LOCK.json @@ -0,0 +1,193 @@ +{ + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", + "files": { + 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`prepare_sources.py` exports +their license/notice files alongside ignored dependency sources. Keep those +notices when redistributing exported or modified dependency code. + +Pinned original test/library files are under `tests/reference/`, with hashes in +`tests/REFERENCE_MANIFEST.json`, from the same Buckyball revision. The FPGA +repository's license remains at the repository root. + +`board/vendor/MANIFEST.json` records the Digilent vivado-boards commit, original +URLs and SHA256 values for the unmodified Arty A7-100T E.0 board/MIG files. +Vivado generates AMD/Xilinx IP locally; generated vendor RTL is not committed. + +`SOFTWARE_BASELINE.json` pins bbkernel, Linux, OpenSBI and BusyBox. Their sources +and original licenses are fetched into ignored `build/software/`; software +adaptations affect board memory/timebase properties, not the Linux ISA model. diff --git a/platforms/arty-a7-toy/UPSTREAM_MANIFEST.json b/platforms/arty-a7-toy/UPSTREAM_MANIFEST.json new file mode 100644 index 0000000..7b394cc --- /dev/null +++ b/platforms/arty-a7-toy/UPSTREAM_MANIFEST.json @@ -0,0 +1,1014 @@ +{ + "upstream_repository": "https://github.com/DangoSys/buckyball.git", + "commit": "1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097", + "files": { + "LICENSE": { + "sha256": "8aaa2affbbd7b350dea52e1ff1b78198f83f9e1117ce83def35f71de9753217a" + }, + "arch/build.sc": { + "sha256": "81f6e27f6bcdb2c40257c39eda333032a9bf9874478e3c8c65b679e1ab270838" + }, + "arch/src/main/resources/bootrom/linux/Makefile": { + "sha256": "25770880805ba5e2f2202b88b4d12c4ee36983d51fca0363bb3207527764ac12" + }, + "arch/src/main/resources/bootrom/linux/bootrom.S": { + "sha256": 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hardware acceptance + +Measured with Vivado 2024.1 on `xc7a100tcsg324-1`, using the exact Chisel core +hash `4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779`. +Read [the preserved detailed report](evidence/2026-10-11/BOARD_REPORT.md) and +[machine record](evidence/2026-10-11/BOARD_RESULT.json) for provenance and scope. + +| Complete routed board | Result | +|---|---:| +| Physical Slice LUT | 54,413 / 63,400 (85.82%) | +| Occupied Slice sites | 15,663 / 15,850 (98.82%) | +| FF / BRAM tiles / DSP | 35,600 / 29 / 117 | +| Gemmini PE DSP | 64 | +| WNS / WHS | +1.276 / +0.013 ns | +| TNS / THS / routing errors | 0 / 0 / 0 | +| Fully routed nets | 95,231 | +| CDC Critical / worst bus-skew slack | 0 / +10.844 ns | +| DRC Error or Critical Warning | 0 | +| Full build / timeout | 1,406.2 / 3,600 seconds | + +Only 187 Slice sites remain. The 8,987 remaining LUTs cannot be treated as free +placement capacity. The LUT6 primitive count, 20,797, is a subset of physical +LUT utilization. An equivalent-driver merge was rejected: it reduced LUTs to +53,976 but increased occupied Slice sites to 15,778. No further core cuts were +made to obtain the selected result. + +## Functional checks + +- Original CPU/Sv39/FPU/AMO/cache/interrupt oracle through board AXI/SCU: + 709,434 cycles. Original Gemmini: 13/13, 251,063 cycles. +- Correct-comparison 40 alternating OS/WS loops: 684,219 cycles; unaligned and + cross-page DMA: 1,914,839 cycles. Test expectations are preserved. +- Fullwidth AXI, SCU and CRC loader unit tests; 200-byte SCU FIFO buffering. + Actual Xilinx CDC IP passes 90 read beats at 25/83.33 MHz independent clocks. +- Real UART RTL signals load and read back all 110,592 original CPU-program + bytes, reject corrupt requests and release CPU only through RUN; original + oracle passes. No preloaded DDR or forced CPU release in that test. +- OpenSBI/Linux 6.6/BusyBox RTL boot: COW, page protection, FP64 process context, + timer and overall system-check PASS, 273,506,752 cycles. The page-protection + test deliberately causes a child SIGSEGV; its parent checks the expected fault. + +Linux testing directly releases the CPU; the loader is verified independently. +RTL simulations substitute a stalled AXI memory model for the DDR PHY. CDC +functional models do not simulate metastability. No routed-netlist functional +simulation or power measurement is claimed. Gemmini stress coverage is limited +to M8/N32/K8, shift zero and no loop bias; arbitrary tails, cross-K-tile loop +accumulation and loop bias are not established by that test. + +## Physical acceptance still required + +The staged repository package was separately relocated into a fresh Linux +directory. Scala/Chisel and OpenSBI were recompiled: generated core/RAM and the +payload exactly match the hashes above. AXI/SCU/loader tests and Python/Bash +syntax checks pass. Pinned dependency exports and the already built Linux image +were reused; the kernel was not rebuilt in this packaging check. The explicit +`sha256` manifest schema exports all 336 Git blobs correctly. See +`evidence/2026-10-11/PACKAGE_PREFLIGHT.json`. + +The source digest of upstream `TokenManager.scala` previously matched a generic +API-key heuristic. The manifest now labels each digest with a `sha256` field; +source paths, Git revision and digest values are unchanged. Gitleaks 8.30.1 +reports no leaks in the staged PR; no ignore rule or scanner waiver was added. + +Physical board revision is unknown; MIG parameters are official Digilent E.0. +DDR calibration, physical Linux boot and operator execution on hardware remain +untested. Treat the image as an engineering target for first bring-up. +DRC retains 360 warnings; methodology retains 49 warnings and 16 advisories, +including DSP pipeline recommendations, MIG clock/reset structure, control-set +packing and a potential D-cache SDQ address collision. Reports are preserved; +severities were not downgraded and no CDC waiver was used. + +The validated engineering bitstream SHA256 is +`ccc33c511e613561fb9dd1e9c847bd3b84037da1d078c44cd3de197d55dffde1`. +The corresponding 17,409,032-byte payload SHA256 is +`eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f`. +These binaries are not stored in Git. Rebuilt software may differ by compiler +and build timestamps; a new core/board toolchain requires fresh functional and +implementation checks rather than inheriting these measured results. diff --git a/platforms/arty-a7-toy/board/README.md b/platforms/arty-a7-toy/board/README.md new file mode 100644 index 0000000..e744dcf --- /dev/null +++ b/platforms/arty-a7-toy/board/README.md @@ -0,0 +1,25 @@ +# Board integration + +Build and programming commands are in [the platform guide](../README.md). +This directory targets Arty A7-100T `xc7a100tcsg324-1` with official Digilent +Rev E.0 DDR parameters. Physical board revision and DDR acceptance are pending. + +- `toy_a7_top.sv`: 100 MHz input, MMCM/BUFG clocks, per-domain reset sequencing, + physical UART/LED/DDR pins, actual MIG and AXI Clock Converter instances. +- `toy_a7_platform.sv`: validated Chisel core, loader/CPU DDR arbitration, + fullwidth memory adapter and SCU console. CPU remains reset until verified RUN. +- `axi_fullwidth.sv`: preserves lanes, strobes, IDs and backpressure while + translating narrow INCR/FIXED beats into aligned 128-bit DDR accesses. +- `ddr_uart_loader.sv` / `loader_axi.sv`: CRC-framed load, readback and release; + acknowledgements wait for DDR responses. INFO bytes preserve LUTRAM inference. +- `axi_scu.sv`: UART/exit MMIO and 256-byte RX FIFO, with accepted-response pops. +- `arty_a7.xdc`: actual pins and targeted asynchronous I/O/reset exceptions; + DDR data/address/control and internal CPU timing remain checked. +- `build_board.tcl`: complete IP generation, synthesis, placement, routing and + bitstream. Setup/hold, CDC Critical, bus skew, routing errors and DRC errors + stop the build. No warning severity downgrade or CDC waiver is applied. +- `program_arty.tcl`: explicit volatile JTAG programming; exactly one target + and one XC7A100T required. It does not program configuration flash. + +`vendor/` contains unmodified pinned Digilent MIG/board inputs and their license. +Vivado generates proprietary vendor IP into ignored build directories locally. diff --git a/platforms/arty-a7-toy/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/board/arty_a7.xdc b/platforms/arty-a7-toy/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/board/axi_fullwidth.sv b/platforms/arty-a7-toy/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/board/build_board.tcl b/platforms/arty-a7-toy/board/build_board.tcl new file mode 100644 index 0000000..b92682e --- /dev/null +++ b/platforms/arty-a7-toy/board/build_board.tcl @@ -0,0 +1,78 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]!=1} {error "Usage: build_board.tcl OUTPUT_DIRECTORY"} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; hardware revision and Linux boot unverified" diff --git a/platforms/arty-a7-toy/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/board/loader_axi.sv b/platforms/arty-a7-toy/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/board/program_arty.tcl b/platforms/arty-a7-toy/board/program_arty.tcl new file mode 100644 index 0000000..f70f054 --- /dev/null +++ b/platforms/arty-a7-toy/board/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +program_hw_devices $device +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/board/toy_a7_platform.sv b/platforms/arty-a7-toy/board/toy_a7_platform.sv new file mode 100644 index 0000000..8757e24 --- /dev/null +++ b/platforms/arty-a7-toy/board/toy_a7_platform.sv @@ -0,0 +1,445 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready +); + wire cpu_reset=reset || !cpu_run; + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq) + ); +endmodule diff --git a/platforms/arty-a7-toy/board/toy_a7_top.sv b/platforms/arty-a7-toy/board/toy_a7_top.sv new file mode 100644 index 0000000..4d86921 --- /dev/null +++ b/platforms/arty-a7-toy/board/toy_a7_top.sv @@ -0,0 +1,288 @@ +module toy_a7_top ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/board/uart_rx.sv b/platforms/arty-a7-toy/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/board/uart_tx.sv b/platforms/arty-a7-toy/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/board/vendor/License.txt b/platforms/arty-a7-toy/board/vendor/License.txt new file mode 100644 index 0000000..b76cf0c --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/License.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Digilent, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/platforms/arty-a7-toy/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/board/vendor/board.xml b/platforms/arty-a7-toy/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Pullups to enable shield I2C + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 4 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 256 MB DDR3L memory SODIMM + + + + + + + DIP Switches 3 to 0 + + + PHY Ethernet on the board + + + + + + + + + + + Shield i2c + + + Shield i2c pullups, must pull high if using the shield I2C on J3 + + + LEDs 3 to 0 + + + Push buttons 3 to 0 + + + 16 MB of nonvolatile storage that can be used for configuration or data storage + + + CPU Reset Push Button, active low + + + RGB leds 12 to 0 (3 per LED) + + + Shield pins 0 through 19 + + + Shield pins 26 through 41 + + + Shield SPI + + + 3.3V Single-Ended 100MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/board/vendor/mig.prj b/platforms/arty-a7-toy/board/vendor/mig.prj new file mode 100644 index 0000000..1bff709 --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a100t-csg324/-1 + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/platforms/arty-a7-toy/board/vendor/part0_pins.xml b/platforms/arty-a7-toy/board/vendor/part0_pins.xml new file mode 100644 index 0000000..dc32e54 --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/part0_pins.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/board/vendor/preset.xml b/platforms/arty-a7-toy/board/vendor/preset.xml new file mode 100644 index 0000000..ec20fb4 --- /dev/null +++ b/platforms/arty-a7-toy/board/vendor/preset.xml @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/build.sbt b/platforms/arty-a7-toy/build.sbt new file mode 100644 index 0000000..c29b46e --- /dev/null +++ b/platforms/arty-a7-toy/build.sbt @@ -0,0 +1,70 @@ +ThisBuild / scalaVersion := "2.13.16" +ThisBuild / organization := "srtp.fpga" +ThisBuild / version := "0.1.0" +ThisBuild / scalacOptions ++= Seq("-language:reflectiveCalls", "-Ymacro-annotations", "-deprecation", "-feature") + +lazy val chiselSettings = Seq( + scalaVersion := "2.13.16", + libraryDependencies += "org.chipsalliance" %% "chisel" % "6.7.0", + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.7.0" cross CrossVersion.full) +) +lazy val cde = project.in(file("thirdparty/cde")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "cde/src/chipsalliance" +) +lazy val diplomacy = project.in(file("thirdparty/diplomacy/diplomacy")).dependsOn(cde).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "src/diplomacy", + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.0" +) +lazy val hardfloat = project.in(file("thirdparty/hardfloat/hardfloat")).dependsOn(cde).settings(chiselSettings) +lazy val macros = project.in(file("thirdparty/rocket-chip/macros")).settings( + libraryDependencies += "org.scala-lang" % "scala-reflect" % "2.13.16" +) +lazy val rocket = project.in(file("thirdparty/rocket-chip")).dependsOn(cde, diplomacy, hardfloat, macros).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "src/main/scala") ** "*.scala").get + original.filterNot(f => f.getName == "FPU.scala") ++ + ((baseDirectory.value / "../../patches/rocket") ** "*.scala").get + }, + libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", + "org.json4s" %% "json4s-jackson" % "4.0.5", + "org.scala-graph" %% "graph-core" % "1.13.5" + ) +) +lazy val inclusive = project.in(file("thirdparty/inclusive-cache")).dependsOn(rocket).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "design/craft" +) +lazy val midas = project.in(file("thirdparty/firesim-compile")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "../firesim/sim/midas/targetutils/src/main/scala" +) +lazy val gemmini = project.in(file("thirdparty/gemmini-compile")).dependsOn(rocket, midas).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "../gemmini/src/main/scala") ** "*.scala").get + original.filterNot(f => Set("PE.scala", "Tile.scala", "Mesh.scala")(f.getName)) ++ + ((baseDirectory.value / "../../patches/gemmini") ** "*.scala").get + }, + Compile / unmanagedResourceDirectories += baseDirectory.value / "../gemmini/src/main/resources" +) +lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chiselSettings).settings( + name := "toy-arty-a7-linux", + libraryDependencies ++= Seq( + "com.lihaoyi" %% "upickle" % "3.3.1", + "tech.sparse" %% "toml-scala" % "0.2.2" + ), + Compile / unmanagedSources ++= { + val upstream = baseDirectory.value / "upstream" + val framework = upstream / "arch/src/main/scala/framework" + val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", + "system/core/rocket", "system/core/accelerator", "system/tile") + val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ + ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => + val ball = upstream / "examples/balls" / name + ((ball / "arch/src/main/scala") ** "*.scala").get.filterNot(f => + Set("GemminiExCtrl.scala", "GemminiExCtrlDefs.scala", + "GemminiExCtrlComputeFeedState.scala", "GemminiExCtrlStoreOps.scala", + "GemminiExCtrlPreloadStates.scala", "GemminiExCtrlCmdStates.scala", "GemminiBall.scala", "LoopMatmulUnroller.scala")(f.getName)) ++ ((ball / "configs") ** "*.scala").get + } + } +) diff --git a/platforms/arty-a7-toy/config/gemmini-8.toml b/platforms/arty-a7-toy/config/gemmini-8.toml new file mode 100644 index 0000000..08da5ab --- /dev/null +++ b/platforms/arty-a7-toy/config/gemmini-8.toml @@ -0,0 +1,12 @@ +# Gemmini Ball Configuration + +[ball] +meshRows = 8 +meshColumns = 8 +tileRows = 1 +tileColumns = 1 +inputWidth = 8 +accWidth = 32 +spatialOutputWidth = 20 +tileLatency = 0 +outputDelay = 1 diff --git a/platforms/arty-a7-toy/dependencies.json b/platforms/arty-a7-toy/dependencies.json new file mode 100644 index 0000000..285ef6d --- /dev/null +++ b/platforms/arty-a7-toy/dependencies.json @@ -0,0 +1,31 @@ +{ + "rocket-chip": { + "repository": "SEU-ACAL/rocket-chip", + "commit": "35488f108c1ee9e42175b5240ae957d8970e9c5b" + }, + "inclusive-cache": { + "repository": "SEU-ACAL/rocket-chip-inclusive-cache", + "commit": "88317ea415459d274026bd59850517a9fcc87ede" + }, + "cde": { + "repository": "chipsalliance/cde", + "commit": "2bcaeae2b9914bd25497ce3c6fa62dc5ca80e09f" + }, + "diplomacy": { + "repository": "chipsalliance/diplomacy", + "commit": "fe5e131d4fc8adec14a3ce4a4935bb5c0a269871" + }, + "hardfloat": { + "repository": "SEU-ACAL/berkeley-hardfloat", + "commit": "536cf3727f655713f424438190100bb08cbf2e5a" + }, + "gemmini": { + "repository": "ucb-bar/gemmini", + "commit": "8c3f9923a44a2fe2c7930587be297d6d4f8c09ca" + }, + "firesim": { + "repository": "firesim/firesim", + "commit": "da2a1cbcebbb96e21c551ebef513fd95a9d73403", + "subtree": "sim/midas/targetutils" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_REPORT.md new file mode 100644 index 0000000..80ddfea --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_REPORT.md @@ -0,0 +1,101 @@ +# Toy 8×8 Arty A7-100T 整板实现核验 + +2026-10-11，Vivado 2024.1，器件 `xc7a100tcsg324-1`。 + +**整板布局布线、时序、CDC 检查及 bitstream 生成通过；板级 RTL 的 Linux 用户态检查通过。** +尚未在实物验证 DDR 校准或 Linux；板卡硬件 revision 未知，当前采用官方 Digilent E.0 MIG 工程参数。 +不能把 RTL 仿真或 bitstream 生成当作实物上板成功。 + +## 保留功能与板级接口 + +保留此前已验证的 Chisel Toy 核心：RV64 CPU、M/S/U、PMP、Sv39、FP16/32/64 共享 FMA、 +I/D cache、Gemmini 8×8、64 个 DSP PE、64 KiB 加速器 SRAM 与现有 23 个 opcode。 +核心 RTL SHA256 未变：`4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779`。本轮没有继续裁剪核心功能。 + +加入官方 MIG 256 MiB DDR3L、实际 Xilinx AXI Clock Converter、窄访问转全宽 DDR 适配器、 +SCU 控制台、CRC 串口加载/读回、时钟、复位和板级引脚约束。 +100 MHz 板载时钟生成 25 MHz 核心、166.67 MHz MIG 输入和 200 MHz 参考时钟； +MIG UI 83.33 MHz，CLINT 实际 500 kHz，串口 1 Mbps、8N1。 + +DDR 地址 `0x80000000..0x8fffffff`；SCU EXIT `0x60000000`，TX/RX/STATUS +`0x60020000/04/05`。串口 RX FIFO 为 256 字节。OpenSBI 适配实际计时频率和 CPU DTB 属性； +Linux/BusyBox Image 与原版本相同，没有去除虚拟内存、FPU 或 Linux。 + +## 最终整板实测 + +| 项目 | 布线后 | A7-100T 容量 | +|---|---:|---:| +| 物理 Slice LUT | 54,413 | 63,400 | +| 占用 Slice | 15,663 | 15,850 | +| FF | 35,600 | 126,800 | +| BRAM tile | 29 | 135 | +| DSP | 117 | 240 | +| WNS / TNS | +1.276 ns / 0 | | +| WHS / THS | +0.013 ns / 0 | | + +LUT 余量 8,987（14.18%）；建立/保持违例端点均 0。 +Slice 占用 98.82%，只余 187 个，控制集 1,256 个。 +尽管已经完成布线，布局打包仍紧，LUT 余量不能当作可自由增加功能的空间。 +LUT6 原语 20,797 是子项；判断容量使用包含各输入规模和 RAM 的物理 Slice LUT。 +95,231 条可布线网络全部布通，路由错误 0。 +整板最大/最小时序涵盖实际 MMCM、MIG 和 CDC，不能用单独的核心 OOC 时序替代。 +10 项总线偏斜约束通过，最差裕量 10.844 ns。 + +`AreaOptimized_high`、`resource_sharing on` 与 `ExploreArea` 保持输入 RTL 不变。 +最终采用完整复位修复版构建，未采用后续两项打包试验。 +等效驱动合并在旧复位网表上曾减少 Slice，但在相同修复版综合检查点上重跑后， +LUT 从 54,413 降至 53,976，Slice 却从 15,663 增至 15,778（99.55%）； +因此保留 Slice 余量更好的 15,663 版本。低扇出使能重映射也因 LUT 增加而未采用。 +这些测量及合并版 bitstream 保留为比较证据，不作为推荐上板版本。 +加载器 INFO 改为直接生成回复字节，使 256 字节 staging RAM 恢复 LUTRAM 推断。 +之前默认策略整板综合 64,077 LUT、布局失败；失败日志及检查点保留，不与最终布线结果混用。 + +## CDC、约束及警告 + +CDC Critical 为 0。MIG 复位改为参考时钟域的同步按钮和寄存器输出，解决上轮两项 +CDC-10（同步器前组合逻辑）；没有降级 severity 或建立 waiver。 +修复版综合快照仍报告两条 MIG 内部辅助复位链；这些无用路径在实现优化后被移除， +最终严格零 Critical 检查通过。历史分析保存在 `evidence/synth-cdc-review`，不参与构建放行。 +CDC-15 警告来自 Xilinx AXI 异步 FIFO 的 RAM 读使能结构，实际 IP 功能回归通过， +相应跨域最大延迟及总线偏斜约束通过；功能模型不模拟亚稳态。 + +内部未约束端点、无时钟、组合环路等检查均为 0。缺少同步 I/O 延迟的端口仅为 +异步 BTN/UART 输入、LED/UART 输出和 MIG 管理的 DDR RESET_N，均有对应定点例外。 +DDR 数据、地址、控制及所有内部 CPU 路径保留时序检查。DRC 无 Error/Critical Warning； +原始 DSP 流水建议、MIG PLL 混合缓冲、MIG 内部复位 LUT、D-cache SDQ 可能读写碰撞、 +缺少同步器属性和控制集数量等方法学警告完整保留，未声称全部消除。 + +## 功能证据 + +| 原有二进制经板级 AXI/SCU | 结果 | 周期 | +|---|---|---:| +| cpu | PASS | 709,434 | +| gemmini | PASS | 251,063 | +| loop | PASS | 684,219 | +| dma | PASS | 1,914,839 | + +原 CPU 程序和比较预期不变。另有 AXI、SCU、CRC loader 三项单元回归，以及实际 Xilinx +CDC IP 的 90 个读回拍：覆盖 8..128 bit 访问、INCR/FIXED、字节掩码、并发读写、停顿、ID +及非法地址/跨 4 KiB 拒绝。SCU 测试包含 200 字节缓冲和读回。 + +串口启动测试经真实 UART 引脚信号写入并逐字节读回 110,592 字节原 CPU 程序， +拒绝坏 CRC/RUN，随后真实 RUN 释放 CPU 并通过原 CPU oracle；没有预加载 DDR 或强制启动。 + +Linux RTL 仿真启动 OpenSBI、Linux 6.6 和 BusyBox，经真实 UART RX 输入 +`/root/linux_system_check-linux`，COW、页保护、FP64 进程上下文、定时器及总检查通过。 +共 273,506,752 核心周期；UART 输入 overflow/framing 均为 0。 +先前结束监测少取一个字符，导致已有 PASS 输出后仍超时；失败日志保留，修正监测后重新运行通过。 +这些仿真用停顿 AXI 存储模型替代 DDR PHY；Linux bench 直接释放启动，加载器另行验证。 +没有布线后功能仿真或功耗实测。Gemmini 任意尾维度、跨 K-tile 累加等原有覆盖边界见 +`GEMMINI_CORRECT_REPORT.md`，未扩充为未经测试的完整算子覆盖。 + +## 文件、超时与使用 + +整板目录 `build/board-20261011-132657`；bitstream `toy_a7.bit`，布线检查点 `routed.dcp`。 +整个 Vivado 进程组硬超时 3,600 秒，TERM 后 15 秒 KILL；实际 1406.2 秒，未触发。 +368 份文件下载后核验远程 SHA256，机器结果 `BOARD_RESULT.json`。 +bitstream SHA256：`ccc33c511e613561fb9dd1e9c847bd3b84037da1d078c44cd3de197d55dffde1`。 + +加载镜像 `build/board-software/fw_payload.bin`，17,409,032 字节， +SHA256 `eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f`。确认实物 DDR/revision 与目标兼容后才使用该工程 bitstream； +加载方式、LED 含义及复现命令见 `board/README.md`。本轮没有烧录或新建 PR。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_RESULT.json new file mode 100644 index 0000000..d19c20a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/BOARD_RESULT.json @@ -0,0 +1,315 @@ +{ + "result": "PASS_BOARD_IMPLEMENTATION_AND_RTL_REGRESSIONS", + "run": "board-20261011-132657", + "part": "xc7a100tcsg324-1", + "elapsed_seconds": 1406.1690039649839, + "timeout_seconds": 3600, + "timeout_triggered": false, + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "board_sources": { + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/README.md": "891e436088f5e2205de4e0dffbaec8217f074e5b9f216657fa29142cd1d46799", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "404cf6ab82b7bc0aeff2d3eeb7855f2e2028784ff4408a6c97eec023464c039f", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "a3d2808a2bcaa1aa4381e51c9df3ba358d96acdbabd08939e60c073c65550dfc", + "board/build_board.tcl": "4fdb448d41a2119eade666fc0b26bd436edd5fda2204a4849e40e00ed4050526", + "board/toy_a7_platform.sv": "db7e7bd98ce81d6c538157e462232d380fe7318a2d0cfeb3afed6773ba127c4c", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "previous_source_files_verified": 98, + "unchanged_upstream_files_verified": 336, + "previous_download_files_verified": 212, + "equivalent_driver_merge_comparison": { + "run": "board-20261011-135159", + "same_synthesis_input": true, + "routed_resources": { + "LUT": 53976.0, + "FF": 35492.0, + "BRAM_tiles": 29.0, + "DSP": 117.0, + "Slice": 15778 + }, + "selected": false, + "reason": "Higher occupied Slice count" + }, + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", + "input_synthesis_run": null, + "control_set_merge": false, + "gemmini_mesh_dsp": 64, + "bitstream_sha256": "ccc33c511e613561fb9dd1e9c847bd3b84037da1d078c44cd3de197d55dffde1", + "routed_dcp_sha256": "6bf677d11975285a207fa734e486faa258a5feae7eca8667154aafe1e94c39fe", + "routed_resources": { + "LUT": 54413.0, + "FF": 35600.0, + "BRAM_tiles": 29.0, + "DSP": 117.0, + "Slice": 15663, + "control_sets": 1256, + "LUT6_primitives": 20797 + }, + "timing": { + "wns_ns": 1.276, + "tns_ns": 0.0, + "failing_setup_endpoints": 0.0, + "setup_endpoints": 112427.0, + "whs_ns": 0.013, + "ths_ns": 0.0, + "failing_hold_endpoints": 0.0, + "hold_endpoints": 112385.0 + }, + "timing_checks": { + "no_clock": 0, + "constant_clock": 0, + "pulse_width_clock": 0, + "unconstrained_internal_endpoints": 0, + "no_input_delay": 2, + "no_output_delay": 6, + "multiple_clock": 0, + "generated_clocks": 0, + "loops": 0, + "partial_input_delay": 0, + "partial_output_delay": 0, + "latch_loops": 0 + }, + "route_status": { + "logical nets": 121758, + "routable nets": 95231, + "fully routed nets": 95231, + "nets with routing errors": 0 + }, + "cdc": [ + { + "rule": "CDC-3", + "severity": "Info", + "count": 17 + }, + { + "rule": "CDC-9", + "severity": "Info", + "count": 10 + }, + { + "rule": "CDC-15", + "severity": "Warning", + "count": 3 + } + ], + "bus_skew_constraints": 10, + "worst_bus_skew_slack_ns": 10.844, + "drc": [ + { + "rule": "DPIP-1", + "severity": "Warning", + "count": 152 + }, + { + "rule": "DPOP-1", + "severity": "Warning", + "count": 102 + }, + { + "rule": "DPOP-2", + "severity": "Warning", + "count": 104 + }, + { + "rule": "REQP-1709", + "severity": "Warning", + "count": 1 + }, + { + "rule": "RTSTAT-10", + "severity": "Warning", + "count": 1 + } + ], + "methodology": [ + { + "rule": "LUTAR-1", + "severity": "Warning", + "count": 2 + }, + { + "rule": "SYNTH-5", + "severity": "Warning", + "count": 16 + }, + { + "rule": "SYNTH-9", + "severity": "Warning", + "count": 5 + }, + { + "rule": "SYNTH-10", + "severity": "Warning", + "count": 21 + }, + { + "rule": "SYNTH-16", + "severity": "Warning", + "count": 1 + }, + { + "rule": "TIMING-10", + "severity": "Warning", + "count": 1 + }, + { + "rule": "ULMTCS-1", + "severity": "Warning", + "count": 1 + }, + { + "rule": "XDCB-5", + "severity": "Warning", + "count": 2 + }, + { + "rule": "REQP-1959", + "severity": "Advisory", + "count": 16 + } + ], + "board_unit": { + "result": "PASS", + "tests": 3, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "404cf6ab82b7bc0aeff2d3eeb7855f2e2028784ff4408a6c97eec023464c039f", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "a3d2808a2bcaa1aa4381e51c9df3ba358d96acdbabd08939e60c073c65550dfc", + "board/toy_a7_platform.sv": "db7e7bd98ce81d6c538157e462232d380fe7318a2d0cfeb3afed6773ba127c4c", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "3f58d9d98ba02663f913caecf0fd3e4aea11d0b2bc637e59566fcfe674fffe86" + } + }, + "regression": { + "result": "PASS", + "tests": { + "cpu": { + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 + }, + "gemmini": { + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 + }, + "loop": { + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 + }, + "dma": { + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 + } + } + }, + "converter": { + "result": "PASS_BOARD_CDC", + "board_run": "board-20261011-132657", + "core_clock_hz": 25000000, + "ui_clock_hz": 83333333, + "read_beats": 90, + "physical_mig_simulated": false, + "xci_sha256": "33a73fd614db8bd3daf6d45a6c747e087caacd7e7ef6f610f3cc894120eac025", + "bench_sha256": "0903001dfe5bb2d8d5a36eb84545f6e08a2eb3c8bd86c8f20a1ff37c9bb51de2" + }, + "uart_boot": { + "result": "PASS_UART_LOAD_VERIFY_BOOT", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "bytes_verified": 110592, + "testbench_cpu_release_override": false, + "preloaded_ddr_image": false, + "physical_mig_simulated": false, + "physical_board_tested": false, + "cycles": 61853990 + }, + "linux": { + "result": "PASS_RTL_LINUX_USERSPACE", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "checks": [ + "OpenSBI", + "Linux version", + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK", + "PASS BOARD_LINUX_USERSPACE" + ], + "physical_mig_simulated": false, + "physical_board_tested": false, + "uart_rx_command_tested": true + }, + "firmware": { + "result": "PASS_BUILD", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "payload_bytes": 17409032, + "linux_image_sha256": "79aef0e6c72be764dfc37a55cbe7587e00531265b59343125b3a6950509d9e7a", + "linux_image_unchanged": true, + "clint_frequency_hz": 500000, + "core_frequency_hz": 25000000, + "console_base": "0x60020000", + "memory_bytes": 268435456, + "original_platform_sha256": "215cc16a14101a2b987fb05f8619ccf20eef610f5f88c6561575e9a25fff7773", + "adapted_platform_sha256": "f1a7a6d2921105055adb66e9df759d12196cdf9d63d15966c66276f69354fc9f", + "original_payload_sha256": "762d608b5e23a0a438c0139bc7487143fd97e30de110d44fb7e2ba27ac07477f", + "boot_tested": false, + "command": [ + "make", + "-C", + "/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/opensbi-src", + "-j8", + "CROSS_COMPILE=riscv64-linux-gnu-", + "PLATFORM_DIR=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/platform", + "PLATFORM=buckyball", + "O=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/opensbi-build", + "FW_PAYLOAD_PATH=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/Image", + "BUCKYBALL_VISIBLE_HART_COUNT=1", + "BUCKYBALL_TOTAL_HART_COUNT=1", + "BUCKYBALL_HIDDEN_HART_BASE=1" + ] + }, + "linux_cycles": 273506752, + "linux_console_characters": 7992, + "downloaded_files_verified": 368, + "physical_board_revision": "unknown", + "vendor_revision": "E.0", + "physical_ddr_calibration_tested": false, + "physical_linux_boot_tested": false, + "post_route_functional_simulation_run": false, + "board_release_ready": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md new file mode 100644 index 0000000..78cc529 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md @@ -0,0 +1,78 @@ +# Toy 8×8 Gemmini 分块与 WS 偏置修复 + +2026-10-11；Arty A7-100T，`xc7a100tcsg324-1`。 +前一轮真实失败的分块与非零 WS 偏置回归已通过；保留原程序、参考算法、比较及二进制。 +CPU、Sv39、FP16/32/64、8×8 阵列、全 DSP PE、RF LUTRAM、共享 FMA 和全部保留指令不变。 + +## 根因与改动 + +- 并发 MVIN/MVOUT 共用分组查询，原实现让 storer 覆盖 loader 的查询地址，两者无条件采样同一回复。 + A 应有 1 组却拿到 C 的 4 组，导致重复覆盖输入行并读到矩阵之外。增加请求/响应握手和轮询仲裁， + 保持两级查询地址及回复归属；仅串行化配置查询，DMA 数据搬运仍可并发。 +- WS 循环原来固定预装 A，并把 B 当作偏置输入。现在按已接受的 CONFIG 锁存模式：WS 预装 B， + 无偏置循环以 zero_op2 清零部分和输入；OS 路径保持原行为。 +- 非零 WS 偏置应从 mesh 的 b 端输入；原实现送到 d 端，偏置被忽略。改为 b=偏置、d=0。 +- SubROB 同周期入队和退休分别赋值 rowCount，后赋值覆盖前赋值。改为统一占用计数更新， + 同时发生时保持不变；最后一行退休且新行入队时继续执行，不提前报告主指令完成。 + +所有改动位于 Chisel 源码覆盖层并重新生成 RTL，原版 336 份 Buckyball 导出源文件未修改。 + +## 回归与负向对照 + +| 检查 | 最终结果 | +|---|---| +| 原 Gemmini C 测试 | 13/13 PASS，245,517 周期 | +| 40 轮 OS/WS 分块，M8/N32/K8 | 10,240 个 INT32 全部匹配，652,682 周期 | +| 64 个非零偏置/移位用例 | 4,096 个结果匹配，979,581 周期 | +| 64 个零偏置移位边界用例 | 4,096 个结果匹配，978,208 周期 | +| CPU/MMU/FPU/缓存/AMO/中断 | PASS，639,544 周期 | +| 非对齐/跨页 DMA 与 guard | PASS，1,879,410 周期 | +| SubROB 连续流/空行/反压 | 40 行、39 指令，269 周期，PASS | +| 分组查询仲裁 | 每轮 256 请求，两轮；双客户端、shared/private、停顿及复位，PASS | +| 舍入单元 | 402,866 次 20/32-bit 比较，PASS | +| RAM、实际路由、RF 差分 | PASS | + +旧 WS-round 核心对同一分块二进制在 OS 第 1 轮失败、同一偏置程序在第 4 项失败；旧基线原样保留。 +中间仅修查询的核心通过 OS 第 1 轮，在 WS 第 2 轮失败；加入模式修复后全部 40 轮通过。 +原 SubROB 在流式测试丢行断言失败，修复后通过。未降低预期、跳过失败用例或换测试二进制。 +历史使用反向比较条件得出的分块 PASS 仍撤回；本轮结果来自修正后的真实比较。 + +共享 FMA 源码不变，CPU 浮点回归已重新运行；历史 250,819 次 FMA 单元差分仅作为来源证据，本轮未重跑。 + +覆盖边界：本轮分块压力程序为 M8/N32/K8、shift=0、无循环偏置；不能推广为任意循环尺寸、 +跨 K-tile 累加、循环偏置和尾维度都已验证。原 13 项及 64 项覆盖也不能替代这些扩展验证。 + +## 同条件 Vivado OOC + +Vivado 2024.1，20 ns 时钟、2 ns I/O、0.2 ns 不确定度；器件、约束和综合选项与旧版相同。 + +| 资源 | WS-round 基线 | 当前 | A7-100T 容量 | +|---|---:|---:|---:| +| 物理 LUT | 56,076 | 56,084 | 63,400 | +| FF | 29,295 | 29,306 | 126,800 | +| BRAM tile | 29 | 29 | 135 | +| DSP | 121 | 121 | 240 | + +LUT 变化 +8；64 个 PE 仍各占 1 DSP。LUT6 原语 26,547， +它是物理 LUT 的子集，不能单独用它判断是否能装下。 +核心加独立 MIG 5,052 LUT 求和估算 61,136 LUT， +估算余量 2,264；尚未包括完整板级集成和布线开销。 +50 MHz WNS -5.057 ns；25 MHz WNS +14.943 ns / TNS 0.000 ns， +WHS -0.028 ns / THS -3.584 ns，保持违例端点 217。 +没有布局布线、集成 MIG、生成 bitstream、烧录、测功耗或启动 Linux。当前是通过所列回归的核心候选。 + +## 复现与证据 + +隔离服务器目录 `/home/yys/codex-builds/toy-a7-gemmini-correct-20261010`；工作副本在 D 盘同名目录。 + +```bash +source scripts/toolchain.sh +bash scripts/run_trial.sh +python3 scripts/summarize_gemmini_correct.py +``` + +`build/serial-bound` 为回归和综合共用 RTL；`build/query-fixed-control` 保留中间失败证据。 +`RESULT.json`、源码审计、完整日志、综合 DCP 和 `evidence/SHA256.json` 记录来源与核验结果。 +本轮没有提交 PR 或烧录。 +核心 SHA256：`4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779`。 +DCP SHA256：`11b8d76e0e4a3201b9cdeea9347c382e8e406a5862bc13e7d1e45b4738b57306`。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/MEMORY_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-11/MEMORY_MANIFEST.json new file mode 100644 index 0000000..55ce36b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/MEMORY_MANIFEST.json @@ -0,0 +1,126 @@ +{ + "emitted_sha256": "37167bb372ca0358b4a4e73cc3ff2e6ab869fee0a229142d51bcf405af6d7341", + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": [ + { + "module_name": "tag_array_ext", + "depth": 32, + "width": 92, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 23, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.meta.tag_array.tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "array_0_0_ext", + "depth": 128, + "width": 128, + "masked": true, + "read": 1, + "write": 1, + "readwrite": 0, + "mask_granularity": 64, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_0.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_0.array_0_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "bbtile_icache_tag_array_ext", + "depth": 64, + "width": 42, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 21, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_tag_array.bbtile_icache_tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "bbtile_icache_data_arrays_0_ext", + "depth": 256, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 32, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_3.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_2.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_1.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_0.bbtile_icache_data_arrays_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "sram_ext", + "depth": 8, + "width": 1269, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.subRob.sram.sram_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "mem_ext", + "depth": 1024, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 8, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_7.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_6.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_5.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_4.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_3.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_2.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_1.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_0.mem.mem_ext" + ], + "ram_style": "block" + } + ], + "baseline_core_rtl_sha256": "ebfa2bb47b7105274f2bc83b5328c18d18e8718173d10dff089589de5162e0a3", + "additional_memory_adapters": [ + { + "module": "regfile_32x65", + "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, + "write_ports": 2, + "read_latency": 0, + "same_address_write_priority": "W1", + "added_cycles": 0, + "adapter_sha256": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/PACKAGE_PREFLIGHT.json b/platforms/arty-a7-toy/evidence/2026-10-11/PACKAGE_PREFLIGHT.json new file mode 100644 index 0000000..d148299 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/PACKAGE_PREFLIGHT.json @@ -0,0 +1,21 @@ +{ + "result": "PASS_RELOCATED_PACKAGE", + "source": "staged FPGA repository package in a fresh isolated Linux directory", + "whole_command_timeout_seconds": 3600, + "scala_and_chisel_recompiled": true, + "dependencies_reused_from_pinned_isolated_build": true, + "linux_image_reused_from_pinned_software_build": true, + "kernel_recompiled_in_this_preflight": false, + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", + "core_and_memory_equal_validated_bytes": true, + "opensbi_recompiled": true, + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "payload_equal_validated_bytes": true, + "python_compile_passed": true, + "bash_syntax_passed": true, + "axi_scu_loader_unit_tests_passed": true, + "explicit_sha256_manifest_export_verified_files": 336, + "new_manifest_export_test": "Git objects from the pinned upstream commit, after manifest schema clarification", + "physical_hardware_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.dts b/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.dts new file mode 100644 index 0000000..1b8eff4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.dts @@ -0,0 +1,118 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.profile.json b/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.profile.json new file mode 100644 index 0000000..8207768 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/ToyLinuxChip.profile.json @@ -0,0 +1,73 @@ +{ + "serial_fpga": true, + "gemmini_only_balls": true, + "ball_count": 1, + "ball_names": [ + "GemminiBall" + ], + "ball_ids": [ + 0 + ], + "ball_funct7": [ + 2, + 3, + 53, + 66, + 67, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105 + ], + "ball_read_ports": 2, + "ball_write_ports": 4, + "accelerator_mmio_scale_pool": false, + "compact_caches": true, + "btb_enabled": false, + "icache_bytes": 8192, + "icache_ways": 2, + "dcache_bytes": 8192, + "dcache_mshrs": 1, + "l2_ways": 0, + "coherence_manager": "broadcast", + "rob_entries": 16, + "sub_rob_depth": 8, + "dma_n_xacts": 2, + "dma_max_in_flight": 4, + "tma_read_channels": 1, + "tma_write_channels": 1, + "cpu_mul_unroll": 8, + "gemmini_rows": 8, + "gemmini_columns": 8, + "virtual_bank_count": 16, + "trimmed_optional_peripherals": true, + "scratchpad_bytes": 0, + "cpu_use_debug": false, + "cpu_breakpoints": 0, + "extra_hpm_counters": 0, + "basic_counters": true, + "use_vm": true, + "fpu_shared_fma": true, + "fpu_sfma_latency": 6, + "fpu_dfma_latency": 6, + "fpu_min_flen": 16, + "fpu_flen": 64, + "bank_count": 8, + "bank_rows": 1024, + "bank_width": 64, + "bank_channels": 7 +} \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/bus-skew.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/bus-skew.rpt new file mode 100644 index 0000000..cae57ad --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/bus-skew.rpt @@ -0,0 +1,1380 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:42 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_bus_skew -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +Table of Contents +----------------- +1. Bus Skew Report Summary +2. Bus Skew Report Per Constraint + +1. Bus Skew Report Summary +-------------------------- + +Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns) +-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- +1 30 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.621 11.379 +2 32 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.637 11.363 +3 34 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.600 11.400 +4 36 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.093 10.907 +5 38 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.887 11.113 +6 40 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.022 10.978 +7 42 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.746 11.254 +8 44 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.895 11.105 +9 46 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.919 11.081 +10 48 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.156 10.844 + + +2. Bus Skew Report Per Constraint +--------------------------------- + +Id: 1 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.621 11.379 + + +Slack (MET) : 11.379ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.861ns + Reference Relative Delay: -1.902ns + Relative CRPR: 0.420ns + Actual Bus Skew: 0.621ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.715 -0.825 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X72Y96 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X72Y96 FDRE (Prop_fdre_C_Q) 0.456 -0.369 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.607 0.238 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X73Y96 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X73Y96 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 1.160 + SLICE_X73Y96 FDRE (Setup_fdre_C_D) -0.061 1.099 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 0.238 + clock arrival 1.099 + ------------------------------------------------------------------- + relative delay -0.861 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.582 -1.439 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X75Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y100 FDRE (Prop_fdre_C_Q) 0.367 -1.072 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.483 -0.588 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X75Y99 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X75Y99 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.143 + SLICE_X75Y99 FDRE (Hold_fdre_C_D) 0.170 1.313 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.588 + clock arrival 1.313 + ------------------------------------------------------------------- + relative delay -1.902 + + + +Id: 2 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.637 11.363 + + +Slack (MET) : 11.363ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.951ns + Reference Relative Delay: -2.116ns + Relative CRPR: 0.529ns + Actual Bus Skew: 0.637ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.702 -0.838 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y128 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y128 FDRE (Prop_fdre_C_Q) 0.456 -0.382 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.492 0.110 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X86Y127 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.757 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y127 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.152 + SLICE_X86Y127 FDRE (Setup_fdre_C_D) -0.092 1.060 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.110 + clock arrival 1.060 + ------------------------------------------------------------------- + relative delay -0.951 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.585 -1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X86Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y129 FDRE (Prop_fdre_C_Q) 0.367 -1.069 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.255 -0.814 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X86Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.706 1.528 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.133 + SLICE_X86Y130 FDRE (Hold_fdre_C_D) 0.170 1.303 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.814 + clock arrival 1.303 + ------------------------------------------------------------------- + relative delay -2.116 + + + +Id: 3 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.600 11.400 + + +Slack (MET) : 11.400ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.641ns + Reference Relative Delay: 2.488ns + Relative CRPR: 0.553ns + Actual Bus Skew: 0.600ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.706 1.528 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X87Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.419 1.947 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.440 2.387 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X88Y131 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.586 -1.435 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X88Y131 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.040 + SLICE_X88Y131 FDRE (Setup_fdre_C_D) -0.215 -1.255 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.387 + clock arrival -1.255 + ------------------------------------------------------------------- + relative delay 3.641 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.588 0.760 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X87Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.337 1.097 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.253 1.350 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X88Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.704 -0.836 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X88Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.231 + SLICE_X88Y130 FDRE (Hold_fdre_C_D) 0.093 -1.138 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.350 + clock arrival -1.138 + ------------------------------------------------------------------- + relative delay 2.488 + + + +Id: 4 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 1.093 10.907 + + +Slack (MET) : 10.907ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.526ns + Reference Relative Delay: -2.116ns + Relative CRPR: 0.497ns + Actual Bus Skew: 1.093ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.698 -0.842 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X75Y111 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.386 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.970 0.584 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X80Y103 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.590 0.762 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X80Y103 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 1.157 + SLICE_X80Y103 FDRE (Setup_fdre_C_D) -0.047 1.110 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 0.584 + clock arrival 1.110 + ------------------------------------------------------------------- + relative delay -0.526 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.585 -1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X79Y101 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y101 FDRE (Prop_fdre_C_Q) 0.367 -1.069 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.278 -0.791 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X79Y103 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.707 1.529 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X79Y103 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.134 + SLICE_X79Y103 FDRE (Hold_fdre_C_D) 0.192 1.326 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.791 + clock arrival 1.326 + ------------------------------------------------------------------- + relative delay -2.116 + + + +Id: 5 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.887 11.113 + + +Slack (MET) : 11.113ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.920ns + Reference Relative Delay: 2.536ns + Relative CRPR: 0.497ns + Actual Bus Skew: 0.887ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.709 1.531 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X80Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y108 FDRE (Prop_fdre_C_Q) 0.478 2.009 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.607 2.616 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X81Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.586 -1.435 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X81Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 -1.040 + SLICE_X81Y108 FDRE (Setup_fdre_C_D) -0.265 -1.305 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 2.616 + clock arrival -1.305 + ------------------------------------------------------------------- + relative delay 3.920 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.586 0.758 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X79Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y107 FDRE (Prop_fdre_C_Q) 0.367 1.125 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.410 1.536 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X78Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.704 -0.836 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X78Y107 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.231 + SLICE_X78Y107 FDRE (Hold_fdre_C_D) 0.231 -1.000 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.536 + clock arrival -1.000 + ------------------------------------------------------------------- + relative delay 2.536 + + + +Id: 6 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 1.022 10.978 + + +Slack (MET) : 10.978ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 4.086ns + Reference Relative Delay: 2.485ns + Relative CRPR: 0.579ns + Actual Bus Skew: 1.022ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.712 1.534 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X84Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y137 FDRE (Prop_fdre_C_Q) 0.478 2.012 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.769 2.781 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.590 -1.431 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.036 + SLICE_X82Y137 FDRE (Setup_fdre_C_D) -0.270 -1.306 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.781 + clock arrival -1.306 + ------------------------------------------------------------------- + relative delay 4.086 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.593 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X84Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y137 FDRE (Prop_fdre_C_Q) 0.418 1.183 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.247 1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.710 -0.830 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.225 + SLICE_X82Y137 FDRE (Hold_fdre_C_D) 0.170 -1.055 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.430 + clock arrival -1.055 + ------------------------------------------------------------------- + relative delay 2.485 + + + +Id: 7 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.746 11.254 + + +Slack (MET) : 11.254ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.680ns + Reference Relative Delay: -1.940ns + Relative CRPR: 0.513ns + Actual Bus Skew: 0.746ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.710 -0.830 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y137 FDRE (Prop_fdre_C_Q) 0.456 -0.374 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.759 0.385 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X85Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.593 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X85Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 1.160 + SLICE_X85Y137 FDRE (Setup_fdre_C_D) -0.095 1.065 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 0.385 + clock arrival 1.065 + ------------------------------------------------------------------- + relative delay -0.680 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X86Y139 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y139 FDRE (Prop_fdre_C_Q) 0.367 -1.060 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.430 -0.630 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X85Y139 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.714 1.536 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X85Y139 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.141 + SLICE_X85Y139 FDRE (Hold_fdre_C_D) 0.169 1.310 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.630 + clock arrival 1.310 + ------------------------------------------------------------------- + relative delay -1.940 + + + +Id: 8 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.895 11.105 + + +Slack (MET) : 11.105ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.683ns + Reference Relative Delay: -2.114ns + Relative CRPR: 0.535ns + Actual Bus Skew: 0.895ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.696 -0.844 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X82Y123 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y123 FDRE (Prop_fdre_C_Q) 0.456 -0.388 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.751 0.363 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X85Y126 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.582 0.754 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X85Y126 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.149 + SLICE_X85Y126 FDRE (Setup_fdre_C_D) -0.103 1.046 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.363 + clock arrival 1.046 + ------------------------------------------------------------------- + relative delay -0.683 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.579 -1.442 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X82Y123 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y123 FDRE (Prop_fdre_C_Q) 0.367 -1.075 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.257 -0.818 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X82Y122 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.699 1.521 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X82Y122 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 1.126 + SLICE_X82Y122 FDRE (Hold_fdre_C_D) 0.170 1.296 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival -0.818 + clock arrival 1.296 + ------------------------------------------------------------------- + relative delay -2.114 + + + +Id: 9 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.919 11.081 + + +Slack (MET) : 11.081ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 4.054ns + Reference Relative Delay: 2.583ns + Relative CRPR: 0.552ns + Actual Bus Skew: 0.919ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.705 1.527 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y129 FDRE (Prop_fdre_C_Q) 0.419 1.946 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.834 2.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X88Y128 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.584 -1.437 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X88Y128 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.042 + SLICE_X88Y128 FDRE (Setup_fdre_C_D) -0.233 -1.275 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.780 + clock arrival -1.275 + ------------------------------------------------------------------- + relative delay 4.054 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.588 0.760 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y129 FDRE (Prop_fdre_C_Q) 0.367 1.127 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.392 1.520 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X86Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.703 -0.837 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X86Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.232 + SLICE_X86Y129 FDRE (Hold_fdre_C_D) 0.169 -1.063 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.520 + clock arrival -1.063 + ------------------------------------------------------------------- + relative delay 2.583 + + + +Id: 10 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 1.156 10.844 + + +Slack (MET) : 10.844ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 4.003ns + Reference Relative Delay: 2.428ns + Relative CRPR: 0.419ns + Actual Bus Skew: 1.156ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X75Y99 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y99 FDRE (Prop_fdre_C_Q) 0.419 1.957 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.730 2.687 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X73Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.580 -1.441 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X73Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 -1.046 + SLICE_X73Y100 FDRE (Setup_fdre_C_D) -0.270 -1.316 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 2.687 + clock arrival -1.316 + ------------------------------------------------------------------- + relative delay 4.003 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.757 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X77Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y100 FDRE (Prop_fdre_C_Q) 0.367 1.124 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.240 1.364 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X75Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.702 -0.838 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X75Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.233 + SLICE_X75Y100 FDRE (Hold_fdre_C_D) 0.170 -1.063 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.364 + clock arrival -1.063 + ------------------------------------------------------------------- + relative delay 2.428 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/cdc.rpt new file mode 100644 index 0000000..f2e8b70 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/cdc.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:38 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 17 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/check-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/check-timing.rpt new file mode 100644 index 0000000..ba733cd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/check-timing.rpt @@ -0,0 +1,108 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:55 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : check_timing -verbose -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/check-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/clocks.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/clocks.rpt new file mode 100644 index 0000000..c61badd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/clocks.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:54 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_clocks -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/clocks.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +board_clk 10.000 {0.000 5.000} P {CLK100MHZ} +clk_pll_i 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} +core_raw 40.000 {0.000 20.000} P,G,A {clock_mmcm/CLKOUT0} +fb 10.000 {0.000 5.000} P,G,A {clock_mmcm/CLKFBOUT} +freq_refclk 1.500 {0.000 0.750} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} +iserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} +iserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} +mem_refclk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} +oserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} +oserdes_clk_1 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} +oserdes_clk_2 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} +oserdes_clk_3 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} +oserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} +oserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} +oserdes_clkdiv_2 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} +oserdes_clkdiv_3 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} +pll_clk3_out 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} +pll_clkfbout 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} +ref_raw 5.000 {0.000 2.500} P,G,A {clock_mmcm/CLKOUT2} +sync_pulse 48.000 {1.312 4.312} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} +sys_raw 6.000 {0.000 3.000} P,G,A {clock_mmcm/CLKOUT1} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clk_pll_i +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Master Clock : pll_clk3_out +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} + +Generated Clock : core_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 15.000 30.000} +Generated Sources : {clock_mmcm/CLKOUT0} + +Generated Clock : fb +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 1 +Generated Sources : {clock_mmcm/CLKFBOUT} + +Generated Clock : freq_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} + +Generated Clock : iserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : iserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : mem_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} + +Generated Clock : oserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} + +Generated Clock : oserdes_clk_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} + +Generated Clock : oserdes_clk_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} + +Generated Clock : oserdes_clk_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} + +Generated Clock : oserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK +Master Clock : oserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK +Master Clock : oserdes_clk_1 +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK +Master Clock : oserdes_clk_2 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK +Master Clock : oserdes_clk_3 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} + +Generated Clock : pll_clk3_out +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 3.000 6.000} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} + +Generated Clock : pll_clkfbout +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} + +Generated Clock : ref_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 2 +Generated Sources : {clock_mmcm/CLKOUT2} + +Generated Clock : sync_pulse +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {1.312 1.313 43.312} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} + +Generated Clock : sys_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -2.000 -4.000} +Generated Sources : {clock_mmcm/CLKOUT1} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/drc.rpt new file mode 100644 index 0000000..61b0bd2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:37 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/io.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/io.rpt new file mode 100644 index 0000000..d563583 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/io.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:52 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_io -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/io.rpt +| Design : toy_a7_top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2012-07-17 +| Package Pin Delay Version : VERS. 2.0 2012-07-17 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 56 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | uart_txd_in | High Range | IO_L14N_T2_SRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | btn0 | High Range | IO_L6N_T0_VREF_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| D10 | uart_rxd_out | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | CLK100MHZ | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | led[0] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | led[1] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | ddr3_dq[2] | High Range | IO_L2P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| K5 | ddr3_dq[0] | High Range | IO_L5P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K6 | ddr3_reset_n | High Range | IO_0_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | ddr3_dm[0] | High Range | IO_L1P_T0_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | ddr3_dq[1] | High Range | IO_L2N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L4 | ddr3_dq[6] | High Range | IO_L5N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | ddr3_dq[3] | High Range | IO_L6P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | ddr3_dq[5] | High Range | IO_L1N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M2 | ddr3_dq[7] | High Range | IO_L4N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M3 | ddr3_dq[4] | High Range | IO_L4P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M4 | ddr3_cas_n | High Range | IO_L16P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | ddr3_addr[1] | High Range | IO_L18P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | ddr3_dqs_n[0] | High Range | IO_L3N_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | ddr3_dqs_p[0] | High Range | IO_L3P_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| N4 | ddr3_addr[2] | High Range | IO_L16N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | ddr3_cke[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | ddr3_addr[4] | High Range | IO_L18N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | ddr3_ba[2] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P3 | ddr3_ras_n | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | ddr3_ba[1] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | ddr3_we_n | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | ddr3_ba[0] | High Range | IO_L17P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | ddr3_addr[0] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | ddr3_dq[15] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | ddr3_odt[0] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | ddr3_addr[10] | High Range | IO_L19P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | ddr3_addr[5] | High Range | IO_L23P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R8 | ddr3_addr[8] | High Range | IO_L24P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | ddr3_addr[3] | High Range | IO_L17N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| T3 | ddr3_dq[13] | High Range | IO_L11N_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | ddr3_dq[9] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T6 | ddr3_addr[12] | High Range | IO_L23N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | ddr3_addr[13] | High Range | IO_L24N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T9 | led[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T10 | led[3] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | ddr3_dm[1] | High Range | IO_L7P_T1_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U2 | ddr3_dqs_p[1] | High Range | IO_L9P_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | ddr3_dq[14] | High Range | IO_L8N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U4 | ddr3_dq[10] | High Range | IO_L8P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| U6 | ddr3_addr[11] | High Range | IO_L22N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U7 | ddr3_addr[7] | High Range | IO_L22P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | ddr3_cs_n[0] | High Range | IO_25_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | ddr3_ck_p[0] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | ddr3_dq[12] | High Range | IO_L7N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V2 | ddr3_dqs_n[1] | High Range | IO_L9N_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | ddr3_dq[8] | High Range | IO_L10N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V5 | ddr3_dq[11] | High Range | IO_L10P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V6 | ddr3_addr[6] | High Range | IO_L20N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V7 | ddr3_addr[9] | High Range | IO_L20P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| V9 | ddr3_ck_n[0] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/methodology.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/methodology.rpt new file mode 100644 index 0000000..3e6174c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/methodology.rpt @@ -0,0 +1,389 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:52 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_methodology -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/methodology.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 65 ++-----------+----------+-----------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 2 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 16 | +| SYNTH-9 | Warning | Small multiplier | 5 | +| SYNTH-10 | Warning | Wide multiplier | 21 | +| SYNTH-16 | Warning | Address collision | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +| XDCB-5 | Warning | Runtime inefficient way to find pin objects | 2 | +| REQP-1959 | Advisory | connects_SERDES_RST_driver_not_FF | 16 | ++-----------+----------+-----------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__7/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__9/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[0]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[10]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[11]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[1]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[3]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[4]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[5]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[6]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[7]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[8]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell platform/loader/in_pipe_v_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR, +platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR, +platform/chip/system/ibus_intsource/reg_0__0/reg_0_reg/CLR, +platform/chip/system/plic_domain/intsource/reg_0/reg_0_reg/CLR +platform/chip/system/plic_domain/intsource_1/reg_0/reg_0_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#9 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#10 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#11 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#12 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#13 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#14 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#15 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#16 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-9#1 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[11]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#2 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[15]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#3 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[19]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#4 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[3]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#5 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[7]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__0 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#5 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#6 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__2 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#7 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#8 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__4 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#9 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#10 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__6 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#11 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#12 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#13 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__9 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#14 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#15 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#16 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__1 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#17 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__2 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#18 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#19 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__4 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#20 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#21 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +ULMTCS-1#1 Warning +Control Sets use limits recommend reduction +This design uses 1256 control sets (vs. available limit of 15850, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. +Related violations: + +XDCB-5#1 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '12' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/board/arty_a7.xdc (Line: 18) +Related violations: + +XDCB-5#2 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '6' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc (Line: 356) +Related violations: + +REQP-1959#1 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#2 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#3 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#4 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#5 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#6 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#7 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#8 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#9 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#10 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#11 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#12 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#13 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#14 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#15 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#16 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/route-status.rpt new file mode 100644 index 0000000..9cb523e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 121758 : + # of nets not needing routing.......... : 26527 : + # of internally routed nets........ : 24402 : + # of nets with no loads............ : 2125 : + # of routable nets..................... : 95231 : + # of fully routed nets............. : 95231 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-hierarchy.rpt new file mode 100644 index 0000000..a72d03f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-hierarchy.rpt @@ -0,0 +1,1148 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:24 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/routed-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 54413 | 50491 | 3644 | 278 | 35600 | 25 | 8 | 117 | +| (toy_a7_top) | (top) | 5 | 5 | 0 | 0 | 63 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 4575 | 3971 | 450 | 154 | 4081 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4359 | 3971 | 234 | 154 | 4081 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 38 | 38 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 6 | 6 | 0 | 0 | 32 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 1 | 1 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4316 | 3928 | 234 | 154 | 3912 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3347 | 3292 | 38 | 17 | 2828 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 2745 | 2699 | 30 | 16 | 2301 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2246 | 2232 | 0 | 14 | 1980 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 95 | 94 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 530 | 530 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 257 | 257 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 146 | 145 | 0 | 1 | 91 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 264 | 263 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 798 | 794 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 159 | 153 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 497 | 465 | 30 | 2 | 321 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 497 | 465 | 30 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 497 | 465 | 30 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 6 | 5 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 51 | 21 | 30 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 50 | 20 | 30 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 24 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 15 | 15 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 211 | 211 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 182 | 182 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 206 | 205 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 183 | 183 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 611 | 602 | 8 | 1 | 527 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 8 | 8 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 495 | 495 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 195 | 195 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 195 | 195 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 71 | 71 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 69 | 69 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 71 | 71 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 26 | 18 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 82 | 81 | 0 | 1 | 66 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 10 | 9 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 72 | 72 | 0 | 0 | 53 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 60 | 60 | 0 | 0 | 47 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 599 | 462 | 0 | 137 | 532 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 122 | 122 | 0 | 0 | 87 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 43 | 43 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 35 | 35 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 125 | 125 | 0 | 0 | 85 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 43 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 47 | 47 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 39 | 39 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 11 | 7 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 390 | 194 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 117 | 25 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 235 | 131 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 456 | 194 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 456 | 194 | 262 | 0 | 1212 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 455 | 193 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 455 | 193 | 262 | 0 | 1212 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 72 | 38 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 72 | 38 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 137 | 39 | 98 | 0 | 386 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 137 | 39 | 98 | 0 | 386 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 288 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 144 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 42 | 38 | 4 | 0 | 110 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 42 | 38 | 4 | 0 | 110 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 49378 | 46322 | 2932 | 124 | 30244 | 25 | 8 | 117 | +| chip | ToyLinuxChip | 48386 | 45442 | 2820 | 124 | 29192 | 25 | 8 | 117 | +| system | ToyLinuxSystem | 48386 | 45442 | 2820 | 124 | 29192 | 25 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 969 | 815 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 377 | 377 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 73 | 73 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 81 | 81 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 77 | 53 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 40 | 16 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 25 | 13 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 21 | 9 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 37 | 37 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 16 | 16 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 379 | 283 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 360 | 264 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 99 | 99 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 261 | 165 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 147 | 51 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 115 | 19 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 292 | 292 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 207 | 207 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 33 | 33 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 28 | 28 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1372 | 1038 | 334 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 741 | 407 | 334 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 204 | 66 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 59 | 27 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 55 | 23 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 47 | 15 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 41 | 9 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 276 | 116 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 77 | 41 | 36 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 13 | 7 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 11 | 5 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 9 | 3 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 88 | 88 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 34 | 34 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 32 | 32 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 491 | 491 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 44227 | 42220 | 1884 | 123 | 27557 | 25 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1208 | 624 | 584 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 158 | 62 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 156 | 60 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 644 | 518 | 126 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 641 | 515 | 126 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 127 | 15 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 43022 | 41599 | 1300 | 123 | 27536 | 25 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 23118 | 22485 | 510 | 123 | 16690 | 16 | 0 | 95 | +| ballDomain | BallDomain | 13141 | 12828 | 190 | 123 | 10878 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 141 | 45 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 12998 | 12781 | 94 | 123 | 10873 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 12998 | 12781 | 94 | 123 | 10863 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 476 | 476 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 33 | 33 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 447 | 447 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 11895 | 11678 | 94 | 123 | 9716 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1306 | 1306 | 0 | 0 | 2443 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 10213 | 10084 | 6 | 123 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 529 | 406 | 0 | 123 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9039 | 9039 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 95 | 95 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 106 | 106 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 30 | 24 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 25 | 19 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 511 | 511 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 305 | 261 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 83 | 39 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 626 | 626 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 32 | 16 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 26 | 10 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 35 | 19 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 29 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5612 | 5416 | 196 | 0 | 3863 | 0 | 0 | 0 | +| boot | BootRom | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5603 | 5407 | 196 | 0 | 3856 | 0 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 5080 | 5080 | 0 | 0 | 3325 | 0 | 0 | 0 | +| (rob) | GlobalROB | 3784 | 3784 | 0 | 0 | 3133 | 0 | 0 | 0 | +| bat | BankAliasTable | 875 | 875 | 0 | 0 | 176 | 0 | 0 | 0 | +| scoreboard | BankScoreboard | 431 | 431 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 491 | 299 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 298 | 298 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 194 | 2 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 194 | 2 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4304 | 4212 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2147 | 2147 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2147 | 2147 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 199 | 199 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 285 | 285 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 265 | 265 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 282 | 282 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 324 | 324 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 508 | 508 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 227 | 227 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2122 | 2030 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 573 | 573 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 133 | 133 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 95 | 95 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 8 | 8 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 380 | 380 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 545 | 545 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 142 | 142 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 142 | 142 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 38 | 38 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 127 | 49 | 78 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 93 | 41 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 34 | 8 | 26 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 31 | 5 | 26 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 111 | 41 | 70 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 107 | 37 | 70 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 104 | 34 | 70 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 236 | 104 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 56 | 4 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 53 | 1 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 180 | 100 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 179 | 99 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 5874 | 5786 | 88 | 0 | 1895 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2303 | 2303 | 0 | 0 | 753 | 0 | 0 | 0 | +| csr | CSRFile | 1829 | 1829 | 0 | 0 | 869 | 0 | 0 | 0 | +| div | MulDiv | 1529 | 1529 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 2957 | 2865 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 513 | 513 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 193 | 193 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 61 | 61 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 61 | 61 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 126 | 126 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 126 | 126 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1144 | 1144 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 633 | 633 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 261 | 261 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 298 | 298 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 73 | 73 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 109 | 109 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 78 | 78 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 78 | 78 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 261 | 261 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 7783 | 7519 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 26 | 26 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 149 | 149 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 149 | 149 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 149 | 149 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 316 | 316 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 311 | 311 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 311 | 311 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 844 | 844 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1021 | 1021 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 971 | 971 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 415 | 415 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 82 | 82 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 214 | 214 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 214 | 214 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1519 | 1519 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 777 | 777 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 750 | 750 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 344 | 344 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 316 | 316 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 343 | 343 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 302 | 302 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1064 | 800 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2440 | 2440 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2426 | 2426 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2040 | 1998 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 745 | 745 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 544 | 502 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 264 | 264 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 750 | 750 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 685 | 685 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 42 | 42 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 78 | 78 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 77 | 77 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 60 | 60 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 434 | 370 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 331 | 331 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 147 | 99 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 37 | 37 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 12 | 12 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-timing.rpt new file mode 100644 index 0000000..ce909ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-timing.rpt @@ -0,0 +1,6689 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:31 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 112427 0.013 0.000 0 112385 0.187 0.000 0 43391 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 7.567 0.000 0 97031 0.013 0.000 0 97031 18.750 0.000 0 37154 + fb 7.845 0.000 0 3 + ref_raw 1.989 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.974 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.957 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.563 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 3.905 0.000 0 14674 0.041 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.483 0.000 0 20 +clk_pll_i ref_raw 15.607 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 9.699 0.000 0 8 45.474 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 10.605 0.000 0 8 45.209 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.079 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.527 0.000 0 20 +ref_raw clk_pll_i 17.041 0.000 0 12 0.137 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.912 0.000 0 111 0.291 0.000 0 111 +**async_default** core_raw core_raw 23.997 0.000 0 116 0.349 0.000 0 116 +**default** clk_pll_i 2.156 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 7.567ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.013ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 7.567ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 32.441ns (logic 7.977ns (24.589%) route 24.464ns (75.411%)) + Logic Levels: 34 (CARRY4=3 LUT2=5 LUT3=4 LUT4=7 LUT5=8 LUT6=7) + Clock Path Skew: 0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.356ns = ( 38.644 - 40.000 ) + Source Clock Delay (SCD): -0.936ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.604 -0.936 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X37Y124 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y124 FDRE (Prop_fdre_C_Q) 0.456 -0.480 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[0]/Q + net (fo=166, routed) 1.729 1.249 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg_n_0_[0] + SLICE_X43Y108 LUT6 (Prop_lut6_I2_O) 0.124 1.373 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.544 1.917 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X43Y109 LUT5 (Prop_lut5_I4_O) 0.124 2.041 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 1.223 3.264 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X34Y117 LUT5 (Prop_lut5_I4_O) 0.124 3.388 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 1.137 4.525 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X32Y134 LUT4 (Prop_lut4_I3_O) 0.124 4.649 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 1.005 5.654 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X43Y138 LUT4 (Prop_lut4_I3_O) 0.119 5.773 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[50]_i_3/O + net (fo=2, routed) 0.967 6.740 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[50] + SLICE_X50Y150 LUT5 (Prop_lut5_I0_O) 0.332 7.072 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[50]_i_2/O + net (fo=1, routed) 0.859 7.931 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[50]_i_2_n_0 + SLICE_X48Y157 LUT3 (Prop_lut3_I0_O) 0.152 8.083 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[50]_i_1/O + net (fo=7, routed) 1.188 9.271 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[50] + SLICE_X59Y160 LUT4 (Prop_lut4_I0_O) 0.358 9.629 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_9/O + net (fo=2, routed) 0.797 10.425 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_9_n_0 + SLICE_X59Y159 LUT3 (Prop_lut3_I1_O) 0.352 10.777 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[51]_i_15/O + net (fo=1, routed) 0.642 11.419 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[51]_i_15_n_0 + SLICE_X58Y159 LUT6 (Prop_lut6_I2_O) 0.326 11.745 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[51]_i_7/O + net (fo=11, routed) 1.188 12.933 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[51]_i_7_n_0 + SLICE_X79Y156 LUT4 (Prop_lut4_I3_O) 0.119 13.052 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_214/O + net (fo=5, routed) 1.103 14.155 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_214_n_0 + SLICE_X78Y161 LUT3 (Prop_lut3_I1_O) 0.332 14.487 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.335 14.822 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X78Y162 LUT2 (Prop_lut2_I0_O) 0.124 14.946 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.306 15.252 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X78Y162 LUT2 (Prop_lut2_I0_O) 0.117 15.369 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.837 16.206 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.356 16.562 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.987 17.549 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X78Y162 LUT3 (Prop_lut3_I0_O) 0.332 17.881 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.562 18.443 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X81Y163 LUT2 (Prop_lut2_I0_O) 0.117 18.560 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.668 19.228 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X81Y163 LUT2 (Prop_lut2_I0_O) 0.332 19.560 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.580 20.140 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X81Y160 LUT5 (Prop_lut5_I3_O) 0.124 20.264 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.465 20.729 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X81Y164 LUT6 (Prop_lut6_I0_O) 0.124 20.853 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.478 21.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X80Y164 CARRY4 (Prop_carry4_DI[0]_O[1]) + 0.422 21.753 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[1] + net (fo=1, routed) 0.450 22.203 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[62] + SLICE_X79Y164 LUT4 (Prop_lut4_I0_O) 0.306 22.509 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135/O + net (fo=3, routed) 0.679 23.187 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135_n_0 + SLICE_X80Y165 LUT4 (Prop_lut4_I3_O) 0.124 23.311 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115/O + net (fo=4, routed) 0.606 23.917 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115_n_0 + SLICE_X80Y166 LUT4 (Prop_lut4_I1_O) 0.150 24.067 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_96/O + net (fo=2, routed) 0.841 24.909 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_96_n_0 + SLICE_X79Y167 LUT6 (Prop_lut6_I4_O) 0.328 25.237 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60/O + net (fo=2, routed) 1.156 26.393 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60_n_0 + SLICE_X79Y159 LUT5 (Prop_lut5_I4_O) 0.152 26.545 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 26.995 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X79Y159 LUT5 (Prop_lut5_I3_O) 0.326 27.321 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.538 27.859 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X78Y159 LUT6 (Prop_lut6_I5_O) 0.124 27.983 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 27.983 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X78Y159 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 28.359 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 28.359 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X78Y160 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 28.682 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/O[1] + net (fo=2, routed) 0.873 29.556 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[5] + SLICE_X63Y160 LUT6 (Prop_lut6_I5_O) 0.306 29.862 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_14/O + net (fo=1, routed) 0.433 30.295 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_14_n_0 + SLICE_X63Y160 LUT6 (Prop_lut6_I5_O) 0.124 30.419 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_5/O + net (fo=1, routed) 0.405 30.824 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_5_n_0 + SLICE_X63Y162 LUT5 (Prop_lut5_I0_O) 0.124 30.948 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_2/O + net (fo=1, routed) 0.433 31.381 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_2_n_0 + SLICE_X63Y164 LUT5 (Prop_lut5_I0_O) 0.124 31.505 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[5]_i_1/O + net (fo=1, routed) 0.000 31.505 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[5] + SLICE_X63Y164 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=37170, routed) 1.664 38.644 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X63Y164 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5]/C + clock pessimism 0.488 39.132 + clock uncertainty -0.091 39.041 + SLICE_X63Y164 FDRE (Setup_fdre_C_D) 0.031 39.072 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[5] + ------------------------------------------------------------------- + required time 39.072 + arrival time -31.505 + ------------------------------------------------------------------- + slack 7.567 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.013ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ibuf/buf_pc_reg[13]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ex_reg_pc_reg[13]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.370ns (logic 0.186ns (50.213%) route 0.184ns (49.787%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.844ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37170, routed) 0.558 -0.606 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ibuf/clk + SLICE_X52Y145 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ibuf/buf_pc_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X52Y145 FDRE (Prop_fdre_C_Q) 0.141 -0.465 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ibuf/buf_pc_reg[13]/Q + net (fo=1, routed) 0.184 -0.281 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/fq/ex_reg_pc_reg[39][11] + SLICE_X51Y146 LUT4 (Prop_lut4_I0_O) 0.045 -0.236 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/fq/ShiftQueue_LUT4_30/O + net (fo=1, routed) 0.000 -0.236 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ex_reg_pc_reg[39]_0[11] + SLICE_X51Y146 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ex_reg_pc_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37170, routed) 0.829 -0.844 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X51Y146 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ex_reg_pc_reg[13]/C + clock pessimism 0.504 -0.340 + SLICE_X51Y146 FDRE (Hold_fdre_C_D) 0.092 -0.248 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/ex_reg_pc_reg[13] + ------------------------------------------------------------------- + required time 0.248 + arrival time -0.236 + ------------------------------------------------------------------- + slack 0.013 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y71 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X80Y121 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X80Y121 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.989ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.989ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.385ns (logic 0.478ns (20.041%) route 1.907ns (79.959%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.446ns = ( 3.554 - 5.000 ) + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X8Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y122 FDRE (Prop_fdre_C_Q) 0.478 -0.449 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 1.907 1.458 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X4Y128 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.575 3.554 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X4Y128 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]/C + clock pessimism 0.560 4.114 + clock uncertainty -0.067 4.047 + SLICE_X4Y128 FDRE (Setup_fdre_C_R) -0.600 3.447 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] + ------------------------------------------------------------------- + required time 3.447 + arrival time -1.458 + ------------------------------------------------------------------- + slack 1.989 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: mig_resetn_pipe_reg[0]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: mig_resetn_pipe_reg[1]/D + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.803ns + Source Clock Delay (SCD): -0.567ns + Clock Pessimism Removal (CPR): -0.236ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.597 -0.567 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r mig_resetn_pipe_reg[0]/Q + net (fo=1, routed) 0.056 -0.370 mig_resetn_pipe[0] + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.870 -0.803 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[1]/C + clock pessimism 0.236 -0.567 + SLICE_X77Y96 FDCE (Hold_fdce_C_D) 0.075 -0.492 mig_resetn_pipe_reg[1] + ------------------------------------------------------------------- + required time 0.492 + arrival time -0.370 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X75Y97 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X75Y97 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.974ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.974ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.061 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.061 + ------------------------------------------------------------------- + slack 9.974 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.957ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.957ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.467ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.114ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.467 2.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y88 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.539 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.068 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d1[3] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.025 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.025 + arrival time -3.068 + ------------------------------------------------------------------- + slack 9.957 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.563ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.563ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.674ns (57.945%) route 0.489ns (42.055%)) + Logic Levels: 0 + Clock Path Skew: 0.406ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.113ns = ( 8.113 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q7[0]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q7[0] + net (fo=1, routed) 0.489 3.583 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[24] + OLOGIC_X1Y84 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.406 8.113 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y84 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.825 + clock uncertainty -0.054 8.771 + OLOGIC_X1Y84 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.146 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[7].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.146 + arrival time -3.583 + ------------------------------------------------------------------- + slack 4.563 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 3.905ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.041ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.905ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[1]/C + (rising edge-triggered cell FDSE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 7.648ns (logic 0.642ns (8.394%) route 7.006ns (91.606%)) + Logic Levels: 1 (SRLC32E=1) + Clock Path Skew: -0.195ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.681ns = ( 12.681 - 12.000 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[5]_1 + SLICE_X76Y104 FDSE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y104 FDSE (Prop_fdse_C_Q) 0.518 2.043 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[1]/Q + net (fo=136, routed) 6.177 8.220 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[1] + SLICE_X66Y86 SRLC32E (Prop_srlc32e_A[1]_Q) + 0.124 8.344 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32/Q + net (fo=1, routed) 0.829 9.173 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/DIB0 + SLICE_X62Y93 RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.508 12.681 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/WCLK + SLICE_X62Y93 RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMB/CLK + clock pessimism 0.649 13.330 + clock uncertainty -0.067 13.263 + SLICE_X62Y93 RAMD32 (Setup_ramd32_CLK_I) + -0.185 13.078 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMB + ------------------------------------------------------------------- + required time 13.078 + arrival time -9.173 + ------------------------------------------------------------------- + slack 3.905 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.041ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[85]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32/D + (rising edge-triggered cell SRLC32E clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.261ns (logic 0.141ns (53.971%) route 0.120ns (46.029%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.198ns + Source Clock Delay (SCD): 0.142ns + Clock Pessimism Removal (CPR): 0.019ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.566 0.142 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.status_ram.rd_buf_we_r1_reg_0 + SLICE_X67Y95 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[85]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y95 FDRE (Prop_fdre_C_Q) 0.141 0.283 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[85]/Q + net (fo=1, routed) 0.120 0.403 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/Q[85] + SLICE_X62Y95 SRLC32E r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.837 0.198 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_reg[5]_1 + SLICE_X62Y95 SRLC32E r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32/CLK + clock pessimism -0.019 0.179 + SLICE_X62Y95 SRLC32E (Hold_srlc32e_CLK_D) + 0.183 0.362 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32 + ------------------------------------------------------------------- + required time -0.362 + arrival time 0.403 + ------------------------------------------------------------------- + slack 0.041 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.483ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.483ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.247ns (logic 0.478ns (38.337%) route 0.769ns (61.663%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X84Y137 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X84Y137 FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.769 1.247 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X82Y137 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X82Y137 FDRE (Setup_fdre_C_D) -0.270 11.730 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 11.730 + arrival time -1.247 + ------------------------------------------------------------------- + slack 10.483 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 15.607ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 15.607ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.346ns (logic 0.456ns (10.492%) route 3.890ns (89.508%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X68Y82 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X68Y82 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 3.890 4.346 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X8Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X8Y122 FDRE (Setup_fdre_C_D) -0.047 19.953 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.953 + arrival time -4.346 + ------------------------------------------------------------------- + slack 15.607 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 9.699ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.474ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.699ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 6.704ns (logic 3.867ns (57.684%) route 2.837ns (42.316%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.287ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.216ns = ( 2.716 - 1.500 ) + Source Clock Delay (SCD): 1.536ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.714 1.536 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X79Y86 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y86 FDRE (Prop_fdre_C_Q) 0.456 1.992 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.837 4.829 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq/IBUFDISABLE + T5 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 7.425 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 7.425 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y76 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 8.240 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 8.240 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.409 17.716 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.324 + clock uncertainty -0.220 18.104 + ILOGIC_X1Y76 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.939 + arrival time -8.240 + ------------------------------------------------------------------- + slack 9.699 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.474ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.809ns (logic 1.068ns (59.024%) route 0.741ns (40.976%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.060ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.992ns + Source Clock Delay (SCD): 0.170ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.594 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X79Y86 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y86 FDRE (Prop_fdre_C_Q) 0.141 60.311 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.741 61.052 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.736 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.736 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.979 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.979 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.180 15.992 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.229 + clock uncertainty 0.220 16.449 + ILOGIC_X1Y85 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.505 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.505 + arrival time 61.979 + ------------------------------------------------------------------- + slack 45.474 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.605ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.209ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.605ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 5.808ns (logic 3.867ns (66.582%) route 1.941ns (33.418%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.536ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.714 1.536 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X79Y86 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y86 FDRE (Prop_fdre_C_Q) 0.456 1.992 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 1.941 3.933 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 6.529 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 6.529 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.344 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.344 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -7.344 + ------------------------------------------------------------------- + slack 10.605 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.209ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.541ns (logic 1.068ns (69.285%) route 0.473ns (30.715%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.057ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.170ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.594 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X79Y86 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y86 FDRE (Prop_fdre_C_Q) 0.141 60.311 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.473 60.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq/IBUFDISABLE + K5 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.468 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.468 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[2] + IDELAY_X1Y90 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.711 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.711 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_3 + ILOGIC_X1Y90 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y90 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y90 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 61.711 + ------------------------------------------------------------------- + slack 45.209 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.079ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.079ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.903ns (logic 0.272ns (30.132%) route 0.631ns (69.868%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 2.013 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST + net (fo=10, routed) 0.631 2.644 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y78 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y78 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.168 2.006 + OLOGIC_X1Y78 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.565 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[3].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.565 + arrival time 2.644 + ------------------------------------------------------------------- + slack 0.079 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.527ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.527ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.426ns (logic 0.456ns (31.972%) route 0.970ns (68.028%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X75Y111 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X75Y111 FDRE (Prop_fdre_C_Q) 0.456 0.456 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.970 1.426 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X80Y103 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X80Y103 FDRE (Setup_fdre_C_D) -0.047 39.953 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 39.953 + arrival time -1.426 + ------------------------------------------------------------------- + slack 38.527 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 17.041ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.137ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 17.041ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.485ns (logic 0.478ns (10.659%) route 4.007ns (89.341%)) + Logic Levels: 0 + Clock Path Skew: 1.994ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.748ns + Source Clock Delay (SCD): -0.851ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.689 -0.851 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X2Y124 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y124 FDRE (Prop_fdre_C_Q) 0.478 -0.373 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/Q + net (fo=1, routed) 4.007 3.634 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[5] + SLICE_X7Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.576 20.748 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X7Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/C + clock pessimism 0.395 21.143 + clock uncertainty -0.245 20.898 + SLICE_X7Y122 FDRE (Setup_fdre_C_D) -0.224 20.674 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5] + ------------------------------------------------------------------- + required time 20.674 + arrival time -3.634 + ------------------------------------------------------------------- + slack 17.041 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.137ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[1]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.811ns (logic 0.164ns (9.053%) route 1.647ns (90.947%)) + Logic Levels: 0 + Clock Path Skew: 1.355ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.219ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.585 -0.579 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X2Y124 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y124 FDRE (Prop_fdre_C_Q) 0.164 -0.415 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[1]/Q + net (fo=1, routed) 1.647 1.232 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[1] + SLICE_X4Y121 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.857 0.219 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X4Y121 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[1]/C + clock pessimism 0.557 0.775 + clock uncertainty 0.245 1.020 + SLICE_X4Y121 FDRE (Hold_fdre_C_D) 0.075 1.095 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[1] + ------------------------------------------------------------------- + required time -1.095 + arrival time 1.232 + ------------------------------------------------------------------- + slack 0.137 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.912ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.291ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.912ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.588ns (logic 0.456ns (17.619%) route 2.132ns (82.381%)) + Logic Levels: 0 + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.755ns = ( 12.755 - 12.000 ) + Source Clock Delay (SCD): 1.528ns + Clock Pessimism Removal (CPR): 0.745ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.706 1.528 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X75Y82 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y82 FDPE (Prop_fdpe_C_Q) 0.456 1.984 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/Q + net (fo=41, routed) 2.132 4.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/SR[0] + SLICE_X77Y78 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.582 12.755 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/my_full_reg[4] + SLICE_X77Y78 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg/C + clock pessimism 0.745 13.500 + clock uncertainty -0.067 13.433 + SLICE_X77Y78 FDCE (Recov_fdce_C_CLR) -0.405 13.028 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rst_out_reg + ------------------------------------------------------------------- + required time 13.028 + arrival time -4.116 + ------------------------------------------------------------------- + slack 8.912 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.291ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.128ns (31.246%) route 0.282ns (68.754%)) + Logic Levels: 0 + Clock Path Skew: 0.268ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.225ns + Source Clock Delay (SCD): 0.172ns + Clock Pessimism Removal (CPR): -0.215ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.596 0.172 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk + SLICE_X77Y99 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y99 FDPE (Prop_fdpe_C_Q) 0.128 0.300 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.282 0.581 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X73Y101 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.863 0.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk + SLICE_X73Y101 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C + clock pessimism 0.215 0.440 + SLICE_X73Y101 FDPE (Remov_fdpe_C_PRE) -0.149 0.291 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg + ------------------------------------------------------------------- + required time -0.291 + arrival time 0.581 + ------------------------------------------------------------------- + slack 0.291 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 23.997ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.349ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 23.997ns (required time - arrival time) + Source: reset_count_reg[6]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 15.248ns (logic 1.303ns (8.545%) route 13.945ns (91.455%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.136ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.535ns = ( 38.465 - 40.000 ) + Source Clock Delay (SCD): -0.839ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.701 -0.839 clk + SLICE_X75Y103 FDRE r reset_count_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y103 FDRE (Prop_fdre_C_Q) 0.456 -0.383 r reset_count_reg[6]/Q + net (fo=2, routed) 1.004 0.621 platform/normalizer/reset_count_reg[6] + SLICE_X74Y104 LUT6 (Prop_lut6_I4_O) 0.124 0.745 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.670 1.416 platform/normalizer/axi_fullwidth_net_1 + SLICE_X72Y105 LUT5 (Prop_lut5_I4_O) 0.124 1.540 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.809 2.349 platform/normalizer/axi_fullwidth_net_3 + SLICE_X74Y105 LUT4 (Prop_lut4_I3_O) 0.124 2.473 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.810 3.283 platform/normalizer/sel + SLICE_X77Y101 LUT4 (Prop_lut4_I3_O) 0.120 3.403 f platform/normalizer/axi_fullwidth_LUT4_10/O + net (fo=899, routed) 2.686 6.090 platform/loader/cpu_run_reg_inv_19 + SLICE_X81Y115 LUT2 (Prop_lut2_I0_O) 0.355 6.445 f platform/loader/in_pipe_v_i_1__0/O + net (fo=5312, routed) 7.965 14.409 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X54Y139 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=37170, routed) 1.486 38.465 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X54Y139 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.560 39.025 + clock uncertainty -0.091 38.934 + SLICE_X54Y139 FDCE (Recov_fdce_C_CLR) -0.527 38.407 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 38.407 + arrival time -14.409 + ------------------------------------------------------------------- + slack 23.997 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.349ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.478ns (logic 0.128ns (26.778%) route 0.350ns (73.222%)) + Logic Levels: 0 + Clock Path Skew: 0.275ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.801ns + Source Clock Delay (SCD): -0.567ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37170, routed) 0.597 -0.567 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X81Y100 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X81Y100 FDPE (Prop_fdpe_C_Q) 0.128 -0.439 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.350 -0.089 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + SLICE_X79Y96 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37170, routed) 0.872 -0.801 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + SLICE_X79Y96 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.509 -0.292 + SLICE_X79Y96 FDCE (Remov_fdce_C_CLR) -0.146 -0.438 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.438 + arrival time -0.089 + ------------------------------------------------------------------- + slack 0.349 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 2.156ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.156ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 2.844ns (logic 0.456ns (16.031%) route 2.388ns (83.969%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X68Y82 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X68Y82 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.388 2.844 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -2.844 + ------------------------------------------------------------------- + slack 2.156 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + (rising edge-triggered cell FDCE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.745ns (logic 2.101ns (36.563%) route 3.645ns (63.437%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.704 1.526 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X73Y82 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X73Y82 FDCE (Prop_fdce_C_Q) 0.456 1.982 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/Q + net (fo=1, routed) 1.357 3.339 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n + SLICE_X85Y81 LUT2 (Prop_lut2_I1_O) 0.124 3.463 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.288 5.751 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.272 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.272 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.310ns (logic 0.141ns (10.760%) route 1.169ns (89.240%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X68Y82 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y82 FDPE (Prop_fdpe_C_Q) 0.141 0.277 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.169 1.446 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/loader/cpu_run_reg_inv/C + (rising edge-triggered cell FDSE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 13.571ns (logic 4.726ns (34.827%) route 8.845ns (65.173%)) + Logic Levels: 2 (LUT5=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.684 -0.856 platform/loader/clk + SLICE_X75Y122 FDSE r platform/loader/cpu_run_reg_inv/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y122 FDSE (Prop_fdse_C_Q) 0.419 -0.437 f platform/loader/cpu_run_reg_inv/Q + net (fo=264, routed) 3.664 3.226 platform/loader/rx_valid1 + SLICE_X77Y101 LUT5 (Prop_lut5_I4_O) 0.296 3.522 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 5.181 8.704 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.011 12.715 r led_OBUF[2]_inst/O + net (fo=0) 0.000 12.715 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: calib_sync_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.892ns (logic 2.171ns (75.046%) route 0.722ns (24.954%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37170, routed) 0.598 -0.566 clk + SLICE_X88Y79 FDRE r calib_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y79 FDRE (Prop_fdre_C_Q) 0.148 -0.418 r calib_sync_reg[1]/Q + net (fo=5, routed) 0.722 0.303 calib_sync[1] + H5 OBUF (Prop_obuf_I_O) 2.023 2.326 r led_OBUF[0]_inst/O + net (fo=0) 0.000 2.326 led[0] + H5 r led[0] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.195ns (logic 0.772ns (18.402%) route 3.423ns (81.598%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.766ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.764ns + Source Clock Delay (SCD): 1.530ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.708 1.530 ui_clk + SLICE_X78Y101 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y101 FDPE (Prop_fdpe_C_Q) 0.478 2.008 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.286 2.294 memory_cdc/inst/m_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I1_O) 0.294 2.588 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.138 5.725 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X88Y133 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.764 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X88Y133 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.573ns (logic 0.251ns (43.821%) route 0.322ns (56.179%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.059ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.232ns + Source Clock Delay (SCD): 0.173ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.597 0.173 ui_clk + SLICE_X78Y101 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y101 FDPE (Prop_fdpe_C_Q) 0.148 0.321 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.093 0.414 memory_cdc/inst/m_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I1_O) 0.103 0.517 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.229 0.746 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X78Y99 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.871 0.232 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X78Y99 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[6]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 8.858ns (logic 1.341ns (15.139%) route 7.517ns (84.861%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.603ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.764ns + Source Clock Delay (SCD): -0.839ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.701 -0.839 clk + SLICE_X75Y103 FDRE r reset_count_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y103 FDRE (Prop_fdre_C_Q) 0.456 -0.383 r reset_count_reg[6]/Q + net (fo=2, routed) 1.004 0.621 platform/normalizer/reset_count_reg[6] + SLICE_X74Y104 LUT6 (Prop_lut6_I4_O) 0.124 0.745 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.670 1.416 platform/normalizer/axi_fullwidth_net_1 + SLICE_X72Y105 LUT5 (Prop_lut5_I4_O) 0.124 1.540 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.809 2.349 platform/normalizer/axi_fullwidth_net_3 + SLICE_X74Y105 LUT4 (Prop_lut4_I3_O) 0.124 2.473 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 1.214 3.687 sel + SLICE_X77Y101 LUT4 (Prop_lut4_I3_O) 0.152 3.839 r memory_cdc_i_1/O + net (fo=1, routed) 0.681 4.520 memory_cdc/inst/s_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I0_O) 0.361 4.881 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.138 8.019 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X88Y133 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.764 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X88Y133 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.579ns (logic 0.337ns (58.248%) route 0.242ns (41.752%)) + Logic Levels: 0 + Clock Path Skew: 2.963ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.527ns + Source Clock Delay (SCD): -1.436ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.585 -1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X86Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y129 FDRE (Prop_fdre_C_Q) 0.337 -1.099 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.242 -0.857 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X89Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.705 1.527 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X89Y129 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.259ns (logic 0.402ns (31.919%) route 0.857ns (68.081%)) + Logic Levels: 0 + Clock Path Skew: 0.954ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.775ns + Source Clock Delay (SCD): -0.179ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.223 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.857 1.081 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X89Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.602 0.775 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.860ns (logic 0.379ns (44.083%) route 0.481ns (55.917%)) + Logic Levels: 0 + Clock Path Skew: 2.371ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.544ns + Source Clock Delay (SCD): -0.827ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.566 -0.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.379 -0.448 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.481 0.033 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X89Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.722 1.544 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.441ns (logic 0.715ns (9.609%) route 6.726ns (90.391%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.479ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.656ns + Source Clock Delay (SCD): -0.823ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.717 -0.823 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y96 FDCE (Prop_fdce_C_Q) 0.419 -0.404 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.803 1.399 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X86Y80 LUT4 (Prop_lut4_I2_O) 0.296 1.695 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.923 6.618 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X67Y126 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.484 0.656 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X67Y126 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.411ns (logic 0.226ns (16.018%) route 1.185ns (83.982%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.788ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.221ns + Source Clock Delay (SCD): -0.567ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.597 -0.567 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y96 FDCE (Prop_fdce_C_Q) 0.128 -0.439 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.758 0.319 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X86Y80 LUT4 (Prop_lut4_I2_O) 0.098 0.417 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.427 0.844 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X75Y82 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.860 0.221 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X75Y82 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__0/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.290ns (logic 1.487ns (20.402%) route 5.803ns (79.598%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.441ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.441ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 5.803 7.290 btn0_IBUF + SLICE_X72Y101 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.580 -1.441 clk + SLICE_X72Y101 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: uart_txd_in + (input port) + Destination: platform/receiver/rx_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.262ns (logic 0.294ns (12.990%) route 1.968ns (87.010%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.810ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.810ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + A9 0.000 0.000 r uart_txd_in (IN) + net (fo=0) 0.000 0.000 uart_txd_in + A9 IBUF (Prop_ibuf_I_O) 0.294 0.294 r uart_txd_in_IBUF_inst/O + net (fo=1, routed) 1.968 2.262 platform/receiver/rx + SLICE_X83Y131 FDRE r platform/receiver/rx_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37170, routed) 0.863 -0.810 platform/receiver/clk + SLICE_X83Y131 FDRE r platform/receiver/rx_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.203ns (logic 0.772ns (18.366%) route 3.431ns (81.634%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.962ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns + Source Clock Delay (SCD): 1.530ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.708 1.530 ui_clk + SLICE_X78Y101 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y101 FDPE (Prop_fdpe_C_Q) 0.478 2.008 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.286 2.294 memory_cdc/inst/m_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I1_O) 0.294 2.588 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.146 5.733 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X83Y135 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.589 -1.432 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X83Y135 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.232ns (logic 0.128ns (55.277%) route 0.104ns (44.723%)) + Logic Levels: 0 + Clock Path Skew: -0.981ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.810ns + Source Clock Delay (SCD): 0.171ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.595 0.171 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X87Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.128 0.299 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.104 0.402 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X88Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37170, routed) 0.862 -0.810 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X88Y130 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[6]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 8.866ns (logic 1.341ns (15.125%) route 7.525ns (84.875%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.593ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns + Source Clock Delay (SCD): -0.839ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=37170, routed) 1.701 -0.839 clk + SLICE_X75Y103 FDRE r reset_count_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y103 FDRE (Prop_fdre_C_Q) 0.456 -0.383 r reset_count_reg[6]/Q + net (fo=2, routed) 1.004 0.621 platform/normalizer/reset_count_reg[6] + SLICE_X74Y104 LUT6 (Prop_lut6_I4_O) 0.124 0.745 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.670 1.416 platform/normalizer/axi_fullwidth_net_1 + SLICE_X72Y105 LUT5 (Prop_lut5_I4_O) 0.124 1.540 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.809 2.349 platform/normalizer/axi_fullwidth_net_3 + SLICE_X74Y105 LUT4 (Prop_lut4_I3_O) 0.124 2.473 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 1.214 3.687 sel + SLICE_X77Y101 LUT4 (Prop_lut4_I3_O) 0.152 3.839 r memory_cdc_i_1/O + net (fo=1, routed) 0.681 4.520 memory_cdc/inst/s_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I0_O) 0.361 4.881 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.146 8.027 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X83Y135 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=37170, routed) 1.589 -1.432 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X83Y135 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.898ns (logic 0.319ns (35.538%) route 0.579ns (64.462%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.804ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=37170, routed) 0.592 -0.572 clk + SLICE_X76Y101 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y101 FDPE (Prop_fdpe_C_Q) 0.164 -0.408 f lock_sync_reg[2]/Q + net (fo=4, routed) 0.147 -0.261 lock_sync[2] + SLICE_X77Y101 LUT4 (Prop_lut4_I1_O) 0.045 -0.216 r memory_cdc_i_1/O + net (fo=1, routed) 0.242 0.026 memory_cdc/inst/s_axi_aresetn + SLICE_X78Y101 LUT2 (Prop_lut2_I0_O) 0.110 0.136 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.189 0.325 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X81Y100 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=37170, routed) 0.868 -0.804 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X81Y100 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.718ns (logic 1.487ns (19.271%) route 6.231ns (80.729%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.422ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.422ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.231 7.718 btn0_IBUF + SLICE_X75Y97 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.598 -1.422 ref_clk + SLICE_X75Y97 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.029ns (logic 0.255ns (8.423%) route 2.774ns (91.577%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.802ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.802ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.774 3.029 btn0_IBUF + SLICE_X75Y97 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.871 -0.802 ref_clk + SLICE_X75Y97 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.805ns (logic 0.141ns (7.811%) route 1.664ns (92.189%)) + Logic Levels: 0 + Clock Path Skew: -0.982ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.846ns + Source Clock Delay (SCD): 0.136ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X68Y82 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y82 FDPE (Prop_fdpe_C_Q) 0.141 0.277 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.664 1.941 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X8Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.827 -0.846 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X8Y122 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.216ns (logic 0.741ns (17.576%) route 3.475ns (82.424%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.412ns + Source Clock Delay (SCD): -0.823ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.717 -0.823 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y96 FDCE (Prop_fdce_C_Q) 0.419 -0.404 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.803 1.399 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X86Y80 LUT1 (Prop_lut1_I0_O) 0.322 1.721 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.672 3.393 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X86Y62 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.608 -1.412 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X86Y62 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][12]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.529ns (logic 0.224ns (14.653%) route 1.305ns (85.347%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.234ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.801ns + Source Clock Delay (SCD): -0.567ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.597 -0.567 ref_clk + SLICE_X77Y96 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y96 FDCE (Prop_fdce_C_Q) 0.128 -0.439 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.758 0.319 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X86Y80 LUT1 (Prop_lut1_I0_O) 0.096 0.415 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 0.547 0.961 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X86Y66 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][12]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.872 -0.801 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X86Y66 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][12]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.669ns (logic 0.124ns (1.859%) route 6.545ns (98.141%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 1.622 1.622 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X86Y80 LUT4 (Prop_lut4_I0_O) 0.124 1.746 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.923 6.669 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X67Y126 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.484 0.656 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X67Y126 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.770ns (logic 0.049ns (6.363%) route 0.721ns (93.637%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.261 0.261 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_r1_reg + SLICE_X88Y80 LUT2 (Prop_lut2_I1_O) 0.049 0.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.460 0.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X73Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.858 0.219 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X73Y83 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-utilization.rpt new file mode 100644 index 0000000..c9477b0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/implementation/routed-utilization.rpt @@ -0,0 +1,264 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Sun Oct 11 13:49:21 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-20261011-132657/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 54413 | 0 | 0 | 63400 | 85.82 | +| LUT as Logic | 50491 | 0 | 0 | 63400 | 79.64 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 35600 | 0 | 0 | 126800 | 28.08 | +| Register as Flip Flop | 35600 | 0 | 0 | 126800 | 28.08 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 913 | 0 | 0 | 31700 | 2.88 | +| F8 Muxes | 221 | 0 | 0 | 15850 | 1.39 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 563 | Yes | Set | - | +| 34734 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15663 | 0 | 0 | 15850 | 98.82 | +| SLICEL | 10952 | 0 | | | | +| SLICEM | 4711 | 0 | | | | +| LUT as Logic | 50491 | 0 | 0 | 63400 | 79.64 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37801 | | | | | +| using O5 and O6 | 12659 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 35600 | 0 | 0 | 126800 | 28.08 | +| Register driven from within the Slice | 15067 | | | | | +| Register driven from outside the Slice | 20533 | | | | | +| LUT in front of the register is unused | 5288 | | | | | +| LUT in front of the register is used | 15245 | | | | | +| Unique Control Sets | 1256 | | 0 | 15850 | 7.92 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 29 | 0 | 0 | 135 | 21.48 | +| RAMB36/FIFO* | 25 | 0 | 0 | 135 | 18.52 | +| RAMB36E1 only | 25 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 56 | 56 | 0 | 210 | 26.67 | +| IOB Master Pads | 26 | | | | | +| IOB Slave Pads | 27 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 34734 | Flop & Latch | +| LUT6 | 20797 | LUT | +| LUT3 | 13520 | LUT | +| LUT5 | 12717 | LUT | +| LUT4 | 10409 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4897 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| MUXF7 | 913 | MuxFx | +| LUT1 | 810 | LUT | +| FDSE | 563 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| MUXF8 | 221 | MuxFx | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 29 | IO | +| RAMB36E1 | 25 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/software/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/software/RESULT.json new file mode 100644 index 0000000..8690063 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/software/RESULT.json @@ -0,0 +1,29 @@ +{ + "result": "PASS_BUILD", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "payload_bytes": 17409032, + "linux_image_sha256": "79aef0e6c72be764dfc37a55cbe7587e00531265b59343125b3a6950509d9e7a", + "linux_image_unchanged": true, + "clint_frequency_hz": 500000, + "core_frequency_hz": 25000000, + "console_base": "0x60020000", + "memory_bytes": 268435456, + "original_platform_sha256": "215cc16a14101a2b987fb05f8619ccf20eef610f5f88c6561575e9a25fff7773", + "adapted_platform_sha256": "f1a7a6d2921105055adb66e9df759d12196cdf9d63d15966c66276f69354fc9f", + "original_payload_sha256": "762d608b5e23a0a438c0139bc7487143fd97e30de110d44fb7e2ba27ac07477f", + "boot_tested": false, + "command": [ + "make", + "-C", + "/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/opensbi-src", + "-j8", + "CROSS_COMPILE=riscv64-linux-gnu-", + "PLATFORM_DIR=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/platform", + "PLATFORM=buckyball", + "O=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/opensbi-build", + "FW_PAYLOAD_PATH=/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-software/Image", + "BUCKYBALL_VISIBLE_HART_COUNT=1", + "BUCKYBALL_TOTAL_HART_COUNT=1", + "BUCKYBALL_HIDDEN_HART_BASE=1" + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/BOARD_REGRESSION.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/BOARD_REGRESSION.json new file mode 100644 index 0000000..79e2fd2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/BOARD_REGRESSION.json @@ -0,0 +1,41 @@ +{ + "result": "PASS", + "tests": { + "cpu": { + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 + }, + "gemmini": { + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 + }, + "loop": { + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 + }, + "dma": { + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/RESULT.json new file mode 100644 index 0000000..b252342 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS_BOARD_CDC", + "board_run": "board-20261011-132657", + "core_clock_hz": 25000000, + "ui_clock_hz": 83333333, + "read_beats": 90, + "physical_mig_simulated": false, + "xci_sha256": "33a73fd614db8bd3daf6d45a6c747e087caacd7e7ef6f610f3cc894120eac025", + "bench_sha256": "0903001dfe5bb2d8d5a36eb84545f6e08a2eb3c8bd86c8f20a1ff37c9bb51de2" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/simulation.log new file mode 100644 index 0000000..1df3da2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cdc/simulation.log @@ -0,0 +1,8 @@ +Time resolution is 1 ps +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +PASS BOARD_CDC: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +$finish called at time : 100800 ns : File "/home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-cdc-final/tb_board_cdc.sv" Line 221 diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/RESULT.json new file mode 100644 index 0000000..8849267 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/simulation.log new file mode 100644 index 0000000..32b6009 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/cpu/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-cpu/tb_board_cpu.sv:51: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.482 s; speed 1.294 ms/s +- Verilator: cpu 5.480 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/RESULT.json new file mode 100644 index 0000000..7f02844 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/simulation.log new file mode 100644 index 0000000..c9b1678 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/dma/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-dma/tb_board_cpu.sv:51: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 15.660 s; speed 1.223 ms/s +- Verilator: cpu 15.660 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/RESULT.json new file mode 100644 index 0000000..e935317 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/simulation.log new file mode 100644 index 0000000..3afbb92 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/gemmini/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-gemmini/tb_board_cpu.sv:51: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 1.917 s; speed 1.310 ms/s +- Verilator: cpu 1.917 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/RESULT.json new file mode 100644 index 0000000..962fe2b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/RESULT.json @@ -0,0 +1,17 @@ +{ + "result": "PASS_RTL_LINUX_USERSPACE", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "checks": [ + "OpenSBI", + "Linux version", + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK", + "PASS BOARD_LINUX_USERSPACE" + ], + "physical_mig_simulated": false, + "physical_board_tested": false, + "uart_rx_command_tested": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/simulation.log new file mode 100644 index 0000000..a7ddc37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/linux-final/simulation.log @@ -0,0 +1,172 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Sat Oct 10 16:24:07 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 241400K/262144K available (2126K kernel code, 4423K rwdata, 2048K rodata, 4385K init, 299K bss, 20744K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 4384K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # +SIM_SHELL_PROMPT cycles=241934865 +/root/linux_system_check-linux +SIM_COMMAND_SENT cycles=249692645 overflow=0 framing=0 pending_rx=1 + +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003f82c1a000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fe9ca4b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fe9ca4bd0 + s1 : 0000003f82c19000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f82c1a000 + s5 : 0000003fe9ca4d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f82c1a000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=101252000 +PASS LINUX_SYSTEM_CHECK +PASS BOARD_LINUX_USERSPACE cycles=273506752 characters=7992 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-linux-final/tb_board_linux.sv:94: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 11s; walltime 2149.901 s; speed 5.089 ms/s +- Verilator: cpu 2149.865 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/RESULT.json new file mode 100644 index 0000000..c426992 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/simulation.log new file mode 100644 index 0000000..7a84e07 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/loop/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-loop/tb_board_cpu.sv:51: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.242 s; speed 1.305 ms/s +- Verilator: cpu 5.241 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/RESULT.json new file mode 100644 index 0000000..eebcde7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS_UART_LOAD_VERIFY_BOOT", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "bytes_verified": 110592, + "testbench_cpu_release_override": false, + "preloaded_ddr_image": false, + "physical_mig_simulated": false, + "physical_board_tested": false, + "cycles": 61853990 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/simulation.log new file mode 100644 index 0000000..83911bf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/uart-boot/simulation.log @@ -0,0 +1,7 @@ +PASS UART_PAYLOAD_READBACK bytes=110592 cycles=61134003 +PASS UART_VERIFIED_RUN cycles=61144580 +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=61853990 +- /home/yys/codex-builds/toy-a7-gemmini-correct-20261010/build/board-uart-boot/tb_board_uart_boot.sv:51: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2s; walltime 429.002 s; speed 5.767 ms/s +- Verilator: cpu 428.937 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-11/tests/unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-11/tests/unit/RESULT.json new file mode 100644 index 0000000..02cd6d7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-11/tests/unit/RESULT.json @@ -0,0 +1,17 @@ +{ + "result": "PASS", + "tests": 3, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "404cf6ab82b7bc0aeff2d3eeb7855f2e2028784ff4408a6c97eec023464c039f", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "a3d2808a2bcaa1aa4381e51c9df3ba358d96acdbabd08939e60c073c65550dfc", + "board/toy_a7_platform.sv": "db7e7bd98ce81d6c538157e462232d380fe7318a2d0cfeb3afed6773ba127c4c", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "3f58d9d98ba02663f913caecf0fd3e4aea11d0b2bc637e59566fcfe674fffe86" + } +} diff --git a/platforms/arty-a7-toy/evidence/README.md b/platforms/arty-a7-toy/evidence/README.md new file mode 100644 index 0000000..c223507 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/README.md @@ -0,0 +1,15 @@ +# Preserved measurements + +`2026-10-11/` contains original measured reports and test transcripts from the +selected isolated candidate. The archived report mentions that candidate's +original build paths; repository build/operation instructions are in `../README.md`. +Checkpoints, generated RTL, images and bitstreams are omitted from Git. + +The core/RAM hashes and original firmware payload hash identify the exact +measured hardware/software. The archived machine record's source paths and +commands describe the original experiment, not installation requirements. +Portable launchers in `scripts/` use PATH or explicit overrides. + +Run `python3 scripts/verify_target.py` from the platform directory to verify +published source hashes, reference oracles, vendor inputs and recorded results. +After elaboration, add `--core` to verify the generated core and RAM binding. diff --git a/platforms/arty-a7-toy/host/load.py b/platforms/arty-a7-toy/host/load.py new file mode 100644 index 0000000..1f83575 --- /dev/null +++ b/platforms/arty-a7-toy/host/load.py @@ -0,0 +1,103 @@ +"""Load and byte-verify a complete Toy/OpenSBI/Linux payload in DDR. + +Reset BTN0 and wait for LED0 (DDR calibration). Requires pyserial. +Example: python host/load.py --port COM5 build/board-software/fw_payload.bin +""" +import argparse +import binascii +import hashlib +from pathlib import Path +import struct +import sys +import time + + +def frame(op, sequence, address, length, data=b""): + body=struct.pack("256:raise ValueError("Invalid response size") + payload=self.read_exact(size) + checksum=struct.unpack("capacity:raise ValueError("Image exceeds reported DDR capacity") + print(f"DDR {capacity} bytes, core {clock} Hz, payload SHA256 {hashlib.sha256(data).hexdigest()}") + started=time.monotonic() + for offset in range(0,len(data),256): + chunk=data[offset:offset+256] + loader.request(1,0x80000000+offset,len(chunk),chunk) + if loader.request(2,0x80000000+offset,len(chunk))!=chunk: + raise RuntimeError(f"DDR readback mismatch at {offset:#x}; CPU remains reset") + if offset%65536==0:print(f"Verified {offset+len(chunk)}/{len(data)} bytes",flush=True) + loader.request(3,0x80000000) + print(f"Full readback passed; CPU started after {time.monotonic()-started:.1f}s. Console:") + deadline=time.monotonic()+args.console_seconds + console=bytearray() + command_sent=False + linux_passed=False + checks=(b"PASS VM_COPY_ON_WRITE",b"PASS VM_PAGE_PROTECTION",b"PASS FP64_PROCESS_CONTEXT", + b"PASS LINUX_TIMER",b"PASS LINUX_SYSTEM_CHECK") + with args.transcript.open("wb") as log: + while time.monotonic() matmulUnroller.io.cmd + cmdArb.io.in(1) <> convUnroller.io.cmd + encoder.io.cmd <> cmdArb.io.out + encoder.io.subRobRow <> io.subRobReq + encoder.io.ballId := ballCommonConfig.ballId.U + encoder.io.masterRobId := rob_id_reg + + // ========================================================================= + // cmdReq.ready: route to correct consumer + // ========================================================================= + val idleReady = + exCtrl.exio.cmdReq.ready && !matmulUnroller.io.busy && !convUnroller.io.busy + io.cmdReq.ready := Mux( + isExUnit, + exCtrl.exio.cmdReq.ready, + Mux( + isLoopWsConfig || isLoopConvConfig, + idleReady, + Mux( + isLoopWsTrigger, + !matmulUnroller.io.busy, + Mux(isLoopConvTrigger, !convUnroller.io.busy, idleReady) + ) + ) + ) + + // ========================================================================= + // cmdResp: mux between exUnit and config immediate response + // ========================================================================= + io.cmdResp <> exCtrl.exio.cmdResp + when(configRespValid) { + io.cmdResp.valid := true.B + io.cmdResp.bits := configRespBits + } + + // ========================================================================= + // Bank connections (unchanged from original) + // ========================================================================= + for (i <- 0 until inBW) { + io.bankRead(i).io.req <> exCtrl.exio.bankReadReq(i) + exCtrl.exio.bankReadResp(i) <> io.bankRead(i).io.resp + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).group_id := 0.U + } + io.bankRead(0).bank_id := exCtrl.exio.op1_bank_o + if (inBW > 1) { + io.bankRead(1).bank_id := exCtrl.exio.op2_bank_o + } + + for (i <- 0 until outBW) { + io.bankWrite(i).io <> exCtrl.exio.bankWrite(i) + io.bankWrite(i).bank_id := exCtrl.exio.wr_bank_o + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).group_id := i.U + } + + io.status <> exCtrl.exio.status + + MmioRead.tieOff(io.mmioRead) +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrl.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrl.scala new file mode 100644 index 0000000..e6d2fed --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrl.scala @@ -0,0 +1,34 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +@instantiable +class GemminiExCtrl(val b: GlobalConfig) + extends Module + with GemminiExCtrlDefs + with GemminiExCtrlDefaults + with GemminiExCtrlCmdStates + with GemminiExCtrlPreloadStates + with GemminiExCtrlComputeReadState + with GemminiExCtrlComputeFeedState + with GemminiExCtrlStoreOps + with GemminiExCtrlFsm { + @public val exio = io + + applyDefaults() + runFsm() + + // WS output is associated with the preceding non-flush mesh request. + // Unlike a ROB ID, the internal token changes for each loop iteration. + when(mesh.io.req.fire && mesh.io.req.bits.flush === 0.U) { + wsResultTag := lastMeshTag + lastMeshTag := mesh.io.req.bits.tag.rob + nextMeshTag := Mux(nextMeshTag === 254.U, 0.U, nextMeshTag + 1.U) + } + + io.status.idle := state === sIdle + io.status.running := state =/= sIdle +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlCmdStates.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlCmdStates.scala new file mode 100644 index 0000000..9c7c62d --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlCmdStates.scala @@ -0,0 +1,92 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlCmdStates { this: GemminiExCtrl => + + protected def handleIdleState(): Unit = { + io.cmdReq.ready := true.B + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op2_bank := io.cmdReq.bits.cmd.op2_bank + wr_bank := io.cmdReq.bits.cmd.wr_bank + op1_base := io.cmdReq.bits.cmd.special(15, 6) + op2_base := io.cmdReq.bits.cmd.special(25, 16) + wr_base := io.cmdReq.bits.cmd.special(35, 26) + total_rows := Mux( + io.cmdReq.bits.cmd.iter === 0.U, + DIM.U, + io.cmdReq.bits.cmd.iter + ) + zero_op2 := io.cmdReq.bits.cmd.special(4) + zero_op1_tail := io.cmdReq.bits.cmd.special(5) + + when(sub_cmd === GemminiSubCmd.CONFIG) { + cfg_dataflow := io.cmdReq.bits.cmd.special(4) + cfg_a_transpose := io.cmdReq.bits.cmd.special(7) + cfg_bd_transpose := io.cmdReq.bits.cmd.special(8) + cfg_in_shift := io.cmdReq.bits.cmd.special( + log2Up(config.accWidth) + 8, + 9 + ) + io.cmdResp.valid := true.B + state := sCommit + }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + req_sent := false.B + xpose_ready := false.B + xpose_row_cnt := 0.U + state := sPreloadRead + }.elsewhen( + sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED + ) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + outBufRows := 0.U + outBufCollected := 0.U + req_sent := false.B + xpose_ready := false.B + xpose_row_cnt := 0.U + read_done.foreach(_ := false.B) + state := sComputeRead + }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { + state := sFlush + } + } + } + + protected def handleCommitState(): Unit = { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + + protected def handleFlushState(): Unit = { + mesh.io.req.valid := true.B + mesh.io.req.bits.flush := 2.U + mesh.io.req.bits.total_rows := DIM.U + mesh.io.req.bits.tag.rob := nextMeshTag + + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + + when(mesh.io.req.ready) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlComputeFeedState.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlComputeFeedState.scala new file mode 100644 index 0000000..cf7b241 --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlComputeFeedState.scala @@ -0,0 +1,121 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlComputeFeedState { this: GemminiExCtrl => + + protected def handleComputeFeedState(): Unit = { + when(cfg_dataflow === Dataflow.WS.id.U && req_sent) { captureWsOutput() } + // OS: do not collect mesh rows here — preload matmul responses still drain during feed; + // sComputeFlush drops tag=0xff (garbage) resps and collects non-garbage rows only. + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + mesh.io.req.bits.bd_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + false.B, + cfg_bd_transpose + ) + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + val op1FromBuf = cfg_dataflow === Dataflow.OS.id.U && !cfg_a_transpose + val op2FromBuf = cfg_dataflow === Dataflow.OS.id.U && cfg_bd_transpose + val needXpose = op1FromBuf || (op2FromBuf && !zero_op2) + + when(req_sent && needXpose && !xpose_ready) { + val op1Ready = !op1FromBuf || rdQueue0.io.deq.valid + val op2Ready = !op2FromBuf || zero_op2 || rdQueue1.io.deq.valid + when(xpose_row_cnt < total_rows && op1Ready && op2Ready) { + when(op1FromBuf) { + op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue0.io.deq.ready := true.B + } + when(op2FromBuf && !zero_op2) { + op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue1.io.deq.ready := true.B + } + xpose_row_cnt := xpose_row_cnt + 1.U + }.elsewhen(xpose_row_cnt >= total_rows) { + xpose_ready := true.B + } + } + + when(req_sent && (!needXpose || xpose_ready) && feed_row_cnt < total_rows) { + val op1Zero = zero_op1_tail && feed_row_cnt =/= 0.U + when( + (op1Zero || op1FromBuf || rdQueue0.io.deq.valid) && (zero_op2 || op2FromBuf || rdQueue1.io.deq.valid) + ) { + val a_mem_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val x_mem_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) + val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) + val a_row = Mux(op1FromBuf, a_col_row, a_mem_row) + val x_row = Mux(op2FromBuf, x_col_row, x_mem_row) + mesh.io.a.valid := true.B + mesh.io.a.bits := Mux( + op1Zero, + 0.U.asTypeOf(mesh.A_TYPE), + VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) + ) + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS: stream A/B, D=0 + mesh.io.b.valid := true.B + mesh.io.b.bits := VecInit( + x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + }.otherwise { + // WS: stream A/D, B comes from preloaded weights + mesh.io.b.valid := true.B + // WS accumulates the incoming bias/partial sum from B. + // D loads the inactive weight register and must not carry bias. + mesh.io.b.bits := Mux( + zero_op2, + 0.U.asTypeOf(mesh.B_TYPE), + VecInit( + x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + ) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + } + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := !op1Zero && !op1FromBuf + rdQueue1.io.deq.ready := !zero_op2 && !op2FromBuf + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + when(cfg_dataflow === Dataflow.OS.id.U) { + outBufRows := total_rows - 1.U + req_sent := false.B + feed_row_cnt := 0.U + state := sComputeFlush + }.otherwise { + state := sDrain + } + } + } + +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlDefs.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlDefs.scala new file mode 100644 index 0000000..3c9e65e --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlDefs.scala @@ -0,0 +1,132 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.public +import framework.balldomain.blink.BallStatus +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} +import framework.top.GlobalConfig +import examples.balls.gemmini.configs.GemminiBallParam +import gemmini._ +import gemmini.Util._ + +trait GemminiExCtrlDefs { this: GemminiExCtrl => + val config = GemminiBallParam(b) + val DIM = config.blockSize + + val ballMapping = b.ballDomain.ballIdMappings + .find(_.ballName == "GemminiBall") + .getOrElse( + throw new IllegalArgumentException("GemminiBall not found in config") + ) + + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + val inputType = SInt(config.inputWidth.W) + val accType = SInt(config.accWidth.W) + val meshOutputType = SInt(config.spatialOutputWidth.W) + + val ctrlIo = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + val op1_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val op2_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val wr_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val status = new BallStatus + }) + + val io = ctrlIo + + // Mesh tags are internal request tokens. They must distinguish different + // operations even when loop subcommands share an architectural ROB ID. + // Reserve 255 for Gemmini garbage tags; at most six requests are live. + val nextMeshTag = RegInit(0.U(8.W)) + val lastMeshTag = RegInit(255.U(8.W)) + val wsResultTag = RegInit(255.U(8.W)) + + val mesh = Module( + new MeshWithDelays( + inputType = inputType, + weightType = inputType, + outputType = meshOutputType, + accType = accType, + tagType = new SimpleTag, + df = Dataflow.BOTH, + tree_reduction = false, + tile_latency = config.tileLatency, + output_delay = config.outputDelay, + tileRows = config.tileRows, + tileColumns = config.tileColumns, + meshRows = config.meshRows, + meshColumns = config.meshColumns, + leftBanks = 1, + upBanks = 1 + ) + ) + + protected def widenMeshToAcc(src: Vec[Vec[SInt]]): Vec[Vec[SInt]] = + VecInit(src.map(col => VecInit(col.map(_.asTypeOf(accType))))) + + val cfg_dataflow = RegInit(0.U(1.W)) + val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) + val cfg_a_transpose = RegInit(false.B) + val cfg_bd_transpose = RegInit(false.B) + val zero_op2 = RegInit(false.B) + val zero_op1_tail = RegInit(false.B) + + val sIdle :: sPreloadRead :: sPreloadFeed :: sComputeRead :: sComputeFeed :: sComputeFlush :: sFlush :: sDrain :: sStore :: sCommit :: Nil = + Enum(10) + val state = RegInit(sIdle) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + + /** Match SimpleTag.rob (8b); must match mesh req tag bits */ + protected def robIdAsTag8(x: UInt): UInt = { + val w = x.getWidth + if (w >= 8) x(7, 0) else Cat(0.U((8 - w).W), x) + } + + val op1_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val op2_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val wr_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val op1_base = RegInit(0.U(10.W)) + val op2_base = RegInit(0.U(10.W)) + val wr_base = RegInit(0.U(10.W)) + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank + io.wr_bank_o := wr_bank + + val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) + val req_sent = RegInit(false.B) + val read_done = RegInit(VecInit(Seq.fill(inBW)(false.B))) + val xpose_ready = RegInit(false.B) + val xpose_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + + val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) + + val rdQueue0 = Module(new Queue(new SramReadResp(b), entries = DIM)) + val rdQueue1 = Module(new Queue(new SramReadResp(b), entries = DIM)) + rdQueue0.io.enq <> io.bankReadResp(0) + rdQueue1.io.enq <> io.bankReadResp(1) + + val outBuf = Reg( + Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, accType))) + ) + + val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) + val op1Buf = Reg(Vec(DIM, Vec(DIM, inputType))) + val op2Buf = Reg(Vec(DIM, Vec(DIM, inputType))) + + val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlPreloadStates.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlPreloadStates.scala new file mode 100644 index 0000000..a3221b2 --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlPreloadStates.scala @@ -0,0 +1,114 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlPreloadStates { this: GemminiExCtrl => + + protected def handlePreloadReadState(): Unit = { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := op1_base + read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + }.otherwise { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + // The mesh expects ordinary WS weights bottom-up. For b_transpose we + // first capture the source matrix in natural row order and explicitly + // feed its columns bottom-up in sPreloadFeed. + io.bankReadReq(0).bits.addr := Mux( + cfg_bd_transpose, + op1_base + read_row_cnt, + op1_base + total_rows - 1.U - read_row_cnt + ) + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + } + } + + protected def handlePreloadFeedState(): Unit = { + val explicitBTranspose = + cfg_dataflow === Dataflow.WS.id.U && cfg_bd_transpose + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + // B transpose is materialized in op2Buf below. Keeping the mesh-side + // transposer disabled avoids the unsupported WS transpose request path. + mesh.io.req.bits.bd_transpose := false.B + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + when(req_sent && explicitBTranspose && !xpose_ready) { + when(xpose_row_cnt < total_rows && rdQueue0.io.deq.valid) { + op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue0.io.deq.ready := true.B + xpose_row_cnt := xpose_row_cnt + 1.U + }.elsewhen(xpose_row_cnt >= total_rows) { + xpose_ready := true.B + } + } + + when( + req_sent && (!explicitBTranspose || xpose_ready) && feed_row_cnt < total_rows + ) { + when(explicitBTranspose || rdQueue0.io.deq.valid) { + val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val transpose_col = total_rows - 1.U - feed_row_cnt + val transposed_data = + VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) + val weight_data = Mux(explicitBTranspose, transposed_data, row_data) + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + // OS preload in Buckyball is used to prime pipeline state before compute. + // Feed D=0 to avoid injecting bias-like data into the following matmul. + mesh.io.d.bits := Mux( + cfg_dataflow === Dataflow.OS.id.U, + 0.U.asTypeOf(mesh.D_TYPE), + VecInit( + weight_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + ) + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := !explicitBTranspose + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlStoreOps.scala b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlStoreOps.scala new file mode 100644 index 0000000..62f9bee --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/GemminiExCtrlStoreOps.scala @@ -0,0 +1,139 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlStoreOps { this: GemminiExCtrl => + + // WS responses carry the preceding internal mesh request token. + // Collect non-garbage rows during feeding as well as draining: a shorter + // mesh can return its first results before all input rows have been sent. + protected def captureWsOutput(): Unit = { + when(mesh.io.resp.valid && mesh.io.resp.bits.tag.rob === wsResultTag && + wsResultTag =/= 0xff.U && + outBufRows < total_rows) { + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) + outBufRows := outBufRows + 1.U + } + } + + + protected def handleComputeFlushState(): Unit = { + when(mesh.io.resp.fire && mesh.io.resp.bits.total_rows === total_rows) { + when( + outBufCollected < total_rows && mesh.io.resp.bits.tag.rob =/= 0xff.U + ) { + outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( + mesh.io.resp.bits.data + ) + outBufCollected := outBufCollected + 1.U + }.otherwise {} + } + + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + }.otherwise { + // Flush once to drain remaining rows after feeding is complete. + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + mesh.io.req.bits.bd_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + false.B, + cfg_bd_transpose + ) + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 1.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + } + } + + protected def handleDrainState(): Unit = { + when(mesh.io.resp.valid) { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(mesh.io.resp.bits.total_rows === total_rows) { + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) + outBufRows := outBufRows - 1.U + outBufCollected := outBufCollected + 1.U + } + } + } + when(cfg_dataflow === Dataflow.WS.id.U) { + captureWsOutput() + } + + when(cfg_dataflow === Dataflow.OS.id.U) { + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + }.otherwise { + when(outBufRows >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + } + } + + protected def handleStoreState(): Unit = { + when(store_row_cnt < total_rows) { + // One row = DIM elements; split across outBW ports (group_id 0..outBW-1). + // mvout reads (addr, group 0), (addr, group 1), ... and concatenates as row. + // So port i (group_id=i) must get elements [i*elemsPerPort .. (i+1)*elemsPerPort). + val rowIdx = store_row_cnt + val row = outBuf(rowIdx) + val flat_raw = VecInit(row.flatten) + val flat_scaled = VecInit( + // Match Gemmini's signed nearest-even shift after collecting the final WS result. + // OS already rounds in the PE; its writeback path remains unscaled. + row.flatten.map(value => FpgaRoundShift(value.asSInt, cfg_in_shift).asTypeOf(accType)) + ) + val row_bits = Cat( + Mux(cfg_dataflow === Dataflow.WS.id.U, flat_scaled, flat_raw) + .map(_.asUInt) + .reverse + ) + + val bitsPerPort = b.memDomain.bankWidth + + for (i <- 0 until outBW) { + when(!port_written(i)) { + val slice = row_bits((i + 1) * bitsPerPort - 1, i * bitsPerPort) + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := wr_base + store_row_cnt + io.bankWrite(i).req.bits.data := slice + io.bankWrite(i).req.bits.mask := VecInit( + Seq.fill(b.memDomain.bankMaskLen)(true.B) + ) + when(io.bankWrite(i).req.ready) { + port_written(i) := true.B + } + } + } + + when(port_written.asUInt.andR) { + store_row_cnt := store_row_cnt + 1.U + port_written.foreach(_ := false.B) + } + }.otherwise { + state := sCommit + } + } + +} diff --git a/platforms/arty-a7-toy/patches/buckyball/LoopMatmulUnroller.scala b/platforms/arty-a7-toy/patches/buckyball/LoopMatmulUnroller.scala new file mode 100644 index 0000000..ae3fbe4 --- /dev/null +++ b/platforms/arty-a7-toy/patches/buckyball/LoopMatmulUnroller.scala @@ -0,0 +1,327 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import examples.balls.gemmini.configs.GemminiBallParam + +/** + * LoopMatmulUnroller — expands LOOP_WS into a stream of LoopCmd rows. + * + * FSM: sIdle → sAllocBanks → sPrimeLoad → sMainLoop (Row1/Row2) → sDrainLast → sFreeBanks → sDone + * + * Row layout per iteration: + * Row 1: [PRELOAD(cur), COMPUTE(cur)] + * Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next)] + * Last iteration: only Row 1, then sDrainLast handles final MVOUT. + */ +@instantiable +class LoopMatmulUnroller(val b: GlobalConfig) extends Module { + val config = GemminiBallParam(b) + val DIM = config.blockSize + val elemSize = config.inputWidth / 8 + val accBytes = config.accWidth / 8 + val bankBytes = b.memDomain.bankWidth / 8 + val bankIdLen = b.memDomain.vbankIdWidth + + @public + val io = IO(new Bundle { + val start = Flipped(Decoupled(new LoopWsConfig(b))) + val cmd = Decoupled(new LoopCmd(b)) + val busy = Output(Bool()) + val dataflow = Input(Bool()) + }) + + // FSM states + val sIdle :: sAllocBanks :: sPrimeLoad :: sMainRow1 :: sMainRow2 :: sDrainLast :: sFreeBanks :: sDone :: Nil = + Enum(8) + val state = RegInit(sIdle) + + // Config registers (latched at start) + val cfg = Reg(new LoopWsConfig(b)) + val weightStationary = RegInit(false.B) + + // Loop iterator registers + val i_reg = RegInit(0.U(16.W)) + val j_reg = RegInit(0.U(16.W)) + val k_reg = RegInit(0.U(16.W)) + + // Total iterations and current iteration index + val totalIter = cfg.max_i * cfg.max_j * cfg.max_k + val curIter = RegInit(0.U(32.W)) + + // Whether this is the last iteration + val isLastIter = curIter === (totalIter - 1.U) + + // Defaults + io.start.ready := state === sIdle + io.cmd.valid := false.B + io.cmd.bits := 0.U.asTypeOf(new LoopCmd(b)) + io.busy := state =/= sIdle + + // Helper to build an invalid LoopSubCmd slot + def emptySlot(): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := false.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v + } + + // Helper to build an MSET slot + def msetSlot( + bankId: UInt, + alloc: Boolean, + row: Int, + col: Int + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := (if (alloc) LoopSubCmdType.MSET_ALLOC + else LoopSubCmdType.MSET_FREE) + v.bits.bank_id := bankId + v.bits.bank_row := row.U + v.bits.bank_col := col.U + v + } + + // Helper to build an MVIN slot + def mvinSlot( + bankId: UInt, + addr: UInt, + iter: UInt, + stride: UInt + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVIN + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.stride := stride + v.bits.iter := iter + v + } + + // Helper to build an MVOUT slot + def mvoutSlot( + bankId: UInt, + addr: UInt, + iter: UInt, + stride: UInt + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVOUT + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.stride := stride + v.bits.iter := iter + v + } + + // Address computation + // addr_a(i,k) = dram_addr_a + i * stride_a + k * DIM * elemSize + // addr_b(k,j) = dram_addr_b + k * stride_b + j * DIM * elemSize + // addr_c(i,j) = dram_addr_c + i * stride_c + j * DIM * accBytes + def addrA(i: UInt, k: UInt): UInt = + cfg.dram_addr_a + i * cfg.stride_a + k * (DIM * elemSize).U + + def addrB(k: UInt, j: UInt): UInt = + cfg.dram_addr_b + k * cfg.stride_b + j * (DIM * elemSize).U + + def addrC(i: UInt, j: UInt): UInt = + cfg.dram_addr_c + i * cfg.stride_c + j * (DIM * accBytes).U + + def inMemStride(bytes: UInt): UInt = + (bytes / bankBytes.U)(18, 0) + + def outMemStride(bytes: UInt): UInt = + (bytes / (bankBytes * 4).U)(18, 0) + + // Next iterator values (advance k, then j, then i) + val next_k = Wire(UInt(16.W)) + val next_j = Wire(UInt(16.W)) + val next_i = Wire(UInt(16.W)) + + when(k_reg + 1.U < cfg.max_k) { + next_k := k_reg + 1.U + next_j := j_reg + next_i := i_reg + }.elsewhen(j_reg + 1.U < cfg.max_j) { + next_k := 0.U + next_j := j_reg + 1.U + next_i := i_reg + }.otherwise { + next_k := 0.U + next_j := 0.U + next_i := i_reg + 1.U + } + + // Compute mode: first k iteration uses PRELOADED (0), rest use ACCUMULATED (1) + val computeMode = Mux(k_reg === 0.U, 0.U(2.W), 1.U(2.W)) + + switch(state) { + is(sIdle) { + io.start.ready := true.B + when(io.start.fire) { + cfg := io.start.bits + weightStationary := io.dataflow + i_reg := 0.U + j_reg := 0.U + k_reg := 0.U + curIter := 0.U + state := sAllocBanks + } + } + + // Row 0: [MSET_alloc(A), MSET_alloc(B), MSET_alloc(C), --] + is(sAllocBanks) { + io.cmd.valid := true.B + io.cmd.bits + .slots(0) := msetSlot(cfg.bank_a, alloc = true, row = 1, col = 1) + io.cmd.bits + .slots(1) := msetSlot(cfg.bank_b, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(2) := msetSlot( + cfg.bank_c, + alloc = true, + row = 1, + col = 4 + ) // accWidth = 4x inputWidth + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sPrimeLoad + } + } + + // Row 1: [MVIN_A(0), MVIN_B(0), --, --] + is(sPrimeLoad) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvinSlot( + cfg.bank_a, + addrA(0.U, 0.U), + DIM.U, + inMemStride(cfg.stride_a) + ) + io.cmd.bits.slots(1) := mvinSlot( + cfg.bank_b, + addrB(0.U, 0.U), + DIM.U, + inMemStride(cfg.stride_b) + ) + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sMainRow1 + } + } + + // Main loop Row 1: [PRELOAD(cur), COMPUTE(cur), --, --] + is(sMainRow1) { + io.cmd.valid := true.B + val preSlot = Wire(Valid(new LoopSubCmd(b))) + preSlot.valid := true.B + preSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + preSlot.bits.cmdType := LoopSubCmdType.PRELOAD + preSlot.bits.op1_bank := Mux(weightStationary, cfg.bank_b, cfg.bank_a) + preSlot.bits.wr_bank := cfg.bank_c + preSlot.bits.iter := DIM.U + + val compSlot = Wire(Valid(new LoopSubCmd(b))) + compSlot.valid := true.B + compSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + compSlot.bits.cmdType := LoopSubCmdType.COMPUTE + compSlot.bits.op1_bank := cfg.bank_a + compSlot.bits.op2_bank := cfg.bank_b + compSlot.bits.wr_bank := cfg.bank_c + compSlot.bits.compute_mode := computeMode + // WS weights are already preloaded; B is not a bias matrix. + compSlot.bits.zero_op2 := weightStationary + compSlot.bits.iter := DIM.U + + io.cmd.bits.slots(0) := preSlot + io.cmd.bits.slots(1) := compSlot + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + when(isLastIter) { + state := sDrainLast // Skip Row 2 for last iteration + }.otherwise { + state := sMainRow2 + } + } + } + + // Main loop Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next), --] + is(sMainRow2) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot( + cfg.bank_c, + addrC(i_reg, j_reg), + DIM.U, + outMemStride(cfg.stride_c) + ) + io.cmd.bits.slots(1) := mvinSlot( + cfg.bank_a, + addrA(next_i, next_k), + DIM.U, + inMemStride(cfg.stride_a) + ) + io.cmd.bits.slots(2) := mvinSlot( + cfg.bank_b, + addrB(next_k, next_j), + DIM.U, + inMemStride(cfg.stride_b) + ) + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + // Advance iterators + i_reg := next_i + j_reg := next_j + k_reg := next_k + curIter := curIter + 1.U + state := sMainRow1 + } + } + + // Drain: emit final MVOUT for last iteration + is(sDrainLast) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot( + cfg.bank_c, + addrC(i_reg, j_reg), + DIM.U, + outMemStride(cfg.stride_c) + ) + io.cmd.bits.slots(1) := emptySlot() + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sFreeBanks + } + } + + // Free: [MSET_free(A), MSET_free(B), MSET_free(C), --] + is(sFreeBanks) { + io.cmd.valid := true.B + io.cmd.bits + .slots(0) := msetSlot(cfg.bank_a, alloc = false, row = 0, col = 0) + io.cmd.bits + .slots(1) := msetSlot(cfg.bank_b, alloc = false, row = 0, col = 0) + io.cmd.bits + .slots(2) := msetSlot(cfg.bank_c, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sDone + } + } + + is(sDone) { + state := sIdle + } + } +} diff --git a/platforms/arty-a7-toy/patches/framework/MemFrontend.scala b/platforms/arty-a7-toy/patches/framework/MemFrontend.scala new file mode 100644 index 0000000..d84e16f --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/MemFrontend.scala @@ -0,0 +1,255 @@ +package framework.memdomain.frontend + +import chisel3._ +import chisel3.util._ +import freechips.rocketchip.tile._ +import framework.memdomain.frontend.mem.dma.{StreamReader, StreamWriter} +import framework.memdomain.frontend.mem.{MemConfiger, MemConfigerIO, MemLoader, MemStorer} +import framework.memdomain.frontend.mem.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} +import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd.decoder.MemDomainDecoder +import framework.memdomain.frontend.cmd.rs.MemReservationStation +import framework.memdomain.utils.pmc.MemCyclePMC + +/** + * MemFrontend: + * Provides DMA interface and Ball Domain interface + */ +@instantiable +class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { + + @public + val io = IO(new Bundle { + // Issue interface from global RS (single channel) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) + // Report completion to global RS (single channel) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) + + // Bank read/write interface - used by load/store + val interdma = new Bundle { + val bankRead = Flipped(new BankRead(b)) + val bankWrite = Flipped(new BankWrite(b)) + val read_is_shared = Output(Bool()) + val write_is_shared = Output(Bool()) + } + + // TLB interfaces for internal DMA modules (Reader/Writer) + // These are NOT exposed to outside - only PTW and TLB exception are exposed + // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) + val ptw = Vec(1, new BBTLBPTWIO(b)) + // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) + val tlbExp = Vec(1, new BBTLBExceptionIO) + + // TileLink physical connections for DMA (Reader/Writer) + val tl_reader = new TLBundle(edge.bundle) + val tl_writer = new TLBundle(edge.bundle) + + val config = Decoupled(new MemConfigerIO(b)) + + // MMIO outputs (to MmioPool via MemDomain) + val is_mvin_mmio_active = Output(Bool()) + val mmio_addr = Output(UInt(17.W)) + val mmio_col = Output(UInt(8.W)) + + // Query interface to backend for group count + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + val hartid = Input(UInt(b.tile.xLen.W)) + + // Busy signal + val busy = Output(Bool()) + }) + + val memDecoder: Instance[MemDomainDecoder] = Instantiate(new MemDomainDecoder(b)) + val memRs: Instance[MemReservationStation] = Instantiate(new MemReservationStation(b)) + val memLoader: Instance[MemLoader] = Instantiate(new MemLoader(b)) + val memStorer: Instance[MemStorer] = Instantiate(new MemStorer(b)) + val pmc: Instance[MemCyclePMC] = Instantiate(new MemCyclePMC(b)) + + // TLB cluster - internal TLB management for DMA modules + // Supports 2 clients: StreamReader (client 1) and StreamWriter (client 0) + val tlbCluster = Instantiate(new BBTLBCluster(b)(edge)) + + // DMA Reader and Writer modules - handle actual DMA transfers + val reader: Instance[StreamReader] = Instantiate(new StreamReader(b)(edge)) + val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)(edge)) + val configer: Instance[MemConfiger] = Instantiate(new MemConfiger(b)) + +// ----------------------------------------------------------------------------- +// Global RS -> MemDecoder +// ----------------------------------------------------------------------------- + memDecoder.io.cmd_i.valid := io.global_issue_i.valid + memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memDecoder.io.cmd_i.ready + + // Config signal goes to backend + io.config <> configer.io.config + + // Loader and storer may query different banks concurrently. Each lookup owns + // the registered backend address and reply until its requester consumes it. + val groupQuery = Module(new MemGroupQueryArbiter(b.memDomain.vbankIdWidth, b.memDomain.groupCountWidth)) + groupQuery.io.request(0).valid := memLoader.io.query_valid + groupQuery.io.request(0).bits.bank := memLoader.io.query_vbank_id + groupQuery.io.request(0).bits.shared := memLoader.io.query_is_shared + memLoader.io.query_ready := groupQuery.io.request(0).ready + memLoader.io.query_resp_valid := groupQuery.io.response(0).valid + memLoader.io.query_group_count := groupQuery.io.response(0).bits + groupQuery.io.response(0).ready := memLoader.io.query_resp_ready + groupQuery.io.request(1).valid := memStorer.io.query_valid + groupQuery.io.request(1).bits.bank := memStorer.io.query_vbank_id + groupQuery.io.request(1).bits.shared := memStorer.io.query_is_shared + memStorer.io.query_ready := groupQuery.io.request(1).ready + memStorer.io.query_resp_valid := groupQuery.io.response(1).valid + memStorer.io.query_group_count := groupQuery.io.response(1).bits + groupQuery.io.response(1).ready := memStorer.io.query_resp_ready + io.query_vbank_id := groupQuery.io.backendBank + io.query_is_shared := groupQuery.io.backendShared + groupQuery.io.backendCount := io.query_group_count + +// ----------------------------------------------------------------------------- +// MemDecoder -> MemReservationStation +// ----------------------------------------------------------------------------- + // Connect decoded instruction and global rob_id + memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid + memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits + memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id + memRs.io.mem_decode_cmd_i.bits.is_sub := io.global_issue_i.bits.is_sub + memRs.io.mem_decode_cmd_i.bits.sub_rob_id := io.global_issue_i.bits.sub_rob_id + memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemReservationStation -> MemLoader/MemStorer +// ----------------------------------------------------------------------------- + memLoader.io.cmdReq <> memRs.io.issue_o.ld + memStorer.io.cmdReq <> memRs.io.issue_o.st + configer.io.cmdReq <> memRs.io.issue_o.cf + configer.io.hartid := io.hartid + memRs.io.commit_i.ld <> memLoader.io.cmdResp + memRs.io.commit_i.st <> memStorer.io.cmdResp + memRs.io.commit_i.cf <> configer.io.cmdResp + +//===-------------------------------------------------------------------===//-- +// PMC - Performance Monitor Counter +// ----------------------------------------------------------------------------- + pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire + pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits + pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire + pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits + pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire + pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits + pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire + pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits + + // Connect Reader and Writer to MemLoader and MemStorer + memLoader.io.dmaReq <> reader.io.req + reader.io.resp <> memLoader.io.dmaResp + memStorer.io.dmaReq <> writer.io.req + writer.io.resp <> memStorer.io.dmaResp + + // TLB connection - internal TLB cluster connected to DMA modules + // Client 0: StreamWriter, Client 1: StreamReader + // Insert pipeline registers to break combinational loops + tlbCluster.io.clients(1).req.valid := reader.io.tlb.req.valid + tlbCluster.io.clients(1).req.bits := reader.io.tlb.req.bits + reader.io.tlb.req.ready := tlbCluster.io.clients(1).req.ready + + reader.io.tlb.resp.valid := tlbCluster.io.clients(1).resp.valid + reader.io.tlb.resp.bits := tlbCluster.io.clients(1).resp.bits + tlbCluster.io.clients(1).resp.ready := reader.io.tlb.resp.ready + + tlbCluster.io.clients(0).req.valid := writer.io.tlb.req.valid + tlbCluster.io.clients(0).req.bits := writer.io.tlb.req.bits + writer.io.tlb.req.ready := tlbCluster.io.clients(0).req.ready + + writer.io.tlb.resp.valid := tlbCluster.io.clients(0).resp.valid + writer.io.tlb.resp.bits := tlbCluster.io.clients(0).resp.bits + tlbCluster.io.clients(0).resp.ready := writer.io.tlb.resp.ready + + // Connect DMA flush signals to TLB exceptions + reader.io.flush := io.tlbExp(0).flush() + writer.io.flush := io.tlbExp(0).flush() + + // PTW interface - connect to upper level page table walker + io.ptw <> tlbCluster.io.ptw + + // TLB exception interface - connect to upper level for flush handling + tlbCluster.io.exp <> io.tlbExp + + // Connect TileLink physical ports from Reader/Writer to external interface + io.tl_reader <> reader.io.tl + io.tl_writer <> writer.io.tl + + // MemLoader and MSET.clear share the frontend write channel. A source owns + // the channel until its write response returns, preserving BankWrite's + // request/response pairing. + val frontendWriteBusy = RegInit(false.B) + val frontendWriteOwnerConfig = RegInit(false.B) + val selectConfigWrite = configer.io.bankWrite.io.req.valid + val selectConfigOwner = Mux(frontendWriteBusy, frontendWriteOwnerConfig, selectConfigWrite) + + io.interdma.bankWrite.io.req.valid := !frontendWriteBusy && + (configer.io.bankWrite.io.req.valid || memLoader.io.bankWrite.io.req.valid) + io.interdma.bankWrite.io.req.bits := Mux( + selectConfigWrite, + configer.io.bankWrite.io.req.bits, + memLoader.io.bankWrite.io.req.bits + ) + io.interdma.bankWrite.bank_id := Mux(selectConfigWrite, configer.io.bankWrite.bank_id, memLoader.io.bankWrite.bank_id) + io.interdma.bankWrite.rob_id := Mux(selectConfigWrite, configer.io.bankWrite.rob_id, memLoader.io.bankWrite.rob_id) + io.interdma.bankWrite.ball_id := Mux(selectConfigWrite, configer.io.bankWrite.ball_id, memLoader.io.bankWrite.ball_id) + io.interdma.bankWrite.group_id := Mux( + selectConfigWrite, + configer.io.bankWrite.group_id, + memLoader.io.bankWrite.group_id + ) + + configer.io.bankWrite.io.req.ready := !frontendWriteBusy && selectConfigWrite && io.interdma.bankWrite.io.req.ready + memLoader.io.bankWrite.io.req.ready := !frontendWriteBusy && !selectConfigWrite && + memLoader.io.bankWrite.io.req.valid && io.interdma.bankWrite.io.req.ready + + io.interdma.bankWrite.io.resp.ready := frontendWriteBusy && Mux( + frontendWriteOwnerConfig, + configer.io.bankWrite.io.resp.ready, + memLoader.io.bankWrite.io.resp.ready + ) + configer.io.bankWrite.io.resp.valid := frontendWriteBusy && frontendWriteOwnerConfig && + io.interdma.bankWrite.io.resp.valid + configer.io.bankWrite.io.resp.bits := io.interdma.bankWrite.io.resp.bits + memLoader.io.bankWrite.io.resp.valid := frontendWriteBusy && !frontendWriteOwnerConfig && + io.interdma.bankWrite.io.resp.valid + memLoader.io.bankWrite.io.resp.bits := io.interdma.bankWrite.io.resp.bits + + when(io.interdma.bankWrite.io.req.fire) { + frontendWriteBusy := true.B + frontendWriteOwnerConfig := selectConfigWrite + } + when(io.interdma.bankWrite.io.resp.fire) { + frontendWriteBusy := false.B + } + + memStorer.io.bankRead <> io.interdma.bankRead + io.interdma.read_is_shared := memStorer.io.is_shared + io.interdma.write_is_shared := Mux(selectConfigOwner, false.B, memLoader.io.is_shared) + + // MMIO signals from MemConfiger and MemLoader, exposed to MemDomain + io.is_mvin_mmio_active := memLoader.io.is_mvin_mmio_active + io.mmio_addr := memLoader.io.mmio_addr + io.mmio_col := memLoader.io.mmio_col + + // Completion signal connected to global RS + io.global_complete_o.valid := memRs.io.complete_o.valid + io.global_complete_o.bits.rob_id := memRs.io.complete_o.bits.rob_id + io.global_complete_o.bits.is_sub := memRs.io.complete_o.bits.is_sub + io.global_complete_o.bits.sub_rob_id := memRs.io.complete_o.bits.sub_rob_id + memRs.io.complete_o.ready := io.global_complete_o.ready + + // Busy signal + // Simple busy signal + io.busy := !memRs.io.complete_o.ready +} diff --git a/platforms/arty-a7-toy/patches/framework/MemGroupQueryArbiter.scala b/platforms/arty-a7-toy/patches/framework/MemGroupQueryArbiter.scala new file mode 100644 index 0000000..ed820c5 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/MemGroupQueryArbiter.scala @@ -0,0 +1,46 @@ +package framework.memdomain.frontend + +import chisel3._ +import chisel3.util._ + +class MemGroupQuery(val bankWidth: Int) extends Bundle { + val bank = UInt(bankWidth.W) + val shared = Bool() +} + +/** Own the two-cycle backend lookup until the selected client accepts its reply. */ +class MemGroupQueryArbiter(bankWidth: Int, countWidth: Int) extends Module { + val io = IO(new Bundle { + val request = Vec(2, Flipped(Decoupled(new MemGroupQuery(bankWidth)))) + val response = Vec(2, Decoupled(UInt(countWidth.W))) + val backendBank = Output(UInt(bankWidth.W)) + val backendShared = Output(Bool()) + val backendCount = Input(UInt(countWidth.W)) + }) + val idle :: waitFirst :: waitSecond :: reply :: Nil = Enum(4) + val state = RegInit(idle) + val owner = RegInit(0.U(1.W)) + val address = RegInit(0.U.asTypeOf(new MemGroupQuery(bankWidth))) + val count = RegInit(0.U(countWidth.W)) + val arbiter = Module(new RRArbiter(new MemGroupQuery(bankWidth), 2)) + arbiter.io.in <> io.request + arbiter.io.out.ready := state === idle + val query = Mux(state === idle, arbiter.io.out.bits, address) + io.backendBank := query.bank + io.backendShared := query.shared + for (i <- 0 until 2) { + io.response(i).valid := state === reply && owner === i.U + io.response(i).bits := count + } + when(arbiter.io.out.fire) { + owner := arbiter.io.chosen + address := arbiter.io.out.bits + state := waitFirst + } + when(state === waitFirst) { state := waitSecond } + when(state === waitSecond) { + count := io.backendCount + state := reply + } + when(io.response(owner).fire) { state := idle } +} diff --git a/platforms/arty-a7-toy/patches/framework/MemLoader.scala b/platforms/arty-a7-toy/patches/framework/MemLoader.scala new file mode 100644 index 0000000..f9a16c8 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/MemLoader.scala @@ -0,0 +1,236 @@ +package framework.memdomain.frontend.mem + +import chisel3._ +import chisel3.util._ +import framework.memdomain.frontend.cmd.rs.{MemRsComplete, MemRsIssue} +import framework.memdomain.backend.banks.SramWriteIO +import framework.memdomain.frontend.mem.dma.{BBReadRequest, BBReadResponse} +import freechips.rocketchip.rocket.MStatus +import framework.balldomain.blink.BankWrite +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +@instantiable +class MemLoader(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) + val cmdResp = Decoupled(new MemRsComplete(b)) + + val dmaReq = Decoupled(new BBReadRequest()) + val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) + + val bankWrite = Flipped(new BankWrite(b)) + + // MMIO routing hint: tells upper level (MemDomain) to route bankWrite to MmioPool + // When is_mvin_mmio_active is true, mmio_addr/col carry MMIO destination info + val is_mvin_mmio_active = Output(Bool()) + val mmio_addr = Output(UInt(17.W)) // rs2[55:39]: MMIO byte address + val mmio_col = Output(UInt(8.W)) // rs2[63:56]: valid bytes per row + + val query_valid = Output(Bool()) + val query_ready = Input(Bool()) + val query_resp_valid = Input(Bool()) + val query_resp_ready = Output(Bool()) + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) + }) + + val s_idle :: s_setup :: s_query :: s_query_wait :: s_mul :: s_dma_req :: s_dma_wait :: s_wait_write_resp :: s_done :: Nil = + Enum(9) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) + val iter_cmd = Reg(UInt(b.frontend.iter_len.W)) + val iter_reg = Reg(UInt(b.frontend.iter_len.W)) + val resp_count = RegInit(0.U(log2Up(16).W)) + val wr_bank_reg = Reg(UInt(b.memDomain.vbankIdWidth.W)) + val stride_reg = Reg(UInt(19.W)) + val is_shared_reg = RegInit(false.B) + + // Group counter for multi-bank writes + val group_counter = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val group_count_reg = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val rowAddr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) + + // MMIO routing info (latched at cmdReq.fire, exposed to upper level) + val is_mvin_mmio_reg = RegInit(false.B) + val is_mvin_2d_reg = RegInit(false.B) + val valid_bytes_reg = RegInit(16.U(5.W)) + val pixel_bytes_reg = RegInit(0.U(10.W)) + val source_width_reg = RegInit(0.U(10.W)) + val tile_width_reg = RegInit(0.U(4.W)) + val mmio_addr_reg = RegInit(0.U(17.W)) + val mmio_col_reg = RegInit(0.U(8.W)) + + io.is_mvin_mmio_active := is_mvin_mmio_reg + io.mmio_addr := mmio_addr_reg + io.mmio_col := mmio_col_reg + + // ----------------------------- + // pending latch for 1-beat DMA -> bankWrite + // ----------------------------- + val pending = RegInit(false.B) + val latData = Reg(UInt(b.memDomain.bankWidth.W)) + val latLast = RegInit(false.B) + + // ----------------------------- + // defaults + // ----------------------------- + io.cmdReq.ready := (state === s_idle) + + io.dmaReq.valid := (state === s_dma_req) + io.dmaReq.bits.vaddr := mem_addr_reg + io.dmaReq.bits.len := iter_reg * (b.memDomain.bankWidth / 8).U + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + io.dmaReq.bits.stride := stride_reg + io.dmaReq.bits.groups := group_count_reg + io.dmaReq.bits.is_2d := is_mvin_2d_reg + io.dmaReq.bits.pixel_bytes := pixel_bytes_reg + io.dmaReq.bits.source_width := source_width_reg + io.dmaReq.bits.tile_width := tile_width_reg + + // only accept DMA beat when waiting AND no pending beat buffered + io.dmaResp.ready := (state === s_dma_wait) && !pending + + // bank write request driven from pending + io.bankWrite.io.req.valid := pending + io.bankWrite.io.req.bits.addr := rowAddr + + val validDataMask = VecInit( + (0 until b.memDomain.bankWidth / 8).map(i => Mux(i.U < valid_bytes_reg, "hff".U(8.W), 0.U(8.W))) + ).asUInt + + io.bankWrite.io.req.bits.data := Mux(is_mvin_2d_reg, latData & validDataMask, latData) + io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + + // IMPORTANT: always ready for write response (avoid deadlock) + io.bankWrite.io.resp.ready := true.B + + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U + io.bankWrite.group_id := group_counter(b.memDomain.groupIdWidth - 1, 0) + io.is_shared := is_shared_reg + + // cmdResp (Decoupled): hold valid until accepted + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg + + // ----------------------------- + // Receive load instruction (both mvin and mvin_mmio go through is_load path) + // ----------------------------- + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + wr_bank_reg := io.cmdReq.bits.cmd.bank_id + resp_count := 0.U + pending := false.B + latLast := false.B + group_counter := 0.U + rowAddr := Mux( + io.cmdReq.bits.cmd.is_mvin_2d, + io.cmdReq.bits.cmd.special(54, 49), + 0.U + ) + is_shared_reg := io.cmdReq.bits.cmd.is_shared + + is_mvin_mmio_reg := io.cmdReq.bits.cmd.is_mvin_mmio + is_mvin_2d_reg := io.cmdReq.bits.cmd.is_mvin_2d + valid_bytes_reg := Mux(io.cmdReq.bits.cmd.special(61, 58) === 0.U, 16.U, io.cmdReq.bits.cmd.special(61, 58)) + pixel_bytes_reg := io.cmdReq.bits.cmd.special(38, 32) << 3 + source_width_reg := io.cmdReq.bits.cmd.special(48, 39) + tile_width_reg := io.cmdReq.bits.cmd.special(57, 55) +& 1.U + when(io.cmdReq.bits.cmd.is_mvin_mmio) { + mmio_addr_reg := io.cmdReq.bits.cmd.special(55, 39) + mmio_col_reg := io.cmdReq.bits.cmd.special(63, 56) + iter_reg := io.cmdReq.bits.cmd.iter + group_count_reg := 1.U + stride_reg := 1.U + state := s_dma_req + }.elsewhen(io.cmdReq.bits.cmd.is_mvin_2d) { + iter_reg := io.cmdReq.bits.cmd.iter * (io.cmdReq.bits.cmd.special(57, 55) +& 1.U) + group_count_reg := 1.U + stride_reg := 1.U + state := s_dma_req + }.otherwise { + stride_reg := io.cmdReq.bits.cmd.special(57, 39) + iter_cmd := io.cmdReq.bits.cmd.iter + state := s_setup + } + } + + io.query_valid := state === s_setup + io.query_resp_ready := state === s_query_wait + io.query_vbank_id := wr_bank_reg + io.query_is_shared := is_shared_reg && io.query_valid + + when(state === s_setup && io.query_ready) { + state := s_query_wait + } + + when(state === s_query_wait && io.query_resp_valid) { + assert(io.query_group_count >= 1.U, "MemLoader groups must be >= 1") + group_count_reg := io.query_group_count + state := s_mul + } + + when(state === s_mul) { + iter_reg := iter_cmd * group_count_reg + state := s_dma_req + } + + // DMA req accepted + when(io.dmaReq.fire) { + state := s_dma_wait + resp_count := 0.U + } + + // Latch DMA beat into pending buffer + when(io.dmaResp.fire) { + pending := true.B + latData := io.dmaResp.bits.data + latLast := io.dmaResp.bits.last + } + + // When bankWrite request handshakes, consume pending beat + when(io.bankWrite.io.req.fire) { + pending := false.B + resp_count := resp_count + 1.U + + when(latLast) { + state := s_wait_write_resp + }.otherwise { + state := s_wait_write_resp + } + } + + // Wait for each write response before accepting the next DMA beat. + when(state === s_wait_write_resp && io.bankWrite.io.resp.fire) { + when(group_counter + 1.U < group_count_reg) { + group_counter := group_counter + 1.U + }.otherwise { + group_counter := 0.U + rowAddr := rowAddr + 1.U + } + state := Mux(latLast, s_done, s_dma_wait) + } + + when(state === s_done && io.cmdResp.fire) { + state := s_idle + } +} diff --git a/platforms/arty-a7-toy/patches/framework/MemMidend.scala b/platforms/arty-a7-toy/patches/framework/MemMidend.scala new file mode 100644 index 0000000..b62d850 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/MemMidend.scala @@ -0,0 +1,345 @@ +package framework.memdomain.midend + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.memdomain.backend.MemRequestIO + +// BankRead/BankWrite with is_shared flag, used for unified midend interface +class BankReadWithShared(val b: GlobalConfig) extends Bundle { + val bankRead = new BankRead(b) + val is_shared = Input(Bool()) +} + +class BankWriteWithShared(val b: GlobalConfig) extends Bundle { + val bankWrite = new BankWrite(b) + val is_shared = Input(Bool()) +} + +/** + * MemMidend: Midend module for memory scheduling + * Connects MemFrontend to MemManager + * + * Unified interface: bankRead/bankWrite Vecs include both balldomain and frontend requests. + * The last entry (index totalBallRead / totalBallWrite) is the frontend (DMA). + * All requests go through the same mapping table and channel allocation logic. + */ +@instantiable +class MemMidend(val b: GlobalConfig, fixedRoutes: Boolean = true) extends Module { + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + + // Total slots: balldomain entries + 1 frontend entry + val totalRead = totalBallRead + 1 + val totalWrite = totalBallWrite + 1 + + @public + val io = IO(new Bundle { + // Unified read/write interfaces: indices [0, totalBallRead) are balldomain, + // index totalBallRead is frontend (DMA). Same for write. + val bankRead = Vec(totalRead, new BankReadWithShared(b)) + val bankWrite = Vec(totalWrite, new BankWriteWithShared(b)) + val ballChannelActive = Input(Vec(b.ballDomain.ballNum, Bool())) + val ballChannelReady = Output(Vec(b.ballDomain.ballNum, Bool())) + + val hartid = Input(UInt(b.tile.xLen.W)) + val inst_ids = Input(Vec(b.frontend.rob_entries, UInt(64.W))) + + // Output to backend (MemManager) + val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + }) + + if (fixedRoutes && b.memDomain.bankNum == 8 && + b.ballDomain.ballNum == 1 && !b.memDomain.sharedEnable) { + require(totalBallRead == 2 && totalBallWrite == 4 && b.memDomain.bankChannel == 7) + require(b.ballDomain.ballIdMappings.head.ballName == "GemminiBall") + io.ballChannelReady(0) := io.ballChannelActive(0) + + for (channel <- 0 until 7) { + val request = io.mem_req(channel) + request.read.req.valid := false.B + request.read.req.bits := 0.U.asTypeOf(request.read.req.bits) + request.read.resp.ready := false.B + request.write.req.valid := false.B + request.write.req.bits := 0.U.asTypeOf(request.write.req.bits) + request.write.resp.ready := false.B + request.bank_id := 0.U + request.group_id := 0.U + request.is_shared := false.B + request.hart_id := io.hartid + request.rob_id := 0.U + request.inst_id := 0.U + } + for (port <- 0 until totalBallRead) { + val source = io.bankRead(port) + val request = io.mem_req(port) + request.read <> source.bankRead.io + request.read.req.valid := source.bankRead.io.req.valid && io.ballChannelActive(0) + source.bankRead.io.req.ready := request.read.req.ready && io.ballChannelActive(0) + request.bank_id := source.bankRead.bank_id + request.group_id := source.bankRead.group_id + request.rob_id := source.bankRead.rob_id + request.inst_id := io.inst_ids(source.bankRead.rob_id) + } + for (port <- 0 until totalBallWrite) { + val source = io.bankWrite(port) + val request = io.mem_req(totalBallRead + port) + request.write <> source.bankWrite.io + request.write.req.valid := source.bankWrite.io.req.valid && io.ballChannelActive(0) + source.bankWrite.io.req.ready := request.write.req.ready && io.ballChannelActive(0) + request.bank_id := source.bankWrite.bank_id + request.group_id := source.bankWrite.group_id + request.rob_id := source.bankWrite.rob_id + request.inst_id := io.inst_ids(source.bankWrite.rob_id) + } + + // The private backend captures its bank route BEFORE AccPipe accepts the + // SRAM request. Lock both direction and metadata from selection until the + // response is consumed; a new opposite-direction request must not replace + // the pending route during this one-cycle look-ahead. + val read = io.bankRead(totalBallRead).bankRead + val write = io.bankWrite(totalBallWrite).bankWrite + val dma = io.mem_req(6) + dma.read <> read.io + dma.write <> write.io + val pending = RegInit(false.B) + val accepted = RegInit(false.B) + val writeSelected = RegInit(false.B) + val bank = Reg(UInt(b.memDomain.vbankIdWidth.W)) + val group = Reg(UInt(b.memDomain.groupIdWidth.W)) + val rob = Reg(UInt(log2Up(b.frontend.rob_entries).W)) + when(!pending && (read.io.req.valid || write.io.req.valid)) { + pending := true.B + accepted := false.B + writeSelected := write.io.req.valid + bank := Mux(write.io.req.valid, write.bank_id, read.bank_id) + group := Mux(write.io.req.valid, write.group_id, read.group_id) + rob := Mux(write.io.req.valid, write.rob_id, read.rob_id) + } + dma.read.req.valid := pending && !accepted && !writeSelected && read.io.req.valid + dma.write.req.valid := pending && !accepted && writeSelected && write.io.req.valid + read.io.req.ready := pending && !accepted && !writeSelected && dma.read.req.ready + write.io.req.ready := pending && !accepted && writeSelected && dma.write.req.ready + when(dma.read.req.fire || dma.write.req.fire) { accepted := true.B } + when(dma.read.resp.fire || dma.write.resp.fire) { pending := false.B } + dma.bank_id := bank + dma.group_id := group + dma.rob_id := rob + dma.inst_id := io.inst_ids(dma.rob_id) + assert(!(dma.read.req.fire && dma.write.req.fire)) + } else { + // ----------------------------------------------------------------------------- + // Mapping table for tracking all requests (balldomain + frontend) + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val isRead = Bool() + val id = UInt(log2Ceil(math.max(totalRead, totalWrite)).W) + val isBall = Bool() + val ballId = UInt(log2Up(b.ballDomain.ballNum).W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(0.U.asTypeOf(new MappingTableEntry)))) + + // A route stays assigned until its Ball releases it (or a frontend channel + // drains), so maintain the reverse ownership at allocation time. This keeps + // readiness and pending detection from repeatedly scanning every backend + // channel for the same port. + val portSlots = math.max(totalRead, totalWrite) + val readPortAllocated = RegInit(VecInit(Seq.fill(portSlots)(false.B))) + val writePortAllocated = RegInit(VecInit(Seq.fill(portSlots)(false.B))) + + def isAllocated(isRead: Bool, id: UInt): Bool = + Mux(isRead, readPortAllocated(id), writePortAllocated(id)) + + val readPortBall = b.ballDomain.ballIdMappings.zipWithIndex.flatMap { case (mapping, ball) => + Seq.fill(mapping.inBW)(ball) + } + + val writePortBall = b.ballDomain.ballIdMappings.zipWithIndex.flatMap { case (mapping, ball) => + Seq.fill(mapping.outBW)(ball) + } + + for (ball <- 0 until b.ballDomain.ballNum) { + val readReady = readPortBall.zipWithIndex + .filter(_._1 == ball) + .map { case (_, port) => isAllocated(true.B, port.U) } + .foldLeft(true.B)(_ && _) + val writeReady = writePortBall.zipWithIndex + .filter(_._1 == ball) + .map { case (_, port) => isAllocated(false.B, port.U) } + .foldLeft(true.B)(_ && _) + io.ballChannelReady(ball) := io.ballChannelActive(ball) && readReady && writeReady + } + + // Allocate exactly one channel per cycle. Ball channels are allocated before + // their data traffic can start; frontend DMA channels are demand-allocated. + for (i <- 0 until totalRead) { + io.bankRead(i).bankRead.io.req.ready := false.B + io.bankRead(i).bankRead.io.resp.valid := false.B + io.bankRead(i).bankRead.io.resp.bits := DontCare + + } + + for (i <- 0 until totalWrite) { + io.bankWrite(i).bankWrite.io.req.ready := false.B + io.bankWrite(i).bankWrite.io.resp.valid := false.B + io.bankWrite(i).bankWrite.io.resp.bits := DontCare + } + + val pendingReads = VecInit((0 until totalRead).map { i => + val active = + if (i < totalBallRead) { + io.ballChannelActive(readPortBall(i)) + } else { + io.bankRead(i).bankRead.io.req.valid + } + active && !isAllocated(true.B, i.U) + }) + + val pendingWrites = VecInit((0 until totalWrite).map { i => + val active = + if (i < totalBallWrite) { + io.ballChannelActive(writePortBall(i)) + } else { + io.bankWrite(i).bankWrite.io.req.valid + } + active && !isAllocated(false.B, i.U) + }) + + val pending = VecInit(pendingReads ++ pendingWrites) + val freeChannels = mappingTable.map(entry => !entry.valid) + + when(pending.asUInt.orR && freeChannels.reduce(_ || _)) { + val channel = PriorityEncoder(freeChannels) + val port = PriorityEncoder(pending) + mappingTable(channel).valid := true.B + mappingTable(channel).isRead := port < totalRead.U + mappingTable(channel).id := Mux(port < totalRead.U, port, port - totalRead.U) + mappingTable(channel).isBall := Mux( + port < totalRead.U, + MuxLookup(port, false.B)((0 until totalBallRead).map(i => i.U -> true.B).toSeq), + MuxLookup(port - totalRead.U, false.B)((0 until totalBallWrite).map(i => i.U -> true.B).toSeq) + ) + mappingTable(channel).ballId := Mux( + port < totalRead.U, + MuxLookup(port, 0.U)(readPortBall.zipWithIndex.map { case (ball, i) => i.U -> ball.U }.toSeq), + MuxLookup(port - totalRead.U, 0.U)(writePortBall.zipWithIndex.map { case (ball, i) => i.U -> ball.U }.toSeq) + ) + + when(port < totalRead.U) { + readPortAllocated(port) := true.B + }.otherwise { + writePortAllocated(port - totalRead.U) := true.B + } + } + + // Connect mapped entries to backend channels + for (i <- 0 until b.memDomain.bankChannel) { + io.mem_req(i).read.req.valid := false.B + io.mem_req(i).read.req.bits := DontCare + io.mem_req(i).read.resp.ready := false.B + io.mem_req(i).write.req.valid := false.B + io.mem_req(i).write.req.bits := DontCare + io.mem_req(i).write.resp.ready := false.B + io.mem_req(i).bank_id := 0.U + io.mem_req(i).group_id := 0.U + io.mem_req(i).is_shared := false.B + io.mem_req(i).hart_id := io.hartid + io.mem_req(i).rob_id := 0.U + io.mem_req(i).inst_id := 0.U + + val isRead = mappingTable(i).isRead + val rid = mappingTable(i).id + val wid = mappingTable(i).id + val ballRead = io.bankRead(rid).bankRead.io + val ballWrite = io.bankWrite(wid).bankWrite.io + val rbank_id = io.bankRead(rid).bankRead.bank_id + val wbank_id = io.bankWrite(wid).bankWrite.bank_id + val rgroup_id = io.bankRead(rid).bankRead.group_id + val wgroup_id = io.bankWrite(wid).bankWrite.group_id + val r_shared = io.bankRead(rid).is_shared + val w_shared = io.bankWrite(wid).is_shared + val rrob_id = io.bankRead(rid).bankRead.rob_id + val wrob_id = io.bankWrite(wid).bankWrite.rob_id + // A released Ball cannot issue new traffic, but its final bank response + // still needs the existing route until the physical channel drains. + val ballRouteOpen = !mappingTable(i).isBall || + io.ballChannelReady(mappingTable(i).ballId) || + !io.ballChannelActive(mappingTable(i).ballId) + + when(mappingTable(i).valid) { + when(isRead) { + when(ballRouteOpen) { + io.mem_req(i).read <> ballRead + io.mem_req(i).bank_id := rbank_id + io.mem_req(i).group_id := rgroup_id + io.mem_req(i).is_shared := r_shared + io.mem_req(i).rob_id := rrob_id + io.mem_req(i).inst_id := io.inst_ids(rrob_id) + } + }.otherwise { + when(ballRouteOpen) { + io.mem_req(i).write <> ballWrite + io.mem_req(i).bank_id := wbank_id + io.mem_req(i).group_id := wgroup_id + io.mem_req(i).is_shared := w_shared + io.mem_req(i).rob_id := wrob_id + io.mem_req(i).inst_id := io.inst_ids(wrob_id) + } + } + } + } + + // Mapping table release + for (i <- 0 until b.memDomain.bankChannel) { + val releaseCounter = RegInit(0.U(5.W)) + + // Releasing a Ball's logical channel can precede the final bank response. + // Keep its physical route until that response has been consumed; otherwise + // the response loses its consumer and leaves the AccPipe busy. + val ballReleased = mappingTable(i).isBall && + !io.ballChannelActive(mappingTable(i).ballId) + val channelDrained = !(io.mem_req(i).read.resp.valid || + io.mem_req(i).write.resp.valid || io.mem_req(i).read.req.valid || + io.mem_req(i).write.req.valid) + + when(mappingTable(i).valid && ballReleased && channelDrained) { + mappingTable(i).valid := false.B + mappingTable(i).isRead := false.B + mappingTable(i).id := 0.U + mappingTable(i).isBall := false.B + mappingTable(i).ballId := 0.U + when(mappingTable(i).isRead) { + readPortAllocated(mappingTable(i).id) := false.B + }.otherwise { + writePortAllocated(mappingTable(i).id) := false.B + } + releaseCounter := 0.U + }.elsewhen(mappingTable(i).valid && !mappingTable(i).isBall && !(io.mem_req(i).read.resp.valid || + io.mem_req(i).write.resp.valid || io.mem_req(i).read.req.valid || + io.mem_req(i).write.req.valid)) { + releaseCounter := releaseCounter + 1.U + + when(releaseCounter === 16.U) { + releaseCounter := 0.U + mappingTable(i).valid := false.B + mappingTable(i).isRead := false.B + mappingTable(i).id := 0.U + mappingTable(i).isBall := false.B + mappingTable(i).ballId := 0.U + when(mappingTable(i).isRead) { + readPortAllocated(mappingTable(i).id) := false.B + }.otherwise { + writePortAllocated(mappingTable(i).id) := false.B + } + } + }.otherwise { + releaseCounter := 0.U + } + } + + } +} diff --git a/platforms/arty-a7-toy/patches/framework/MemStorer.scala b/platforms/arty-a7-toy/patches/framework/MemStorer.scala new file mode 100644 index 0000000..24af185 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/MemStorer.scala @@ -0,0 +1,271 @@ +package framework.memdomain.frontend.mem + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd.rs.{MemRsComplete, MemRsIssue} +import freechips.rocketchip.rocket.MStatus +import framework.memdomain.frontend.mem.dma.{BBWriteRequest, BBWriteResponse} +import framework.balldomain.blink.BankRead +import chisel3.experimental.hierarchy.{instantiable, public} + +@instantiable +class MemStorer(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) + + // One bank line bytes + private val line_bytes = b.memDomain.bankWidth / 8 + // Pack/send one bank-width aligned beat to DMA. + private val align_bytes = b.memDomain.dma_buswidth / 8 + require(align_bytes == line_bytes, "Bank and DMA beat widths must match") + require(isPow2(line_bytes), "MemStorer line_bytes must be power of 2") + private val lgLine = log2Ceil(line_bytes) + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) + val cmdResp = Decoupled(new MemRsComplete(b)) + + val dmaReq = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) + val dmaResp = Flipped(Decoupled(new BBWriteResponse)) + + val bankRead = Flipped(new BankRead(b)) + + val query_valid = Output(Bool()) + val query_ready = Input(Bool()) + val query_resp_valid = Input(Bool()) + val query_resp_ready = Output(Bool()) + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) + }) + + // ----------------------------- + // State + // ----------------------------- + val s_idle :: s_setup :: s_query :: s_query_wait :: s_mul :: s_issue_sram_req :: s_wait_sram_resp :: s_have_sram_beat :: s_push_dma :: s_wait_dma_resp :: s_done :: Nil = + Enum(11) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) + val rd_bank_reg = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val stride_reg = RegInit(1.U(19.W)) + val group_count_reg = RegInit(1.U(b.memDomain.groupCountWidth.W)) + val is_shared_reg = RegInit(false.B) + + val addr_counter = RegInit(0.U(b.frontend.iter_len.W)) + val group_counter = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val cursor = RegInit(0.U(b.memDomain.memAddrLen.W)) + val rowDelta = RegInit(0.U(b.memDomain.memAddrLen.W)) + + // ----------------------------- + // Pending buffer for SRAM resp + // ----------------------------- + val pending = RegInit(false.B) + val pendData = Reg(UInt(b.memDomain.bankWidth.W)) + val pendIsLast = RegInit(false.B) + + val split_valid = RegInit(false.B) + val split_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + val split_data = RegInit(0.U((align_bytes * 8).W)) + val split_mask = RegInit(0.U(align_bytes.W)) + + // Convenience + val target_bank = rd_bank_reg + + // ----------------------------- + // Cmd accept + // ----------------------------- + io.cmdReq.ready := (state === s_idle) + + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { + val strideIn = io.cmdReq.bits.cmd.special(57, 39) + assert(strideIn >= 1.U, "MemStorer stride must be >= 1") + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + rd_bank_reg := io.cmdReq.bits.cmd.bank_id + stride_reg := strideIn + iter_reg := io.cmdReq.bits.cmd.iter + is_shared_reg := io.cmdReq.bits.cmd.is_shared + + addr_counter := 0.U + group_counter := 0.U + cursor := io.cmdReq.bits.cmd.mem_addr + + pending := false.B + split_valid := false.B + split_addr := 0.U + split_data := 0.U + split_mask := 0.U + + state := s_setup + } + + io.query_valid := state === s_setup + io.query_resp_ready := state === s_query_wait + io.query_vbank_id := rd_bank_reg + io.query_is_shared := is_shared_reg && io.query_valid + + when(state === s_setup && io.query_ready) { + state := s_query_wait + } + + when(state === s_query_wait && io.query_resp_valid) { + assert(io.query_group_count >= 1.U, "MemStorer groups must be >= 1") + group_count_reg := io.query_group_count + state := s_mul + } + + when(state === s_mul) { + rowDelta := ((group_count_reg * (stride_reg - 1.U)) + 1.U) << lgLine + state := s_issue_sram_req + } + + // ----------------------------- + // SRAM read request + // ----------------------------- + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U + io.bankRead.group_id := group_counter(b.memDomain.groupIdWidth - 1, 0) + io.is_shared := is_shared_reg + + io.bankRead.io.req.valid := (state === s_issue_sram_req) + io.bankRead.io.req.bits.addr := addr_counter + + // SRAMBank read resp is a 1-cycle pulse, so we must ALWAYS be ready to take it, + // but only if we don't already hold a pending beat. + io.bankRead.io.resp.ready := !pending + + when(state === s_issue_sram_req) { + // Once request handshakes, wait for resp + when(io.bankRead.io.req.fire) { + state := s_wait_sram_resp + } + } + + // ----------------------------- + // Latch SRAM resp into pending (never drop it) + // ----------------------------- + val bank_resp_fire = io.bankRead.io.resp.fire + when(bank_resp_fire) { + pending := true.B + pendData := io.bankRead.io.resp.bits.data + // Last beat: last row and last group + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + pendIsLast := is_last_row && is_last_group && (iter_reg =/= 0.U) + state := s_have_sram_beat + } + + val addr_offset = cursor(log2Ceil(align_bytes) - 1, 0) + + val aligned_addr = Cat( + cursor(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), + 0.U(log2Ceil(align_bytes).W) + ) + + val incoming_data = pendData + val first_bytes = align_bytes.U - addr_offset + val first_mask = (~0.U(align_bytes.W)) << addr_offset + val second_mask = (1.U(align_bytes.W) << addr_offset) - 1.U + + // ----------------------------- + // DMA request (Decoupled correct): hold valid until fire + // ----------------------------- + val dma_v = RegInit(false.B) + val dma_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + val dma_data = RegInit(0.U((align_bytes * 8).W)) + val dma_mask = RegInit(0.U(align_bytes.W)) + + io.dmaReq.valid := dma_v + io.dmaReq.bits.vaddr := dma_addr + io.dmaReq.bits.data := dma_data + io.dmaReq.bits.len := align_bytes.U + io.dmaReq.bits.mask := dma_mask + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + + io.dmaResp.ready := state === s_wait_dma_resp + + // When we have a pending SRAM beat, prepare one DMA beat (and keep it until fire) + when(state === s_have_sram_beat) { + // Only arm dma_v if not already armed + when(!dma_v) { + dma_v := true.B + dma_addr := aligned_addr + dma_data := Mux(addr_offset === 0.U, incoming_data, incoming_data << (addr_offset * 8.U)) + dma_mask := Mux(addr_offset === 0.U, ~0.U(align_bytes.W), first_mask) + split_valid := addr_offset =/= 0.U + split_addr := aligned_addr + align_bytes.U + split_data := incoming_data >> (first_bytes * 8.U) + split_mask := second_mask + state := s_push_dma + } + } + + // When DMA accepts the beat, consume pending and move forward + when(state === s_push_dma) { + when(io.dmaReq.fire) { + dma_v := false.B + state := s_wait_dma_resp + } + } + + when(state === s_wait_dma_resp && io.dmaResp.fire) { + when(split_valid) { + dma_v := true.B + dma_addr := split_addr + dma_data := split_data + dma_mask := split_mask + split_valid := false.B + state := s_push_dma + }.otherwise { + pending := false.B + + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + val all_done = is_last_row && is_last_group && (iter_reg =/= 0.U) + + when(iter_reg =/= 0.U) { + when(group_counter + 1.U < group_count_reg) { + group_counter := group_counter + 1.U + cursor := cursor + line_bytes.U + }.otherwise { + group_counter := 0.U + addr_counter := addr_counter + 1.U + cursor := cursor + rowDelta + } + } + + when(pendIsLast || iter_reg === 0.U || all_done) { + state := s_done + }.otherwise { + state := s_issue_sram_req + } + } + } + + // If we are waiting for SRAM resp (but resp will pulse), just stay here + when(state === s_wait_sram_resp) { + // nothing; latch happens in bank_resp_fire block above + } + + // ----------------------------- + // Completion + // ----------------------------- + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg + + when(io.cmdResp.fire) { + state := s_idle + } +} diff --git a/platforms/arty-a7-toy/patches/framework/PrivateMemBackend.scala b/platforms/arty-a7-toy/patches/framework/PrivateMemBackend.scala new file mode 100644 index 0000000..edce8b1 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/PrivateMemBackend.scala @@ -0,0 +1,422 @@ +package framework.memdomain.backend.privatepath + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.memdomain.frontend.mem.MemConfigerIO +import framework.memdomain.backend.{MTraceDPI, MemRequestIO} +import sims.hash.BankHashMonitor +import framework.memdomain.backend.accpipe.AccPipe +import framework.memdomain.backend.banks.SramBank +import framework.memdomain.backend.banks.btrace.PhysicalBankHash +import framework.top.GlobalConfig + +@instantiable +class PrivateMemBackend(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val config = Flipped(Decoupled(new MemConfigerIO(b))) + + // Query interface for frontend to get group count + val query_vbank_id = Input(UInt(b.memDomain.vbankIdWidth.W)) + val query_group_count = Output(UInt(b.memDomain.groupCountWidth.W)) + val bank_hashes = if (b.sim.diffTest) Some(Output(Vec(b.memDomain.bankNum, new PhysicalBankHash(b)))) else None + }) + + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + + val hashMonitors = + if (b.sim.diffTest) { + Some(Seq.fill(b.memDomain.bankNum)(Instantiate(new BankHashMonitor(b)))) + } else { + None + } + + // Per-channel memory trace DPI-C modules to avoid losing simultaneous events + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + for (mt <- mtraces) { + mt.io.clock := clock + mt.io.reset := reset.asBool + mt.io.is_write := 0.U + mt.io.is_shared := 0.U + mt.io.channel := 0.U + mt.io.hart_id := 0.U + mt.io.rob_id := 0.U + mt.io.inst_id := 0.U + mt.io.vbank_id := 0.U + mt.io.pbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.write_mask := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B + } + + // ----------------------------------------------------------------------------- + // Mapping table + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val hart_id = UInt(b.tile.xLen.W) + val vbank_id = UInt(b.memDomain.vbankIdWidth.W) + val is_multi = Bool() + val group_id = UInt(b.memDomain.groupIdWidth.W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) + // The frontend contract reserves [0, vbank_id_upper_bound] for private + // banks. Keep the direct route table at that architectural size. + private val privateVbankCount = b.frontend.vbank_id_upper_bound + 1 + require( + privateVbankCount > 0 && privateVbankCount <= b.memDomain.virtualBankCount, + s"private vbank table size ($privateVbankCount) exceeds virtualBankCount(${b.memDomain.virtualBankCount})" + ) + private val groupIndexWidth = log2Up(b.memDomain.bankNum) + private val pbankIndexWidth = log2Up(b.memDomain.bankNum) + private val privateVbankIdWidth = log2Up(privateVbankCount) + + // A non-multi vbank has exactly one route, so keep that common case as a + // small indexed table. Multi-bank mappings retain their per-group entries + // in mappingTable and use the fallback scan below. This avoids the much + // larger 32x24 valid+pbank register matrix while still removing the full + // mapping scan from the overwhelmingly common single-bank path. + val singleRouteValid = RegInit(VecInit(Seq.fill(privateVbankCount)(false.B))) + + val singleRoutePbank = RegInit( + VecInit(Seq.fill(privateVbankCount)(0.U(pbankIndexWidth.W))) + ) + + // The private namespace is bounded by the frontend contract, while + // multi-bank groups remain represented individually in mappingTable. + val groupCountByVbank = RegInit( + VecInit(Seq.fill(privateVbankCount)(0.U(b.memDomain.groupCountWidth.W))) + ) + + def addEntry( + hart_id: UInt, + vbank_id: UInt, + pbank_id: UInt, + is_multi: Bool, + group_id: UInt + ): Unit = { + val entry = mappingTable(pbank_id) + entry.valid := true.B + entry.hart_id := hart_id + entry.vbank_id := vbank_id + entry.is_multi := is_multi + entry.group_id := group_id + } + + def deleteEntry(vbank_id: UInt): Unit = { + for (i <- 0 until b.memDomain.bankNum) { + when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id) { + mappingTable(i).valid := false.B + } + } + } + + // ----------------------------------------------------------------------------- + // Default Value + // ----------------------------------------------------------------------------- + + for (i <- 0 until b.memDomain.bankChannel) { + accPipes(i).io.mem_req.write <> io.mem_req(i).write + accPipes(i).io.mem_req.read <> io.mem_req(i).read + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared + accPipes(i).io.mem_req.hart_id := io.mem_req(i).hart_id + accPipes(i).io.mem_req.rob_id := io.mem_req(i).rob_id + accPipes(i).io.mem_req.inst_id := io.mem_req(i).inst_id + + // Bank-side defaults (only driven when a bank is actually connected) + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare + + accPipes(i).io.sramWrite.req.ready := false.B + accPipes(i).io.sramWrite.resp.valid := false.B + accPipes(i).io.sramWrite.resp.bits := DontCare + + accPipes(i).io.is_multi := false.B + } + + banks.zipWithIndex.foreach { + case (bank, _) => + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := DontCare + bank.io.sramRead.resp.ready := true.B + + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := DontCare + bank.io.sramWrite.resp.ready := true.B + } + + val realloc = io.config.bits.group_id === 0.U + val freePbankMask = + VecInit(mappingTable.map(entry => !entry.valid || (realloc && entry.vbank_id === io.config.bits.vbank_id))) + val hasFreePbank = freePbankMask.asUInt.orR + io.config.ready := !io.config.bits.alloc || hasFreePbank + when(io.config.valid && io.config.bits.alloc && !hasFreePbank) { + assert(false.B, "PrivateMemBackend allocation failed: no free physical bank\n") + } + + // ----------------------------------------------------------------------------- + // Bank Alloc/Release + // ----------------------------------------------------------------------------- + + hashMonitors.foreach(_.foreach(_.io.bind := false.B)) + + when(io.config.fire) { + val vbank = io.config.bits.vbank_id + val vbankIdx = vbank(privateVbankIdWidth - 1, 0) + when(io.config.bits.alloc) { + val freePbank = PriorityEncoder(freePbankMask) + hashMonitors.foreach { hashes => + for (i <- 0 until b.memDomain.bankNum) { + hashes(i).io.bind := freePbank === i.U + } + } + // Match bemu mset: realloc of the same vbank frees prior physical banks first. + // MemConfiger emits one fire per group; only group 0 drops the old mapping. + when(io.config.bits.group_id === 0.U) { + deleteEntry(io.config.bits.vbank_id) + singleRouteValid(vbankIdx) := false.B + } + addEntry( + io.config.bits.hart_id, + io.config.bits.vbank_id, + freePbank, + io.config.bits.is_multi, + io.config.bits.group_id + ) + when(!io.config.bits.is_multi) { + singleRoutePbank(vbankIdx) := freePbank + singleRouteValid(vbankIdx) := true.B + } + groupCountByVbank(vbankIdx) := Mux(io.config.bits.is_multi, io.config.bits.group_id +& 1.U, 1.U) + }.otherwise { + deleteEntry(io.config.bits.vbank_id) + singleRouteValid(vbankIdx) := false.B + groupCountByVbank(vbankIdx) := 0.U + } + } + + // ----------------------------------------------------------------------------- + // Query interface: return group count for a given vbank_id + // ----------------------------------------------------------------------------- + val queryVbankId = RegNext(io.query_vbank_id, 0.U) + val queryVbank = queryVbankId(privateVbankIdWidth - 1, 0) + io.query_group_count := RegNext(groupCountByVbank(queryVbank), 0.U) + + // ----------------------------------------------------------------------------- + // Connect AccPipe and Banks + // ----------------------------------------------------------------------------- + private def emitTrace( + ch: Int, + isWrite: UInt, + pbankId: UInt, + addr: UInt, + writeMask: UInt, + dataLo: UInt, + dataHi: UInt, + en: Bool + ): Unit = { + mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt + mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id + mtraces(ch).io.rob_id := io.mem_req(ch).rob_id + mtraces(ch).io.inst_id := io.mem_req(ch).inst_id + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.pbank_id := pbankId + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.write_mask := writeMask + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en + } + + // The route is held for the complete AccPipe transaction. Keep the route + // vectors in one place so the bank-side command mux and response demux share + // exactly the same ownership predicate. + val activeRouteOHs = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.bankNum.W))) + val channelReqValid = Seq.fill(b.memDomain.bankChannel)(Wire(Bool())) + val channelReqIsWrite = Seq.fill(b.memDomain.bankChannel)(Wire(Bool())) + val channelReqAddr = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(log2Ceil(b.memDomain.bankEntries).W))) + val channelReqData = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.bankWidth.W))) + val channelReqMask = Seq.fill(b.memDomain.bankChannel)(Wire(Vec(b.memDomain.bankMaskLen, Bool()))) + val channelHartId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.tile.xLen.W))) + val channelInstId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(64.W))) + val channelVbankId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.vbankIdWidth.W))) + val channelGroupId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.groupIdWidth.W))) + + for (i <- 0 until b.memDomain.bankChannel) { + val routePbankReg = RegInit(0.U(pbankIndexWidth.W)) + val routeValidReg = RegInit(false.B) + val routePending = RegInit(false.B) + val requestVbank = io.mem_req(i).bank_id + val requestVbankIdx = requestVbank(privateVbankIdWidth - 1, 0) + val requestGroup = io.mem_req(i).group_id(groupIndexWidth - 1, 0) + val singleRoute = singleRoutePbank(requestVbankIdx) + val singleValid = singleRouteValid(requestVbankIdx) + val multiRouteMatch = VecInit(mappingTable.map(entry => + entry.valid && entry.is_multi && + entry.vbank_id === requestVbank && entry.group_id === requestGroup + )) + val multiRoute = PriorityEncoder(multiRouteMatch) + val multiValid = multiRouteMatch.asUInt.orR + val requestRoute = Mux(singleValid, singleRoute, multiRoute) + val requestRouteValid = singleValid || multiValid + // Route lookup is deliberately one cycle ahead of the SRAM request. The + // route is captured while the AccPipe is idle, then held through the + // entire request/response lifetime. This removes the live mapping-table + // lookup from every wide bank-side mux select while preserving one request + // per channel per cycle once the pipe is running. + val requestSeen = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + val activeRoute = routePbankReg + val requestActive = routePending || accPipes(i).io.busy + val activeRouteValid = routeValidReg && requestActive + val activeRouteOH = UIntToOH(activeRoute, b.memDomain.bankNum) & + Fill(b.memDomain.bankNum, activeRouteValid) + + activeRouteOHs(i) := activeRouteOH + channelReqValid(i) := accPipes(i).io.sramRead.req.valid || + accPipes(i).io.sramWrite.req.valid + channelReqIsWrite(i) := accPipes(i).io.sramWrite.req.valid + channelReqAddr(i) := Mux( + channelReqIsWrite(i), + accPipes(i).io.sramWrite.req.bits.addr, + accPipes(i).io.sramRead.req.bits.addr + ) + channelReqData(i) := accPipes(i).io.sramWrite.req.bits.data + channelReqMask(i) := accPipes(i).io.sramWrite.req.bits.mask + channelHartId(i) := io.mem_req(i).hart_id + channelInstId(i) := io.mem_req(i).inst_id + channelVbankId(i) := io.mem_req(i).bank_id + channelGroupId(i) := io.mem_req(i).group_id + + // SramBank is a pure single-port SRAM: the selected operation is always + // accepted when its route is active. Using the held route directly avoids + // feeding 24 bank-ready signals back through every channel. + accPipes(i).io.sramRead.req.ready := activeRouteValid + accPipes(i).io.sramWrite.req.ready := activeRouteValid + + when(!routePending && !accPipes(i).io.busy && requestSeen && requestRouteValid) { + routePbankReg := requestRoute + routeValidReg := true.B + routePending := true.B + } + when(io.mem_req(i).read.req.fire || io.mem_req(i).write.req.fire) { + routePending := false.B + } + + // Requests are attributed once the selected SRAM accepts them. + when(accPipes(i).io.sramRead.req.fire) { + emitTrace(i, 0.U, activeRoute, accPipes(i).io.sramRead.req.bits.addr, 0.U, 0.U, 0.U, true.B) + } + + // Arrival trace: the write has crossed arbitration and is accepted by the + // selected SPM SRAM port. Keep attribution metadata from the same AccPipe + // transaction and data from the bank-side request. + when(accPipes(i).io.sramWrite.req.fire) { + emitTrace( + i, + 1.U, + activeRoute, + accPipes(i).io.sramWrite.req.bits.addr, + accPipes(i).io.sramWrite.req.bits.mask.asUInt, + accPipes(i).io.sramWrite.req.bits.data.pad(128)(63, 0), + accPipes(i).io.sramWrite.req.bits.data.pad(128)(127, 64), + true.B + ) + } + + } + + // Bank-side command crossbar. A physical bank is single-port, so both read + // and write requests share one selected channel/address path. The operation + // type then gates the corresponding SRAM request valid. + for (j <- 0 until b.memDomain.bankNum) { + val selectedReq = VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && channelReqValid(i) + }).asUInt + val selectedReqValid = selectedReq.orR + // The scheduler guarantees one live owner per physical bank. Express the + // one-hot selection as AND/OR wiring instead of a priority mux tree; this + // keeps the wide address/data path shallow and lets synthesis share the + // route gates across fields. + def oneHotOr(width: Int, values: Seq[UInt]): UInt = + values.zipWithIndex + .map { case (value, i) => Fill(width, selectedReq(i)) & value } + .reduce(_ | _) + + val selectedReqIsWrite = oneHotOr(1, channelReqIsWrite).asBool + val selectedReqAddr = oneHotOr(log2Ceil(b.memDomain.bankEntries), channelReqAddr) + val selectedReqData = oneHotOr(b.memDomain.bankWidth, channelReqData) + val selectedReqMask = VecInit((0 until b.memDomain.bankMaskLen).map { k => + oneHotOr(1, channelReqMask.map(_(k))).asBool + }) + val selectedHartId = oneHotOr(b.tile.xLen, channelHartId) + val selectedInstId = oneHotOr(64, channelInstId) + val selectedVbankId = oneHotOr(b.memDomain.vbankIdWidth, channelVbankId) + val selectedGroupId = oneHotOr(b.memDomain.groupIdWidth, channelGroupId) + + banks(j).io.sramRead.req.valid := selectedReqValid && !selectedReqIsWrite + banks(j).io.sramRead.req.bits.addr := selectedReqAddr + banks(j).io.sramWrite.req.valid := selectedReqValid && selectedReqIsWrite + banks(j).io.sramWrite.req.bits.addr := selectedReqAddr + banks(j).io.sramWrite.req.bits.data := selectedReqData + banks(j).io.sramWrite.req.bits.mask := selectedReqMask + + hashMonitors.foreach { hashes => + val monitor = hashes(j) + monitor.io.write.valid := banks(j).io.sramWrite.req.fire + monitor.io.write.bits.addr := selectedReqAddr + monitor.io.write.bits.mask := selectedReqMask + monitor.io.write.bits.data := selectedReqData + } + + // Only the channel holding this bank can consume its one-cycle response. + banks(j).io.sramRead.resp.ready := VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && accPipes(i).io.sramRead.resp.ready + }).asUInt.orR + banks(j).io.sramWrite.resp.ready := VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && accPipes(i).io.sramWrite.resp.ready + }).asUInt.orR + } + + // Response demux. Read data remains the only wide bank-to-channel mux; the + // request side above shares its address/data path between read and write. + for (i <- 0 until b.memDomain.bankChannel) { + val readRespSel = VecInit((0 until b.memDomain.bankNum).map { j => + activeRouteOHs(i)(j) && banks(j).io.sramRead.resp.valid + }).asUInt + val writeRespSel = VecInit((0 until b.memDomain.bankNum).map { j => + activeRouteOHs(i)(j) && banks(j).io.sramWrite.resp.valid + }).asUInt + + accPipes(i).io.sramRead.resp.valid := readRespSel.orR + accPipes(i).io.sramRead.resp.bits.data := (0 until b.memDomain.bankNum).map { j => + Fill(b.memDomain.bankWidth, activeRouteOHs(i)(j)) & banks(j).io.sramRead.resp.bits.data + }.reduce(_ | _) + accPipes(i).io.sramWrite.resp.valid := writeRespSel.orR + accPipes(i).io.sramWrite.resp.bits.ok := writeRespSel.orR + } + + io.bank_hashes.foreach { states => + for (i <- 0 until b.memDomain.bankNum) { + states(i).valid := mappingTable(i).valid + states(i).hartId := mappingTable(i).hart_id + states(i).vbankId := mappingTable(i).vbank_id + states(i).pbankId := i.U + states(i).groupId := mappingTable(i).group_id + states(i).statusHash := hashMonitors.get(i).io.statusHash + } + } +} diff --git a/platforms/arty-a7-toy/patches/framework/SubROB.scala b/platforms/arty-a7-toy/patches/framework/SubROB.scala new file mode 100644 index 0000000..178b870 --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/SubROB.scala @@ -0,0 +1,200 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.blink.SubRobRow +import framework.frontend.decoder.PostGDCmd + +@instantiable +class SubROB(val b: GlobalConfig) extends Module { + val subRobDepth = b.frontend.sub_rob_depth + val subIdBits = log2Up(subRobDepth * 4) + val robIdBits = log2Up(b.frontend.rob_entries) + val ballIdBits = log2Up(b.ballDomain.ballNum) + val rowIdBits = log2Up(subRobDepth) + + @public + val io = IO(new Bundle { + // Ball → SubROB: write a row of sub-instructions + val write = Flipped(Decoupled(new SubRobRow(b))) + // SubROB → GlobalRS: issue one slot at a time (PostGDCmd, domain_id determines target) + val issue = Decoupled(new PostGDCmd(b)) + val issueSubId = Output(UInt(subIdBits.W)) + val issueMasterRobId = Output(UInt(robIdBits.W)) + // GlobalRS → SubROB: a sub-instruction completed (sub_rob_id) + val subComplete = Flipped(Decoupled(UInt(subIdBits.W))) + // SubROB → main ROB: all sub-instructions done + val masterComplete = Decoupled(UInt(robIdBits.W)) + // Status + val occupied = Output(Bool()) + val lockedBallId = Output(UInt(ballIdBits.W)) + }) + + // ------------------------------------------------------------------------- + // Storage + // ------------------------------------------------------------------------- + val sram = SyncReadMem(subRobDepth, new SubRobRow(b)) + + val writePtr = RegInit(0.U(rowIdBits.W)) + val readPtr = RegInit(0.U(rowIdBits.W)) + val rowCount = RegInit(0.U((log2Up(subRobDepth) + 1).W)) + val lockedBallId = RegInit(0.U(ballIdBits.W)) + val masterRobId = RegInit(0.U(robIdBits.W)) + + def nextPtr(p: UInt): UInt = Mux(p === (subRobDepth - 1).U, 0.U, p + 1.U) + + val occupied = rowCount > 0.U + val isFull = rowCount === subRobDepth.U + val ballMatch = !occupied || (io.write.bits.ball_id === lockedBallId) + + // Write path: accept if not full AND ball_id matches (or not occupied yet) + io.write.ready := !isFull && ballMatch + + when(io.write.fire) { + when(occupied) { + assert(io.write.bits.master_rob_id === masterRobId, "SubROB row master_rob_id mismatch") + } + sram.write(writePtr, io.write.bits) + writePtr := nextPtr(writePtr) + when(!occupied) { + lockedBallId := io.write.bits.ball_id + masterRobId := io.write.bits.master_rob_id + } + } + + // ------------------------------------------------------------------------- + // FSM + // ------------------------------------------------------------------------- + // States: + // sIdle - nothing to do (rowCount == 0) + // sReadReq - issue SRAM read request for readPtr row + // sReadWait - wait 1 cycle for sramRaw to be latched into sramData + // sReadResp - sramData valid; dispatch valid slots one per cycle + // sWaitSlots - all slots issued; wait for all subCompletes + // sWaitMaster - all rows done; fire masterComplete then return to sIdle + val sIdle :: sReadReq :: sReadWait :: sReadResp :: sWaitSlots :: sWaitMaster :: Nil = Enum(6) + val state = RegInit(sIdle) + + // SyncReadMem: read issued in sReadReq (cycle N), data valid on cycle N+1. + // We latch it into sramData with RegEnable so it stays stable during sReadResp + // and sWaitSlots, even when the read port is not enabled. + val sramReadEn = state === sReadReq + val sramRaw = sram.read(readPtr, sramReadEn) + val dataFresh = RegNext(sramReadEn, false.B) // pulse on first cycle of sReadResp + val sramData = RegEnable(sramRaw, dataFresh) + val readPtrReg = RegEnable(readPtr, sramReadEn) + + // Per-row tracking registers (reset when moving to next row) + // slotIssued: have we already sent this slot to a domain? + // slotDone: have we received subComplete for this slot? + val slotIssued = RegInit(VecInit(Seq.fill(4)(false.B))) + val slotDone = RegInit(VecInit(Seq.fill(4)(false.B))) + + // Combinational: which slots still need to be issued? + val slotNeedsIssue = VecInit((0 until 4).map(i => sramData.slots(i).valid && !slotIssued(i))) + val hasSlotToIssue = slotNeedsIssue.asUInt.orR + val firstSlotIdx = PriorityEncoder(slotNeedsIssue.asUInt) + + // Combinational: are all valid slots done? + val allSlotsDone = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR + + // Issue output (valid only in sReadResp when there's a slot to issue) + io.issue.valid := (state === sReadResp) && hasSlotToIssue + io.issue.bits := sramData.slots(firstSlotIdx).cmd + io.issueSubId := readPtrReg * 4.U + firstSlotIdx + io.issueMasterRobId := masterRobId + + // subComplete: always ready, mark the corresponding slot done + io.subComplete.ready := true.B + when(io.subComplete.fire) { + val subId = io.subComplete.bits + val subRow = subId / 4.U + val slotIdx = subId(1, 0) + assert( + state === sReadResp || state === sWaitSlots || state === sWaitMaster, + "SubROB subComplete arrived in invalid state" + ) + assert(subRow === readPtrReg, "SubROB subComplete points to non-active row") + slotDone(slotIdx) := true.B + } + + // masterComplete + io.masterComplete.valid := state === sWaitMaster + io.masterComplete.bits := masterRobId + + // Status outputs + io.occupied := occupied + io.lockedBallId := lockedBallId + + // ------------------------------------------------------------------------- + // FSM transitions + // ------------------------------------------------------------------------- + // Helper: advance past current row (called when row is complete) + val retireRow = WireDefault(false.B) + def advanceRow(): Unit = { + readPtr := nextPtr(readPtr) + retireRow := true.B + slotIssued.foreach(_ := false.B) + slotDone.foreach(_ := false.B) + } + + switch(state) { + is(sIdle) { + when(occupied)(state := sReadReq) + } + is(sReadReq) { + // SRAM read issued, data available on sramRaw next cycle + state := sReadWait + } + is(sReadWait) { + // sramRaw is valid; RegEnable latches it into sramData at this clock edge. + // sramData will be stable starting next cycle (sReadResp). + state := sReadResp + } + is(sReadResp) { + // Fire issued slot + when(io.issue.fire) { + slotIssued(firstSlotIdx) := true.B + } + // Check if all slots have been issued + // After marking current slot issued, recalculate + val allIssued = VecInit((0 until 4).map(i => + !sramData.slots(i).valid || slotIssued(i) || + (io.issue.fire && firstSlotIdx === i.U) + )).asUInt.andR + + when(allIssued) { + // Check fast path: all already done (e.g., empty row or immediate completion) + val allDoneNow = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR + when(allDoneNow) { + // Fast path: skip sWaitSlots + advanceRow() + state := Mux(rowCount === 1.U && !io.write.fire, sWaitMaster, sReadReq) + }.otherwise { + state := sWaitSlots + } + } + // else: stay in sReadResp to dispatch remaining slots + } + is(sWaitSlots) { + when(allSlotsDone) { + advanceRow() + state := Mux(rowCount === 1.U && !io.write.fire, sWaitMaster, sReadReq) + } + } + is(sWaitMaster) { + when(io.masterComplete.fire) { + lockedBallId := 0.U + masterRobId := 0.U + state := sIdle + } + } + } + + // A simultaneous row write and retirement leave occupancy unchanged. + when(io.write.fire =/= retireRow) { + rowCount := Mux(io.write.fire, rowCount + 1.U, rowCount - 1.U) + } +} diff --git a/platforms/arty-a7-toy/patches/gemmini/FpgaArithmetic.scala b/platforms/arty-a7-toy/patches/gemmini/FpgaArithmetic.scala new file mode 100644 index 0000000..e5d389d --- /dev/null +++ b/platforms/arty-a7-toy/patches/gemmini/FpgaArithmetic.scala @@ -0,0 +1,40 @@ +package gemmini + +import chisel3._ +import chisel3.util._ + +/** Signed round-to-nearest-even. Two low bits carry guard and sticky state. */ +object FpgaRoundShift { + def apply(value: SInt, amount: UInt): SInt = { + require(Set(20, 32)(value.getWidth) && amount.getWidth == 5) + val width = value.getWidth + 2 + var stage = Cat(value.asUInt, 0.U(2.W)) + for (bit <- 0 until amount.getWidth) { + val distance = 1 << bit + val shifted = (stage.asSInt >> distance).pad(width).asUInt + val jammed = Cat(shifted(width - 1, 1), shifted(0) || stage(distance - 1, 0).orR) + stage = Mux(amount(bit), jammed, stage) + } + val integer = stage(width - 1, 2).asSInt + val increment = stage(1) && (stage(0) || stage(2)) + // Rounding a right shift cannot overflow the original signed input range. + (integer + Mux(increment, 1.S(value.getWidth.W), 0.S(value.getWidth.W))).asSInt + } +} + +/** No added registers: preserves the original PE cycle interface. */ +class FpgaDspMac extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { + val a = Input(UInt(8.W)) + val b = Input(UInt(8.W)) + val c = Input(UInt(20.W)) + val y = Output(UInt(20.W)) + }) + setInline("FpgaDspMac.v", """ +module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + (* use_dsp = "yes" *) wire signed [19:0] result; + assign result = $signed(a) * $signed(b) + $signed(c); + assign y = result; +endmodule +""") +} diff --git a/platforms/arty-a7-toy/patches/gemmini/LICENSE b/platforms/arty-a7-toy/patches/gemmini/LICENSE new file mode 100644 index 0000000..17824de --- /dev/null +++ b/platforms/arty-a7-toy/patches/gemmini/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2018-2019, The Regents of the University of California +(Regents). All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/platforms/arty-a7-toy/patches/gemmini/Mesh.scala b/platforms/arty-a7-toy/patches/gemmini/Mesh.scala new file mode 100644 index 0000000..51c4950 --- /dev/null +++ b/platforms/arty-a7-toy/patches/gemmini/Mesh.scala @@ -0,0 +1,134 @@ + +package gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ + +/** + * A Grid is a 2D array of Tile modules with registers in between each tile and + * registers from the bottom row and rightmost column of tiles to the Grid outputs. + * @param width + * @param tileRows + * @param tileColumns + * @param meshRows + * @param meshColumns + */ +class Mesh[T <: Data : Arithmetic](inputType: T, weightType: T, outputType: T, accType: T, + df: Dataflow.Value, tree_reduction: Boolean, tile_latency: Int, + max_simultaneous_matmuls: Int, output_delay: Int, + val tileRows: Int, val tileColumns: Int, + val meshRows: Int, val meshColumns: Int) extends Module { + val io = IO(new Bundle { + val in_a = Input(Vec(meshRows, Vec(tileRows, inputType))) + val in_b = Input(Vec(meshColumns, Vec(tileColumns, weightType))) + val in_d = Input(Vec(meshColumns, Vec(tileColumns, weightType))) // TODO should this be weightType, inputType, or something like max(inputType, weightType)? + val in_control = Input(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) + val in_id = Input(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) // The unique id of this particular matmul + val in_last = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_b = Output(Vec(meshColumns, Vec(tileColumns, outputType))) + val out_c = Output(Vec(meshColumns, Vec(tileColumns, outputType))) + val in_valid = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_valid = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_control = Output(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) + val out_id = Output(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) + val out_last = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) + }) + + // mesh(r)(c) => Tile at row r, column c + val mesh: Seq[Seq[Tile[T]]] = Seq.tabulate(meshRows, meshColumns) { (r, c) => + // Use one DSP MAC per PE in this 8x8 FPGA profile; retain OS/WS timing. + Module(new Tile(inputType, weightType, outputType, accType, df, + tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns, + fpgaDsp = true)) + } + val meshT = mesh.transpose + + def pipe[T <: Data](valid: Bool, t: T, latency: Int): T = { + // The default "Pipe" function apparently resets the valid signals to false.B. We would like to avoid using global + // signals in the Mesh, so over here, we make it clear that the reset signal will never be asserted + chisel3.withReset(false.B) { Pipe(valid, t, latency).bits } + } + + // Chain tile_a_out -> tile_a_in (pipeline a across each row) + // TODO clock-gate A signals with in_garbage + for (r <- 0 until meshRows) { + mesh(r).foldLeft(io.in_a(r)) { + case (in_a, tile) => + tile.io.in_a := ShiftRegister(in_a, tile_latency+1) + tile.io.out_a + } + } + + // Chain tile_out_b -> tile_b_in (pipeline b across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_b(c), io.in_valid(c))) { + case ((in_b, valid), tile) => + tile.io.in_b := pipe(valid.head, in_b, tile_latency+1) + (tile.io.out_b, tile.io.out_valid) + } + } + + // Chain tile_out -> tile_propag (pipeline output across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_d(c), io.in_valid(c))) { + case ((in_propag, valid), tile) => + tile.io.in_d := pipe(valid.head, in_propag, tile_latency+1) + (tile.io.out_c, tile.io.out_valid) + } + } + + // Chain control signals (pipeline across each column) + assert(!(mesh.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_))) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_control(c), io.in_valid(c))) { + case ((in_ctrl, valid), tile) => + (tile.io.in_control, in_ctrl, valid).zipped.foreach { case (tile_ctrl, ctrl, v) => + tile_ctrl.shift := pipe(v, ctrl.shift, tile_latency+1) + tile_ctrl.dataflow := pipe(v, ctrl.dataflow, tile_latency+1) + tile_ctrl.propagate := pipe(v, ctrl.propagate, tile_latency+1) + } + (tile.io.out_control, tile.io.out_valid) + } + } + + // Chain in_valid (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_valid(c)) { + case (in_v, tile) => + tile.io.in_valid := ShiftRegister(in_v, tile_latency+1) + tile.io.out_valid + } + } + + // Chain in_id (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_id(c)) { + case (in_id, tile) => + tile.io.in_id := ShiftRegister(in_id, tile_latency+1) + tile.io.out_id + } + } + + // Chain in_last (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_last(c)) { + case (in_last, tile) => + tile.io.in_last := ShiftRegister(in_last, tile_latency+1) + tile.io.out_last + } + } + + // Capture out_vec and out_control_vec (connect IO to bottom row of mesh) + // (The only reason we have so many zips is because Scala doesn't provide a zipped function for Tuple4) + for (((((((b, c), v), ctrl), id), last), tile) <- io.out_b zip io.out_c zip io.out_valid zip io.out_control zip io.out_id zip io.out_last zip mesh.last) { + // TODO we pipelined this to make physical design easier. Consider removing these if possible + // TODO shouldn't we clock-gate these signals with "garbage" as well? + b := ShiftRegister(tile.io.out_b, output_delay) + c := ShiftRegister(tile.io.out_c, output_delay) + v := ShiftRegister(tile.io.out_valid, output_delay) + ctrl := ShiftRegister(tile.io.out_control, output_delay) + id := ShiftRegister(tile.io.out_id, output_delay) + last := ShiftRegister(tile.io.out_last, output_delay) + } +} diff --git a/platforms/arty-a7-toy/patches/gemmini/PE.scala b/platforms/arty-a7-toy/patches/gemmini/PE.scala new file mode 100644 index 0000000..1a71132 --- /dev/null +++ b/platforms/arty-a7-toy/patches/gemmini/PE.scala @@ -0,0 +1,162 @@ +// See README.md for license details. +package gemmini + +import chisel3._ +import chisel3.util._ + +class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { + val dataflow = UInt(1.W) // TODO make this an Enum + val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? + val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats + +} + +class MacUnit[T <: Data](inputType: T, weightType: T, cType: T, dType: T, fpgaDsp: Boolean = false) (implicit ev: Arithmetic[T]) extends Module { + import ev._ + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(weightType) + val in_c = Input(cType) + val out_d = Output(dType) + }) + + if (fpgaDsp) { + require(inputType.getWidth == 8 && weightType.getWidth == 8 && dType.getWidth == 20) + val mac = Module(new FpgaDspMac) + mac.io.a := io.in_a.asUInt + mac.io.b := io.in_b.asUInt + mac.io.c := io.in_c.asUInt + io.out_d := mac.io.y.asTypeOf(dType) + } else io.out_d := io.in_c.mac(io.in_a, io.in_b) +} + +// TODO update documentation +/** + * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. + * @param width Data width of operands + */ +class PE[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int, fpgaDsp: Boolean = false) + (implicit ev: Arithmetic[T]) extends Module { // Debugging variables + import ev._ + + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(outputType) + val in_d = Input(outputType) + val out_a = Output(inputType) + val out_b = Output(outputType) + val out_c = Output(outputType) + + val in_control = Input(new PEControl(accType)) + val out_control = Output(new PEControl(accType)) + + val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) + val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) + + val in_last = Input(Bool()) + val out_last = Output(Bool()) + + val in_valid = Input(Bool()) + val out_valid = Output(Bool()) + + val bad_dataflow = Output(Bool()) + }) + + require(inputType.isInstanceOf[SInt] && inputType.getWidth == 8 && + weightType.getWidth == 8 && outputType.getWidth == 20 && accType.getWidth == 32 && + df == Dataflow.BOTH, "FPGA PE specialization is for the pinned Toy profile") + // Every state update comes from the 20-bit MAC result or 20-bit input d. + // Keep that exact representation; the original 32-bit state is sign extension. + val cType = outputType + + // When creating PEs that support multiple dataflows, the + // elaboration/synthesis tools often fail to consolidate and de-duplicate + // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" + // module here which just performs a single MAC operation + val mac_unit = Module(new MacUnit(inputType, weightType, + cType, outputType, fpgaDsp)) + + val a = io.in_a + val b = io.in_b + val d = io.in_d + val c1 = Reg(cType) + val c2 = Reg(cType) + val dataflow = io.in_control.dataflow + val prop = io.in_control.propagate + val shift = io.in_control.shift + val id = io.in_id + val last = io.in_last + val valid = io.in_valid + + io.out_a := a + io.out_control.dataflow := dataflow + io.out_control.propagate := prop + io.out_control.shift := shift + io.out_id := id + io.out_last := last + io.out_valid := valid + + mac_unit.io.in_a := a + + val last_s = RegEnable(prop, valid) + val flip = last_s =/= prop + val shift_offset = Mux(flip, shift, 0.U) + // Select before rounding: both branches previously duplicated a full quantizer. + val propagated = Mux(prop === 1.U, c1, c2) + val rounded = FpgaRoundShift(propagated.asUInt.asSInt, shift_offset).asTypeOf(outputType) + + // Which dataflow are we using? + val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) + val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) + + // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? + val COMPUTE = 0.U(1.W) + val PROPAGATE = 1.U(1.W) + + io.bad_dataflow := false.B + when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := rounded + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + c2 := mac_unit.io.out_d + c1 := d.withWidthOf(cType) + }.otherwise { + io.out_c := rounded + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c1 + c1 := mac_unit.io.out_d + c2 := d.withWidthOf(cType) + } + }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := c1 + mac_unit.io.in_b := c2.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c1 := d + }.otherwise { + io.out_c := c2 + mac_unit.io.in_b := c1.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c2 := d + } + }.otherwise { + io.bad_dataflow := true.B + //assert(false.B, "unknown dataflow") + io.out_c := DontCare + io.out_b := DontCare + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + } + + when (!valid) { + c1 := c1 + c2 := c2 + mac_unit.io.in_b := DontCare + mac_unit.io.in_c := DontCare + } +} diff --git a/platforms/arty-a7-toy/patches/gemmini/Tile.scala b/platforms/arty-a7-toy/patches/gemmini/Tile.scala new file mode 100644 index 0000000..135ae95 --- /dev/null +++ b/platforms/arty-a7-toy/patches/gemmini/Tile.scala @@ -0,0 +1,132 @@ +// See README.md for license details. + +package gemmini + +import chisel3._ +import chisel3.util._ +import Util._ + +/** + * A Tile is a purely combinational 2D array of passThrough PEs. + * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs + * @param width The data width of each PE in bits + * @param rows Number of PEs on each row + * @param columns Number of PEs on each column + */ +class Tile[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int, fpgaDsp: Boolean = false)(implicit ev: Arithmetic[T]) extends Module { + val io = IO(new Bundle { + val in_a = Input(Vec(rows, inputType)) + val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it + val in_d = Input(Vec(columns, outputType)) + + val in_control = Input(Vec(columns, new PEControl(accType))) + val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) + val in_last = Input(Vec(columns, Bool())) + + val out_a = Output(Vec(rows, inputType)) + val out_c = Output(Vec(columns, outputType)) + val out_b = Output(Vec(columns, outputType)) + + val out_control = Output(Vec(columns, new PEControl(accType))) + val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) + val out_last = Output(Vec(columns, Bool())) + + val in_valid = Input(Vec(columns, Bool())) + val out_valid = Output(Vec(columns, Bool())) + + val bad_dataflow = Output(Bool()) + }) + + import ev._ + + val tile = Seq.fill(rows, columns)(Module(new PE(inputType, weightType, outputType, accType, df, max_simultaneous_matmuls, fpgaDsp))) + val tileT = tile.transpose + + // TODO: abstract hori/vert broadcast, all these connections look the same + // Broadcast 'a' horizontally across the Tile + for (r <- 0 until rows) { + tile(r).foldLeft(io.in_a(r)) { + case (in_a, pe) => + pe.io.in_a := in_a + pe.io.out_a + } + } + + // Broadcast 'b' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_b(c)) { + case (in_b, pe) => + pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) + pe.io.out_b + } + } + + // Broadcast 'd' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_d(c)) { + case (in_d, pe) => + pe.io.in_d := in_d + pe.io.out_c + } + } + + // Broadcast 'control' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_control(c)) { + case (in_ctrl, pe) => + pe.io.in_control := in_ctrl + pe.io.out_control + } + } + + // Broadcast 'garbage' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_valid(c)) { + case (v, pe) => + pe.io.in_valid := v + pe.io.out_valid + } + } + + // Broadcast 'id' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_id(c)) { + case (id, pe) => + pe.io.in_id := id + pe.io.out_id + } + } + + // Broadcast 'last' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_last(c)) { + case (last, pe) => + pe.io.in_last := last + pe.io.out_last + } + } + + // Drive the Tile's bottom IO + for (c <- 0 until columns) { + io.out_c(c) := tile(rows-1)(c).io.out_c + io.out_control(c) := tile(rows-1)(c).io.out_control + io.out_id(c) := tile(rows-1)(c).io.out_id + io.out_last(c) := tile(rows-1)(c).io.out_last + io.out_valid(c) := tile(rows-1)(c).io.out_valid + + io.out_b(c) := { + if (tree_reduction) { + val prods = tileT(c).map(_.io.out_b) + accumulateTree(prods :+ io.in_b(c)) + } else { + tile(rows - 1)(c).io.out_b + } + } + } + io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) + + // Drive the Tile's right IO + for (r <- 0 until rows) { + io.out_a(r) := tile(r)(columns-1).io.out_a + } +} diff --git a/platforms/arty-a7-toy/patches/rocket/FPU.scala b/platforms/arty-a7-toy/patches/rocket/FPU.scala new file mode 100644 index 0000000..c1eca79 --- /dev/null +++ b/platforms/arty-a7-toy/patches/rocket/FPU.scala @@ -0,0 +1,1220 @@ +// See LICENSE.Berkeley for license details. +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.tile + +import chisel3._ +import chisel3.util._ +import chisel3.{DontCare, WireInit, withClock, withReset} +import chisel3.experimental.SourceInfo +import chisel3.experimental.dataview._ +import org.chipsalliance.cde.config.{Parameters, Field} +import freechips.rocketchip.rocket._ +import freechips.rocketchip.rocket.Instructions._ +import freechips.rocketchip.util._ +import freechips.rocketchip.util.property + +case object FpgaSharedFma extends Field[Boolean](false) + +case class FPUParams( + minFLen: Int = 32, + fLen: Int = 64, + divSqrt: Boolean = true, + sfmaLatency: Int = 5, + dfmaLatency: Int = 6, + fpmuLatency: Int = 2, + ifpuLatency: Int = 4 +) + +object FPConstants +{ + val RM_SZ = 3 + val FLAGS_SZ = 5 +} + +trait HasFPUCtrlSigs { + val ldst = Bool() + val wen = Bool() + val ren1 = Bool() + val ren2 = Bool() + val ren3 = Bool() + val swap12 = Bool() + val swap23 = Bool() + val typeTagIn = UInt(2.W) + val typeTagOut = UInt(2.W) + val fromint = Bool() + val toint = Bool() + val fastpipe = Bool() + val fma = Bool() + val div = Bool() + val sqrt = Bool() + val wflags = Bool() + val vec = Bool() +} + +class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs + +class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val inst = Input(Bits(32.W)) + val sigs = Output(new FPUCtrlSigs()) + }) + + private val X2 = BitPat.dontCare(2) + + val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) + val h: Array[(BitPat, List[BitPat])] = + Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), + FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), + FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), + FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), + FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), + FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), + FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), + FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), + FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), + FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), + FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), + FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), + FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) + val f: Array[(BitPat, List[BitPat])] = + Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), + FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), + FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), + FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), + FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), + FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), + FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), + FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), + FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), + FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), + FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) + val d: Array[(BitPat, List[BitPat])] = + Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), + FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), + FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), + FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), + FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), + FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), + FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), + FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), + FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), + FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), + FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), + FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), + FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) + val fcvt_hd: Array[(BitPat, List[BitPat])] = + Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), + FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) + val vfmv_f_s: Array[(BitPat, List[BitPat])] = + Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) + + val insns = ((minFLen, fLen) match { + case (32, 32) => f + case (16, 32) => h ++ f + case (32, 64) => f ++ d + case (16, 64) => h ++ f ++ d ++ fcvt_hd + case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") + }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) + val decoder = DecodeLogic(io.inst, default, insns) + val s = io.sigs + val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, + s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, + s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) + sigs zip decoder map {case(s,d) => s := d} +} + +class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { + val hartid = Input(UInt(hartIdLen.W)) + val time = Input(UInt(xLen.W)) + + val inst = Input(Bits(32.W)) + val fromint_data = Input(Bits(xLen.W)) + + val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) + val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) + + val v_sew = Input(UInt(3.W)) + + val store_data = Output(Bits(fLen.W)) + val toint_data = Output(Bits(xLen.W)) + + val ll_resp_val = Input(Bool()) + val ll_resp_type = Input(Bits(3.W)) + val ll_resp_tag = Input(UInt(5.W)) + val ll_resp_data = Input(Bits(fLen.W)) + + val valid = Input(Bool()) + val fcsr_rdy = Output(Bool()) + val nack_mem = Output(Bool()) + val illegal_rm = Output(Bool()) + val killx = Input(Bool()) + val killm = Input(Bool()) + val dec = Output(new FPUCtrlSigs()) + val sboard_set = Output(Bool()) + val sboard_clr = Output(Bool()) + val sboard_clra = Output(UInt(5.W)) + + val keep_clock_enabled = Input(Bool()) +} + +class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { + val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs + val cp_resp = Decoupled(new FPResult()) +} + +class FPResult(implicit p: Parameters) extends CoreBundle()(p) { + val data = Bits((fLen+1).W) + val exc = Bits(FPConstants.FLAGS_SZ.W) +} + +class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { + val rm = Bits(FPConstants.RM_SZ.W) + val typ = Bits(2.W) + val in1 = Bits(xLen.W) +} + +class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { + val rm = Bits(FPConstants.RM_SZ.W) + val fmaCmd = Bits(2.W) + val typ = Bits(2.W) + val fmt = Bits(2.W) + val in1 = Bits((fLen+1).W) + val in2 = Bits((fLen+1).W) + val in3 = Bits((fLen+1).W) + +} + +case class FType(exp: Int, sig: Int) { + def ieeeWidth = exp + sig + def recodedWidth = ieeeWidth + 1 + + def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) + def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) + def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR + def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) + + def classify(x: UInt) = { + val sign = x(sig + exp) + val code = x(exp + sig - 1, exp + sig - 3) + val codeHi = code(2, 1) + val isSpecial = codeHi === 3.U + + val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U + val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn + val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U + val isZero = code === 0.U + val isInf = isSpecial && !code(0) + val isNaN = code.andR + val isSNaN = isNaN && !x(sig-2) + val isQNaN = isNaN && x(sig-2) + + Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, + isSubnormal && !sign, isZero && !sign, isZero && sign, + isSubnormal && sign, isNormal && sign, isInf && sign) + } + + // convert between formats, ignoring rounding, range, NaN + def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { + val sign = x(sig + exp) + val fractIn = x(sig - 2, 0) + val expIn = x(sig + exp - 1, sig - 1) + val fractOut = fractIn << to.sig >> sig + val expOut = { + val expCode = expIn(exp, exp - 2) + val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U + Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) + } + Cat(sign, expOut, fractOut) + } + + private def ieeeBundle = { + val expWidth = exp + class IEEEBundle extends Bundle { + val sign = Bool() + val exp = UInt(expWidth.W) + val sig = UInt((ieeeWidth-expWidth-1).W) + } + new IEEEBundle + } + + def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) + + def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) + def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) +} + +object FType { + val H = new FType(5, 11) + val S = new FType(8, 24) + val D = new FType(11, 53) + + val all = List(H, S, D) +} + +trait HasFPUParameters { + require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) + val minFLen: Int + val fLen: Int + def xLen: Int + val minXLen = 32 + val nIntTypes = log2Ceil(xLen/minXLen) + 1 + def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) + def minType = floatTypes.head + def maxType = floatTypes.last + def prevType(t: FType) = floatTypes(typeTag(t) - 1) + def maxExpWidth = maxType.exp + def maxSigWidth = maxType.sig + def typeTag(t: FType) = floatTypes.indexOf(t) + def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U + def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U + // typeTag + def H = typeTagGroup(FType.H) + def S = typeTagGroup(FType.S) + def D = typeTagGroup(FType.D) + def I = typeTag(maxType).U + + private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR + + private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { + require(xt.ieeeWidth == 2 * yt.ieeeWidth) + val swizzledNaN = Cat( + x(xt.sig + xt.exp, xt.sig + xt.exp - 3), + x(xt.sig - 2, yt.recodedWidth - 1).andR, + x(xt.sig + xt.exp - 5, xt.sig), + y(yt.recodedWidth - 2), + x(xt.sig - 2, yt.recodedWidth - 1), + y(yt.recodedWidth - 1), + y(yt.recodedWidth - 3, 0)) + Mux(xt.isNaN(x), swizzledNaN, x) + } + + // implement NaN unboxing for FU inputs + def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { + val outType = exactType.getOrElse(maxType) + def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { + val prev = + if (t == minType) { + Seq() + } else { + val prevT = prevType(t) + val unswizzled = Cat( + x(prevT.sig + prevT.exp - 1), + x(t.sig - 1), + x(prevT.sig + prevT.exp - 2, 0)) + val prev = helper(unswizzled, prevT) + val isbox = isBox(x, t) + prev.map(p => (isbox && p._1, p._2)) + } + prev :+ (true.B, t.unsafeConvert(x, outType)) + } + + val (oks, floats) = helper(x, maxType).unzip + if (exactType.isEmpty || floatTypes.size == 1) { + Mux(oks(tag), floats(tag), maxType.qNaN) + } else { + val t = exactType.get + floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) + } + } + + // make sure that the redundant bits in the NaN-boxed encoding are consistent + def consistent(x: UInt): Bool = { + def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { + val prevT = prevType(t) + val unswizzled = Cat( + x(prevT.sig + prevT.exp - 1), + x(t.sig - 1), + x(prevT.sig + prevT.exp - 2, 0)) + val prevOK = !isBox(x, t) || helper(unswizzled, prevT) + val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR + prevOK && curOK + } + helper(x, maxType) + } + + // generate a NaN box from an FU result + def box(x: UInt, t: FType): UInt = { + if (t == maxType) { + x + } else { + val nt = floatTypes(typeTag(t) + 1) + val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) + bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U + } + } + + // generate a NaN box from an FU result + def box(x: UInt, tag: UInt): UInt = { + val opts = floatTypes.map(t => box(x, t)) + opts(tag) + } + + // zap bits that hardfloat thinks are don't-cares, but we do care about + def sanitizeNaN(x: UInt, t: FType): UInt = { + if (typeTag(t) == 0) { + x + } else { + val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) + Mux(t.isNaN(x), maskedNaN, x) + } + } + + // implement NaN boxing and recoding for FL*/fmv.*.x + def recode(x: UInt, tag: UInt): UInt = { + def helper(x: UInt, t: FType): UInt = { + if (typeTag(t) == 0) { + t.recode(x) + } else { + val prevT = prevType(t) + box(t.recode(x), t, helper(x, prevT), prevT) + } + } + + // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value + val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) + helper(boxes(tag) | x, maxType) + } + + // implement NaN unboxing and un-recoding for FS*/fmv.x.* + def ieee(x: UInt, t: FType = maxType): UInt = { + if (typeTag(t) == 0) { + t.ieee(x) + } else { + val unrecoded = t.ieee(x) + val prevT = prevType(t) + val prevRecoded = Cat( + x(prevT.recodedWidth-2), + x(t.sig-1), + x(prevT.recodedWidth-3, 0)) + val prevUnrecoded = ieee(prevRecoded, prevT) + Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) + } + } +} + +abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters + +class FPToInt(implicit p: Parameters) extends FPUModule()(p) { + class Output extends Bundle { + val in = new FPInput + val lt = Bool() + val store = Bits(fLen.W) + val toint = Bits(xLen.W) + val exc = Bits(FPConstants.FLAGS_SZ.W) + } + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new Output) + }) + + val in = RegEnable(io.in.bits, io.in.valid) + val valid = RegNext(io.in.valid) + + val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) + dcmp.io.a := in.in1 + dcmp.io.b := in.in2 + dcmp.io.signaling := !in.rm(1) + + val tag = in.typeTagOut + val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) + else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) + + val toint = WireDefault(toint_ieee) + val intType = WireDefault(in.fmt(0)) + io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) + io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) + io.out.bits.exc := 0.U + + when (in.rm(0)) { + val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) + toint := classify_out | (toint_ieee >> minXLen << minXLen) + intType := false.B + } + + when (in.wflags) { // feq/flt/fle, fcvt + toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) + io.out.bits.exc := dcmp.io.exceptionFlags + intType := false.B + + when (!in.ren2) { // fcvt + val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) + intType := cvtType + val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) + conv.io.in := in.in1 + conv.io.roundingMode := in.rm + conv.io.signedOut := ~in.typ(0) + toint := conv.io.out + io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) + + for (i <- 0 until nIntTypes-1) { + val w = minXLen << i + when (cvtType === i.U) { + val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) + narrow.io.in := in.in1 + narrow.io.roundingMode := in.rm + narrow.io.signedOut := ~in.typ(0) + + val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) + val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) + val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) + when (invalid) { toint := Cat(conv.io.out >> w, excOut) } + io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) + } + } + } + } + + io.out.valid := valid + io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) + io.out.bits.in := in +} + +class PipelinedINToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends Module { + val io = IO(new Bundle { + val validin = Input(Bool()) + val signedIn = Input(Bool()) + val in = Input(Bits(intWidth.W)) + val bypassIn = Input(Bits(intWidth.W)) + val roundingMode = Input(UInt(3.W)) + val detectTininess = Input(UInt(1.W)) + val typeTagIn = Input(UInt(2.W)) + val wflagsIn = Input(Bool()) + val out = Output(Bits((expWidth + sigWidth + 1).W)) + val exceptionFlags = Output(Bits(5.W)) + val typeTagOut = Output(UInt(2.W)) + val wflagsOut = Output(Bool()) + val inOut = Output(Bits(intWidth.W)) + val validout = Output(Bool()) + }) + + val rawExpWidth = log2Up(intWidth) + 1 + val extIntWidth = 1 << (rawExpWidth - 1) + val normalizationLevels = rawExpWidth - 1 + val firstStageLevels = 2 + val secondStageLevels = normalizationLevels - firstStageLevels + require(secondStageLevels > 0) + + val sign = io.signedIn && io.in(intWidth - 1) + val absIn = Mux(sign, -io.in.asUInt, io.in.asUInt) + val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) + + // Complete the 32- and 16-bit normalization decisions before the cut. + val firstNormStages = Wire(Vec(firstStageLevels + 1, UInt(extIntWidth.W))) + val firstNormDist = Wire(Vec(firstStageLevels, Bool())) + firstNormStages(0) := extAbsIn + for (level <- 0 until firstStageLevels) { + val shiftAmt = extIntWidth >> (level + 1) + val upperHalfIsZero = + !firstNormStages(level)(extIntWidth - 1, extIntWidth - shiftAmt).orR + firstNormStages(level + 1) := Mux( + upperHalfIsZero, + (firstNormStages(level) << shiftAmt)(extIntWidth - 1, 0), + firstNormStages(level) + ) + firstNormDist(firstStageLevels - 1 - level) := upperHalfIsZero + } + + val midNormStage = RegEnable(firstNormStages(firstStageLevels), io.validin) + val midNormDist = RegEnable(firstNormDist.asUInt, io.validin) + val midSign = RegEnable(sign, io.validin) + val midRoundingMode = RegEnable(io.roundingMode, io.validin) + val midDetectTininess = RegEnable(io.detectTininess, io.validin) + val midTypeTag = RegEnable(io.typeTagIn, io.validin) + val midWflags = RegEnable(io.wflagsIn, io.validin) + val midIn = RegEnable(io.bypassIn, io.validin) + val midValid = RegNext(io.validin, false.B) + + val secondNormStages = Wire(Vec(secondStageLevels + 1, UInt(extIntWidth.W))) + val secondNormDist = Wire(Vec(secondStageLevels, Bool())) + secondNormStages(0) := midNormStage + for (offset <- 0 until secondStageLevels) { + val level = firstStageLevels + offset + val shiftAmt = extIntWidth >> (level + 1) + val upperHalfIsZero = + !secondNormStages(offset)(extIntWidth - 1, extIntWidth - shiftAmt).orR + secondNormStages(offset + 1) := Mux( + upperHalfIsZero, + (secondNormStages(offset) << shiftAmt)(extIntWidth - 1, 0), + secondNormStages(offset) + ) + secondNormDist(secondStageLevels - 1 - offset) := upperHalfIsZero + } + + val adjustedNormDist = Cat(midNormDist, secondNormDist.asUInt) + val sig = secondNormStages(secondStageLevels)(extIntWidth - 1, extIntWidth - intWidth) + val intAsRawFloat = Wire(new hardfloat.RawFloat(rawExpWidth, intWidth)) + intAsRawFloat.isNaN := false.B + intAsRawFloat.isInf := false.B + intAsRawFloat.isZero := !sig(intWidth - 1) + intAsRawFloat.sign := midSign + intAsRawFloat.sExp := (2.U(2.W) ## ~adjustedNormDist).zext + intAsRawFloat.sig := sig + + // Isolate the remaining normalization and raw-float construction from the + // target-format rounding and packing logic. + val roundInput = RegEnable(intAsRawFloat, midValid) + val roundRoundingMode = RegEnable(midRoundingMode, midValid) + val roundDetectTininess = RegEnable(midDetectTininess, midValid) + val roundTypeTag = RegEnable(midTypeTag, midValid) + val roundWflags = RegEnable(midWflags, midValid) + val roundIn = RegEnable(midIn, midValid) + val roundValid = RegNext(midValid, false.B) + + val roundAnyRawFNToRecFN = Module(new hardfloat.RoundAnyRawFNToRecFN( + rawExpWidth, + intWidth, + expWidth, + sigWidth, + hardfloat.consts.flRoundOpt_sigMSBitAlwaysZero | hardfloat.consts.flRoundOpt_neverUnderflows + )) + roundAnyRawFNToRecFN.io.invalidExc := false.B + roundAnyRawFNToRecFN.io.infiniteExc := false.B + roundAnyRawFNToRecFN.io.in := roundInput + roundAnyRawFNToRecFN.io.roundingMode := roundRoundingMode + roundAnyRawFNToRecFN.io.detectTininess := roundDetectTininess + + io.out := roundAnyRawFNToRecFN.io.out + io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags + io.typeTagOut := roundTypeTag + io.wflagsOut := roundWflags + io.inOut := roundIn + io.validout := roundValid +} + +class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val in = Flipped(Valid(new IntToFPInput)) + val out = Valid(new FPResult) + }) + + require(latency >= 3) + + val in = Pipe(io.in) + + val intValue = { + val res = WireDefault(in.bits.in1.asSInt) + for (i <- 0 until nIntTypes-1) { + val smallInt = in.bits.in1((minXLen << i) - 1, 0) + when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { + res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) + } + } + res.asUInt + } + + val i2f = for (t <- floatTypes) yield { + val converter = Module(new PipelinedINToRecFN(xLen, t.exp, t.sig)) + converter.io.validin := in.valid + converter.io.signedIn := ~in.bits.typ(0) + converter.io.in := intValue + converter.io.bypassIn := in.bits.in1 + converter.io.roundingMode := in.bits.rm + converter.io.detectTininess := hardfloat.consts.tininess_afterRounding + converter.io.typeTagIn := in.bits.typeTagIn + converter.io.wflagsIn := in.bits.wflags + converter + } + val tag = i2f.head.io.typeTagOut + + val mux = Wire(new FPResult) + mux.exc := 0.U + mux.data := recode(i2f.head.io.inOut, tag) + + when (i2f.head.io.wflagsOut) { // fcvt + // could be improved for RVD/RVQ with a single variable-position rounding + // unit, rather than N fixed-position ones + val i2fResults = i2f.zip(floatTypes).map { case (converter, t) => + (sanitizeNaN(converter.io.out, t), converter.io.exceptionFlags) + } + + val (data, exc) = i2fResults.unzip + val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last + mux.data := dataPadded(tag) + mux.exc := exc(tag) + } + + io.out <> Pipe(i2f.head.io.validout, mux, latency-3) +} + +class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + val lt = Input(Bool()) // from FPToInt + }) + + val in = Pipe(io.in) + + val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) + val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) + + val fsgnjMux = Wire(new FPResult) + fsgnjMux.exc := 0.U + fsgnjMux.data := fsgnj + + when (in.bits.wflags) { // fmin/fmax + val isnan1 = maxType.isNaN(in.bits.in1) + val isnan2 = maxType.isNaN(in.bits.in2) + val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) + val isNaNOut = isnan1 && isnan2 + val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 + fsgnjMux.exc := isInvalid << 4 + fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) + } + + val inTag = in.bits.typeTagIn + val outTag = in.bits.typeTagOut + val mux = WireDefault(fsgnjMux) + for (t <- floatTypes.init) { + when (outTag === typeTag(t).U) { + mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) + } + } + + when (in.bits.wflags && !in.bits.ren2) { // fcvt + if (floatTypes.size > 1) { + // widening conversions simply canonicalize NaN operands + val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) + fsgnjMux.data := widened + fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 + + // narrowing conversions require rounding (for RVQ, this could be + // optimized to use a single variable-position rounding unit, rather + // than two fixed-position ones) + for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { + val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) + narrower.io.in := in.bits.in1 + narrower.io.roundingMode := in.bits.rm + narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding + val narrowed = sanitizeNaN(narrower.io.out, outType) + mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) + mux.exc := narrower.io.exceptionFlags + } + } + } + + io.out <> Pipe(in.valid, mux, latency-1) +} + +class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module +{ + override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" + require(latency<=4) + + val io = IO(new Bundle { + val validin = Input(Bool()) + val op = Input(Bits(2.W)) + val a = Input(Bits((expWidth + sigWidth + 1).W)) + val b = Input(Bits((expWidth + sigWidth + 1).W)) + val c = Input(Bits((expWidth + sigWidth + 1).W)) + val roundingMode = Input(UInt(3.W)) + val detectTininess = Input(UInt(1.W)) + val out = Output(Bits((expWidth + sigWidth + 1).W)) + val exceptionFlags = Output(Bits(5.W)) + val validout = Output(Bool()) + }) + + //------------------------------------------------------------------------ + //------------------------------------------------------------------------ + + val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) + val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) + + mulAddRecFNToRaw_preMul.io.op := io.op + mulAddRecFNToRaw_preMul.io.a := io.a + mulAddRecFNToRaw_preMul.io.b := io.b + mulAddRecFNToRaw_preMul.io.c := io.c + + // Isolate preMul's unpack/alignment logic from the multiplier-add stage. + val preMulRegs = if (latency >= 3) 1 else 0 + val preMulMulAddA = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddA, preMulRegs) + val preMulMulAddB = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddB, preMulRegs) + val preMulMulAddC = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddC, preMulRegs) + val preMulToPostMul = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, preMulRegs) + + // Keep the full-precision product unrounded while separating multiplication + // from the final addition. The aligned addend and post-processing metadata + // must cross this stage with the product to preserve fused FMA semantics. + val mulRegs = if (latency == 4) 1 else 0 + val mulResult = preMulMulAddA.bits * preMulMulAddB.bits + val mulResultPipe = Pipe(preMulToPostMul.valid, mulResult, mulRegs) + val mulAddCPipe = Pipe(preMulToPostMul.valid, preMulMulAddC.bits, mulRegs) + val mulToPostMul = Pipe(preMulToPostMul.valid, preMulToPostMul.bits, mulRegs) + val mulAddResult = mulResultPipe.bits +& mulAddCPipe.bits + + val valid_stage0 = Wire(Bool()) + val roundingMode_stage0 = Wire(UInt(3.W)) + val detectTininess_stage0 = Wire(UInt(1.W)) + + val postmul_regs = if(latency>0) 1 else 0 + mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(mulToPostMul.valid, mulToPostMul.bits, postmul_regs).bits + mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(mulToPostMul.valid, mulAddResult, postmul_regs).bits + mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, preMulRegs + mulRegs + postmul_regs).bits + roundingMode_stage0 := Pipe(io.validin, io.roundingMode, preMulRegs + mulRegs + postmul_regs).bits + detectTininess_stage0 := Pipe(io.validin, io.detectTininess, preMulRegs + mulRegs + postmul_regs).bits + valid_stage0 := Pipe(io.validin, false.B, preMulRegs + mulRegs + postmul_regs).valid + + //------------------------------------------------------------------------ + //------------------------------------------------------------------------ + + val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) + + val round_regs = if(latency>=2) 1 else 0 + roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits + roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits + roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits + roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits + io.validout := Pipe(valid_stage0, false.B, round_regs).valid + + roundRawFNToRecFN.io.infiniteExc := false.B + + io.out := roundRawFNToRecFN.io.out + io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags +} + +class FPUFMAPipe(val latency: Int, val t: FType) + (implicit p: Parameters) extends FPUModule()(p) { + override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" + require(latency>0) + + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + }) + + val valid = RegNext(io.in.valid) + val in = Reg(new FPInput) + when (io.in.valid) { + val one = 1.U << (t.sig + t.exp - 1) + val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) + val cmd_fma = io.in.bits.ren3 + val cmd_addsub = io.in.bits.swap23 + in := io.in.bits + when (cmd_addsub) { in.in2 := one } + when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } + } + + val fmaLatency = (latency - 1) min 4 + val fma = Module(new MulAddRecFNPipe(fmaLatency, t.exp, t.sig)) + fma.io.validin := valid + fma.io.op := in.fmaCmd + fma.io.roundingMode := in.rm + fma.io.detectTininess := hardfloat.consts.tininess_afterRounding + fma.io.a := in.in1 + fma.io.b := in.in2 + fma.io.c := in.in3 + + val res = Wire(new FPResult) + res.data := sanitizeNaN(fma.io.out, t) + res.exc := fma.io.exceptionFlags + + io.out := Pipe(fma.io.validout, res, (latency - 1 - fmaLatency) max 0) +} + +class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new FPUIO) + + val (useClockGating, useDebugROB) = coreParams match { + case r: RocketCoreParams => + val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 + (r.clockGate, sz < 1) + case _ => (false, false) + } + val clock_en_reg = Reg(Bool()) + val clock_en = clock_en_reg || io.cp_req.valid + val gated_clock = + if (!useClockGating) clock + else ClockGate(clock, clock_en, "fpu_clock_gate") + + val fp_decoder = Module(new FPUDecoder) + fp_decoder.io.inst := io.inst + val id_ctrl = WireInit(fp_decoder.io.sigs) + coreParams match { case r: RocketCoreParams => r.vector.map(v => { + val v_decode = v.decoder(p) // Only need to get ren1 + v_decode.io.inst := io.inst + v_decode.io.vconfig := DontCare // core deals with this + v_decode.io.vconfig.vtype.vsew := io.v_sew + when (v_decode.io.legal && v_decode.io.read_frs1) { + id_ctrl.ren1 := true.B + id_ctrl.swap12 := false.B + id_ctrl.toint := true.B + id_ctrl.typeTagIn := I + id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) + } + when (v_decode.io.write_frd) { id_ctrl.wen := true.B } + })} + + val ex_reg_valid = RegNext(io.valid, false.B) + val ex_reg_inst = RegEnable(io.inst, io.valid) + val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) + val ex_ra = List.fill(3)(Reg(UInt())) + + // load/vector response + val load_wb = RegNext(io.ll_resp_val) + val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) + val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) + val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) + + class FPUImpl { // entering gated-clock domain + + val req_valid = ex_reg_valid || io.cp_req.valid + val ex_cp_valid = io.cp_req.fire + val mem_cp_valid = RegNext(ex_cp_valid, false.B) + val wb_cp_valid = RegNext(mem_cp_valid, false.B) + val mem_reg_valid = RegInit(false.B) + val killm = (io.killm || io.nack_mem) && !mem_cp_valid + // Kill X-stage instruction if M-stage is killed. This prevents it from + // speculatively being sent to the div-sqrt unit, which can cause priority + // inversion for two back-to-back divides, the first of which is killed. + val killx = io.killx || mem_reg_valid && killm + mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid + val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) + val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) + + val cp_ctrl = Wire(new FPUCtrlSigs) + cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) + io.cp_resp.valid := false.B + io.cp_resp.bits.data := 0.U + io.cp_resp.bits.exc := DontCare + + val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) + val mem_ctrl = RegEnable(ex_ctrl, req_valid) + val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) + + // CoreMonitorBundle to monitor fp register file writes + val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) + frfWriteBundle.foreach { i => + i.clock := clock + i.reset := reset + i.hartid := io.hartid + i.timer := io.time(31,0) + i.valid := false.B + i.wrenx := false.B + i.wrenf := false.B + i.excpt := false.B + } + + // regfile + val regfile = Mem(32, Bits((fLen+1).W)) + when (load_wb) { + val wdata = recode(load_wb_data, load_wb_typeTag) + regfile(load_wb_tag) := wdata + assert(consistent(wdata)) + if (enableCommitLog) + printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) + if (useDebugROB) + DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) + frfWriteBundle(0).wrdst := load_wb_tag + frfWriteBundle(0).wrenf := true.B + frfWriteBundle(0).wrdata := ieee(wdata) + } + + val ex_rs = ex_ra.map(a => regfile(a)) + when (io.valid) { + when (id_ctrl.ren1) { + when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } + when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } + } + when (id_ctrl.ren2) { + when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } + when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } + when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } + } + when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } + } + val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) + + def fuInput(minT: Option[FType]): FPInput = { + val req = Wire(new FPInput) + val tag = ex_ctrl.typeTagIn + req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) + req.rm := ex_rm + req.in1 := unbox(ex_rs(0), tag, minT) + req.in2 := unbox(ex_rs(1), tag, minT) + req.in3 := unbox(ex_rs(2), tag, minT) + req.typ := ex_reg_inst(21,20) + req.fmt := ex_reg_inst(26,25) + req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) + when (ex_cp_valid) { + req := io.cp_req.bits + when (io.cp_req.bits.swap12) { + req.in1 := io.cp_req.bits.in2 + req.in2 := io.cp_req.bits.in1 + } + when (io.cp_req.bits.swap23) { + req.in2 := io.cp_req.bits.in3 + req.in3 := io.cp_req.bits.in2 + } + } + req + } + + // FMA units are selected with their writeback metadata below. + + val fpiu = Module(new FPToInt) + fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) + fpiu.io.in.bits := fuInput(None) + io.store_data := fpiu.io.out.bits.store + io.toint_data := fpiu.io.out.bits.toint + when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ + io.cp_resp.bits.data := fpiu.io.out.bits.toint + io.cp_resp.valid := true.B + } + + val ifpu = Module(new IntToFP(cfg.ifpuLatency)) + ifpu.io.in.valid := req_valid && ex_ctrl.fromint + ifpu.io.in.bits := fpiu.io.in.bits + ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) + + val fpmu = Module(new FPToFP(cfg.fpmuLatency)) + fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe + fpmu.io.in.bits := fpiu.io.in.bits + fpmu.io.lt := fpiu.io.out.bits.lt + + val divSqrt_wen = WireDefault(false.B) + val divSqrt_inFlight = WireDefault(false.B) + val divSqrt_waddr = Reg(UInt(5.W)) + val divSqrt_cp = Reg(Bool()) + val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) + val divSqrt_wdata = Wire(UInt((fLen+1).W)) + val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) + divSqrt_typeTag := DontCare + divSqrt_wdata := DontCare + divSqrt_flags := DontCare + // writeback arbitration + case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) + val fmaPipes = if (p(FpgaSharedFma)) { + require(fLen == 64 && minFLen == 16) + require(cfg.sfmaLatency == cfg.dfmaLatency) + val sharedFma = Module(new FPUSharedFMAPipe(cfg.dfmaLatency)) + sharedFma.io.in.valid := req_valid && ex_ctrl.fma + sharedFma.io.in.bits := fuInput(Some(FType.D)) + for (t <- floatTypes.init) { + when (ex_ctrl.typeTagOut === typeTag(t).U) { + sharedFma.io.in.bits := fuInput(Some(t)) + } + } + List(Pipe(sharedFma, sharedFma.latency, (c: FPUCtrlSigs) => c.fma, sharedFma.io.out.bits)) + } else { + val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) + sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S + sfma.io.in.bits := fuInput(Some(sfma.t)) + List( + Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ + (fLen > 32).option({ + val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) + dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D + dfma.io.in.bits := fuInput(Some(dfma.t)) + Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) + }) ++ + (minFLen == 16).option({ + val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) + hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H + hfma.io.in.bits := fuInput(Some(hfma.t)) + Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) + }) + + } + val pipes = List( + Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), + Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits)) ++ fmaPipes + def latencyMask(c: FPUCtrlSigs, offset: Int) = { + require(pipes.forall(_.lat >= offset)) + pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) + } + def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) + val maxLatency = pipes.map(_.lat).max + val memLatencyMask = latencyMask(mem_ctrl, 2) + + class WBInfo extends Bundle { + val rd = UInt(5.W) + val typeTag = UInt(log2Up(floatTypes.size).W) + val cp = Bool() + val pipeid = UInt(log2Ceil(pipes.size).W) + } + + val wen = RegInit(0.U((maxLatency-1).W)) + val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) + val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) + val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) + ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") + + for (i <- 0 until maxLatency-2) { + when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } + } + wen := wen >> 1 + when (mem_wen) { + when (!killm) { + wen := wen >> 1 | memLatencyMask + } + for (i <- 0 until maxLatency-1) { + when (!write_port_busy && memLatencyMask(i)) { + wbInfo(i).cp := mem_cp_valid + wbInfo(i).typeTag := mem_ctrl.typeTagOut + wbInfo(i).pipeid := pipeid(mem_ctrl) + wbInfo(i).rd := mem_reg_inst(11,7) + } + } + } + + val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) + val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) + val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) + val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) + val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) + when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { + assert(consistent(wdata)) + regfile(waddr) := wdata + if (enableCommitLog) { + printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) + } + frfWriteBundle(1).wrdst := waddr + frfWriteBundle(1).wrenf := true.B + frfWriteBundle(1).wrdata := ieee(wdata) + } + if (useDebugROB) { + DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) + } + + when (wb_cp && (wen(0) || divSqrt_wen)) { + io.cp_resp.bits.data := wdata + io.cp_resp.valid := true.B + } + + assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, + s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") + // Avoid structural hazards and nacking of external requests + // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs + io.cp_req.ready := !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight + + val wb_toint_valid = wb_reg_valid && wb_ctrl.toint + val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) + io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) + io.fcsr_flags.bits := + Mux(wb_toint_valid, wb_toint_exc, 0.U) | + Mux(divSqrt_wen, divSqrt_flags, 0.U) | + Mux(wen(0), wexc, 0.U) + + val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR + io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) + io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight || mem_cp_valid) + io.dec <> id_ctrl + def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) + io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) + io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) + io.sboard_clra := waddr + ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") + // we don't currently support round-max-magnitude (rm=4) + io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U + + if (cfg.divSqrt) { + val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight + val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) + when (divSqrt_inValid) { + divSqrt_waddr := mem_reg_inst(11,7) + divSqrt_cp := mem_cp_valid + } + + ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") + ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") + ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") + + for (t <- floatTypes) { + val tag = mem_ctrl.typeTagOut + val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } + divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U + divSqrt.io.sqrtOp := mem_ctrl.sqrt + divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) + divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) + divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm + divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding + + when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight + + when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { + divSqrt_wen := !divSqrt_killed + divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) + divSqrt_flags := divSqrt.io.exceptionFlags + divSqrt_typeTag := typeTag(t).U + } + } + + when (divSqrt_killed) { divSqrt_inFlight := false.B } + } else { + when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } + } + + // gate the clock + clock_en_reg := !useClockGating.B || + io.keep_clock_enabled || // chicken bit + io.valid || // ID stage + req_valid || // EX stage + mem_reg_valid || mem_cp_valid || // MEM stage + wb_reg_valid || wb_cp_valid || // WB stage + wen.orR || divSqrt_inFlight || // post-WB stage + io.ll_resp_val // load writeback + + } // leaving gated-clock domain + val fpuImpl = withClock (gated_clock) { new FPUImpl } + + def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = + property.cover(cond, s"FPU_$label", "Core;;" + desc) +} diff --git a/platforms/arty-a7-toy/patches/rocket/SharedFma.scala b/platforms/arty-a7-toy/patches/rocket/SharedFma.scala new file mode 100644 index 0000000..a05e40b --- /dev/null +++ b/platforms/arty-a7-toy/patches/rocket/SharedFma.scala @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +package freechips.rocketchip.tile + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters + +/** One unrounded FP64 FMA datapath, with direct H/S/D final rounding. */ +class SharedMulAddRecFNPipe(implicit p: Parameters) extends FPUModule { + require(fLen == 64 && minFLen == 16) + val io = IO(new Bundle { + val validin = Input(Bool()) + val op = Input(UInt(2.W)) + val typeTag = Input(UInt(2.W)) + val a = Input(UInt(65.W)) + val b = Input(UInt(65.W)) + val c = Input(UInt(65.W)) + val roundingMode = Input(UInt(3.W)) + val out = Output(new FPResult) + val validout = Output(Bool()) + }) + val pre = Module(new hardfloat.MulAddRecFNToRaw_preMul(11, 53)) + val post = Module(new hardfloat.MulAddRecFNToRaw_postMul(11, 53)) + pre.io.op := io.op + pre.io.a := io.a + pre.io.b := io.b + pre.io.c := io.c + + // Retain the original four-stage raw FMA partition: align, multiply, add, + // normalize. Full product bits and sticky information survive until rounding. + val mulA = Pipe(io.validin, pre.io.mulAddA, 1) + val mulB = Pipe(io.validin, pre.io.mulAddB, 1) + val alignedC = Pipe(io.validin, pre.io.mulAddC, 1) + val meta = Pipe(io.validin, pre.io.toPostMul, 1) + val product = Pipe(meta.valid, mulA.bits * mulB.bits, 1) + val delayedC = Pipe(meta.valid, alignedC.bits, 1) + val delayedMeta = Pipe(meta.valid, meta.bits, 1) + val sum = product.bits +& delayedC.bits + post.io.fromPreMul := Pipe(delayedMeta.valid, delayedMeta.bits, 1).bits + post.io.mulAddResult := Pipe(delayedMeta.valid, sum, 1).bits + val rmPost = Pipe(io.validin, io.roundingMode, 3) + post.io.roundingMode := rmPost.bits + + val raw = Pipe(rmPost.valid, post.io.rawOut, 1) + val invalid = Pipe(rmPost.valid, post.io.invalidExc, 1) + val rm = Pipe(io.validin, io.roundingMode, 4) + val tag = Pipe(io.validin, io.typeTag, 4) + val results = floatTypes.map { t => + // Do not round to FP64 and convert afterward: that would double-round. + val round = Module(new hardfloat.RoundAnyRawFNToRecFN(11, 55, t.exp, t.sig, 0)) + round.io.in := raw.bits + round.io.invalidExc := invalid.bits + round.io.infiniteExc := false.B + round.io.roundingMode := rm.bits + round.io.detectTininess := hardfloat.consts.tininess_afterRounding + val result = Wire(new FPResult) + result.data := sanitizeNaN(round.io.out, t) + result.exc := round.io.exceptionFlags + result + } + io.out := VecInit(results)(tag.bits) + io.validout := tag.valid +} + +/** The Rocket core issues at most one FMA per cycle; all formats share it. */ +class FPUSharedFMAPipe(val latency: Int)(implicit p: Parameters) extends FPUModule { + require(latency >= 5) + require(fLen == 64 && minFLen == 16) + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + }) + def widen(x: UInt): UInt = { + VecInit(floatTypes.map(t => t.unsafeConvert(x(t.recodedWidth - 1, 0), maxType)))(io.in.bits.typeTagOut) + } + val a = widen(io.in.bits.in1) + val b = widen(io.in.bits.in2) + val c = widen(io.in.bits.in3) + val valid = RegNext(io.in.valid, false.B) + val in = Reg(new FPInput) + when (io.in.valid) { + in := io.in.bits + in.in1 := a + in.in2 := Mux(io.in.bits.swap23, (BigInt(1) << 63).U(65.W), b) + val zero = (a ^ b) & (BigInt(1) << 64).U(65.W) + in.in3 := Mux(io.in.bits.ren3 || io.in.bits.swap23, c, zero) + } + val fma = Module(new SharedMulAddRecFNPipe) + fma.io.validin := valid + fma.io.op := in.fmaCmd + fma.io.typeTag := in.typeTagOut + fma.io.a := in.in1 + fma.io.b := in.in2 + fma.io.c := in.in3 + fma.io.roundingMode := in.rm + io.out := Pipe(fma.io.validout, fma.io.out, latency - 5) +} diff --git a/platforms/arty-a7-toy/program.ps1 b/platforms/arty-a7-toy/program.ps1 new file mode 100644 index 0000000..a0ac4bc --- /dev/null +++ b/platforms/arty-a7-toy/program.ps1 @@ -0,0 +1,12 @@ +param( + [string]$VivadoBin = $env:VIVADO_BIN, + [Parameter(Mandatory = $true)][string]$Bitstream +) +$ErrorActionPreference = "Stop" +if (!$VivadoBin) { $VivadoBin = Split-Path (Get-Command vivado.bat -ErrorAction Stop).Source } +if (!(Test-Path -LiteralPath $Bitstream -PathType Leaf)) { throw "Bitstream not found: $Bitstream" } +Push-Location $PSScriptRoot +try { + & (Join-Path $VivadoBin "vivado.bat") -mode batch -source board/program_arty.tcl -tclargs $Bitstream + if ($LASTEXITCODE -ne 0) { throw "FPGA programming failed; inspect Vivado log" } +} finally { Pop-Location } diff --git a/platforms/arty-a7-toy/project/build.properties b/platforms/arty-a7-toy/project/build.properties new file mode 100644 index 0000000..dabdb15 --- /dev/null +++ b/platforms/arty-a7-toy/project/build.properties @@ -0,0 +1 @@ +sbt.version=1.12.11 diff --git a/platforms/arty-a7-toy/project/repositories b/platforms/arty-a7-toy/project/repositories new file mode 100644 index 0000000..60add57 --- /dev/null +++ b/platforms/arty-a7-toy/project/repositories @@ -0,0 +1,3 @@ +[repositories] +local +maven-central: https://repo.maven.apache.org/maven2 diff --git a/platforms/arty-a7-toy/rtl/FpuRfLvt.sv b/platforms/arty-a7-toy/rtl/FpuRfLvt.sv new file mode 100644 index 0000000..a929eda --- /dev/null +++ b/platforms/arty-a7-toy/rtl/FpuRfLvt.sv @@ -0,0 +1,44 @@ +module FpuRfLvt( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [64:0] R0_data, + input [4:0] R1_addr, + input R1_en, + R1_clk, + output [64:0] R1_data, + input [4:0] R2_addr, + input R2_en, + R2_clk, + output [64:0] R2_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [64:0] W0_data, + input [4:0] W1_addr, + input W1_en, + W1_clk, + input [64:0] W1_data +); + + // Each data bank has one synchronous write port and three asynchronous reads. + // A 32-bit table identifies the bank containing each register's newest value. + // Match original W1-over-W0 priority when both ports write the same address. + // Original RTL clocks both write ports with W0_clk; retain that contract. + (* ram_style = "distributed" *) reg [64:0] bank0 [0:31]; + (* ram_style = "distributed" *) reg [64:0] bank1 [0:31]; + reg [31:0] latest; + always @(posedge W0_clk) begin + if (W0_en) begin + bank0[W0_addr] <= W0_data; + latest[W0_addr] <= 1'b0; + end + if (W1_en) begin + bank1[W1_addr] <= W1_data; + latest[W1_addr] <= 1'b1; + end + end + assign R0_data = R0_en ? (latest[R0_addr] ? bank1[R0_addr] : bank0[R0_addr]) : 65'bx; + assign R1_data = R1_en ? (latest[R1_addr] ? bank1[R1_addr] : bank0[R1_addr]) : 65'bx; + assign R2_data = R2_en ? (latest[R2_addr] ? bank1[R2_addr] : bank0[R2_addr]) : 65'bx; +endmodule diff --git a/platforms/arty-a7-toy/rtl/FpuRfOriginal.sv b/platforms/arty-a7-toy/rtl/FpuRfOriginal.sv new file mode 100644 index 0000000..582263c --- /dev/null +++ b/platforms/arty-a7-toy/rtl/FpuRfOriginal.sv @@ -0,0 +1,34 @@ +module FpuRfOriginal( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [64:0] R0_data, + input [4:0] R1_addr, + input R1_en, + R1_clk, + output [64:0] R1_data, + input [4:0] R2_addr, + input R2_en, + R2_clk, + output [64:0] R2_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [64:0] W0_data, + input [4:0] W1_addr, + input W1_en, + W1_clk, + input [64:0] W1_data +); + + reg [64:0] Memory[0:31]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + if (W1_en & 1'h1) + Memory[W1_addr] <= W1_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 65'bx; + assign R1_data = R1_en ? Memory[R1_addr] : 65'bx; + assign R2_data = R2_en ? Memory[R2_addr] : 65'bx; +endmodule diff --git a/platforms/arty-a7-toy/scripts/bind_fpu_rf.py b/platforms/arty-a7-toy/scripts/bind_fpu_rf.py new file mode 100644 index 0000000..4646b37 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/bind_fpu_rf.py @@ -0,0 +1,33 @@ +"""Bind the already validated zero-latency FPU RF adapter after SRAM binding.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +output = ROOT / "build/serial-bound" +core = output / "ToyLinuxChip.sv" +original = core.read_text(encoding="utf-8") +matches = list(re.finditer(r"^module regfile_32x65\(.*?^endmodule", original, re.M | re.S)) +assert len(matches) == 1 +match = matches[0] +reference = (ROOT / "rtl/FpuRfOriginal.sv").read_text(encoding="utf-8").strip() +assert match.group() == reference.replace("module FpuRfOriginal(", "module regfile_32x65(") +replacement = (ROOT / "rtl/FpuRfLvt.sv").read_text(encoding="utf-8").strip() +replacement = replacement.replace("module FpuRfLvt(", "module regfile_32x65(") +adapted = original[:match.start()] + replacement + original[match.end():] +core.write_text(adapted, encoding="utf-8", newline="\n") +assert adapted.replace(replacement, match.group(), 1) == original +manifest = json.loads((output / "MEMORY_MANIFEST.json").read_text()) +manifest["baseline_core_rtl_sha256"] = manifest["core_rtl_sha256"] +manifest["core_rtl_sha256"] = hashlib.sha256(core.read_bytes()).hexdigest() +manifest["additional_memory_adapters"] = [{ + "module": "regfile_32x65", "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, "write_ports": 2, "read_latency": 0, + "same_address_write_priority": "W1", "added_cycles": 0, + "adapter_sha256": hashlib.sha256((ROOT / "rtl/FpuRfLvt.sv").read_bytes()).hexdigest(), +}] +(output / "MEMORY_MANIFEST.json").write_text(json.dumps(manifest, indent=2) + "\n") +print("PASS RF adapter matches original port contract; only RF module body replaced") +print("Final core SHA256:", manifest["core_rtl_sha256"]) diff --git a/platforms/arty-a7-toy/scripts/build_board_firmware.py b/platforms/arty-a7-toy/scripts/build_board_firmware.py new file mode 100644 index 0000000..6232633 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/build_board_firmware.py @@ -0,0 +1,82 @@ +"""Rebuild the pinned OpenSBI payload for the board's actual CLINT frequency. + +Uses the existing pinned Linux+BusyBox image unchanged. Copies OpenSBI and its +platform into this isolated candidate, never modifies the earlier software. +""" +import hashlib +import argparse +import json +from pathlib import Path +import shutil +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +BASE=ROOT +OUT=ROOT/"build/board-software" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + global BASE + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--software-base",type=Path,default=ROOT, + help="Root containing build/software from software/build.sh") + parser.add_argument("--cross-compile",default="riscv64-linux-gnu-") + args=parser.parse_args() + BASE=args.software_base.resolve() + OUT.mkdir(parents=True,exist_ok=True) + source=BASE/"build/software/bb-tests/thirdparty/opensbi" + platform=BASE/"build/software/bb-tests/workloads/lib/kernel/opensbi-platform" + image=BASE/"build/software/kernel-build/linux/arch/riscv/boot/Image" + image_sha=sha(image) + for original,target in ((source,OUT/"opensbi-src"),(platform,OUT/"platform")): + if not target.exists(): + shutil.copytree(original,target,ignore=shutil.ignore_patterns(".git","build")) + original=(platform/"buckyball/platform.c").read_text() + assert original.count("#define BUCKYBALL_MTIMER_FREQ 1000000")==1 + adapted=original.replace("#define BUCKYBALL_MTIMER_FREQ 1000000","#define BUCKYBALL_MTIMER_FREQ 500000") + old=""" if (fdt_open_into(src, dst, size) == 0) + return BUCKYBALL_DTB_STAGING_ADDR;""" + new=""" if (fdt_open_into(src, dst, size + 512) == 0) { + int cpus = fdt_path_offset(dst, "/cpus"); + if (cpus >= 0) { + if (fdt_setprop_u32(dst, cpus, "timebase-frequency", + BUCKYBALL_MTIMER_FREQ) != 0) + return 0; + int cpu; + fdt_for_each_subnode(cpu, dst, cpus) { + fdt_setprop_u32(dst, cpu, "timebase-frequency", BUCKYBALL_MTIMER_FREQ); + fdt_setprop_u32(dst, cpu, "clock-frequency", 25000000); + } + } + return BUCKYBALL_DTB_STAGING_ADDR; + }""" + assert adapted.count(old)==1 + adapted=adapted.replace(old,new) + (OUT/"platform/buckyball/platform.c").write_text(adapted) + shutil.copy2(image,OUT/"Image") + command=["make","-C",str(OUT/"opensbi-src"),"-j8","CROSS_COMPILE="+args.cross_compile, + "PLATFORM_DIR="+str(OUT/"platform"),"PLATFORM=buckyball","O="+str(OUT/"opensbi-build"), + "FW_PAYLOAD_PATH="+str(OUT/"Image"),"BUCKYBALL_VISIBLE_HART_COUNT=1", + "BUCKYBALL_TOTAL_HART_COUNT=1","BUCKYBALL_HIDDEN_HART_BASE=1"] + with (OUT/"build.log").open("w") as log: + subprocess.run(command,stdout=log,stderr=log,check=True,timeout=900) + payload=OUT/"opensbi-build/platform/buckyball/firmware/fw_payload.bin" + shutil.copy2(payload,OUT/"fw_payload.bin") + assert sha(image)==image_sha==sha(OUT/"Image") + record=dict(result="PASS_BUILD",payload_sha256=sha(payload),payload_bytes=payload.stat().st_size, + linux_image_sha256=image_sha,linux_image_unchanged=True,clint_frequency_hz=500000, + core_frequency_hz=25000000,console_base="0x60020000",memory_bytes=268435456, + original_platform_sha256=sha(platform/"buckyball/platform.c"), + adapted_platform_sha256=sha(OUT/"platform/buckyball/platform.c"), + original_payload_sha256=sha(BASE/"build/software/kernel-build/opensbi/platform/buckyball/firmware/fw_payload.bin"), + boot_tested=False,command=command) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(json.dumps(record,indent=2)) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/build_test_programs.sh b/platforms/arty-a7-toy/scripts/build_test_programs.sh new file mode 100644 index 0000000..987fbed --- /dev/null +++ b/platforms/arty-a7-toy/scripts/build_test_programs.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 tests/check_cpu_smoke.py +python3 tests/check_gemmini.py +python3 tests/check_loop_stress.py +python3 tests/check_dma_beat64.py diff --git a/platforms/arty-a7-toy/scripts/check_board.py b/platforms/arty-a7-toy/scripts/check_board.py new file mode 100644 index 0000000..5f711c2 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board.py @@ -0,0 +1,67 @@ +"""Test the exact board loader, AXI normalizer and OpenSBI SCU with stalls.""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-unit" + + +def run(name, files, marker): + executable=OUT/name + command=["iverilog","-g2012","-s",name,"-o",str(executable)]+[str(f) for f in files] + compiled=subprocess.run(command,capture_output=True,text=True,timeout=60) + (OUT/(name+"-compile.log")).write_text(compiled.stdout+compiled.stderr) + compiled.check_returncode() + result=subprocess.run(["vvp",str(executable)],capture_output=True,text=True,timeout=60) + (OUT/(name+".log")).write_text(result.stdout+result.stderr) + print(result.stdout,end="") + result.check_returncode() + assert marker in result.stdout + + +def main(): + OUT.mkdir(parents=True,exist_ok=True) + run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") + run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, + # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. + template=(ROOT/"tests/board_loader_template.sv").read_text() + template=template.replace("module tb_uart_loader", "module tb_ddr_loader") + template=template.replace("uart_loader #", "ddr_uart_loader #") + template=template.replace("32'h01374150", "32'h02374154") + template=template.replace("axi_bram #(.WORDS(256)) memory(", "/* legacy memory removed\naxi_bram #(.WORDS(256)) memory(") + template=template.replace(" always @(posedge clk) begin\n", "*/\n"+LOADER_MEMORY+"\n always @(posedge clk) begin\n",1) + template=template.replace("wire cpu_run,error_seen,load_en,load_valid;", "wire cpu_run,error_seen,load_en,load_valid,load_error;") + template=template.replace("PASS: UART loader", "PASS: DDR UART loader") + (OUT/"tb_ddr_loader.sv").write_text(template) + run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") + files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] + record=dict(result="PASS",tests=3,physical_mig_simulated=False, + sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +LOADER_MEMORY=""" + wire [27:0] awaddr,araddr; + wire awvalid,wvalid,arvalid,bready,rready,awready,wready,arready,bvalid,rvalid; + wire [127:0] wdata,rdata; + wire [15:0] wstrb; + wire [1:0] bresp,rresp; + loader_axi bridge(.clk(clk),.reset(reset),.load_en(load_en),.load_addr({16'd0,load_addr}), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result), + .awaddr(awaddr),.araddr(araddr),.awvalid(awvalid),.wvalid(wvalid),.arvalid(arvalid), + .bready(bready),.rready(rready),.awready(awready),.wready(wready),.arready(arready), + .bvalid(bvalid),.rvalid(rvalid),.wdata(wdata),.wstrb(wstrb),.bresp(bresp),.rresp(rresp),.rdata(rdata)); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset),.aw_bits_id(4'd0),.aw_bits_addr(awaddr),.aw_bits_len(8'd0),.aw_bits_size(3'd4),.aw_bits_burst(2'd1), + .aw_valid(awvalid),.aw_ready(awready),.w_bits_data(wdata),.w_bits_strb(wstrb),.w_bits_last(1'b1),.w_valid(wvalid),.w_ready(wready), + .b_ready(bready),.b_valid(bvalid),.b_bits_id(),.b_bits_resp(bresp), + .ar_bits_id(4'd0),.ar_bits_addr(araddr),.ar_bits_len(8'd0),.ar_bits_size(3'd4),.ar_bits_burst(2'd1),.ar_valid(arvalid),.ar_ready(arready), + .r_ready(rready),.r_valid(rvalid),.r_bits_id(),.r_bits_data(rdata),.r_bits_resp(rresp),.r_bits_last()); +""" + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/check_board_cdc.py b/platforms/arty-a7-toy/scripts/check_board_cdc.py new file mode 100644 index 0000000..4a5c443 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board_cdc.py @@ -0,0 +1,80 @@ +"""Exercise the actual Xilinx AXI Clock Converter with the adapter oracle. + +The MIG PHY is replaced by the stalled memory model. The converter uses the +same generated IP as the specified board build, copied into a test directory. +""" +import argparse +import hashlib +import json +import os +from pathlib import Path +import re +import shutil +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("board_run") + parser.add_argument("--output-name", default="board-cdc") + args = parser.parse_args() + source = ROOT / "build" / args.board_run / "ip/toy_axi_cdc" + assert source.is_dir(), source + assert re.fullmatch(r"board-cdc(?:-[a-zA-Z0-9-]+)?", args.output_name) + out = ROOT / "build" / args.output_name + out.mkdir(parents=True, exist_ok=True) + ip = out / "ip/toy_axi_cdc" + assert not ip.exists(), "Keep previous simulation evidence; use a fresh output" + shutil.copytree(source, ip) + + bench = (ROOT / "tests/tb_axi_fullwidth.sv").read_text() + bench = bench.replace("tb_axi_fullwidth", "tb_board_cdc") + bench = bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;\n reg ui_clk=0; initial begin #3; forever #6 ui_clk=~ui_clk; end") + # Reuse exactly the board's converter instance and port tie-offs. + top = (ROOT / "board/toy_a7_top.sv").read_text() + declarations = top[top.index(" wire [3:0] ui_awid;"):top.index(" toy_a7_platform platform")] + instance = top[top.index(" toy_axi_cdc memory_cdc"):top.index(" arty_ddr3 ddr_controller")] + instance = instance.replace("ddr_", "m_").replace("ui_aresetn", "!reset") + bench = bench.replace(" axi_fullwidth dut(.*);", declarations + instance + " axi_fullwidth dut(.*);") + first = bench.index(" axi_smoke_memory") + last = bench.index(" always @(posedge clk)", first) + memory = bench[first:last].replace(".clock(clk)", ".clock(ui_clk)").replace("(m_", "(ui_") + bench = bench[:first] + memory + bench[last:] + bench = bench.replace("repeat(5) @(negedge clk);reset=0;", "repeat(20) @(negedge clk);reset=0;repeat(60) @(negedge clk);") + bench = bench.replace("PASS fullwidth AXI:", "PASS BOARD_CDC:") + bench = bench.replace("#2000000", "#10000000") + (out / "tb_board_cdc.sv").write_text(bench) + tcl = f"""create_project -force cdc_test {{{out / 'project'}}} -part xc7a100tcsg324-1 +read_ip {{{ip / 'toy_axi_cdc.xci'}}} +read_verilog -sv {{{ROOT / 'board/axi_fullwidth.sv'}}} +read_verilog -sv {{{ROOT / 'tests/axi_smoke_memory.sv'}}} +read_verilog -sv {{{out / 'tb_board_cdc.sv'}}} +set_property top tb_board_cdc [get_filesets sim_1] +set_property xsim.simulate.runtime all [get_filesets sim_1] +launch_simulation +close_sim +exit +""" + script = out / "simulate.tcl" + script.write_text(tcl) + with (out / "console.log").open("w") as log: + result = subprocess.run([os.environ.get("VIVADO", "vivado"), "-mode", "batch", "-source", str(script), + "-log", str(out / "vivado.log"), "-journal", str(out / "vivado.jou")], + cwd=out, stdout=log, stderr=log, timeout=900) + result.check_returncode() + simulation = out / "project/cdc_test.sim/sim_1/behav/xsim/simulate.log" + transcript = simulation.read_text() + assert "PASS BOARD_CDC:" in transcript, transcript[-2000:] + record = dict(result="PASS_BOARD_CDC", board_run=args.board_run, + core_clock_hz=25000000, ui_clock_hz=83333333, + read_beats=90, physical_mig_simulated=False, + xci_sha256=hashlib.sha256((ip / "toy_axi_cdc.xci").read_bytes()).hexdigest(), + bench_sha256=hashlib.sha256(bench.encode()).hexdigest()) + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript[-1600:]) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/check_board_cpu.py b/platforms/arty-a7-toy/scripts/check_board_cpu.py new file mode 100644 index 0000000..6596ecb --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board_cpu.py @@ -0,0 +1,93 @@ +"""Run the existing CPU/VM/FPU oracle through the real board platform RTL. + +The DDR PHY/CDC is replaced by a stalled AXI memory model here. Loader start is +forced only in this testbench so this separately tests CPU-to-DDR/SCU wiring. +""" +import hashlib +import argparse +import json +from pathlib import Path +import re +import subprocess +import shutil + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-cpu" + + +def main(): + global OUT + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--test",choices=("cpu","gemmini","loop","dma"),default="cpu") + args=parser.parse_args() + OUT=ROOT/("build/board-"+args.test) + OUT.mkdir(parents=True,exist_ok=True) + binary=ROOT/"build/cpu-smoke/smoke.bin" + if args.test!="cpu": + subdir={"gemmini":"gemmini-tests","loop":"loop-stress","dma":"dma-beat64"}[args.test] + elf=ROOT/"build"/subdir/"simulation/smoke.elf" + binary=OUT/"program.bin" + subprocess.run(["riscv64-unknown-elf-objcopy","-O","binary",str(elf),str(binary)],check=True) + assert binary.exists() + shutil.copy2(binary,OUT/"smoke.bin") + (OUT/"smoke.hex").write_text("\n".join(f"{b:02x}" for b in binary.read_bytes())+"\n") + platform=ROOT/"board/toy_a7_platform.sv" + header=platform.read_text().split(") (",1)[1].split(");",1)[0] + signals=[] + direction,width=None,"" + for part in header.split(","): + m=re.fullmatch(r"\s*(?:(input|output)\s+wire\s+)?(\[[^]]+\]\s*)?(\w+)\s*",part) + assert m,part + if m[1]:direction,width=m[1],m[2] or "" + signals.append((direction,width,m[3])) + lines=["`timescale 1ns/1ps","module tb_board_cpu;", " reg clk=0;always #5 clk=~clk;", + " reg reset=1,uart_rx_in=1;"] + for _,width,name in signals: + if name not in ("clk","reset","uart_rx_in"):lines.append(f" wire {width}{name};") + lines += [" toy_a7_platform platform(.*);", " initial begin", + " repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end", + " integer cycles=0;", + " always @(posedge clk) if(!reset) begin", + " cycles<=cycles+1;", + " if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,\"Unexpected AXI exclusive write\");", + " if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,\"Unexpected AXI exclusive read\");", + " if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,\"Narrow DDR write\");", + " if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,\"Narrow DDR read\");", + " if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,\"CPU oracle failed stage=%h\",exit_code);", + " if(exited && exit_code==32'h600d600d) begin", + ' $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end', + " if(cycles>4000000) $fatal(1,\"Board CPU watchdog\");", + " end"] + mapping={"awid":"aw_bits_id","awaddr":"aw_bits_addr","awlen":"aw_bits_len","awsize":"aw_bits_size", + "awburst":"aw_bits_burst","wdata":"w_bits_data","wstrb":"w_bits_strb","wlast":"w_bits_last", + "bid":"b_bits_id","bresp":"b_bits_resp","arid":"ar_bits_id","araddr":"ar_bits_addr", + "arlen":"ar_bits_len","arsize":"ar_bits_size","arburst":"ar_bits_burst","rid":"r_bits_id", + "rdata":"r_bits_data","rresp":"r_bits_resp","rlast":"r_bits_last"} + connections=[".clock(clk)",".reset(reset)"] + for _,_,name in signals: + if name.startswith("ddr_"): + suffix=name[4:] + connections.append(f".{mapping.get(suffix,suffix.replace('ready','_ready').replace('valid','_valid'))}({name})") + lines += [' axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory (', + " "+",\n ".join(connections)+"\n );","endmodule"] + bench=OUT/"tb_board_cpu.sv" + bench.write_text("\n".join(lines)+"\n") + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",bench]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_cpu","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + result=subprocess.run([str(OUT/"obj/Vtb_board_cpu")],cwd=OUT,capture_output=True,text=True,timeout=180) + (OUT/"simulation.log").write_text(result.stdout+result.stderr) + print(result.stdout) + result.check_returncode() + assert "PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU" in result.stdout + record=dict(result="PASS",test=args.test,binary_sha256=hashlib.sha256(binary.read_bytes()).hexdigest(), + original_cpu_oracle=True,ddr_phy_simulated=False,physical_linux_boot_tested=False, + cycles=int(re.search(r"cycles=(\d+)",result.stdout)[1])) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/check_board_linux.py b/platforms/arty-a7-toy/scripts/check_board_linux.py new file mode 100644 index 0000000..9007ba9 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board_linux.py @@ -0,0 +1,91 @@ +"""Boot OpenSBI/Linux/BusyBox on the actual core and board AXI/SCU RTL. + +The external DDR PHY/CDC is a stalled AXI memory model. Loader start is forced +only in this bench; commands enter through the real 1 Mbps UART receiver. +""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-linux-final" + + +def main(): + OUT.mkdir(parents=True,exist_ok=True) + payload=ROOT/"build/board-software/fw_payload.bin" + # Chunked writes avoid creating a giant intermediate Python string. + with payload.open("rb") as src,(OUT/"payload.hex").open("w") as dst: + while data:=src.read(65536):dst.write("\n".join(f"{b:02x}" for b in data)+"\n") + bench=(ROOT/"build/board-cpu/tb_board_cpu.sv").read_text() + bench=bench.replace("tb_board_cpu","tb_board_linux") + bench=bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;") + first=bench.index(" if(exited &&") + last=bench.index(" end\n axi_smoke_memory",first) + bench=bench[:first]+" if(cycles>500000000) $fatal(1,\"Linux cycle watchdog\");\n"+bench[last:] + bench=bench.replace(".CAPACITY(262144)",".CAPACITY(268435456)") + bench=bench.replace('"smoke.hex"','"payload.hex"') + console=''' + reg [255:0] tail=0; + reg init_seen=0,prompt_seen=0; + integer characters=0; + always @(posedge clk) if(!reset && platform.mmio_tx_valid && platform.tx_ready && cpu_run) begin + tail={tail[247:0],platform.mmio_tx_data};characters=characters+1; + $write("%c",platform.mmio_tx_data);$fflush(); + if(tail[95:0]=="init process") init_seen=1; + if(init_seen && tail[15:0]==16'h2320) prompt_seen=1; + if(tail[183:0]=="PASS LINUX_SYSTEM_CHECK") begin + $display("\\nPASS BOARD_LINUX_USERSPACE cycles=%0d characters=%0d",cycles,characters);$finish; + end + if(tail[95:0]=="Kernel panic") $fatal(1,"Kernel panic"); + end + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer n=0;n<8;n=n+1) begin uart_rx_in=value[n];repeat(25) @(negedge clk);end + uart_rx_in=1;repeat(25) @(negedge clk); + // Allow the polled SBI/HVC console to drain its RAM-backed RX FIFO. + repeat(250000) @(negedge clk); + endtask + initial begin + wait(prompt_seen); + $display("\\nSIM_SHELL_PROMPT cycles=%0d",cycles);$fflush(); + send_byte("/");send_byte("r");send_byte("o");send_byte("o");send_byte("t");send_byte("/"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte("_"); + send_byte("s");send_byte("y");send_byte("s");send_byte("t");send_byte("e");send_byte("m");send_byte("_"); + send_byte("c");send_byte("h");send_byte("e");send_byte("c");send_byte("k");send_byte("-"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte(10); + $display("\\nSIM_COMMAND_SENT cycles=%0d overflow=%0d framing=%0d pending_rx=%0d",cycles, + platform.peripherals.overflow,platform.peripherals.framing,platform.peripherals.count);$fflush(); + if(platform.peripherals.overflow || platform.peripherals.framing) $fatal(1,"UART input loss"); + end +''' + bench=bench.replace("endmodule",console+"\nendmodule") + path=OUT/"tb_board_linux.sv" + path.write_text(bench) + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",path]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_linux","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + with (OUT/"simulation.log").open("w") as log: + result=subprocess.run([str(OUT/"obj/Vtb_board_linux")],cwd=OUT,stdout=log,stderr=log,timeout=3000) + transcript=(OUT/"simulation.log").read_text() + result.check_returncode() + required=["OpenSBI","Linux version","PASS VM_COPY_ON_WRITE","PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT","PASS LINUX_TIMER","PASS LINUX_SYSTEM_CHECK","PASS BOARD_LINUX_USERSPACE"] + for marker in required:assert marker in transcript,marker + record=dict(result="PASS_RTL_LINUX_USERSPACE",payload_sha256=hashlib.sha256(payload.read_bytes()).hexdigest(), + checks=required,physical_mig_simulated=False,physical_board_tested=False,uart_rx_command_tested=True) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(transcript[-2000:]) + + +if __name__=="__main__": + try: + main() + except Exception as error: + OUT.mkdir(parents=True,exist_ok=True) + (OUT/"RESULT.json").write_text(json.dumps(dict(result="FAIL",error=str(error),physical_board_tested=False),indent=2)+"\n") + raise diff --git a/platforms/arty-a7-toy/scripts/check_board_uart_boot.py b/platforms/arty-a7-toy/scripts/check_board_uart_boot.py new file mode 100644 index 0000000..7aafa66 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board_uart_boot.py @@ -0,0 +1,143 @@ +"""Load, byte-verify and boot the original CPU oracle through actual UART RTL. + +Only the external DDR PHY is replaced with the stalled AXI memory model. No +testbench override releases the CPU and no initial image is put into DDR. +""" +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/board-uart-boot" + +UART = r''' + reg [7:0] firmware[0:PROGRAM_BYTES-1]; + reg [7:0] reply_bytes[0:511]; + integer received=0; + reg run_requested=0; + initial $readmemh("program.hex",firmware); + // Independent receiver observes real TX transitions, not tx_valid/data. + always begin : receiver + reg [7:0] value; + @(negedge uart_tx_out); + repeat(37) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + value[bit_index]=uart_tx_out;repeat(25) @(negedge clk); + end + if(uart_tx_out!==1) $fatal(1,"UART TX framing error"); + if(!cpu_run) begin + if(received>=512) $fatal(1,"UART reply overflow"); + reply_bytes[received]=value;received=received+1; + end + end + always @(posedge clk) if(!reset && cpu_run && !run_requested) + $fatal(1,"CPU released before verified RUN request"); + function automatic [15:0] crc_step(input [15:0] previous,input [7:0] value); + reg [15:0] crc; + begin + crc=previous; + for(integer bit_index=7;bit_index>=0;bit_index=bit_index-1) + crc=(crc<<1)^((crc[15]^value[bit_index]) ? 16'h1021 : 16'd0); + crc_step=crc; + end + endfunction + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + uart_rx_in=value[bit_index];repeat(25) @(negedge clk); + end + uart_rx_in=1;repeat(25) @(negedge clk); + endtask + task automatic request(input [7:0] op,input integer offset,length,input bit corrupt); + reg [15:0] crc;reg [31:0] address;reg [7:0] value; + begin + received=0;crc=16'hffff;address=32'h80000000+offset; + send_byte(8'ha5);send_byte(8'h5a); + send_byte(op);crc=crc_step(crc,op); + send_byte(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(8*n);send_byte(value);crc=crc_step(crc,value); + end + value=length&255;send_byte(value);crc=crc_step(crc,value); + value=(length>>8)&255;send_byte(value);crc=crc_step(crc,value); + if(op==1) for(integer n=0;n=length+9); + if(reply_bytes[0]!==8'h5a || reply_bytes[1]!==8'ha5 || reply_bytes[2]!==(op|8'h80) || + reply_bytes[3]!==8'h37 || reply_bytes[4]!==status || {reply_bytes[6],reply_bytes[5]}!==length) + $fatal(1,"UART reply header/status op=%h status=%h count=%0d",op,reply_bytes[4],received); + crc=16'hffff; + for(integer n=2;n256) count=256; + request(1,offset,count,0);reply(1,0,0); + request(2,offset,count,0);reply(2,0,count); + for(integer n=0;n4000000", "cycles>120000000") + bench = bench.replace("endmodule", f" localparam PROGRAM_BYTES={len(data)};\n" + UART + "\nendmodule") + path = OUT / "tb_board_uart_boot.sv" + path.write_text(bench) + files = [ROOT / "build/serial-bound/ToyLinuxChip.sv", ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", path] + files += [p for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run(["verilator", "--binary", "--timing", "-j", "8", "-Wno-fatal", "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_board_uart_boot", "--Mdir", str(OUT / "obj")] + + [str(p) for p in files], stdout=log, stderr=log, check=True, timeout=900) + with (OUT / "simulation.log").open("w") as log: + result = subprocess.run([str(OUT / "obj/Vtb_board_uart_boot")], cwd=OUT, + stdout=log, stderr=log, timeout=1200) + result.check_returncode() + transcript = (OUT / "simulation.log").read_text() + for marker in ("PASS UART_PAYLOAD_READBACK", "PASS UART_VERIFIED_RUN", "PASS CPU Sv39/FPU/AMO/cache/interrupt"): + assert marker in transcript, marker + record = dict(result="PASS_UART_LOAD_VERIFY_BOOT", binary_sha256=hashlib.sha256(data).hexdigest(), + bytes_verified=len(data), testbench_cpu_release_override=False, preloaded_ddr_image=False, + physical_mig_simulated=False, physical_board_tested=False, + cycles=int(re.search(r"through board AXI/SCU cycles=(\d+)", transcript)[1])) + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/elaborate.sh b/platforms/arty-a7-toy/scripts/elaborate.sh new file mode 100644 index 0000000..a80d469 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/elaborate.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 scripts/prepare_sources.py "$@" +python3 scripts/resolve_config.py +sbt -batch 'runMain fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga' \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga' \ + 'runMain fpga.arty.linux.EmitRoutingCheck build/routing-check' +python3 scripts/prepare_fpga_memories.py build/serial-raw/ToyLinuxChip.sv --output-dir build/serial-bound +python3 scripts/bind_fpu_rf.py +python3 scripts/export_capabilities.py +python3 scripts/verify_target.py --core diff --git a/platforms/arty-a7-toy/scripts/export_capabilities.py b/platforms/arty-a7-toy/scripts/export_capabilities.py new file mode 100644 index 0000000..a68349c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/export_capabilities.py @@ -0,0 +1,52 @@ +"""Export software instruction definitions from the actual elaborated profile.""" + +import json +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) +original = json.loads((ROOT / "build/original-toy.json").read_text()) +entries = original["accelerator"]["ballDomain"]["ballISA"] +supported = set(profile["ball_funct7"]) +retained = [e for e in entries if e["funct7"] in supported] +assert {e["funct7"] for e in retained} == supported +assert all(e["bid"] in profile["ball_ids"] for e in retained) +out = ROOT / "build/software" +out.mkdir(parents=True, exist_ok=True) +header = ["#ifndef TOY_FPGA_BALL_ISA_H", "#define TOY_FPGA_BALL_ISA_H"] +header += [f"#define BB_FUNC7_{e['mnemonic']} {e['funct7']}" for e in retained] +header += ["#endif", ""] +(out / "ballISA.h").write_text("\n".join(header), encoding="utf-8", newline="\n") +(out / "CAPABILITIES.json").write_text( + json.dumps( + { + "balls": profile["ball_names"], + "gemmini_dimension": profile["gemmini_rows"], + "physical_bank_count": profile["bank_count"], + "virtual_bank_count": profile["virtual_bank_count"], + "bank_entries": profile["bank_rows"], + "bank_width": profile["bank_width"], + "l2_present": False, + "coherence_manager": profile["coherence_manager"], + "ball_isa": retained, + "removed_ball_isa": [e for e in entries if e["funct7"] not in supported], + "mvin_mmio_supported": profile["accelerator_mmio_scale_pool"], + "automatic_software_emulation": False, + "unsupported_rocc_instruction_trap_guaranteed": False, + }, + indent=2, + ) + + "\n", + encoding="utf-8", + newline="\n", +) +(out / "params.h").write_text( + f"#define BANK_WIDTH {profile['bank_width']}\n" + f"#define VIRTUAL_BANK_NUM {profile['virtual_bank_count']}\n" + f"#define PHYSICAL_BANK_NUM {profile['bank_count']}\n" + f"#define BANK_ENTRIES {profile['bank_rows']}\n" + f"#define GEMMINI_DIM {profile['gemmini_rows']}\n", + encoding="utf-8", + newline="\n", +) +print(f"Exported {len(retained)} Ball opcodes from the elaborated profile") diff --git a/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py new file mode 100644 index 0000000..6c2b253 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py @@ -0,0 +1,191 @@ +"""Bind CIRCT 1RW and 1R1W SRAM macros to synchronous FPGA RAM templates. + +The emitted CPU/operator RTL is not rewritten. Only compiler-declared external +memory modules receive implementations. Undefined read results during a write +or disabled cycle hold their previous value. No memory contents are reset. +""" + +import argparse +import hashlib +import json +import re +from pathlib import Path + + +def unpack_emission(raw): + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', raw) + rtl = [parts[0]] + metadata = None + config = None + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + rtl.append(body) + elif name == "metadata/seq_mems.json": + assert metadata is None + metadata = json.loads(body) + elif name.endswith("/memories.conf"): + assert config is None + config = body.strip() + "\n" + elif name == "firrtl_black_box_resource_files.f": + assert all(x.strip().endswith(".v") for x in body.splitlines() if x.strip()) + else: + raise ValueError(f"Unrecognized emitted section: {name}") + assert metadata and config, "Elaborate with --fpga-memories first" + return "\n".join(rtl), metadata, config + + +def validate(metadata, config): + entries = {} + for line in config.splitlines(): + words = line.split() + assert len(words) % 2 == 0 + row = dict(zip(words[::2], words[1::2])) + assert set(row) <= {"name", "depth", "width", "ports", "mask_gran"} + assert row["ports"] in ("rw", "mrw", "write,read", "mwrite,read"), row + assert row["name"] not in entries + entries[row["name"]] = row + assert len(entries) == len(metadata) + for mem in metadata: + name = mem["module_name"] + assert re.fullmatch(r"[A-Za-z_][A-Za-z0-9_]*", name) + topology = (mem["read"], mem["write"], mem["readwrite"]) + assert topology in ((0, 0, 1), (1, 1, 0)) + assert not mem["extra_ports"] + row = entries[name] + assert int(row["depth"]) == mem["depth"] > 1 + assert int(row["width"]) == mem["width"] > 0 + assert (row["ports"] in ("mrw", "mwrite,read")) == mem["masked"] + assert ("," in row["ports"]) == (topology == (1, 1, 0)) + if mem["masked"]: + gran = mem["mask_granularity"] + assert int(row["mask_gran"]) == gran and mem["width"] % gran == 0 + + +def emit_dual_memory(mem, style): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + mask = f",\n input [{lanes-1}:0] W0_mask" if mem["masked"] else "" + lines = [ + f"""module {name}( + input [{addr-1}:0] R0_addr, + input R0_en, R0_clk, + output reg [{width-1}:0] R0_data, + input [{addr-1}:0] W0_addr, + input W0_en, W0_clk, + input [{width-1}:0] W0_data{mask} +);""" + ] + # Split non-native masks into independent RAM lanes; keep both clocks. + write_enable = "W0_en && W0_mask[lane]" if mem["masked"] else "W0_en" + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge W0_clk)", + f" if ({write_enable}) ram[W0_addr] <= W0_data[lane*{gran} +: {gran}];", + " always @(posedge R0_clk)", + f" if (R0_en) R0_data[lane*{gran} +: {gran}] <= ram[R0_addr];", + " end", + "endmodule", + "", + ] + return "\n".join(lines), style + + +def emit_memory(mem): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks + # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. + style = "distributed" if depth <= 64 else "block" + if mem["read"] == 1: + return emit_dual_memory(mem, style) + ports = [ + f" input [{addr-1}:0] RW0_addr", + " input RW0_en, RW0_clk, RW0_wmode", + f" input [{width-1}:0] RW0_wdata", + f" output reg [{width-1}:0] RW0_rdata", + ] + if mem["masked"]: + ports.append(f" input [{lanes-1}:0] RW0_wmask") + lines = [f"module {name}(" + ",\n".join(ports) + "\n);"] + # Native byte masks share a wide array. Other mask widths get independent + # arrays so e.g. 17-bit L2 tags never require unsupported byte enables. + if not mem["masked"] or gran in (8, 9): + lines += [ + f' (* ram_style = "{style}" *) reg [{width-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + ] + if mem["masked"]: + lines += [ + f" for (integer lane = 0; lane < {lanes}; lane = lane + 1)", + " if (RW0_wmask[lane])", + f" ram[RW0_addr][lane*{gran} +: {gran}] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + ] + else: + lines.append(" ram[RW0_addr] <= RW0_wdata;") + lines += [ + " end else RW0_rdata <= ram[RW0_addr];", + " end", + " end", + ] + else: + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + " if (RW0_wmask[lane]) ram[RW0_addr] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + f" end else RW0_rdata[lane*{gran} +: {gran}] <= ram[RW0_addr];", + " end", + " end", + " end", + ] + return "\n".join(lines + ["endmodule", ""]), style + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("emission", type=Path) + parser.add_argument("--output-dir", type=Path, required=True) + args = parser.parse_args() + raw = args.emission.read_bytes() + rtl, metadata, config = unpack_emission(raw.decode()) + validate(metadata, config) + modules, mappings = [], [] + for mem in metadata: + module, style = emit_memory(mem) + modules.append(module) + mappings.append({**mem, "ram_style": style}) + macros = "\n".join(modules) + args.output_dir.mkdir(parents=True, exist_ok=True) + (args.output_dir / "ToyLinuxChip.sv").write_bytes(rtl.encode()) + (args.output_dir / "FpgaMemories.sv").write_bytes(macros.encode()) + (args.output_dir / "memories.conf").write_bytes(config.encode()) + record = { + "emitted_sha256": hashlib.sha256(raw).hexdigest(), + "core_rtl_sha256": hashlib.sha256(rtl.encode()).hexdigest(), + "memory_rtl_sha256": hashlib.sha256(macros.encode()).hexdigest(), + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": mappings, + } + (args.output_dir / "MEMORY_MANIFEST.json").write_text( + json.dumps(record, indent=2) + "\n" + ) + instances = sum(len(m["hierarchy"]) for m in metadata) + print(f"Bound {len(metadata)} memory types, {instances} instances") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/prepare_sources.py b/platforms/arty-a7-toy/scripts/prepare_sources.py new file mode 100644 index 0000000..127051c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/prepare_sources.py @@ -0,0 +1,151 @@ +"""Prepare pinned Buckyball sources without changing the FPGA checkout. + +Requires Git and curl. Existing exported files are verified, never overwritten. +Use --repository to reuse a local Git repository containing the baseline commit. +""" + +import argparse +import hashlib +import io +import json +import subprocess +import tarfile +from pathlib import Path, PurePosixPath + +ROOT = Path(__file__).resolve().parents[1] + + +def run(*args): + return subprocess.check_output(args, timeout=600) + + +def save(path, data): + if path.exists(): + if path.read_bytes() != data: + raise RuntimeError(f"Refusing to overwrite changed source: {path}") + return + path.parent.mkdir(parents=True, exist_ok=True) + path.write_bytes(data) + + +def prepare_upstream(repository): + manifest = json.loads((ROOT / "UPSTREAM_MANIFEST.json").read_text()) + commit = manifest["commit"] + if repository is None: + try: + checkout = Path( + run("git", "-C", str(ROOT), "rev-parse", "--show-toplevel") + .decode() + .strip() + ) + except subprocess.CalledProcessError: + checkout = None + candidates = [checkout / "thirdparty/buckyball", checkout] if checkout else [] + for candidate in candidates: + if (candidate / ".git").exists() and subprocess.run( + ["git", "-C", str(candidate), "cat-file", "-e", commit], + capture_output=True, + ).returncode == 0: + repository = candidate + break + if repository is None: + repository = ROOT / "build" / "baseline.git" + if not repository.exists(): + repository.mkdir(parents=True) + run("git", "init", "--bare", str(repository)) + if subprocess.run( + ["git", "-C", str(repository), "cat-file", "-e", commit], capture_output=True + ).returncode: + run( + "git", + "-C", + str(repository), + "fetch", + "--no-tags", + "--depth=1", + manifest["upstream_repository"], + commit, + ) + requests = "".join(f"{commit}:{name}\n" for name in manifest["files"]).encode() + output = subprocess.run( + ["git", "-C", str(repository), "cat-file", "--batch"], + input=requests, + stdout=subprocess.PIPE, + check=True, + ).stdout + stream = io.BytesIO(output) + for name, metadata in manifest["files"].items(): + expected = metadata["sha256"] + header = stream.readline().split() + if len(header) != 3 or header[1] != b"blob": + raise RuntimeError(f"Missing Git blob: {name}") + data = stream.read(int(header[2])) + assert stream.read(1) == b"\n" + if hashlib.sha256(data).hexdigest() != expected: + raise RuntimeError(f"Original source hash mismatch: {name}") + save(ROOT / "upstream" / name, data) + print(f"Verified {len(manifest['files'])} original Buckyball files at {commit}") + + +def prepare_dependencies(): + lock = json.loads((ROOT / "dependencies.json").read_text()) + cache = ROOT / "build" / "downloads" + cache.mkdir(parents=True, exist_ok=True) + for name, spec in lock.items(): + archive = cache / f"{name}-{spec['commit']}.tar.gz" + if not archive.exists(): + temporary = archive.with_suffix(".partial") + url = ( + f"https://codeload.github.com/{spec['repository']}" + f"/tar.gz/{spec['commit']}" + ) + run( + "curl", + "--fail", + "--location", + "--retry", + "2", + "--connect-timeout", + "15", + "--max-time", + "300", + "--output", + str(temporary), + url, + ) + temporary.replace(archive) + destination = ROOT / "thirdparty" / name + count = 0 + with tarfile.open(archive) as source: + for member in source: + if not member.isfile(): + continue + relative = PurePosixPath(*PurePosixPath(member.name).parts[1:]) + if ( + relative.is_absolute() + or ".." in relative.parts + or not relative.parts + ): + raise ValueError(f"Unsafe archive path: {member.name}") + subtree = spec.get("subtree") + if subtree and not ( + str(relative).startswith(subtree + "/") + or relative.name.upper().startswith( + ("LICENSE", "COPYING", "NOTICE") + ) + ): + continue + target = (destination / str(relative)).resolve() + if not target.is_relative_to(destination.resolve()): + raise ValueError(f"Archive path escapes destination: {member.name}") + save(target, source.extractfile(member).read()) + count += 1 + print(f"Verified/exported {name}: {count} files at {spec['commit']}") + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--repository", type=Path) + arguments = parser.parse_args() + prepare_upstream(arguments.repository) + prepare_dependencies() diff --git a/platforms/arty-a7-toy/scripts/resolve_config.py b/platforms/arty-a7-toy/scripts/resolve_config.py new file mode 100644 index 0000000..8ca4ee3 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/resolve_config.py @@ -0,0 +1,106 @@ +"""Read the pinned Toy TOMLs; emit inputs to the upstream parameter readers.""" + +import json +from pathlib import Path + +try: + import tomllib +except ModuleNotFoundError: + import tomli as tomllib + +ROOT = Path(__file__).resolve().parents[1] +UPSTREAM = ROOT / "upstream" + + +def read(path): + return tomllib.loads(path.read_text(encoding="utf-8")) + + +def resolve(): + tile_path = UPSTREAM / "examples/chips/toy/configs/designs/tiles/default.toml" + tile = read(tile_path) + assert len(tile["cores"]) == 1 + assert not tile["privateDCache"]["enable"] + assert not tile["sharedMem"]["enable"] + core_path = (tile_path.parent / tile["cores"][0]["include"]).resolve() + core = read(core_path) + cpu_path = core_path.parent / core["cpu"] + cpu_ref = read(cpu_path) + assert cpu_ref["kind"] == "rocket" + cpu = read(cpu_path.parent / cpu_ref["config"]) + mem = read(core_path.parent / core["memdomain"]) + front = read(core_path.parent / core["frontend"]) + domain_path = core_path.parent / core["balldomain"] + balls = read(domain_path) + for mapping in balls["ballIdMappings"]: + config = (domain_path.parent / mapping["config"]).resolve() + assert config.is_file() and config.is_relative_to(UPSTREAM.resolve()) + mapping["config"] = [config.relative_to(UPSTREAM.resolve()).as_posix()] + shared = tile["sharedMem"] + frontend_keys = { + "robEntries": "rob_entries", + "rsOutOfOrderResponse": "rs_out_of_order_response", + "bankIdLen": "bank_id_len", + "vbankIdUpperBound": "vbank_id_upper_bound", + "sharedBankIdBase": "shared_bank_id_base", + "iterLen": "iter_len", + "subRobEnable": "sub_rob_enable", + "subRobDepth": "sub_rob_depth", + } + result = { + "cpu": cpu, + "accelerator": { + "tile": { + k: tile[k] + for k in ( + "coreDataBytes", + "xLen", + "vaddrBits", + "paddrBits", + "pgIdxBits", + "pgLevels", + "nPMPs", + ) + }, + "frontend": {frontend_keys[k]: v for k, v in front.items()}, + "gpDomain": read(core_path.parent / core["gpdomain"]), + "ballDomain": balls, + "sim": {"diffTest": False}, + "memDomain": { + "bankNum": mem["bank"]["num"], + "bankWidth": mem["bank"]["width"], + "bankEntries": mem["bank"]["entries"], + "bankMaskLen": mem["bank"]["maskLen"], + # bbdev 2_parameter_derivation.py: explicit shared override, + # otherwise the largest private-bank count in this tile. + "virtualBankCount": shared.get("virtualBankCount", mem["bank"]["num"]), + "sharedEnable": shared["enable"], + "sharedEntries": shared["entries"], + "sharedBankNum": 0, + "sharedInputChannels": shared["inputChannels"], + "sharedDefaultGroupCount": shared["defaultGroupCount"], + "nCores": 1, + "tlb_size": mem["tlb"]["size"], + "dma_n_xacts": mem["dma"]["nXacts"], + "dma_burst_maxbytes": mem["dma"]["burstMaxBytes"], + "bankChannel": mem["bank"]["channel"], + "max_in_flight_mem_reqs": mem["dma"]["maxInFlightMemReqs"], + "dma_buswidth": mem["dma"]["busWidth"], + "memAddrLen": mem["mem"]["addrLen"], + "tmaReadChannel": mem["tma"]["readChannel"], + "tmaWriteChannel": mem["tma"]["writeChannel"], + **{"mmio" + k[0].upper() + k[1:]: v for k, v in mem["mmio"].items()}, + }, + }, + } + output = ROOT / "build/original-toy.json" + output.parent.mkdir(parents=True, exist_ok=True) + output.write_text(json.dumps(result, indent=2) + "\n", encoding="utf-8") + print( + f"Original Toy: VM={cpu['useVM']}, FPU={cpu['fpu']}, " + f"Balls={balls['ballNum']}, banks={mem['bank']}" + ) + + +if __name__ == "__main__": + resolve() diff --git a/platforms/arty-a7-toy/scripts/run_board_regression.py b/platforms/arty-a7-toy/scripts/run_board_regression.py new file mode 100644 index 0000000..6d17780 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/run_board_regression.py @@ -0,0 +1,14 @@ +"""Repeat the unchanged CPU/Gemmini/loop/DMA oracles through board RTL.""" +import json +from pathlib import Path +import subprocess +import sys + +ROOT=Path(__file__).resolve().parents[1] +subprocess.run([sys.executable,str(ROOT/"scripts/check_board.py")],check=True,timeout=180) +records={} +for name in ("cpu","gemmini","loop","dma"): + subprocess.run([sys.executable,str(ROOT/"scripts/check_board_cpu.py"),"--test",name],check=True,timeout=1000) + records[name]=json.loads((ROOT/("build/board-"+name)/"RESULT.json").read_text()) +(ROOT/"build/BOARD_REGRESSION.json").write_text(json.dumps(dict(result="PASS",tests=records),indent=2)+"\n") +print("PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA") diff --git a/platforms/arty-a7-toy/scripts/start_board_build.py b/platforms/arty-a7-toy/scripts/start_board_build.py new file mode 100644 index 0000000..f2b5ee0 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/start_board_build.py @@ -0,0 +1,84 @@ +"""Run the complete board flow in isolation with a one-hour hard timeout.""" +from datetime import datetime, timedelta, timezone +import argparse +import hashlib +import json +import os +from pathlib import Path +import subprocess +import sys +import time + +ROOT=Path(__file__).resolve().parents[1] +TZ=timezone(timedelta(hours=8)) +EXPECTED="4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def save(path, record): + temp=path.with_suffix(".tmp") + temp.write_text(json.dumps(record,indent=2)+"\n",encoding="utf-8") + temp.replace(path) + + +def worker(out): + manifest=out/"RUN.json" + record=json.loads(manifest.read_text()) + now=datetime.now(TZ) + script=Path(record.get("execution_script",str(ROOT/"board/build_board.tcl"))) + if "execution_script_sha256" in record: + assert sha(script)==record["execution_script_sha256"] + command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), + "-mode","batch","-source",str(script), + "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), + command=command,worker_pid=os.getpid()) + started=time.monotonic() + try: + with (out/"console.log").open("w") as log: + p=subprocess.Popen(command,cwd=ROOT,stdin=subprocess.DEVNULL,stdout=log, + stderr=subprocess.STDOUT,start_new_session=True) + record["timeout_process_pid"]=p.pid + save(manifest,record) + code=p.wait() + record.update(exit_code=code,status="TIMED_OUT" if code in (124,137) else "COMPLETED" if code==0 else "FAILED") + except Exception as e: + record.update(status="LAUNCH_FAILED",error=str(e)) + record.update(elapsed_seconds=time.monotonic()-started,finished_at=datetime.now(TZ).isoformat(), + core_unchanged=sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED, + bitstream_generated=(out/"toy_a7.bit").is_file()) + save(manifest,record) + + +def main(): + p=argparse.ArgumentParser(description=__doc__) + p.add_argument("--worker",type=Path) + args=p.parse_args() + if args.worker: + worker(args.worker.resolve());return + assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + for path in (ROOT/"build").glob("board-*/RUN.json"): + assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" + out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + # Snapshot the exact board sources used by this attempt, including failures. + import shutil + shutil.copytree(ROOT/"board",out/"inputs/board") + files={str(p.relative_to(ROOT)):sha(p) for p in (ROOT/"board").rglob("*") if p.is_file()} + record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, + output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, + board_sources=files,core_clock_hz=25000000,uart_baud=1000000, + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False) + save(out/"RUN.json",record) + with (out/"launcher.log").open("w") as log: + p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], + cwd=ROOT,stdout=log,stderr=subprocess.STDOUT,stdin=subprocess.DEVNULL, + start_new_session=True,close_fds=True) + print(json.dumps({"output_directory":str(out),"worker_pid":p.pid,"timeout_seconds":3600})) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_target.py b/platforms/arty-a7-toy/scripts/verify_target.py new file mode 100644 index 0000000..9bf24d8 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_target.py @@ -0,0 +1,73 @@ +"""Verify published sources/evidence and, optionally, the regenerated core.""" +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +EVIDENCE = ROOT / "evidence/2026-10-11" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core", action="store_true") + args = parser.parse_args() + lock = read(ROOT / "SOURCE_LOCK.json") + for name, expected in lock["files"].items(): + assert sha(ROOT / name) == expected, name + reference = read(ROOT / "tests/REFERENCE_MANIFEST.json") + for name, expected in reference["files"].items(): + assert sha(ROOT / "tests/reference" / name) == expected, name + vendor = read(ROOT / "board/vendor/MANIFEST.json") + for name, spec in vendor["files"].items(): + assert sha(ROOT / "board/vendor" / name) == spec["sha256"], name + record = read(EVIDENCE / "BOARD_RESULT.json") + assert record["result"] == "PASS_BOARD_IMPLEMENTATION_AND_RTL_REGRESSIONS" + assert record["part"] == "xc7a100tcsg324-1" + assert record["core_rtl_sha256"] == lock["core_rtl_sha256"] + assert record["gemmini_mesh_dsp"] == 64 + assert not record["physical_linux_boot_tested"] and not record["board_release_ready"] + for name, expected in record["board_sources"].items(): + if not name.endswith(".md"): + assert sha(ROOT / name) == expected, name + area = {} + labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Block RAM Tile": "BRAM_tiles", + "DSPs": "DSP", "Slice": "Slice"} + for line in (EVIDENCE / "implementation/routed-utilization.rpt").read_text().splitlines(): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + area[labels[fields[1]]] = float(fields[2]) + for name, value in area.items(): + assert value == record["routed_resources"][name], name + assert set(area) == set(labels.values()) + assert record["timing"]["wns_ns"] >= 0 and record["timing"]["whs_ns"] >= 0 + assert all(row["severity"] != "Critical" for row in record["cdc"]) + assert "nets with routing errors" in record["route_status"] + assert record["route_status"]["nets with routing errors"] == 0 + transcript = (EVIDENCE / "tests/linux-final/simulation.log").read_text() + for marker in record["linux"]["checks"]: + assert marker in transcript, marker + assert re.search(r"PASS BOARD_LINUX_USERSPACE cycles=273506752", transcript) + assert read(EVIDENCE / "tests/uart-boot/RESULT.json")["result"] == "PASS_UART_LOAD_VERIFY_BOOT" + if args.core: + assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == lock["core_rtl_sha256"] + assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == lock["memory_rtl_sha256"] + upstream = read(ROOT / "UPSTREAM_MANIFEST.json") + for name, metadata in upstream["files"].items(): + assert sha(ROOT / "upstream" / name) == metadata["sha256"], name + print(f"PASS Toy target: {len(lock['files'])} source hashes; published implementation and RTL evidence") + if args.core: + print("PASS regenerated Chisel core and FPGA memory/RF binding match the validated bytes") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/software/build.sh b/platforms/arty-a7-toy/software/build.sh new file mode 100644 index 0000000..1193069 --- /dev/null +++ b/platforms/arty-a7-toy/software/build.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash +# Build a real OpenSBI + Linux + BusyBox payload. Operator regression binaries +# still need to be installed before full Pebble acceptance can be claimed. +set -euo pipefail +cd "$(dirname "$0")/.." +python3 software/prepare_platform.py +python3 software/prepare_dependencies.py +mkdir -p build/software/bb-tests/output/workloads +riscv64-unknown-linux-gnu-gcc -O2 -Wall -Wextra -Werror -ffp-contract=off \ + -march=rv64gc -mabi=lp64d -static software/linux_system_check.c -lm \ + -o build/software/bb-tests/output/workloads/linux_system_check-linux +cmake -S build/software/bb-tests/workloads/lib/kernel \ + -B build/software/kernel-build \ + -DBUCKYBALL_VISIBLE_HART_COUNT=1 -DBUCKYBALL_TOTAL_HART_COUNT=1 \ + -DBUCKYBALL_KERNEL_INTERACTIVE=ON +cmake --build build/software/kernel-build --target kernel-build diff --git a/platforms/arty-a7-toy/software/linux_system_check.c b/platforms/arty-a7-toy/software/linux_system_check.c new file mode 100644 index 0000000..fa90a06 --- /dev/null +++ b/platforms/arty-a7-toy/software/linux_system_check.c @@ -0,0 +1,135 @@ +// Linux acceptance workload: processes, Sv39-backed memory and floating point. +// A host run validates the test program only; the FPGA run is the acceptance. +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void fail(const char *message) { + fprintf(stderr, "FAIL %s\n", message); + exit(1); +} + +static int wait_child(pid_t pid) { + int status; + pid_t result; + do { + result = waitpid(pid, &status, 0); + } while (result < 0 && errno == EINTR); + if (result != pid) + fail("waitpid"); + return status; +} + +static void check_virtual_memory(void) { + long page_size = sysconf(_SC_PAGESIZE); + if (page_size <= 0) + fail("page size"); + volatile unsigned char *memory = mmap(NULL, (size_t)page_size * 2, + PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (memory == MAP_FAILED) + fail("mmap"); + memory[0] = 0x42; + memory[page_size] = 0x7b; + + pid_t child = fork(); + if (child < 0) + fail("fork for copy-on-write"); + if (child == 0) { + if (memory[0] != 0x42) + _exit(2); + memory[0] = 0xa5; + _exit(memory[0] == 0xa5 ? 0 : 3); + } + int status = wait_child(child); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0 || memory[0] != 0x42) + fail("process isolation / copy-on-write"); + puts("PASS VM_COPY_ON_WRITE"); + + if (mprotect((void *)(memory + page_size), (size_t)page_size, PROT_NONE)) + fail("mprotect"); + child = fork(); + if (child < 0) + fail("fork for page fault"); + if (child == 0) { + volatile unsigned char forbidden = memory[page_size]; + (void)forbidden; + _exit(4); + } + status = wait_child(child); + if (!WIFSIGNALED(status) || WTERMSIG(status) != SIGSEGV) + fail("protected page must deliver SIGSEGV"); + if (mprotect((void *)(memory + page_size), (size_t)page_size, PROT_READ)) + fail("restore page access"); + if (memory[page_size] != 0x7b) + fail("page contents after protection change"); + if (munmap((void *)memory, (size_t)page_size * 2)) + fail("munmap"); + puts("PASS VM_PAGE_PROTECTION"); +} + +static int float_work(double seed) { + volatile double scale = 1.5; + double value = seed; + for (int i = 0; i < 1000; ++i) { + value = value * scale + 0.25; + if (sched_yield()) + return 1; + value = (value - 0.25) / scale; + if (!isfinite(value) || fabs(value - seed) > 1e-10) + return 1; + } + return 0; +} + +static void check_float_context(void) { + pid_t child = fork(); + if (child < 0) + fail("fork for floating-point context"); + if (child == 0) + _exit(float_work(-3.125)); + int parent_result = float_work(7.25); + int status = wait_child(child); + if (parent_result || !WIFEXITED(status) || WEXITSTATUS(status)) + fail("floating-point arithmetic/context"); + puts("PASS FP64_PROCESS_CONTEXT"); +} + +static void check_timer(void) { + struct timespec before, after, remaining = {0, 100000000}; + if (clock_gettime(CLOCK_MONOTONIC, &before)) + fail("clock_gettime start"); + while (nanosleep(&remaining, &remaining)) { + if (errno != EINTR) + fail("nanosleep"); + } + if (clock_gettime(CLOCK_MONOTONIC, &after)) + fail("clock_gettime end"); + int64_t elapsed = (after.tv_sec - before.tv_sec) * INT64_C(1000000000) + + after.tv_nsec - before.tv_nsec; + if (elapsed < 100000000) + fail("monotonic timer / scheduled wakeup"); + printf("PASS LINUX_TIMER elapsed_ns=%lld\n", (long long)elapsed); +} + +int main(void) { + const struct rlimit no_core_dump = {0, 0}; + if (setrlimit(RLIMIT_CORE, &no_core_dump)) + fail("disable expected-fault core dumps"); + setvbuf(stdout, NULL, _IONBF, 0); + puts("BEGIN LINUX_SYSTEM_CHECK"); + check_virtual_memory(); + check_float_context(); + check_timer(); + puts("PASS LINUX_SYSTEM_CHECK"); + return 0; +} diff --git a/platforms/arty-a7-toy/software/prepare_dependencies.py b/platforms/arty-a7-toy/software/prepare_dependencies.py new file mode 100644 index 0000000..b00cbfb --- /dev/null +++ b/platforms/arty-a7-toy/software/prepare_dependencies.py @@ -0,0 +1,67 @@ +"""Fetch the three pinned OS dependencies into this platform's build directory.""" + +import json +import subprocess +import tarfile +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +BASELINE = json.loads((ROOT / "SOFTWARE_BASELINE.json").read_text()) +REPOSITORIES = { + "linux": "firesim/linux", + "opensbi": "riscv-software-src/opensbi", + "busybox": "mirror/busybox", +} + + +def main(): + cache = ROOT / "build/downloads" + cache.mkdir(parents=True, exist_ok=True) + destination = ROOT / "build/software/bb-tests/thirdparty" + destination.mkdir(parents=True, exist_ok=True) + for name, repository in REPOSITORIES.items(): + commit = BASELINE[name] + target = destination / name + marker = destination / f"{name}.commit" + if target.exists(): + if not marker.exists() or marker.read_text().strip() != commit: + raise RuntimeError(f"Unrecognized existing source directory: {target}") + print(f"Reusing {name} at {commit}", flush=True) + continue + archive = cache / f"{name}-{commit}.tar.gz" + if not archive.exists(): + temporary = archive.with_suffix(".partial") + subprocess.run( + [ + "curl", + "--fail", + "--location", + "--retry", + "2", + "--connect-timeout", + "15", + "--max-time", + "600", + f"https://codeload.github.com/{repository}/tar.gz/{commit}", + "--output", + str(temporary), + ], + check=True, + ) + temporary.replace(archive) + staging = destination / f".extract-{name}-{commit}" + staging.mkdir(exist_ok=True) + with tarfile.open(archive) as source: + prefixes = {member.name.split("/")[0] for member in source.getmembers()} + assert len(prefixes) == 1, "Expected one Git archive root" + prefix = prefixes.pop() + assert prefix not in ("", ".", "..") + source.extractall(staging, filter="data") + (staging / prefix).rename(target) + staging.rmdir() + marker.write_text(commit + "\n") + print(f"Prepared {repository} at {commit}", flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/software/prepare_platform.py b/platforms/arty-a7-toy/software/prepare_platform.py new file mode 100644 index 0000000..a05b0a2 --- /dev/null +++ b/platforms/arty-a7-toy/software/prepare_platform.py @@ -0,0 +1,89 @@ +"""Prepare the original bbkernel with board memory/timebase adaptations only. + +This prepares sources, not a kernel image. It never modifies a shared checkout. +""" + +import hashlib +import io +import json +import tarfile +import urllib.request +from pathlib import Path, PurePosixPath + +ROOT = Path(__file__).resolve().parents[1] +BASELINE = json.loads((ROOT / "SOFTWARE_BASELINE.json").read_text()) +OUTPUT = ROOT / "build/software/bb-tests/workloads/lib/kernel" + + +def prepare(): + commit = BASELINE["bbkernel"] + url = f"https://codeload.github.com/DangoSys/bbkernel/tar.gz/{commit}" + cache = ROOT / "build/downloads" / f"bbkernel-{commit}.tar.gz" + cache.parent.mkdir(parents=True, exist_ok=True) + if not cache.exists(): + with urllib.request.urlopen(url, timeout=60) as response: + archive = response.read() + cache.write_bytes(archive) + changes = { + "opensbi-platform/buckyball/platform.c": ( + b"#define BUCKYBALL_MTIMER_FREQ 10000000", + b"#define BUCKYBALL_MTIMER_FREQ 1000000", + ), + "config/linux-config": (b"mem=512M", b"mem=256M"), + } + records = {} + with tarfile.open(fileobj=io.BytesIO(cache.read_bytes())) as source: + for member in source: + if not member.isfile(): + continue + relative = PurePosixPath(*PurePosixPath(member.name).parts[1:]) + if not relative.parts or relative.is_absolute() or ".." in relative.parts: + raise ValueError(f"Unsafe archive member: {member.name}") + data = source.extractfile(member).read() + original = hashlib.sha256(data).hexdigest() + name = relative.as_posix() + if name in changes: + before, after = changes[name] + if data.count(before) != 1: + raise ValueError( + f"Expected exactly one board adaptation site: {name}" + ) + data = data.replace(before, after) + target = OUTPUT / name + if target.exists() and target.read_bytes() != data: + raise RuntimeError( + f"Refusing to overwrite changed platform source: {target}" + ) + target.parent.mkdir(parents=True, exist_ok=True) + target.write_bytes(data) + records[name] = { + "original_sha256": original, + "fpga_sha256": hashlib.sha256(data).hexdigest(), + } + assert changes.keys() <= records.keys() + config = (OUTPUT / "config/linux-config").read_text() + for required in ( + "CONFIG_RISCV_ROCC=y", + "CONFIG_HVC_RISCV_SBI=y", + "CONFIG_RISCV_SBI_V01=y", + ): + assert required in config, required + result = { + "repository": "https://github.com/DangoSys/bbkernel", + "commit": commit, + "archive_sha256": hashlib.sha256(cache.read_bytes()).hexdigest(), + "adaptations": {"clint_hz": 1000000, "memory_limit_mib": 256}, + "files": records, + "kernel_image_built": False, + } + (ROOT / "build/software/SOURCE_MANIFEST.json").write_text( + json.dumps(result, indent=2) + "\n" + ) + print( + f"Prepared {len(records)} pinned bbkernel files; " + "two board adaptations; no image built" + ) + + +if __name__ == "__main__": + prepare() diff --git a/platforms/arty-a7-toy/src/main/scala/EmitFmaChecks.scala b/platforms/arty-a7-toy/src/main/scala/EmitFmaChecks.scala new file mode 100644 index 0000000..5cc26c7 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitFmaChecks.scala @@ -0,0 +1,74 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile._ +import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} +import framework.system.tile.BBTileAttachParams + +class FmaPrecisionCheck(implicit p: Parameters) extends Module { + val valid = IO(Input(Bool())) + val tag = IO(Input(UInt(2.W))) + val kind = IO(Input(UInt(2.W))) // 0=FMA, 1=add/subtract, 2=multiply + val op = IO(Input(UInt(2.W))) + val rm = IO(Input(UInt(3.W))) + val a = IO(Input(UInt(64.W))) + val b = IO(Input(UInt(64.W))) + val c = IO(Input(UInt(64.W))) + val expected = IO(Output(UInt(64.W))) + val actual = IO(Output(UInt(64.W))) + val expectedFlags = IO(Output(UInt(5.W))) + val actualFlags = IO(Output(UInt(5.W))) + val outValid = IO(Output(Bool())) + val equal = IO(Output(Bool())) + val types = Seq(FType.H, FType.S, FType.D) + val inputs = types.zipWithIndex.map { case (t, index) => + val in = Wire(new FPInput) + in := 0.U.asTypeOf(new FPInput) + in.ren3 := kind === 0.U + in.swap23 := kind === 1.U + in.typeTagIn := index.U + in.typeTagOut := index.U + in.fmaCmd := op + in.rm := rm + in.in1 := t.recode(a(t.ieeeWidth - 1, 0)) + in.in2 := t.recode(b(t.ieeeWidth - 1, 0)) + in.in3 := t.recode(c(t.ieeeWidth - 1, 0)) + in + } + val refs = types.zipWithIndex.map { case (t, index) => + val latency = if (t == FType.D) 6 else 5 + val unit = Module(new FPUFMAPipe(latency, t)) + unit.io.in.valid := valid && tag === index.U + unit.io.in.bits := inputs(index) + Pipe(unit.io.out, 6 - latency) + } + val shared = Module(new FPUSharedFMAPipe(6)) + shared.io.in.valid := valid + shared.io.in.bits := VecInit(inputs)(tag) + val outputTag = Pipe(valid, tag, 6) + val originalData = VecInit(types.zip(refs).map { case (t, r) => t.ieee(r.bits.data(t.recodedWidth - 1, 0)).pad(64) }) + val sharedData = VecInit(types.map(t => t.ieee(shared.io.out.bits.data(t.recodedWidth - 1, 0)).pad(64))) + expected := originalData(outputTag.bits) + actual := sharedData(outputTag.bits) + expectedFlags := VecInit(refs.map(_.bits.exc))(outputTag.bits) + actualFlags := shared.io.out.bits.exc + outValid := shared.io.out.valid + equal := shared.io.out.valid === outputTag.valid && + (!outputTag.valid || (expected === actual && expectedFlags === actualFlags)) +} + +object EmitFmaChecks extends App { + val base: Parameters = new ToyLinux8x8Config().toInstance + val tile = base(TilesLocated(InSubsystem)).collect { + case attachment: BBTileAttachParams => attachment.tileParams + }.head + implicit val p: Parameters = base.alterPartial { + case TileKey => tile.copy(core = tile.rocketCorePerCore.head) + } + ChiselStage.emitSystemVerilogFile(new FmaPrecisionCheck, + Array("--target-dir", "build/fma-check"), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/src/main/scala/EmitGroupQueryCheck.scala b/platforms/arty-a7-toy/src/main/scala/EmitGroupQueryCheck.scala new file mode 100644 index 0000000..f247b74 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitGroupQueryCheck.scala @@ -0,0 +1,45 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.memdomain.frontend.MemGroupQueryArbiter + +class GroupQueryCheck extends Module { + val passed = IO(Output(Bool())) + val dut = Module(new MemGroupQueryArbiter(4, 4)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 10000.U, "Group query arbitration timeout") + def lookup(bank: UInt, shared: Bool): UInt = + ((bank ^ Mux(shared, 4.U, 0.U))(2, 0) +& 1.U) + dut.io.backendCount := RegNext(RegNext(lookup(dut.io.backendBank, dut.io.backendShared), 0.U), 0.U) + val sent = RegInit(VecInit(Seq.fill(2)(0.U(8.W)))) + val received = RegInit(VecInit(Seq.fill(2)(0.U(8.W)))) + for (i <- 0 until 2) { + val expected = Module(new Queue(UInt(4.W), 4)) + dut.io.request(i).valid := sent(i) < 128.U + dut.io.request(i).bits.bank := sent(i)(3, 0) ^ (i * 7).U + dut.io.request(i).bits.shared := sent(i)(4) ^ (i == 1).B + expected.io.enq.valid := dut.io.request(i).fire + expected.io.enq.bits := lookup(dut.io.request(i).bits.bank, dut.io.request(i).bits.shared) + dut.io.response(i).ready := cycle(i + 1) && cycle(0) + expected.io.deq.ready := dut.io.response(i).fire + when(dut.io.request(i).fire) { + assert(expected.io.enq.ready) + sent(i) := sent(i) + 1.U + } + when(dut.io.response(i).valid) { + assert(expected.io.deq.valid, "Query reply without an accepted request") + assert(dut.io.response(i).bits === expected.io.deq.bits, "Reply belongs to another bank/client") + } + when(dut.io.response(i).fire) { received(i) := received(i) + 1.U } + } + passed := received.map(_ === 128.U).reduce(_ && _) +} + +object EmitGroupQueryCheck extends App { + ChiselStage.emitSystemVerilogFile(new GroupQueryCheck, + Array("--target-dir", args.headOption.getOrElse("build/group-query-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/src/main/scala/EmitPeChecks.scala b/platforms/arty-a7-toy/src/main/scala/EmitPeChecks.scala new file mode 100644 index 0000000..8ee77d7 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitPeChecks.scala @@ -0,0 +1,59 @@ +package fpga.arty.linux + +import chisel3._ +import circt.stage.ChiselStage +import gemmini._ + +class QuantizerEquivalence extends RawModule { + val value = IO(Input(SInt(20.W))) + val amount = IO(Input(UInt(5.W))) + val equal = IO(Output(Bool())) + val reference = IO(Output(SInt(20.W))) + val actual = IO(Output(SInt(20.W))) + import Arithmetic.SIntArithmetic._ + reference := cast(value.pad(32)).>>(amount).clippedToWidthOf(0.S(20.W)) + actual := FpgaRoundShift(value, amount) + equal := reference === actual +} + +class PeCycleEquivalence extends Module { + val original = Module(new ReferencePE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4)) + val logic = Module(new PE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4, fpgaDsp = false)) + val dsp = Module(new PE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4, fpgaDsp = true)) + val in_a = IO(Input(SInt(8.W))) + val in_b = IO(Input(SInt(20.W))) + val in_d = IO(Input(SInt(20.W))) + val control = IO(Input(new PEControl(SInt(32.W)))) + val id = IO(Input(UInt(2.W))) + val last = IO(Input(Bool())) + val valid = IO(Input(Bool())) + // Explicit wiring keeps all three independently emitted implementations. + original.io.in_a := in_a; logic.io.in_a := in_a; dsp.io.in_a := in_a + original.io.in_b := in_b; logic.io.in_b := in_b; dsp.io.in_b := in_b + original.io.in_d := in_d; logic.io.in_d := in_d; dsp.io.in_d := in_d + original.io.in_control := control; logic.io.in_control := control; dsp.io.in_control := control + original.io.in_id := id; logic.io.in_id := id; dsp.io.in_id := id + original.io.in_last := last; logic.io.in_last := last; dsp.io.in_last := last + original.io.in_valid := valid; logic.io.in_valid := valid; dsp.io.in_valid := valid + val equal = IO(Output(Bool())) + equal := (original.io.out_b === logic.io.out_b && original.io.out_c === logic.io.out_c && + original.io.out_b === dsp.io.out_b && original.io.out_c === dsp.io.out_c && + original.io.out_a === logic.io.out_a && original.io.out_a === dsp.io.out_a && + original.io.out_control.asUInt === logic.io.out_control.asUInt && + original.io.out_control.asUInt === dsp.io.out_control.asUInt && + original.io.out_id === logic.io.out_id && original.io.out_id === dsp.io.out_id && + original.io.out_last === logic.io.out_last && original.io.out_last === dsp.io.out_last && + original.io.out_valid === logic.io.out_valid && original.io.out_valid === dsp.io.out_valid && + original.io.bad_dataflow === logic.io.bad_dataflow && original.io.bad_dataflow === dsp.io.bad_dataflow) +} + +object EmitPeChecks extends App { + val opts = Array("-disable-all-randomization", "-strip-debug-info") + ChiselStage.emitSystemVerilogFile(new QuantizerEquivalence, + Array("--target-dir", "build/pe-checks/quantizer"), opts) + ChiselStage.emitSystemVerilogFile(new PeCycleEquivalence, + Array("--target-dir", "build/pe-checks/cycles"), opts) +} diff --git a/platforms/arty-a7-toy/src/main/scala/EmitRoundShiftChecks.scala b/platforms/arty-a7-toy/src/main/scala/EmitRoundShiftChecks.scala new file mode 100644 index 0000000..27e1a2f --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitRoundShiftChecks.scala @@ -0,0 +1,27 @@ +package fpga.arty.linux + +import chisel3._ +import circt.stage.ChiselStage +import gemmini._ + +/** Check both the existing PE width and the final WS accumulator width. */ +class RoundShiftChecks extends RawModule { + val value20 = IO(Input(SInt(20.W))) + val value32 = IO(Input(SInt(32.W))) + val amount = IO(Input(UInt(5.W))) + val actual20 = IO(Output(SInt(20.W))) + val actual32 = IO(Output(SInt(32.W))) + val original20 = IO(Output(SInt(20.W))) + val original32 = IO(Output(SInt(32.W))) + import Arithmetic.SIntArithmetic._ + actual20 := FpgaRoundShift(value20, amount) + actual32 := FpgaRoundShift(value32, amount) + original20 := cast(value20.pad(32)).>>(amount).clippedToWidthOf(0.S(20.W)) + original32 := cast(value32).>>(amount).clippedToWidthOf(0.S(32.W)) +} + +object EmitRoundShiftChecks extends App { + ChiselStage.emitSystemVerilogFile(new RoundShiftChecks, + Array("--target-dir", "build/round-check"), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/src/main/scala/EmitRoutingCheck.scala b/platforms/arty-a7-toy/src/main/scala/EmitRoutingCheck.scala new file mode 100644 index 0000000..d843105 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitRoutingCheck.scala @@ -0,0 +1,122 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.memdomain.midend.MemMidend +import framework.memdomain.backend.accpipe.AccPipe + +// Real routing and AccPipe modules, with independently checked SRAM endpoints. +// Stalls cover request acceptance, SRAM response, and final response consumption. +class RoutingCheck extends Module { + val passed = IO(Output(Bool())) + val b = OriginalToy.serial + val midend = Module(new MemMidend(b)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 20000.U, "Routing regression timeout") + midend.io.hartid := 0.U + midend.io.inst_ids.zipWithIndex.foreach { case (id, index) => id := (100 + index).U } + val readSent = RegInit(VecInit(Seq.fill(3)(0.U(7.W)))) + val readSeen = RegInit(VecInit(Seq.fill(3)(0.U(7.W)))) + val writeSent = RegInit(VecInit(Seq.fill(5)(0.U(7.W)))) + val writeSeen = RegInit(VecInit(Seq.fill(5)(0.U(7.W)))) + val ballAccepted = readSent.take(2).map(_ === 64.U).reduce(_ && _) && + writeSent.take(4).map(_ === 64.U).reduce(_ && _) + // Release the Ball as soon as its final requests are accepted, while responses + // can still be in flight. Fixed routes must keep delivering these responses. + midend.io.ballChannelActive(0) := !ballAccepted + for (port <- 0 until 3) { + val source = midend.io.bankRead(port) + val bank = if (port < 2) port else 6 + source.is_shared := false.B + source.bankRead.bank_id := bank.U + source.bankRead.group_id := 0.U + source.bankRead.ball_id := 0.U + source.bankRead.rob_id := (port % 4).U + source.bankRead.io.req.valid := readSent(port) < 64.U + source.bankRead.io.req.bits.addr := readSent(port) + source.bankRead.io.resp.ready := cycle((port + 1) % 5) + when(source.bankRead.io.req.fire) { readSent(port) := readSent(port) + 1.U } + when(source.bankRead.io.resp.fire) { + assert(source.bankRead.io.resp.bits.data === + (readSeen(port) + (bank << 16).U), "Read response lost or misrouted") + readSeen(port) := readSeen(port) + 1.U + } + } + for (port <- 0 until 5) { + val source = midend.io.bankWrite(port) + val bank = if (port < 4) port + 2 else 7 + source.is_shared := false.B + source.bankWrite.bank_id := bank.U + source.bankWrite.group_id := (port % 4).U + source.bankWrite.ball_id := 0.U + source.bankWrite.rob_id := (port % 4).U + source.bankWrite.io.req.valid := writeSent(port) < 64.U && + (if (port == 4) cycle >= 1.U else true.B) + source.bankWrite.io.req.bits.addr := writeSent(port) + source.bankWrite.io.req.bits.data := writeSent(port) + (bank << 16).U + source.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + source.bankWrite.io.resp.ready := cycle((port + 2) % 5) + when(source.bankWrite.io.req.fire) { writeSent(port) := writeSent(port) + 1.U } + when(source.bankWrite.io.resp.fire) { + assert(source.bankWrite.io.resp.bits.ok, "Write response lost or misrouted") + writeSeen(port) := writeSeen(port) + 1.U + } + } + for (channel <- 0 until 7) { + val request = midend.io.mem_req(channel) + val pipe = Module(new AccPipe(b)) + pipe.io.mem_req <> request + pipe.io.is_multi := false.B + val readPending = RegInit(false.B) + val writePending = RegInit(false.B) + val readData = Reg(UInt(b.memDomain.bankWidth.W)) + val routePending = RegInit(false.B) + val routeBank = Reg(UInt(b.memDomain.vbankIdWidth.W)) + when(!routePending && !pipe.io.busy && + (request.read.req.valid || request.write.req.valid)) { + routePending := true.B + routeBank := request.bank_id + } + when(request.read.req.fire || request.write.req.fire) { routePending := false.B } + pipe.io.sramRead.req.ready := routePending && !readPending && !writePending && cycle(channel % 5) + pipe.io.sramWrite.req.ready := routePending && !readPending && !writePending && cycle((channel + 1) % 5) + pipe.io.sramRead.resp.valid := readPending && cycle((channel + 3) % 5) + pipe.io.sramRead.resp.bits.data := readData + pipe.io.sramWrite.resp.valid := writePending && cycle((channel + 4) % 5) + pipe.io.sramWrite.resp.bits.ok := true.B + when(pipe.io.sramRead.req.fire) { + readPending := true.B + readData := pipe.io.sramRead.req.bits.addr + (routeBank << 16) + assert(request.bank_id === routeBank, "Route metadata changed before SRAM acceptance") + assert(request.bank_id === (if (channel < 2) channel else 6).U) + assert(request.group_id === 0.U) + assert(request.rob_id === (if (channel < 2) channel else 2).U) + assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U) + } + when(pipe.io.sramWrite.req.fire) { + writePending := true.B + assert(request.bank_id === routeBank, "Write replaced a pending read route") + val bank = if (channel < 6) channel else 7 + assert(request.bank_id === bank.U, "Wrong write bank metadata") + assert(pipe.io.sramWrite.req.bits.data === + (pipe.io.sramWrite.req.bits.addr + (bank << 16).U)) + assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR) + val port = if (channel < 6) math.max(0, channel - 2) else 4 + assert(request.group_id === (port % 4).U) + assert(request.rob_id === (port % 4).U) + assert(request.inst_id === (100 + port % 4).U) + } + when(pipe.io.sramRead.resp.fire) { readPending := false.B } + when(pipe.io.sramWrite.resp.fire) { writePending := false.B } + assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire)) + } + passed := (readSeen ++ writeSeen).map(_ === 64.U).reduce(_ && _) +} + +object EmitRoutingCheck extends App { + ChiselStage.emitSystemVerilogFile(new RoutingCheck, + args = Array("--target-dir", args.head), + firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/src/main/scala/EmitSubRobCheck.scala b/platforms/arty-a7-toy/src/main/scala/EmitSubRobCheck.scala new file mode 100644 index 0000000..7d0b2e0 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitSubRobCheck.scala @@ -0,0 +1,59 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.SubROB + +/** Stream more than the FIFO depth, including empty rows and stalled completion. */ +class SubRobCheck extends Module { + val passed = IO(Output(Bool())) + val sub = Module(new SubROB(OriginalToy.serial)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 10000.U, "SubROB streaming timeout") + val sent = RegInit(0.U(6.W)) + val issued = RegInit(0.U(6.W)) + val completed = RegInit(0.U(6.W)) + val masters = RegInit(0.U(2.W)) + val expected = (0 until 40).flatMap { row => + if (row % 3 == 0) Seq.empty else if (row % 3 == 1) Seq(row * 4) else Seq(row * 4, row * 4 + 1) + } + val commands = VecInit(expected.map(_.U(32.W))) + sub.io.write.valid := sent < 40.U + sub.io.write.bits := 0.U.asTypeOf(sub.io.write.bits) + sub.io.write.bits.master_rob_id := 3.U + sub.io.write.bits.ball_id := 0.U + for (slot <- 0 until 4) { + sub.io.write.bits.slots(slot).valid := + (if (slot == 0) sent % 3.U =/= 0.U else if (slot == 1) sent % 3.U === 2.U else false.B) + sub.io.write.bits.slots(slot).cmd.cmd.raw_inst := sent * 4.U + slot.U + } + when(sub.io.write.fire) { sent := sent + 1.U } + val pending = Module(new Queue(UInt(5.W), 8)) + sub.io.issue.ready := pending.io.enq.ready && cycle(0) + pending.io.enq.valid := sub.io.issue.fire + pending.io.enq.bits := sub.io.issueSubId + sub.io.subComplete.valid := pending.io.deq.valid && cycle(1) + sub.io.subComplete.bits := pending.io.deq.bits + pending.io.deq.ready := sub.io.subComplete.ready && cycle(1) + when(sub.io.issue.fire) { + assert(issued < expected.size.U) + assert(sub.io.issue.bits.cmd.raw_inst === commands(issued), "SubROB dropped/reordered a row") + issued := issued + 1.U + } + when(sub.io.subComplete.fire) { completed := completed + 1.U } + sub.io.masterComplete.ready := cycle(2) + when(sub.io.masterComplete.fire) { + assert(sent === 40.U && issued === expected.size.U && completed === expected.size.U, + "SubROB completed master before all accepted rows were executed") + masters := masters + 1.U + } + passed := masters === 1.U +} + +object EmitSubRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new SubRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/subrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/src/main/scala/ReferencePE.scala b/platforms/arty-a7-toy/src/main/scala/ReferencePE.scala new file mode 100644 index 0000000..463bdda --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/ReferencePE.scala @@ -0,0 +1,137 @@ +package gemmini +import chisel3._ +import chisel3.util._ +class ReferenceMacUnit[T <: Data](inputType: T, weightType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { + import ev._ + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(weightType) + val in_c = Input(cType) + val out_d = Output(dType) + }) + + io.out_d := io.in_c.mac(io.in_a, io.in_b) +} + +// TODO update documentation +/** + * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. + * @param width Data width of operands + */ +class ReferencePE[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) + (implicit ev: Arithmetic[T]) extends Module { // Debugging variables + import ev._ + + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(outputType) + val in_d = Input(outputType) + val out_a = Output(inputType) + val out_b = Output(outputType) + val out_c = Output(outputType) + + val in_control = Input(new PEControl(accType)) + val out_control = Output(new PEControl(accType)) + + val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) + val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) + + val in_last = Input(Bool()) + val out_last = Output(Bool()) + + val in_valid = Input(Bool()) + val out_valid = Output(Bool()) + + val bad_dataflow = Output(Bool()) + }) + + val cType = if (df == Dataflow.WS) inputType else accType + + // When creating PEs that support multiple dataflows, the + // elaboration/synthesis tools often fail to consolidate and de-duplicate + // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" + // module here which just performs a single MAC operation + val mac_unit = Module(new ReferenceMacUnit(inputType, weightType, + if (df == Dataflow.WS) outputType else accType, outputType)) + + val a = io.in_a + val b = io.in_b + val d = io.in_d + val c1 = Reg(cType) + val c2 = Reg(cType) + val dataflow = io.in_control.dataflow + val prop = io.in_control.propagate + val shift = io.in_control.shift + val id = io.in_id + val last = io.in_last + val valid = io.in_valid + + io.out_a := a + io.out_control.dataflow := dataflow + io.out_control.propagate := prop + io.out_control.shift := shift + io.out_id := id + io.out_last := last + io.out_valid := valid + + mac_unit.io.in_a := a + + val last_s = RegEnable(prop, valid) + val flip = last_s =/= prop + val shift_offset = Mux(flip, shift, 0.U) + + // Which dataflow are we using? + val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) + val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) + + // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? + val COMPUTE = 0.U(1.W) + val PROPAGATE = 1.U(1.W) + + io.bad_dataflow := false.B + when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + c2 := mac_unit.io.out_d + c1 := d.withWidthOf(cType) + }.otherwise { + io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c1 + c1 := mac_unit.io.out_d + c2 := d.withWidthOf(cType) + } + }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := c1 + mac_unit.io.in_b := c2.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c1 := d + }.otherwise { + io.out_c := c2 + mac_unit.io.in_b := c1.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c2 := d + } + }.otherwise { + io.bad_dataflow := true.B + //assert(false.B, "unknown dataflow") + io.out_c := DontCare + io.out_b := DontCare + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + } + + when (!valid) { + c1 := c1 + c2 := c2 + mac_unit.io.in_b := DontCare + mac_unit.io.in_c := DontCare + } +} diff --git a/platforms/arty-a7-toy/src/main/scala/ToyLinuxChip.scala b/platforms/arty-a7-toy/src/main/scala/ToyLinuxChip.scala new file mode 100644 index 0000000..5c9dbb5 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/ToyLinuxChip.scala @@ -0,0 +1,134 @@ +package fpga.arty.linux + +import java.nio.file.{Files, Paths} +import chisel3._ +import circt.stage.ChiselStage +import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.diplomacy.lazymodule.LazyModule +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} +import freechips.rocketchip.system.ExampleRocketSystem +import freechips.rocketchip.subsystem.{InSubsystem, InclusiveCacheKey, MBUS, TilesLocated} +import framework.system.tile.BBTileAttachParams +import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter, TLRAM} +import freechips.rocketchip.resources.{Description, MemoryDevice, ResourceBindings, ResourceString} +import freechips.rocketchip.util.ElaborationArtefacts + +class ToyLinuxSystem(implicit p: Parameters) extends ExampleRocketSystem { + // Optional auxiliary RAM. The Linux boot ROM jumps to DDR at 0x80000000; + // it never uses this separate 0x08000000 region. + if (!p(TrimOptionalPeripherals)) { + val bus = locateTLBusWrapper(MBUS) + val scratchDevice = new MemoryDevice { + override def describe(resources: ResourceBindings): Description = { + val original = super.describe(resources) + original.copy(mapping = original.mapping + ("status" -> Seq(ResourceString("disabled")))) + } + } + val scratchpad = bus { + LazyModule(new TLRAM(AddressSet(BigInt("08000000", 16), 65535), + beatBytes = bus.beatBytes, devOverride = Some(scratchDevice))) + } + bus.coupleTo("toy-scratchpad") { + scratchpad.node := TLFragmenter(bus.beatBytes, bus.blockBytes) := + TLBuffer(BufferParams.default) := TLBuffer(BufferParams.default) := _ + } + } +} + +// Complete CPU/cache/accelerator resource boundary. External AXI ports must +// terminate in real DDR and peripherals before this becomes a board design. +class ToyLinuxChip(implicit p: Parameters) extends Module { + val system = LazyModule(new ToyLinuxSystem) + val core = Module(system.module) + system.io_clocks.get.elements.values.foreach { domain => + domain.clock := clock + domain.reset := reset.asBool + } + val interrupt = IO(Input(Bool())) + core.interrupts := interrupt.asUInt + require(system.mem_axi4.size == 1 && system.mmio_axi4.size == 1) + val memory = IO(chiselTypeOf(system.mem_axi4.head)) + val peripherals = IO(chiselTypeOf(system.mmio_axi4.head)) + memory <> system.mem_axi4.head + peripherals <> system.mmio_axi4.head +} + +object EmitToyLinux extends App { + val serial = args.drop(1).contains("--serial-fpga") + val gemminiOnly = args.drop(1).contains("--gemmini-only") + val compact = gemminiOnly || args.drop(1).contains("--compact-caches") + val trimmed = compact || args.drop(1).contains("--trim-peripherals") + implicit val parameters: Parameters = + (if (serial) new ToyLinux8x8Config + else if (gemminiOnly) new ToyLinuxGemminiOnlyConfig + else if (compact) new ToyLinuxCompactConfig + else if (trimmed) new ToyLinuxTrimmedConfig + else new ToyLinuxConfig).toInstance + val directory = args.headOption.getOrElse("generated") + // Use CIRCT's memory-macro boundary for a board-specific SRAM implementation. + // Original upstream sources stay intact; Gemmini arithmetic uses explicit overlays. + val memoryOptions = if (args.drop(1).contains("--fpga-memories")) { + Array("--repl-seq-mem", s"--repl-seq-mem-file=$directory/memories.conf") + } else Array.empty[String] + ChiselStage.emitSystemVerilogFile( + new ToyLinuxChip, + args = Array("--target-dir", directory), + firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") ++ memoryOptions + ) + ElaborationArtefacts.files.foreach { case (name, content) => + Files.writeString(Paths.get(directory, s"ToyLinuxChip.$name"), content()) + } + val tiles = parameters(TilesLocated(InSubsystem)).collect { + case attachment: BBTileAttachParams => attachment.tileParams + } + require(tiles.size == 1) + val tile = tiles.head + val core = tile.rocketCorePerCore.headOption.getOrElse(tile.core) + val accelerator = tile.resolvedBuckyballPerCore.flatten.head + val profile = ujson.Obj( + "serial_fpga" -> parameters(SerialFpga), + "gemmini_only_balls" -> parameters(GemminiOnlyBalls), + "ball_count" -> accelerator.ballDomain.ballNum, + "ball_names" -> ujson.Arr.from(accelerator.ballDomain.ballIdMappings.map(_.ballName)), + "ball_ids" -> ujson.Arr.from(accelerator.ballDomain.ballIdMappings.map(_.ballId)), + "ball_funct7" -> ujson.Arr.from(accelerator.ballDomain.ballISA.map(_.funct7)), + "ball_read_ports" -> accelerator.ballDomain.ballIdMappings.map(_.inBW).sum, + "ball_write_ports" -> accelerator.ballDomain.ballIdMappings.map(_.outBW).sum, + "accelerator_mmio_scale_pool" -> accelerator.memDomain.mmioEnable, + "compact_caches" -> parameters(CompactCaches), + "btb_enabled" -> tile.btb.nonEmpty, + "icache_bytes" -> (tile.icache.get.nSets * tile.icache.get.nWays * tile.icache.get.blockBytes), + "icache_ways" -> tile.icache.get.nWays, + "dcache_bytes" -> (tile.dcache.get.nSets * tile.dcache.get.nWays * tile.dcache.get.blockBytes), + "dcache_mshrs" -> tile.dcache.get.nMSHRs, + "l2_ways" -> (if (serial) 0 else parameters(InclusiveCacheKey).ways), + "coherence_manager" -> (if (serial) "broadcast" else "inclusive"), + "rob_entries" -> accelerator.frontend.rob_entries, + "sub_rob_depth" -> accelerator.frontend.sub_rob_depth, + "dma_n_xacts" -> accelerator.memDomain.dma_n_xacts, + "dma_max_in_flight" -> accelerator.memDomain.max_in_flight_mem_reqs, + "tma_read_channels" -> accelerator.memDomain.tmaReadChannel, + "tma_write_channels" -> accelerator.memDomain.tmaWriteChannel, + "cpu_mul_unroll" -> core.mulDiv.get.mulUnroll, + "gemmini_rows" -> examples.balls.gemmini.configs.GemminiBallParam(accelerator).totalRows, + "gemmini_columns" -> examples.balls.gemmini.configs.GemminiBallParam(accelerator).totalColumns, + "virtual_bank_count" -> accelerator.memDomain.virtualBankCount, + "trimmed_optional_peripherals" -> parameters(TrimOptionalPeripherals), + "scratchpad_bytes" -> (if (parameters(TrimOptionalPeripherals)) 0 else 65536), + "cpu_use_debug" -> core.useDebug, + "cpu_breakpoints" -> core.nBreakpoints, + "extra_hpm_counters" -> core.nPerfCounters, + "basic_counters" -> core.haveBasicCounters, + "use_vm" -> core.useVM, + "fpu_shared_fma" -> parameters(freechips.rocketchip.tile.FpgaSharedFma), + "fpu_sfma_latency" -> core.fpu.get.sfmaLatency, + "fpu_dfma_latency" -> core.fpu.get.dfmaLatency, + "fpu_min_flen" -> core.fpu.get.minFLen, + "fpu_flen" -> core.fpu.get.fLen, + "bank_count" -> accelerator.memDomain.bankNum, + "bank_rows" -> accelerator.memDomain.bankEntries, + "bank_width" -> accelerator.memDomain.bankWidth, + "bank_channels" -> accelerator.memDomain.bankChannel + ) + Files.writeString(Paths.get(directory, "ToyLinuxChip.profile.json"), ujson.write(profile, indent = 2)) +} diff --git a/platforms/arty-a7-toy/src/main/scala/ToyLinuxConfig.scala b/platforms/arty-a7-toy/src/main/scala/ToyLinuxConfig.scala new file mode 100644 index 0000000..98a89fd --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/ToyLinuxConfig.scala @@ -0,0 +1,186 @@ +package fpga.arty.linux + +import java.nio.file.{Files, Paths} +import org.chipsalliance.cde.config.{Config, Field} +import freechips.rocketchip.rocket.RocketCoreParams +import freechips.rocketchip.tile.FpgaSharedFma +import freechips.rocketchip.devices.debug.DebugModuleKey +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.util.SystemFileName +import framework.system.core.rocket.configs.RocketCpuParam +import framework.system.tile.{BBTileAttachParams, WithBBTile} +import framework.top.GlobalConfig + +case object TrimOptionalPeripherals extends Field[Boolean](false) +case object CompactCaches extends Field[Boolean](false) +case object SerialFpga extends Field[Boolean](false) +case object GemminiOnlyBalls extends Field[Boolean](false) + +object OriginalToy { + private val json = ujson.read(Files.readString(Paths.get("build/original-toy.json"))) + val cpu = upickle.default.read[RocketCpuParam](json("cpu")) + private val original = upickle.default.read[GlobalConfig](json("accelerator")) + val accelerator = original.copy(ballDomain = original.ballDomain.copy( + ballIdMappings = original.ballDomain.ballIdMappings.map { mapping => + mapping.copy(config = mapping.config.map(path => Paths.get("upstream", path).toAbsolutePath.toString)) + } + )) + require(cpu.useVM && cpu.fpu.enable && cpu.useZba && cpu.useZbb && cpu.useZbs) + require(accelerator.ballDomain.ballNum == 4) + val gemminiOnly = accelerator.copy( + ballDomain = accelerator.ballDomain.copy( + ballNum = 1, + ballIdMappings = accelerator.ballDomain.ballIdMappings.filter(_.ballId == 0), + ballISA = accelerator.ballDomain.ballISA.filter(_.bid == 0) + ), + // Only the removed MXFP converter consumes this private scale-byte pool. + // This is unrelated to the CPU's external MMIO/peripheral AXI port. + memDomain = accelerator.memDomain.copy(mmioEnable = false) + ) + require(gemminiOnly.ballDomain.ballIdMappings.map(_.ballName) == Seq("GemminiBall")) + require(gemminiOnly.ballDomain.ballIdMappings.forall(m => m.mmioReadBW == 0 && m.mmioWriteBW == 0)) + // Keep all 23 Gemmini instructions and the 8x8 arithmetic profile. + // Eight physical banks hold 64 KiB; architectural virtual IDs stay 0..15. + val serial = gemminiOnly.copy( + ballDomain = gemminiOnly.ballDomain.copy( + ballIdMappings = gemminiOnly.ballDomain.ballIdMappings.map(mapping => + mapping.copy(config = Some(Paths.get("config/gemmini-8.toml").toAbsolutePath.toString)))), + frontend = gemminiOnly.frontend.copy(sub_rob_depth = 8), + memDomain = gemminiOnly.memDomain.copy( + bankNum = 8, bankWidth = 64, bankMaskLen = 8, dma_buswidth = 64, dma_n_xacts = 2, max_in_flight_mem_reqs = 4, + tmaReadChannel = 1, tmaWriteChannel = 1) + ) + require(serial.memDomain.bankChannel == 7) +} + +class WithArtyLinuxPorts extends Config((site, here, up) => { + case FpgaSharedFma => true + case ExtMem => Some(MemoryPortParams( + master = MasterPortParams(BigInt("80000000", 16), BigInt(256) * 1024 * 1024, 16, 4, 64), + nMemoryChannels = 1 + )) + // Reserve the original SCU address range for the physical peripheral bridge. + case ExtBus => Some(MasterPortParams(BigInt("60000000", 16), BigInt("10000000", 16), 8, 2, 8)) + case ExtIn => None + case DebugModuleKey => None + case BootROMLocated(InSubsystem) => Seq(BootROMParams( + hang = BigInt("10000", 16), + appendDTB = true, + contentFileName = SystemFileName("upstream/arch/src/main/resources/bootrom/linux/bootrom.rv64.img") + )) + case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) + case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + // FPGA clock enables replace ASIC clock gates; execution features stay intact. + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + core = tile.core.copy(clockGate = false, haveSimTimeout = false, + fpu = tile.core.fpu.map(f => f.copy(sfmaLatency = f.dfmaLatency))), + rocketCorePerCore = tile.rocketCorePerCore.map(c => c.copy(clockGate = false, haveSimTimeout = false, + fpu = c.fpu.map(f => f.copy(sfmaLatency = f.dfmaLatency)))), + dcache = tile.dcache.map(_.copy(clockGate = false)) + )) + case other => other + } +}) + +class ToyLinuxConfig(accelerator: GlobalConfig = OriginalToy.accelerator, withL2: Boolean = true) extends Config( + new WithArtyLinuxPorts ++ + new WithBBTile( + tileParam = accelerator.tile, + buckyballConfig = accelerator, + rocketCpuPerCore = Some(Seq(OriginalToy.cpu)) + ) ++ + new WithNExtTopInterrupts(1) ++ + new WithDTS("ucb-bar,buckyball", Nil) ++ + (if (withL2) new WithInclusiveCache(capacityKB = 64) else new Config((site, here, up) => PartialFunction.empty)) ++ + new WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig +) + +// Remove optional debug facilities and unused auxiliary RAM only. +// Linux privilege levels, MMU, FPU, caches and architectural counters stay intact. +class WithTrimOptionalPeripherals extends Config((site, here, up) => { + case TrimOptionalPeripherals => true + case TilesLocated(InSubsystem) => + def trim(core: RocketCoreParams): RocketCoreParams = { + require(core.nPerfCounters == 0, "The baseline already has no extra HPM counters") + require(core.haveBasicCounters && core.useVM && core.fpu.nonEmpty) + core.copy(useDebug = false, nBreakpoints = 0, useBPWatch = false) + } + up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + core = trim(tile.core), + rocketCorePerCore = tile.rocketCorePerCore.map(trim) + )) + case other => other + } +}) + +class ToyLinuxTrimmedConfig extends Config( + new WithTrimOptionalPeripherals ++ new ToyLinuxConfig +) + +// Capacity and speculation tradeoffs only; keep the ISA and coherence protocol. +class WithCompactCaches extends Config((site, here, up) => { + case CompactCaches => true + case InclusiveCacheKey => + val cache = up(InclusiveCacheKey, site) + require(cache.ways == 8 && cache.sets == 128) + cache.copy(ways = 4) // 128 sets * 4 ways * 64 bytes = 32 KiB. + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + btb = None, + icache = tile.icache.map(_.copy(nWays = 2)), // 64 sets, 8 KiB. + dcache = tile.dcache.map(_.copy(nMSHRs = 1)) // Capacity stays 8 KiB. + )) + case other => other + } +}) + +class ToyLinuxCompactConfig extends Config( + new WithCompactCaches ++ new ToyLinuxTrimmedConfig +) + +class WithGemminiOnlyMarker extends Config((site, here, up) => { + case GemminiOnlyBalls => true +}) + +class ToyLinuxGemminiOnlyConfig extends Config( + new WithGemminiOnlyMarker ++ new WithCompactCaches ++ + new WithTrimOptionalPeripherals ++ new ToyLinuxConfig(OriginalToy.gemminiOnly) +) + + +// Broadcast coherence still probes dirty CPU cache lines for accelerator DMA. +// It replaces the inclusive data cache, not the coherence protocol. +class WithSerialFpga extends Config((site, here, up) => { + case SerialFpga => true + case GemminiOnlyBalls => true + case CompactCaches => true + case BroadcastKey => up(BroadcastKey).copy(nTrackers = 2) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + btb = None, + icache = tile.icache.map(_.copy(nWays = 2)), + dcache = tile.dcache.map(_.copy(nMSHRs = 1)) + )) + case other => other + } +}) + +class ToyLinux8x8Config extends Config( + new WithSerialFpga ++ new WithTrimOptionalPeripherals ++ + new ToyLinuxConfig(OriginalToy.serial, withL2 = false) +) diff --git a/platforms/arty-a7-toy/tests/REFERENCE_MANIFEST.json b/platforms/arty-a7-toy/tests/REFERENCE_MANIFEST.json new file mode 100644 index 0000000..b6d0d0c --- /dev/null +++ b/platforms/arty-a7-toy/tests/REFERENCE_MANIFEST.json @@ -0,0 +1,41 @@ +{ + "commit": "1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097", + "files": { + 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"2c277ac5740e7cc28198ba3b213fb29bbb1af4c7cfe114c23f30240955b026f7", + "examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c": "c34824e7d4fefbe98d1f8d606bdb14c042917e1603ebdfe4d98a7f8a31147158", + "examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c": "3869bc9ce52591118fcfb6fe1ceab4f3a8a0fe496b12dbd2b84f20ac3fde0fbc", + "examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c": "ba8cd9b3148f707c7a451dc016fff5d0bb6df3b7f05accd6a22c3202ea7bd663", + "examples/balls/gemmini/workloads/isa/gemmini.h": "28d76de0a7cea15ad56857dc0bf96e66931a004d43531d57415fef9180060794", + "examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h": "884721bb02de7c8e5ad5df6ce64a55eb1877de69ce1b5b82ddeed32615f59e21", + "examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h": "bbab5fa3af8537b10dd9102008e4fac64553a6f265837aea7fa7ffa07d941fa3", + "examples/balls/gemmini/workloads/isa/gemmini_config.h": "c02b851181bbba2e3c562714dade47ef9fd37d94671827df9fca2da99b429265", + "examples/balls/gemmini/workloads/isa/gemmini_flush.h": "9e57eb61e455a3296e3177c2f56a50ee4b85467e17db925ec959e83e9d469822", + "examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h": "3111bf7ece22ff56a2a248c802dd5dc0cc5a7cb8323a427b916c2de98b306fe6", + "examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h": "19530b9162e59cce3deb707312c2cfe4ec885fa73b54cc79bf3e6f52d45a73e0", + "examples/balls/gemmini/workloads/isa/gemmini_preload.h": "a5ac4c839a9ec1c33e8a34a1ebc282c6470196b8c19d91a429df3afa24f4b85e", + "bb-tests/workloads/lib/buckyball.h": "c832025bdcbd13960537c317145623fe99eb15d333ad4645e3cd2aee0c493c50", + "bb-tests/workloads/lib/buckyball.c": "c4c4b9fb107b89407c0654dab809885af7b855e985d7a6d2b80ea2d3d4394673" + } +} diff --git a/platforms/arty-a7-toy/tests/axi_smoke_memory.sv b/platforms/arty-a7-toy/tests/axi_smoke_memory.sv new file mode 100644 index 0000000..f8e7dc6 --- /dev/null +++ b/platforms/arty-a7-toy/tests/axi_smoke_memory.sv @@ -0,0 +1,115 @@ +// Single outstanding read and write, with independent AXI channels. +// Backpressure is legal: W is accepted after AW; R/B are held until accepted. +module axi_smoke_memory #( + parameter DATA_BITS=128, ID_BITS=4, ADDR_BITS=32, + parameter BASE=32'h80000000, CAPACITY=262144, + parameter IMAGE="", parameter MONITOR=0, + parameter TEST_LABEL="whole Toy CPU smoke" +) ( + input clock, reset, + output aw_ready, input aw_valid, + input [ID_BITS-1:0] aw_bits_id, + input [ADDR_BITS-1:0] aw_bits_addr, + input [7:0] aw_bits_len, input [2:0] aw_bits_size, + input [1:0] aw_bits_burst, + output w_ready, input w_valid, + input [DATA_BITS-1:0] w_bits_data, + input [DATA_BITS/8-1:0] w_bits_strb, input w_bits_last, + input b_ready, output reg b_valid, + output reg [ID_BITS-1:0] b_bits_id, output [1:0] b_bits_resp, + output ar_ready, input ar_valid, + input [ID_BITS-1:0] ar_bits_id, + input [ADDR_BITS-1:0] ar_bits_addr, + input [7:0] ar_bits_len, input [2:0] ar_bits_size, + input [1:0] ar_bits_burst, + input r_ready, output reg r_valid, + output reg [ID_BITS-1:0] r_bits_id, + output reg [DATA_BITS-1:0] r_bits_data, + output [1:0] r_bits_resp, output reg r_bits_last +); + localparam LANES=DATA_BITS/8; + reg [7:0] mem [0:CAPACITY-1]; + reg write_active; + reg [ADDR_BITS-1:0] write_addr, read_addr; + reg [7:0] write_remaining, read_remaining; + reg [2:0] write_size, read_size; + reg [3:0] stall_cycle; + integer read_bursts, write_bursts; + assign aw_ready = !write_active && !b_valid && stall_cycle[1:0]!=0; + assign w_ready = write_active && !b_valid && stall_cycle[2:0]!=0; + assign ar_ready = !r_valid && stall_cycle[1:0]!=1; + assign b_bits_resp = 0; + assign r_bits_resp = 0; + + initial begin + for (integer i=0; iCAPACITY) + $fatal(1,"AXI read out of range: %h",addr); + for (integer lane=0; laneCAPACITY) + $fatal(1,"AXI write out of range: %h",write_addr); + if (w_bits_last != (write_remaining==0)) $fatal(1,"WLAST mismatch"); + for (integer lane=0; lane=0;n=n-1) c=(c<<1)^((c[15]^value[n]) ? 16'h1021 : 16'd0); + crc_step=c; + end + endfunction + task automatic byte_send(input [7:0] value); + begin @(negedge clk);rx_data=value;rx_valid=1;@(negedge clk);rx_valid=0;end + endtask + task automatic request(input [7:0] op,input [31:0] address,input [15:0] length,input bit corrupt); + reg [15:0] crc; + reg [7:0] value; + begin + received=0;crc=16'hffff; + byte_send(8'ha5);byte_send(8'h5a); + byte_send(op);crc=crc_step(crc,op); + byte_send(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(n*8);byte_send(value);crc=crc_step(crc,value); + end + byte_send(length[7:0]);crc=crc_step(crc,length[7:0]); + byte_send(length[15:8]);crc=crc_step(crc,length[15:8]); + if(op==1) for(integer n=0;n 0, "The test did not exercise dirty writeback to external memory" + record = { + "result": "PASS", + "test_label": args.label, + "core_rtl_sha256": hashlib.sha256(core.read_bytes()).hexdigest(), + "test_binary_sha256": hashlib.sha256(binary.read_bytes()).hexdigest(), + "cycles_including_boot": cycles, + "memory_read_bursts": reads, + "memory_write_bursts": writes, + "linux_boot_tested": False, + } + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/tests/check_dma_beat64.py b/platforms/arty-a7-toy/tests/check_dma_beat64.py new file mode 100644 index 0000000..b29cc80 --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_dma_beat64.py @@ -0,0 +1,55 @@ +"""Check unaligned and strided DMA round trips, with guards and page crossings.""" + +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/dma-beat64" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +elf = out / "dma.elf" +subprocess.run( + [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(ROOT / "build/software"), + "-I", + str(library), + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/dma_beat64.c"), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + "-lgcc", + "-o", + str(elf), + ], + check=True, +) +subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy unaligned DMA 64 bit beats", + ], + check=True, +) diff --git a/platforms/arty-a7-toy/tests/check_fpga_memories.py b/platforms/arty-a7-toy/tests/check_fpga_memories.py new file mode 100644 index 0000000..6e41a8c --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_fpga_memories.py @@ -0,0 +1,213 @@ +"""Compare FPGA SRAM macros with the actual pre-mapping Chisel memory RTL. + +Initialize every row, exercise every write-mask lane, disabled writes, random +transactions, and read back the full memory. Check only defined read cycles. +""" + +import argparse +import json +import re +import subprocess +from pathlib import Path + + +def find_reference(original, mem): + for match in re.finditer(r"^module (\w+)\(.*?^endmodule", original, re.M | re.S): + body = match.group() + width, depth = mem["width"], mem["depth"] + pattern = rf"reg\s+\[{width-1}:0\]\s+Memory\[0:{depth-1}\]" + data_port = "R0_data" if mem["read"] else "RW0_wmode" + mask_name = "W0_mask" if mem["read"] else "RW0_wmask" + if not re.search(pattern, body) or data_port not in body: + continue + if mem["masked"]: + lanes = width // mem["mask_granularity"] + if not re.search(rf"input\s+\[{lanes-1}:0\]\s+{mask_name}", body): + continue + elif mask_name in body: + continue + name = mem["module_name"] + "_reference" + return re.sub(r"^module \w+", "module " + name, body), name + raise ValueError(f"No original Chisel memory matches {mem['module_name']}") + + +def dual_bench(mem, reference): + name, width, depth = mem["module_name"], mem["width"], mem["depth"] + gran = mem.get("mask_granularity", width) + lanes = width // gran + mask_port = ", .W0_mask(mask)" if mem["masked"] else "" + connections = ( + ".R0_addr(ra), .R0_clk(clk), .R0_en(re), " + ".W0_addr(wa), .W0_clk(clk), .W0_en(we), .W0_data(data)" + ) + return f""" +module test_{name}(output reg done = 0); + localparam W={width}, D={depth}, G={gran}, M={lanes}; + reg clk=0; + always #5 clk=~clk; + reg [{(depth-1).bit_length()-1}:0] ra=0, wa=0; + reg re=0, we=0; + reg [W-1:0] data=0; + reg [M-1:0] mask=0; + wire [W-1:0] actual, reference; + reg [W-1:0] model[0:D-1]; + integer seed=98765; + {name} dut({connections}{mask_port}, .R0_data(actual)); + {reference} original({connections}{mask_port}, .R0_data(reference)); + task step(input integer r, input integer w, input bit ren, + input bit wen, input [M-1:0] m); + reg [W-1:0] expected; + begin + @(negedge clk); + ra=r; wa=w; re=ren; we=wen; mask=m; + for (integer b=0; b", + "struct Vector { uint64_t a,b,c,expected; unsigned tag,kind,op,rm,flags; };", + "static const struct Vector vectors[] = {"] +for tag, kind, op, rm, a, b, c, expected, flags in rows: + code.append(f" {{0x{a:x}ULL,0x{b:x}ULL,0x{c:x}ULL,0x{expected:x}ULL,{tag},{kind},{op},{rm},{flags}}},") +code += ["};", "static uint64_t execute(const struct Vector *v, uint64_t *flags) {", + " uint64_t result = 0, f;", ' asm volatile("csrw frm, %0" :: "r"((uint64_t)v->rm));'] +for tag, precision, load, store in ((0, "h", "flh", "fsh"), (1, "s", "flw", "fsw"), (2, "d", "fld", "fsd")): + code += [f" {'if' if tag == 0 else 'else if'} (v->tag == {tag}) {{"] + for kind, op, instruction, operands in ( + (0, 0, "fmadd", "ft3, ft0, ft1, ft2, dyn"), + (0, 1, "fmsub", "ft3, ft0, ft1, ft2, dyn"), + (0, 2, "fnmsub", "ft3, ft0, ft1, ft2, dyn"), + (0, 3, "fnmadd", "ft3, ft0, ft1, ft2, dyn"), + (1, 0, "fadd", "ft3, ft0, ft2, dyn"), + (1, 1, "fsub", "ft3, ft0, ft2, dyn"), + (2, 0, "fmul", "ft3, ft0, ft1, dyn"), + ): + code += [f" if (v->kind == {kind} && v->op == {op}) {{", + ' asm volatile("csrw fflags, zero\\n"', + f' "{load} ft0, 0(%2)\\n{load} ft1, 8(%2)\\n{load} ft2, 16(%2)\\n"', + f' "{instruction}.{precision} {operands}\\n{store} ft3, 0(%1)\\nfrflags %0\\n"', + ' : "=r"(f) : "r"(&result), "r"(v)', + ' : "memory", "ft0", "ft1", "ft2", "ft3");', + " }"] + code += [" }"] +code += [" *flags = f; return result;", "}", "static int dependency_benchmark(void) {", + " volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL;"] +for tag, precision, load, store, one, expected in ( + (0, "h", "flh", "fsh", 0x3c00, 0x6401), + (1, "s", "flw", "fsw", 0x3f800000, 0x44802000), + (2, "d", "fld", "fsd", 0x3ff0000000000000, 0x4090040000000000), +): + code += [" {", f" uint64_t one=0x{one:x}ULL, result=0, begin, end;", + f' asm volatile("{load} ft0, 0(%2)\\n{load} ft1, 0(%2)\\nli t0, 32\\ncsrr %0, cycle\\n"', + f' "1: .rept 32\\nfadd.{precision} ft0, ft0, ft1, rne\\n.endr\\n"', + f' "addi t0, t0, -1\\nbnez t0, 1b\\n{store} ft0, 0(%3)\\ncsrr %1, cycle\\n"', + ' : "=&r"(begin), "=&r"(end) : "r"(&one), "r"(&result)', + ' : "memory", "t0", "ft0", "ft1");', + f" if (result != 0x{expected:x}ULL) return 32;", + f" status[0] = 0x{0x7300000000000000 | (tag << 32):016x}ULL | (end-begin);", " }"] +code += [" return 0;", "}", "int main(void) {", + " volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL;", + " for (unsigned i = 0; i < sizeof(vectors)/sizeof(vectors[0]); ++i) {", + " uint64_t flags; uint64_t actual = execute(&vectors[i], &flags);", + " if (actual != vectors[i].expected || flags != vectors[i].flags) {", + " status[2] = i; status[3] = actual; status[4] = vectors[i].expected;", + " status[5] = flags; status[6] = vectors[i].flags; return 31;", " }", " }", + " return dependency_benchmark();", "}"] +source = out / "fpu_vectors.c" +source.write_text("\n".join(code) + "\n") +elf = out / "fpu_vectors.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", "-ffunction-sections", + "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", "-T", + str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), str(source), + str(ROOT / "tests/gemmini_runtime.c"), "-lgcc", "-o", str(elf)], check=True) +subprocess.run([sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), "--label", "whole Toy shared FPU 1536 oracle vectors"], check=True) +baseline_output = out / "baseline-simulation" +subprocess.run([sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--core-dir", str(ROOT.parent / "toy-a7-all-dsp-20261010/build/serial-bound"), + "--output-dir", str(baseline_output), "--label", "whole Toy baseline FPU 1536 oracle vectors"], check=True) +def measures(path): + log = (path / "simulation.log").read_text() + cycles = {int(tag): int(value, 16) for tag, value in re.findall(r"CPU status = 7300000([012])([0-9a-f]{8})", log)} + assert set(cycles) == {0, 1, 2} + return cycles +new_cycles = measures(out / "simulation") +old_cycles = measures(baseline_output) +record = {"result": "PASS", "vector_count": len(rows), "precision_counts": [sum(row[0] == tag for row in rows) for tag in range(3)], + "rounding_modes": sorted({row[3] for row in rows}), "vector_sha256": hashlib.sha256(vectors.read_bytes()).hexdigest(), + "oracle": "unchanged original H/S/D FPUFMAPipe data and exception flags", + "regression": json.loads((out / "simulation/RESULT.json").read_text()), + "baseline_regression": json.loads((baseline_output / "RESULT.json").read_text()), + "dependency_benchmark": {"operation": "1024 dependent FADD; groups of 32, including loop overhead and final store", + "baseline_cycles_HSD": old_cycles, "candidate_cycles_HSD": new_cycles, + "delta_cycles_HSD": {tag: new_cycles[tag] - old_cycles[tag] for tag in range(3)}}} +assert record["regression"]["test_binary_sha256"] == record["baseline_regression"]["test_binary_sha256"] +(out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") diff --git a/platforms/arty-a7-toy/tests/check_gemmini.py b/platforms/arty-a7-toy/tests/check_gemmini.py new file mode 100644 index 0000000..a501064 --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_gemmini.py @@ -0,0 +1,165 @@ +"""Run pinned upstream Gemmini C tests on the complete emitted chip.""" + +import argparse +import hashlib +import json +import re +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core-dir", type=Path, default=ROOT / "build/serial-bound") + parser.add_argument("--output-dir", type=Path, default=ROOT / "build/gemmini-tests") + parser.add_argument("--cases", nargs="+") + parser.add_argument("--diagnostic", action="store_true") + args = parser.parse_args() + out = args.output_dir.resolve() + out.mkdir(parents=True, exist_ok=True) + reference = ROOT / "tests/reference" + manifest = json.loads((ROOT / "tests/REFERENCE_MANIFEST.json").read_text()) + for name, expected in manifest["files"].items(): + assert hashlib.sha256((reference / name).read_bytes()).hexdigest() == expected + library = reference / "bb-tests/workloads/lib" + workloads = reference / "examples/balls/gemmini/workloads" + config = json.loads((ROOT / "build/original-toy.json").read_text()) + entries = config["accelerator"]["ballDomain"]["ballISA"] + (out / "ballISA.h").write_text( + "// Retained Gemmini encodings, unchanged from upstream.\n" + + "\n".join( + f"#define BB_FUNC7_{e['mnemonic']} {e['funct7']}" + for e in entries + if e["bid"] == 0 + ) + + "\n" + ) + (out / "params.h").write_text( + "#define BANK_WIDTH 64\n#define VIRTUAL_BANK_NUM 16\n" + ) + sources = sorted((workloads / "ctests").glob("*.c")) + if args.cases: + sources = [p for p in sources if p.stem in args.cases] + assert {p.stem for p in sources} == set(args.cases) + adapted = out / "dimension-8-sources" + adapted.mkdir(exist_ok=True) + adapted_sources = [] + for source in sources: + text = source.read_text() + assert "#define DIM 16" in text, source + target = adapted / source.name + target.write_text(text.replace("#define DIM 16", "#define DIM 8")) + adapted_sources.append(target) + sources = adapted_sources + common = [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(out), + "-I", + str(library), + "-I", + str(workloads), + ] + objects = [] + for i, source in enumerate(sources, 1): + obj = out / f"case_{i}.o" + subprocess.run( + common + [f"-Dmain=case_{i}", "-c", str(source), "-o", str(obj)], check=True + ) + objects.append(obj) + runner = out / "runner.c" + lines = ["#include "] + lines += [f"int case_{i}(void);" for i in range(1, len(sources) + 1)] + lines += ["int main(void) {", " volatile uint64_t *status=(void *)0x60000000;"] + for i in range(1, len(sources) + 1): + lines += [ + f" *status=0x71000000u+{i};", + f" if (case_{i}()) return {i};", + f" *status=0x72000000u+{i};", + ] + lines += [" return 0;", "}"] + runner.write_text("\n".join(lines) + "\n") + elf = out / "gemmini.elf" + subprocess.run( + common + + [ + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(runner), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + *map(str, objects), + "-lgcc", + "-o", + str(elf), + ], + check=True, + ) + (out / "CASES.json").write_text( + json.dumps({i: p.stem for i, p in enumerate(sources, 1)}, indent=2) + "\n" + ) + simulation = subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--core-dir", + str(args.core_dir.resolve()), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy Gemmini regression", + *(["--diagnostic-accelerator"] if args.diagnostic else []), + ], + check=False, + ) + output = (out / "simulation/simulation.log").read_text() + passed = [ + int(x, 16) & 0xFFFF + for x in re.findall(r"CPU status = (0000000072[0-9a-f]+)", output) + ] + succeeded = simulation.returncode == 0 and passed == list( + range(1, len(sources) + 1) + ) + failures = [ + int(x, 16) & 0xFFFF + for x in re.findall(r"CPU status = (00000000bad0[0-9a-f]+)", output) + ] + record = { + "result": "PASS" if succeeded else "FAIL", + "upstream_commit": manifest["commit"], + "tests": [p.stem for p in sources], + "test_count": len(sources), + "passed_tests": [sources[i - 1].stem for i in passed], + "failed_status_codes": failures, + "runtime": ( + "bare-metal adapter; dimension adapted 16->8; " + "unchanged upstream test bodies/ISA/matrix reference" + ), + "simulation_returncode": simulation.returncode, + } + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"{len(passed)}/{len(sources)} upstream Gemmini workloads passed") + if not succeeded: + raise SystemExit(1) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/tests/check_loop_stress.py b/platforms/arty-a7-toy/tests/check_loop_stress.py new file mode 100644 index 0000000..509dceb --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_loop_stress.py @@ -0,0 +1,58 @@ +"""Run alternating OS/WS multi-tile loops across internal mesh-tag wrap.""" + +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/loop-stress" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "stress.elf" +subprocess.run( + [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(ROOT / "build/software"), + "-I", + str(library), + "-I", + str(workloads), + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/serial_loop_stress.c"), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + "-lgcc", + "-o", + str(elf), + ], + check=True, +) +subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy 40 alternating multi tile OS WS loops", + ], + check=True, +) diff --git a/platforms/arty-a7-toy/tests/check_pe.py b/platforms/arty-a7-toy/tests/check_pe.py new file mode 100644 index 0000000..5f54ca1 --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_pe.py @@ -0,0 +1,129 @@ +"""Prove the quantizer and compare original/LUT/DSP PEs cycle by cycle.""" + +import argparse +import subprocess +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] + + +def rtl(path): + data = path.read_text() + marker = '// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----' + if marker in data: + data, filelist = data.split(marker) + assert all(x.strip().endswith(".v") for x in filelist.splitlines() if x.strip()) + output = path.with_name(path.stem + "_rtl.sv") + output.write_text(data) + return output + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--yosys", default="yosys") + args = parser.parse_args() + out = ROOT / "build/pe-checks" + quant = rtl(out / "quantizer/QuantizerEquivalence.sv") + command = ( + f"read_verilog -sv {quant}; prep -top QuantizerEquivalence -flatten; " + "sat -prove equal 1 -verify -show-inputs -show-outputs" + ) + with (out / "quantizer-proof.log").open("w") as log: + subprocess.run( + [args.yosys, "-p", command], stdout=log, stderr=log, check=True, timeout=180 + ) + cycles = rtl(out / "cycles/PeCycleEquivalence.sv") + bench = out / "tb_pe.sv" + bench.write_text( + """ +`timescale 1ns/1ps +module tb; + reg clock=0; + always #5 clock=~clock; + reg reset=0; + reg [7:0] in_a=0; + reg [19:0] in_b=0, in_d=0; + reg control_dataflow=0, control_propagate=0; + reg [4:0] control_shift=0; + reg [1:0] id=0; + reg last=0, valid=1; + wire equal; + integer checked=0; + integer seed=57201; + PeCycleEquivalence dut(.*); + task step(input bit df, input bit prop, input integer shift, + input integer a, input integer b, input integer d, + input bit v, input bit check); + begin + @(negedge clock); + control_dataflow=df; control_propagate=prop; control_shift=shift; + in_a=a; in_b=b; in_d=d; valid=v; + id=$random(seed); last=$random(seed); + #1; + if (check && v) begin + if (equal !== 1'b1) begin + $display("PE mismatch df=%0d prop=%0d shift=%0d",df,prop,shift); + $fatal(1,"a=%0d b=%0d d=%0d cycle=%0d",a,b,d,checked); + end + checked=checked+1; + end + @(posedge clock); #1; + end + endtask + initial begin + // Initialize both original accumulator registers through legal loading. + step(0,1,0,0,0,0,1,0); + step(0,0,0,0,0,0,1,0); + for (integer shift=0; shift<32; shift=shift+1) + for (integer df=0; df<2; df=df+1) + for (integer p=0; p<2; p=p+1) + for (integer n=0; n<16; n=n+1) begin + step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + (n&4)?-524288:524287,1,1); + step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + step(df,p,shift,0,0,0,0,1); + end + for (integer n=0; n<100000; n=n+1) + step($random(seed)&1,$random(seed)&1,$random(seed)&31, + $random(seed),$random(seed),$random(seed),($random(seed)&7)!=0,1); + $display("PASS original/LUT/DSP PE: %0d valid-cycle comparisons",checked); + $finish; + end + initial begin #2000000; $fatal(1,"PE test timeout"); end +endmodule +""" + ) + obj = out / "obj" + with (out / "verilator-build.log").open("w") as log: + subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "-j", + "8", + "-Wno-fatal", + "-DSYNTHESIS", + "--top-module", + "tb", + "--Mdir", + str(obj), + str(cycles), + str(bench), + ], + stdout=log, + stderr=log, + check=True, + timeout=180, + ) + result = subprocess.run( + [str(obj / "Vtb")], capture_output=True, text=True, check=True, timeout=120 + ) + (out / "cycles-test.log").write_text(result.stdout + result.stderr) + assert "PASS original/LUT/DSP PE" in result.stdout + print("PASS formal quantizer equivalence for all 2^25 input/shift pairs") + print(result.stdout) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/tests/check_routing.py b/platforms/arty-a7-toy/tests/check_routing.py new file mode 100644 index 0000000..c34e412 --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_routing.py @@ -0,0 +1,76 @@ +"""Exercise fixed routes using the real AccPipe and delayed SRAM responses.""" + +import hashlib +import json +import subprocess +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/routing-check" +rtl = out / "RoutingCheck.sv" +tb = out / "tb.sv" +tb.write_text( + """`timescale 1ns/1ps +module tb; + reg clock=0, reset=1; + wire passed; + RoutingCheck dut(.*); + always #5 clock=~clock; + initial begin + repeat(10) @(negedge clock); + reset=0; + wait(passed); + $display("PASS fixed routing: 512 transactions, DMA arbitration, stalls"); + $finish; + end + initial begin + repeat(20000) @(posedge clock); + $fatal(1, "Routing check timeout"); + end +endmodule +""" +) +subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "--assert", + "-j", + "8", + "-Wno-fatal", + "--top-module", + "tb", + "--Mdir", + str(out / "obj"), + str(rtl), + str(tb), + ], + check=True, + stdout=subprocess.DEVNULL, +) +result = subprocess.run([str(out / "obj/Vtb")], capture_output=True, text=True) +(out / "simulation.log").write_text(result.stdout + result.stderr) +print(result.stdout) +assert result.returncode == 0 and "PASS fixed routing" in result.stdout +(out / "RESULT.json").write_text( + json.dumps( + { + "result": "PASS", + "transactions": 512, + "coverage": [ + "two Gemmini reads", + "four Gemmini writes", + "concurrent DMA requests", + "request stalls", + "response stalls", + "backend route look-ahead", + "opposite-direction request arriving during pending route", + "Ball release with responses pending", + ], + "rtl_sha256": hashlib.sha256(rtl.read_bytes()).hexdigest(), + }, + indent=2, + ) + + "\n" +) diff --git a/platforms/arty-a7-toy/tests/check_ws_round.py b/platforms/arty-a7-toy/tests/check_ws_round.py new file mode 100644 index 0000000..5b7b2db --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_ws_round.py @@ -0,0 +1,26 @@ +"""Run signed/tie/boundary shift cases on the full CPU/Gemmini chip.""" +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/ws-round-edges" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "edges.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", + "-ffunction-sections", "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", "-mabi=lp64d", + "-I", str(ROOT / "build/software"), "-I", str(library), "-I", str(workloads), + "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/ws_round_edges.c"), str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), "-lgcc", "-o", str(elf) +], check=True) +subprocess.run([ + sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), + "--label", "whole Toy 64 OS WS RNE edge cases 4096 results" +], check=True) diff --git a/platforms/arty-a7-toy/tests/check_ws_shift_edges.py b/platforms/arty-a7-toy/tests/check_ws_shift_edges.py new file mode 100644 index 0000000..43ffe56 --- /dev/null +++ b/platforms/arty-a7-toy/tests/check_ws_shift_edges.py @@ -0,0 +1,26 @@ +"""Run signed/tie/boundary shift cases on the full CPU/Gemmini chip.""" +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/ws-shift-edges" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "edges.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", + "-ffunction-sections", "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", "-mabi=lp64d", + "-I", str(ROOT / "build/software"), "-I", str(library), "-I", str(workloads), + "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/ws_shift_edges.c"), str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), "-lgcc", "-o", str(elf) +], check=True) +subprocess.run([ + sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), + "--label", "whole Toy 64 OS WS RNE edge cases 4096 results" +], check=True) diff --git a/platforms/arty-a7-toy/tests/cpu_smoke.S b/platforms/arty-a7-toy/tests/cpu_smoke.S new file mode 100644 index 0000000..c3caf3a --- /dev/null +++ b/platforms/arty-a7-toy/tests/cpu_smoke.S @@ -0,0 +1,248 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mie, zero + li s10, 0 + li s11, 0 + li gp, 1 + li t0, 0x60000000 + li t1, 0xb007 + sd t1, 0(t0) + + # EBREAK remains an ordinary architectural breakpoint exception. + li s10, 3 + ebreak + li t0, 1 + bne s11, t0, fail + # Debug CSR access is illegal when useDebug=false. + li s10, 2 + csrr t0, 0x7b0 + li t0, 2 + bne s11, t0, fail + # The removed auxiliary RAM must fault rather than hang or alias DDR. + li s10, 5 + li t0, 0x08000000 + ld t1, 0(t0) + li t0, 3 + bne s11, t0, fail + li s10, 0 + + li gp, 2 + csrr s0, mcycle + csrr s1, minstret + li t0, 256 +1: addi t0, t0, -1 + bnez t0, 1b + csrr t0, mcycle + bgeu s0, t0, fail + csrr t0, minstret + bgeu s1, t0, fail + + li gp, 3 + li t0, 0x0200bff8 + ld s0, 0(t0) + li t1, 256 +2: addi t1, t1, -1 + bnez t1, 2b + ld t1, 0(t0) + bgeu s0, t1, fail + li t0, 0x0c000004 + li t1, 1 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + + li gp, 4 + li t0, 0x6000 + csrs mstatus, t0 + li t0, 3 + fcvt.d.w f0, t0 + fadd.d f1, f0, f0 + fcvt.w.d t1, f1, rtz + li t2, 6 + bne t1, t2, fail + fcvt.s.w f0, t0 + fmul.s f1, f0, f0 + fcvt.w.s t1, f1, rtz + li t2, 9 + bne t1, t2, fail + fcvt.h.w f0, t0 + fadd.h f1, f0, f0 + fcvt.w.h t1, f1, rtz + li t2, 6 + bne t1, t2, fail + la t0, datum + fsd f1, 8(t0) + fld f2, 8(t0) + fmv.x.d t1, f1 + fmv.x.d t2, f2 + bne t1, t2, fail + + li gp, 5 + la t0, datum + li t1, 35 + sd t1, 0(t0) + li t2, 7 + amoadd.d t3, t2, (t0) + bne t1, t3, fail + ld t3, 0(t0) + li t1, 42 + bne t1, t3, fail + mul t3, t1, t2 + div t3, t3, t2 + bne t1, t3, fail + + # Indirect calls and returns at 512-byte spacing force I-cache conflicts. + # Each of 64 stubs is called three times, including with no BTB/RAS. + li gp, 9 + li s2, 0 + li s3, 3 +icache_pass: + la s0, instruction_stubs + li s1, 64 +icache_call: + jalr ra, s0, 0 + addi s0, s0, 512 + addi s1, s1, -1 + bnez s1, icache_call + addi s3, s3, -1 + bnez s3, icache_pass + li t0, 192 + bne s2, t0, fail + + # 64 KiB of dirty lines exceeds both L1 and the compact 32 KiB L2. + # Write/read both directions and repeat with a changed data pattern. + li gp, 10 + li s3, 2 +cache_pass: + la s0, cache_data + li s1, 8192 + li s2, 0 +cache_fill: + xor t0, s2, s3 + sd t0, 0(s0) + addi s0, s0, 8 + addi s2, s2, 1 + addi s1, s1, -1 + bnez s1, cache_fill + fence rw, rw + li s1, 8192 +cache_read_reverse: + addi s0, s0, -8 + addi s2, s2, -1 + ld t0, 0(s0) + xor t1, s2, s3 + bne t0, t1, fail + addi s1, s1, -1 + bnez s1, cache_read_reverse + li s1, 8192 +cache_read_forward: + ld t0, 0(s0) + xor t1, s2, s3 + bne t0, t1, fail + addi s0, s0, 8 + addi s2, s2, 1 + addi s1, s1, -1 + bnez s1, cache_read_forward + addi s3, s3, -1 + bnez s3, cache_pass + + li gp, 6 + # Three identity 1 GiB mappings plus a virtual DDR alias at 0xc0000000. + la t0, root_page + li t1, 0xcf + sd t1, 0(t0) + li t1, 0x100000cf + sd t1, 8(t0) + li t1, 0x200000cf + sd t1, 16(t0) + sd t1, 24(t0) + fence rw, rw + li t1, -1 + csrw pmpaddr0, t1 + li t1, 0xf + csrw pmpcfg0, t1 + li t1, 7 + csrw mcounteren, t1 + srli t0, t0, 12 + li t1, 0x8000000000000000 + or t0, t0, t1 + csrw satp, t0 + sfence.vma + la t0, supervisor + csrw mepc, t0 + li t0, 0x1800 + csrc mstatus, t0 + li t0, 0x800 + csrs mstatus, t0 + mret + +supervisor: + li gp, 7 + la t0, datum + li t1, 0x40000000 + add t0, t0, t1 + ld t2, 0(t0) + li t3, 42 + bne t2, t3, fail + li t2, 43 + sd t2, 0(t0) + la t0, datum + ld t3, 0(t0) + bne t2, t3, fail + csrr t0, cycle + beqz t0, fail + li gp, 8 + li s10, 9 + ecall + j fail + +trap_handler: + csrr t0, mcause + bne t0, s10, fail + addi s11, s11, 1 + li t1, 9 + beq t0, t1, passed + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + mret + +passed: + li t0, 4 + bne s11, t0, fail + li t0, 0x60000000 + li t1, 0x600d600d + sd t1, 0(t0) +3: j 3b + +fail: + li t0, 0x60000000 + li t1, 0xbad00000 + or t1, t1, gp + sd t1, 0(t0) +4: j 4b + +.balign 512 +instruction_stubs: +.rept 64 + addi s2, s2, 1 + ret + .space 504 +.endr + +.section .data,"aw",@progbits +.balign 16 +datum: + .dword 0, 0 +.balign 4096 +root_page: + .zero 4096 +.balign 4096 +cache_data: + .zero 65536 diff --git a/platforms/arty-a7-toy/tests/cpu_smoke.ld b/platforms/arty-a7-toy/tests/cpu_smoke.ld new file mode 100644 index 0000000..b262154 --- /dev/null +++ b/platforms/arty-a7-toy/tests/cpu_smoke.ld @@ -0,0 +1,10 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS { + . = 0x80000000; + .text : { *(.text.init) *(.text*) } + . = ALIGN(16); + .data : { *(.data*) } + .bss : { *(.bss*) *(COMMON) } + /DISCARD/ : { *(.comment) *(.riscv.attributes) } +} diff --git a/platforms/arty-a7-toy/tests/dma_beat64.c b/platforms/arty-a7-toy/tests/dma_beat64.c new file mode 100644 index 0000000..7dc30d1 --- /dev/null +++ b/platforms/arty-a7-toy/tests/dma_beat64.c @@ -0,0 +1,36 @@ +// Exercise the actual CPU/DMA/cache path after adapting DMA beats to eight bytes. +#include "buckyball.h" +#include +#include + +static uint8_t source[8192] __attribute__((aligned(4096))); +static uint8_t destination[8192] __attribute__((aligned(4096))); + +int main(void) { + const int rows = 9; + const int offsets[] = {0, 1, 3, 7, 4093}; + for (unsigned t = 0; t < sizeof(offsets) / sizeof(offsets[0]); ++t) { + const int in = offsets[t]; + const int out = offsets[(t + 2) % 5]; + const int stride = (t & 1) + 1; + for (int i = 0; i < 8192; ++i) { + source[i] = (uint8_t)(i * 37 + t * 19); + destination[i] = 0xa5; + } + // Four groups exercise splitting and the row skip independently of matrix math. + bb_mem_alloc(0, 1, 4); + bb_mvin((uintptr_t)(source + in), 0, rows, stride); + bb_mvout((uintptr_t)(destination + out), 0, rows, stride); + bb_fence(); + bb_mem_release(0); + for (int i = 0; i < 8192; ++i) { + int relative = i - out; + int row = relative >= 0 ? relative / (stride * 32) : -1; + int column = relative >= 0 ? relative % (stride * 32) : -1; + uint8_t expected = row >= 0 && row < rows && column < 32 + ? source[in + row * stride * 32 + column] : 0xa5; + if (destination[i] != expected) return (int)t + 1; + } + } + return 0; +} diff --git a/platforms/arty-a7-toy/tests/fma_differential.cpp b/platforms/arty-a7-toy/tests/fma_differential.cpp new file mode 100644 index 0000000..d3aee18 --- /dev/null +++ b/platforms/arty-a7-toy/tests/fma_differential.cpp @@ -0,0 +1,122 @@ +#include "VFmaPrecisionCheck.h" +#include "verilated.h" +#include +#include +#include +#include +#include +#include +#include +#include + +struct Request { + int tag, kind, op, rm; + uint64_t a, b, c; + bool random; +}; + +int main(int argc, char **argv) { + Verilated::commandArgs(argc, argv); + VFmaPrecisionCheck dut; + std::mt19937_64 rng(0xf00d531124ULL); + std::deque pending; + std::ofstream vectors("vectors.csv"); + std::array comparisons{}; + std::array, 3> saved{}; + uint64_t cycles = 0, resets = 0, dropped = 0; + bool failed = false; + auto tick = [&](bool valid, Request r, bool reset = false) { + dut.clock = 0; + dut.reset = reset; + dut.valid = valid && !reset; + dut.tag = r.tag; + dut.kind = r.kind; + dut.op = r.op; + dut.rm = r.rm; + dut.a = r.a; dut.b = r.b; dut.c = r.c; + if (reset) { dropped += pending.size(); pending.clear(); } + else if (valid) pending.push_back(r); + dut.eval(); + dut.clock = 1; + dut.eval(); + ++cycles; + if (reset) return; + if (!dut.equal) { + std::cerr << "FAIL cycle=" << cycles << " expected=0x" << std::hex + << dut.expected << " actual=0x" << dut.actual + << " expectedFlags=" << unsigned(dut.expectedFlags) + << " actualFlags=" << unsigned(dut.actualFlags) << std::dec << "\n"; + if (!pending.empty()) { + auto x = pending.front(); + std::cerr << "tag=" << x.tag << " kind=" << x.kind << " op=" << x.op << " rm=" << x.rm + << " a=" << std::hex << x.a << " b=" << x.b << " c=" << x.c << std::dec << "\n"; + } + failed = true; + return; + } + if (dut.outValid) { + if (pending.empty()) { std::cerr << "FAIL unexpected response\n"; failed = true; return; } + auto x = pending.front(); pending.pop_front(); + auto n = ++comparisons[x.tag]; + int cohort = x.random ? 1 : 0; + if (saved[x.tag][cohort] < 256 && n % (x.random ? 41 : 61) == 0) { + vectors << x.tag << ',' << x.kind << ',' << x.op << ',' << x.rm << ',' << std::hex + << x.a << ',' << x.b << ',' << x.c << ',' << dut.expected << ',' + << unsigned(dut.expectedFlags) << std::dec << '\n'; + ++saved[x.tag][cohort]; + } + } + }; + Request empty{}; + for (int i = 0; i < 8; ++i) tick(false, empty, true); + for (int tag = 0; tag < 3 && !failed; ++tag) { + int sig = tag == 0 ? 11 : tag == 1 ? 24 : 53; + int exp = tag == 0 ? 5 : tag == 1 ? 8 : 11; + int bits = sig + exp; + uint64_t sign = uint64_t(1) << (bits - 1); + uint64_t inf = ((uint64_t(1) << exp) - 1) << (sig - 1); + uint64_t one = ((uint64_t(1) << (exp - 1)) - 1) << (sig - 1); + uint64_t minNormal = uint64_t(1) << (sig - 1); + std::vector edge{ + 0, sign, 1, sign | 1, minNormal - 1, sign | (minNormal - 1), minNormal, sign | minNormal, + one, sign | one, one + 1, one - 1, one + (uint64_t(1) << (sig - 1)), + one - (uint64_t(1) << (sig - 1)), inf - 1, sign | (inf - 1), + inf, sign | inf, inf | (uint64_t(1) << (sig - 2)), inf | 1, + sign | inf | (uint64_t(1) << (sig - 2)), sign | inf | 1 + }; + for (int rm = 0; rm < 5 && !failed; ++rm) + for (int kind = 0; kind < 3 && !failed; ++kind) + for (int op = 0; op < (kind == 0 ? 4 : kind == 1 ? 2 : 1) && !failed; ++op) + for (size_t i = 0; i < edge.size() && !failed; ++i) + for (size_t j = 0; j < edge.size() && !failed; ++j) { + tick(true, {tag, kind, op, rm, edge[i], edge[j], edge[(i * 3 + j * 5) % edge.size()], false}); + if ((rng() & 15) == 0) tick(false, empty); + } + // Fusion cancellation: (1+ulp)*(1-ulp)-1 must retain its tiny exact residue. + for (int rm = 0; rm < 5 && !failed; ++rm) { + tick(true, {tag, 0, 0, rm, one + 1, one - 2, sign | one, false}); + tick(true, {tag, 0, 0, rm, inf - 1, one + (uint64_t(1) << (sig - 1)), 0, false}); + } + } + for (int i = 0; i < 200000 && !failed; ++i) { + int tag = rng() % 3, kind = rng() % 3; + int op = rng() % (kind == 0 ? 4 : kind == 1 ? 2 : 1); + tick(true, {tag, kind, op, int(rng() % 5), rng(), rng(), rng(), true}); + if ((rng() & 7) == 0) tick(false, empty); + if (i != 0 && i % 25000 == 0) { + ++resets; + for (int j = 0; j < 8; ++j) tick(false, empty, true); + } + } + for (int i = 0; i < 12 && !failed; ++i) tick(false, empty); + if (failed || !pending.empty()) return 1; + vectors.close(); + dut.final(); + for (int tag = 0; tag < 3; ++tag) { + if (saved[tag][0] != 256 || saved[tag][1] != 256) return 2; + } + std::cout << "PASS FMA_SHARED cycles=" << cycles << " comparisons=" + << comparisons[0] + comparisons[1] + comparisons[2] + << " H=" << comparisons[0] << " S=" << comparisons[1] << " D=" << comparisons[2] + << " resets=" << resets << " reset_discarded=" << dropped << " cpu_vectors=1536\n"; +} diff --git a/platforms/arty-a7-toy/tests/gemmini_runtime.c b/platforms/arty-a7-toy/tests/gemmini_runtime.c new file mode 100644 index 0000000..8d7eb15 --- /dev/null +++ b/platforms/arty-a7-toy/tests/gemmini_runtime.c @@ -0,0 +1,31 @@ +// Bare-metal test adapter only. Test C bodies, ISA headers and matrix reference +// functions come unchanged from the pinned upstream repository. +#include +#include + +static uint32_t bank_columns[16]; + +void bb_dma_bank_set_cols(uint32_t bank, uint32_t columns) { + if (bank >= 16) { + *(volatile uint64_t *)0x60000000 = 0xbad0ee01; + for (;;) {} + } + bank_columns[bank] = columns; +} + +uint32_t bb_dma_bank_cols(uint32_t bank) { + return bank_columns[bank]; +} + +// Console formatting is irrelevant to the return-value checks. Progress and +// pass/fail events are emitted explicitly by the test runner over MMIO. +int printf(const char *format, ...) { + (void)format; + return 0; +} + +void *memset(void *destination, int value, size_t size) { + unsigned char *bytes = destination; + for (size_t i = 0; i < size; ++i) bytes[i] = (unsigned char)value; + return destination; +} diff --git a/platforms/arty-a7-toy/tests/gemmini_start.S b/platforms/arty-a7-toy/tests/gemmini_start.S new file mode 100644 index 0000000..7bfe8f1 --- /dev/null +++ b/platforms/arty-a7-toy/tests/gemmini_start.S @@ -0,0 +1,28 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + li sp, 0x8003fff0 + la t0, trap_failure + csrw mtvec, t0 + csrw mie, zero + csrw medeleg, zero + li t0, 0x1e000 + csrs mstatus, t0 + call main + li t0, 0x60000000 + li t1, 0x600d600d + beqz a0, passed + li t1, 0xbad00000 + or t1, t1, a0 +passed: + sd t1, 0(t0) +1: j 1b +trap_failure: + csrr t2, mcause + li t0, 0x60000000 + li t1, 0xbad0f000 + or t1, t1, t2 + sd t1, 0(t0) +2: j 2b diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c new file mode 100644 index 0000000..78c87a9 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c @@ -0,0 +1,23 @@ +#ifndef _BB_FENCE_H_ +#define _BB_FENCE_H_ + +#include "isa.h" + +#define BB_FENCE_FUNC7 0 + +#if defined(BUCKYBALL_RUSHB) +#define bb_dma_cache_flush() \ + do { \ + } while (0) +#define bb_fence() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7) +#else +#define bb_dma_cache_flush() asm volatile("fence.i" ::: "memory") +#define bb_fence() \ + do { \ + BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7); \ + asm volatile("fence rw, rw" ::: "memory"); \ + bb_dma_cache_flush(); \ + } while (0) +#endif + +#endif // _BB_FENCE_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c new file mode 100644 index 0000000..5bfbff3 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c @@ -0,0 +1,22 @@ +#ifndef _BB_BARRIER_H_ +#define _BB_BARRIER_H_ + +#include "isa.h" + +#define BB_BARRIER_FUNC7 1 + +/** + * bb_barrier() - hardware multi-core barrier synchronization. + * + * Semantics: + * 1. Waits for this core's own instruction ROB to drain (implicit fence). + * 2. Signals arrive to the tile-level BarrierUnit. + * 3. Stalls until all nCores cores have arrived (hardware all-reduce). + * + * All cores in the same BBTile must call bb_barrier() at the same point. + * Mixing bb_barrier() with bb_fence() within the same barrier epoch is + * undefined behaviour. + */ +#define bb_barrier() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_BARRIER_FUNC7) + +#endif // _BB_BARRIER_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c new file mode 100644 index 0000000..04dedb1 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c @@ -0,0 +1,50 @@ +#ifndef _BB_MVOUT_H_ +#define _BB_MVOUT_H_ + +#include "isa.h" +#include + +#define BB_MVOUT_FUNC7 16 + +/* Linux needs private destination pages before a DMA store. */ +#if defined(__linux__) +#define BB_MVOUT_TOUCH(addr, depth, stride, bank) \ + bb_dma_touch_mvout((void *)(addr), (depth), (stride), (bank)) +#else +#define BB_MVOUT_TOUCH(addr, depth, stride, bank) \ + do { \ + } while (0) +#endif + +#if defined(BUCKYBALL_RUSHB) +#define bb_mvout(mem_addr, bank_id, depth, stride) \ + do { \ + uintptr_t _bb_mo_addr = (uintptr_t)(mem_addr); \ + uint32_t _bb_mo_bank = (uint32_t)(bank_id); \ + uint64_t _bb_mo_depth = (uint64_t)(depth); \ + uint64_t _bb_mo_stride = (uint64_t)(stride); \ + BB_MVOUT_TOUCH(_bb_mo_addr, _bb_mo_depth, _bb_mo_stride, _bb_mo_bank); \ + bb_dma_cache_flush(); \ + rushb_mvout( \ + BUCKYBALL_RUSHB_CORE, \ + (uint64_t)(BB_BANK0(_bb_mo_bank) | BB_ITER(_bb_mo_depth)), \ + (uint64_t)(FIELD(_bb_mo_addr, 0, 38) | FIELD(_bb_mo_stride, 39, 57)), \ + (void *)_bb_mo_addr); \ + } while (0) +#else +#define bb_mvout(mem_addr, bank_id, depth, stride) \ + do { \ + uintptr_t _bb_mo_addr = (uintptr_t)(mem_addr); \ + uint32_t _bb_mo_bank = (uint32_t)(bank_id); \ + uint64_t _bb_mo_depth = (uint64_t)(depth); \ + uint64_t _bb_mo_stride = (uint64_t)(stride); \ + BB_MVOUT_TOUCH(_bb_mo_addr, _bb_mo_depth, _bb_mo_stride, _bb_mo_bank); \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(_bb_mo_bank) | BB_ITER(_bb_mo_depth)), \ + (FIELD(_bb_mo_addr, 0, 38) | FIELD(_bb_mo_stride, 39, 57)), \ + BB_MVOUT_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVOUT_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c new file mode 100644 index 0000000..f3b1bf9 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c @@ -0,0 +1,46 @@ +#ifndef _BB_MSET_H_ +#define _BB_MSET_H_ + +#include "isa.h" +#include + +#define BB_MSET_FUNC7 32 + +#define BB_MSET_CLEAR_BIT 11 + +#define BB_MSET_RS2(row, col, alloc, clear) \ + (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10) | \ + FIELD(clear, BB_MSET_CLEAR_BIT, BB_MSET_CLEAR_BIT)) + +#if defined(BUCKYBALL_RUSHB) +#define bb_mset(bank_id, alloc, row, col) \ + rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id), \ + (uint64_t)BB_MSET_RS2(row, col, alloc, 0)) +#define bb_mset_clear(bank_id, row, col) \ + rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id), \ + (uint64_t)BB_MSET_RS2(row, col, 1, 1)) +#else +#define bb_mset(bank_id, alloc, row, col) \ + BUCKYBALL_INSTRUCTION_R_R(BB_BANK0(bank_id), \ + BB_MSET_RS2(row, col, alloc, 0), BB_MSET_FUNC7) +#define bb_mset_clear(bank_id, row, col) \ + BUCKYBALL_INSTRUCTION_R_R(BB_BANK0(bank_id), BB_MSET_RS2(row, col, 1, 1), \ + BB_MSET_FUNC7) +#endif + +#define bb_mem_release(bank_id) \ + do { \ + uint32_t _bb_mr_bank = (uint32_t)(bank_id); \ + bb_dma_bank_set_cols(_bb_mr_bank, 1); \ + bb_mset(_bb_mr_bank, 0, 0, 0); \ + } while (0) + +#define bb_mem_alloc(bank_id, row, col) \ + do { \ + uint32_t _bb_ma_bank = (uint32_t)(bank_id); \ + uint32_t _bb_ma_col = (uint32_t)(col); \ + bb_dma_bank_set_cols(_bb_ma_bank, _bb_ma_col); \ + bb_mset(_bb_ma_bank, 1, (row), _bb_ma_col); \ + } while (0) + +#endif // _BB_MSET_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c new file mode 100644 index 0000000..feb39b9 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c @@ -0,0 +1,27 @@ +#ifndef _BB_MVIN_H_ +#define _BB_MVIN_H_ + +#include "isa.h" + +#define BB_MVIN_FUNC7 33 + +#if defined(BUCKYBALL_RUSHB) +#define bb_mvin(mem_addr, bank_id, depth, stride) \ + do { \ + bb_dma_cache_flush(); \ + rushb_mvin(BUCKYBALL_RUSHB_CORE, \ + (uint64_t)(BB_BANK2(bank_id) | BB_ITER(depth)), \ + (uint64_t)(FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + (const void *)(uintptr_t)(mem_addr)); \ + } while (0) +#else +#define bb_mvin(mem_addr, bank_id, depth, stride) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK2(bank_id) | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), BB_MVIN_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVIN_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c new file mode 100644 index 0000000..ae62a65 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c @@ -0,0 +1,25 @@ +#ifndef _BB_MVIN_2D_H_ +#define _BB_MVIN_2D_H_ + +#include "isa.h" + +#define BB_MVIN_2D_FUNC7 34 + +// rs1: write bank in BANK2 and tile height. +// rs2: [31:0] address, [38:32] physical pixel bytes / 8, +// [48:39] source width, [54:49] destination row base, +// [57:55] tile width - 1, [61:58] valid bytes (0 encodes 16). +#define bb_mvin_2d(mem_addr, bank_id, height, pixel_bytes, source_width, \ + dst_base, tile_width, valid_bytes) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK2(bank_id) | BB_ITER(height)), \ + (FIELD(mem_addr, 0, 31) | FIELD((pixel_bytes) / 8, 32, 38) | \ + FIELD(source_width, 39, 48) | FIELD(dst_base, 49, 54) | \ + FIELD((tile_width) - 1, 55, 57) | \ + FIELD((valid_bytes) == 16 ? 0 : (valid_bytes), 58, 61)), \ + BB_MVIN_2D_FUNC7); \ + } while (0) + +#endif // _BB_MVIN_2D_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c new file mode 100644 index 0000000..91cbb0c --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c @@ -0,0 +1,46 @@ +#ifndef _BB_MVIN_MMIO_H_ +#define _BB_MVIN_MMIO_H_ + +#include "isa.h" + +#define BB_MVIN_MMIO_FUNC7 35 + +// mvin_mmio: DMA-load metadata from DRAM into MMIO SRAM. +// DMA transfers full 128-bit rows (16 bytes each); `col` controls the per-row +// byte mask written into MMIO (first `col` bytes written, rest zero-masked). +// +// dram_addr : source DRAM virtual address (39-bit) +// mmio_addr : destination MMIO byte address (17-bit) +// row : number of 128-bit rows to load (uses BB_ITER) +// col : valid bytes per row (1..16); rest is mask-zeroed in MMIO +// +// rs1 (dependencies): +// [9:0] = 0 (no main bank dependency) +// [63:30] = row (BB_ITER, also serves as DMA beat count) +// +// rs2 (logic): +// [38:0] = dram_addr +// [55:39] = mmio_addr (17-bit byte address) +// [63:56] = col (write mask: valid bytes per row, 1..16) +// +// funct7 = 0x23 (35 decimal) +#if defined(BUCKYBALL_RUSHB) +#define bb_mvin_mmio(dram_addr, mmio_addr, row, col) \ + do { \ + rushb_mvin_mmio(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_ITER(row), \ + (uint64_t)(FIELD(dram_addr, 0, 38) | \ + FIELD(mmio_addr, 39, 55) | FIELD(col, 56, 63)), \ + (const void *)(uintptr_t)(dram_addr)); \ + } while (0) +#else +#define bb_mvin_mmio(dram_addr, mmio_addr, row, col) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R(BB_ITER(row), \ + (FIELD(dram_addr, 0, 38) | \ + FIELD(mmio_addr, 39, 55) | FIELD(col, 56, 63)), \ + BB_MVIN_MMIO_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVIN_MMIO_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h new file mode 100644 index 0000000..5b712fd --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h @@ -0,0 +1,8 @@ +#ifndef BB_FUNC7_H +#define BB_FUNC7_H + +#include "ballISA.h" + +#define BB_FUNC7(mne) BB_FUNC7_##mne + +#endif diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c new file mode 100644 index 0000000..2831564 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c @@ -0,0 +1 @@ +#include "isa.h" diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h new file mode 100644 index 0000000..365653b --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -0,0 +1,69 @@ +#ifndef BUCKYBALL_ISA_H +#define BUCKYBALL_ISA_H + +#include +#include + +#if defined(BUCKYBALL_RUSHB) +#include +#if !defined(BUCKYBALL_RUSHB_CORE_ID) +#error "RushB workloads require a Core ID" +#endif +#define BUCKYBALL_RUSHB_CORE (uint32_t)BUCKYBALL_RUSHB_CORE_ID +#endif + +// Data type for matrix elements +typedef int8_t elem_t; +typedef int32_t result_t; + +// Custom instruction opcodes +#define CUSTOM_3 0x7b + +// String macros +#define STR1(x) #x +#ifndef STR +#define STR(x) STR1(x) +#endif + +// Field encoding macro with start and end bit +#define FIELD(val, start_bit, end_bit) \ + (((val) & ((2UL << ((end_bit) - (start_bit))) - 1)) << (start_bit)) + +// rs1 bank field helpers (10-bit each) +#define BB_BANK0(id) FIELD(id, 0, 9) +#define BB_BANK1(id) FIELD(id, 10, 19) +#define BB_BANK2(id) FIELD(id, 20, 29) + +// rs1 iter field (34-bit, bits 30-63) +#define BB_ITER(n) FIELD(n, 30, 63) + +// funct7 encoding: [6:4]=enable, [3:0]=opcode +// enable: 000=none, 001=1rd, 010=1wr, 011=1rd+1wr, 100=2rd+1wr +// 101/110/111 = none (extended opcode space) + +// Generic RISC-V custom instruction macro (funct3 always 0x3 = CUSTOM3_RS1_RS2) +#if defined(BUCKYBALL_RUSHB) +#define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ + do { \ + rushb_custom(BUCKYBALL_RUSHB_CORE, (uint64_t)(rs1_val), \ + (uint64_t)(rs2_val), (uint32_t)(func7)); \ + } while (0) +#else +#define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ + asm volatile(".insn r " STR(CUSTOM_3) ", 3, %c2, x0, %0, %1" \ + : \ + : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ + : "memory") +#endif + +// Base (mem/frontend) instruction definitions only. +// Ball-specific ISA macros live under examples/balls//workloads/isa/. +#include "00_fence.c" +#include "01_barrier.c" +#include "16_mvout.c" +#include "32_mset.c" +#include "33_mvin.c" +#include "34_mvin_2d.c" +#include "35_mvin_mmio.c" + +#endif // BUCKYBALL_ISA_H diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c new file mode 100644 index 0000000..c573193 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c @@ -0,0 +1,51 @@ +#include + +#include +#include + +static uint8_t bank_cols[VIRTUAL_BANK_NUM]; +static uint8_t bank_cols_init; + +static void ensure_bank_cols(void) { + uint32_t i; + + if (bank_cols_init) + return; + for (i = 0; i < VIRTUAL_BANK_NUM; i++) + bank_cols[i] = 1; + bank_cols_init = 1; +} + +void bb_dma_bank_set_cols(uint32_t bank_id, uint32_t cols) { + ensure_bank_cols(); + if (bank_id >= VIRTUAL_BANK_NUM) { + fprintf(stderr, "bb_dma_bank_set_cols: bank_id %u out of range\n", bank_id); + exit(1); + } + bank_cols[bank_id] = cols < 1 ? 1 : (cols > 255 ? 255 : (uint8_t)cols); +} + +uint32_t bb_dma_bank_cols(uint32_t bank_id) { + ensure_bank_cols(); + if (bank_id >= VIRTUAL_BANK_NUM) { + fprintf(stderr, "bb_dma_bank_cols: bank_id %u out of range\n", bank_id); + exit(1); + } + return bank_cols[bank_id]; +} + +void bb_dma_touch(void *p, size_t n) { + volatile uint8_t *b = (volatile uint8_t *)p; + size_t i; + + if (n == 0) + return; + for (i = 0; i < n; i += 4096) + b[i] = b[i]; + b[n - 1] = b[n - 1]; +} + +void bb_dma_touch_mvout(void *p, uint64_t depth, uint64_t stride, + uint32_t bank_id) { + bb_dma_touch(p, bb_dma_span_bytes(depth, stride, bb_dma_bank_cols(bank_id))); +} diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h new file mode 100644 index 0000000..8914f6e --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h @@ -0,0 +1,43 @@ +#ifndef _MEM_H_ +#define _MEM_H_ + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Bytes covered by mvin/mvout for a bank with `groups` (= alloc col, min 1). */ +static inline size_t bb_dma_span_bytes(uint64_t depth, uint64_t stride, + uint32_t groups) { + size_t row_bytes = (size_t)BANK_WIDTH / 8; + uint32_t g = groups < 1 ? 1 : groups; + + if (depth == 0) + return 0; + return ((size_t)(depth - 1) * (size_t)stride + 1) * row_bytes * (size_t)g; +} + +void bb_dma_bank_set_cols(uint32_t bank_id, uint32_t cols); +uint32_t bb_dma_bank_cols(uint32_t bank_id); + +/* + * Force private writable pages for a DMA buffer under Linux. + * Untouched BSS is CoW-mapped to the shared zero page; accelerator stores + * translate to that PPN and do not install a private page, so CPU reads stay 0. + * Prefer clear_* or memset when the buffer should also be zeroed. + */ +void bb_dma_touch(void *p, size_t n); + +/* Touch host span for mvout using cols recorded by bb_mem_alloc. */ +void bb_dma_touch_mvout(void *p, uint64_t depth, uint64_t stride, + uint32_t bank_id); + +#ifdef __cplusplus +} +#endif + +#endif // _MEM_H_ diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.c b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.c new file mode 100644 index 0000000..bd0e10a --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.c @@ -0,0 +1,325 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +#define DIM (BANK_WIDTH / sizeof(elem_t)) + +/* Read cycle counter (rdcycle) helper. Works on RV64 with a single rdcycle. + On RV32 we read low/high and detect rollover to produce a 64-bit value. */ +unsigned long long read_rdcycle(void) { +#if defined(BUCKYBALL_RUSHB) + return rushb_cycles(BUCKYBALL_RUSHB_CORE); +#elif defined(__riscv_xlen) && __riscv_xlen == 64 + unsigned long long cycles; + asm volatile("rdcycle %0" : "=r"(cycles)); + return cycles; +#else + unsigned int lo1, hi, lo2; + /* Loop until two consecutive low reads are equal to avoid rollover window */ + asm volatile("1: rdcycle %0\n" + " rdcycleh %1\n" + " rdcycle %2\n" + " bne %0, %2, 1b\n" + : "=&r"(lo1), "=&r"(hi), "=&r"(lo2)); + return ((unsigned long long)hi << 32) | lo1; +#endif +} + +void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + matrix[i] = rand() % 128; + } +} + +// Initialize matrix with incrementing values for debugging +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = (start_value + i) & 0xFF; // Keep values in 0-255 range + } +} + +void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + matrix[i] = rand() % 256; + } +} +int compare_u8_matrices(elem_t *a, elem_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + // print_matrix("Expected", b, 1, cols); + // print_matrix("Actual", a, 1, cols); + return 0; + } + } + return 1; +} +int compare_u32_matrices(result_t *a, result_t *b, int rows, int cols) { + for (int i = 0; i <= rows * cols - 1; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} + +void init_i8_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + /* produce values in range -128 .. 127 */ + matrix[i] = (elem_t)((rand() % 256) - 128); + } +} +void init_i32_random_matrix(result_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + /* produce values in a reasonable 16-bit signed range -32768 .. 32767 */ + matrix[i] = (result_t)((rand() % 65536) - 32768); + } +} +int compare_i8_matrices(elem_t *a, elem_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} +int compare_i32_matrices(result_t *a, result_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} + +void print_u32_matrix(const char *name, result_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +void print_u8_matrix(const char *name, elem_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +// Signed print variants +void print_i32_matrix(const char *name, result_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} + +void print_i8_matrix(const char *name, elem_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + /* cast to int to avoid printing as char */ + printf("%4d ", (int)matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +void clear_u32_matrix(result_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(result_t)); +} +void clear_u8_matrix(elem_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(elem_t)); +} +void clear_i32_matrix(result_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(result_t)); +} +void clear_i8_matrix(elem_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(elem_t)); +} + +void init_ones_matrix(elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = 1; + } +} + +void init_identity_matrix(elem_t *matrix, int size) { + clear_u8_matrix(matrix, size, size); + for (int i = 0; i < size; i++) { + matrix[i * size + i] = 1; + } +} + +void init_row_vector(elem_t *matrix, int cols, elem_t value) { + clear_u8_matrix(matrix, DIM, DIM); + for (int j = 0; j < cols; j++) { + matrix[j] = value; + } +} + +void init_col_vector(elem_t *matrix, int rows, elem_t value) { + clear_u8_matrix(matrix, DIM, DIM); + for (int i = 0; i < rows; i++) { + matrix[i * DIM] = value; + } +} + +void init_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + // Random number in range 0-4 + matrix[i * cols + j] = (rand() % 5); + } + } +} + +void init_matrix_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = (rand() % 16); + } + } +} + +void init_sequence_matrix(elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = i + j; + } + } +} +// Initialize column-aligned random matrix and original matrix +void init_col_aligned_random_matrix(elem_t *aligned_matrix, elem_t *matrix, + int align, int rows, int cols, int seed) { + srand(seed); + int aligned_cols = (cols + align - 1) / align * align; + for (int i = 0; i < rows; i++) { + for (int j = 0; j < aligned_cols; j++) { + aligned_matrix[i * aligned_cols + j] = (j < cols) ? (rand() % 128) : 0; + } + } + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = aligned_matrix[i * aligned_cols + j]; + } + } +} +// Transpose matrix +void transpose_u8_matrix(elem_t *src, elem_t *dst, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + dst[j * rows + i] = src[i * cols + j]; + } + } +} +void transpose_u32_matrix(result_t *src, result_t *dst, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + dst[j * rows + i] = src[i * cols + j]; + } + } +} + +result_t gemmini_in_shift(result_t v, int shift) { + if (shift <= 0) + return v; + if (shift >= 32) + return 0; + + uint32_t s = (uint32_t)shift; + uint32_t bits = (uint32_t)v; + uint32_t point_five = (bits >> (s - 1)) & 1; + uint32_t zeros = (s <= 1) ? 0 : ((bits & ((1u << (s - 1)) - 1)) != 0); + uint32_t ones_digit = (bits >> s) & 1; + uint32_t r = point_five & (zeros | ones_digit); + return (v >> s) + (result_t)r; +} + +// CPU matrix multiplication (used to generate expected results) +void cpu_matmul(elem_t *a, elem_t *b, result_t *c, int rows, int cols, + int inner) { + clear_u32_matrix(c, rows, cols); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + for (int k = 0; k < inner; k++) { + c[i * cols + j] += a[i * inner + k] * b[k * cols + j]; + } + } + } +} + +// CPU ReLU activation function +void cpu_relu(elem_t *a, elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = (a[i] > 0) ? a[i] : 0; + } +} + +// CPU transfer from elem_t to result_t +void cpu_transfer(elem_t *src, elem_t *dst, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + dst[i] = (result_t)src[i]; + } +} +unsigned long long read_cycle(void) { +#if defined(BUCKYBALL_RUSHB) + return rushb_cycles(BUCKYBALL_RUSHB_CORE); +#else + unsigned long long c; + asm volatile("csrr %0, cycle" : "=r"(c)); + return c; +#endif +} + +// MMIO stubs are for baremetal/BBSim only. +// Linux user-mode tests (`*-linux` under `spike pk`) must use libc/syscall exit +// path. +#if !defined(__linux__) +// MMIO address map (BBSimHarness, WithDefaultMMIOPort base=0x6000_0000): +// 0x6000_0000 : simulation exit — write triggers sim_exit() +// 0x6002_0000 : UART0 TX — write low byte → putchar in C++ +#define MMIO_SIM_EXIT ((volatile uint32_t *)0x60000000UL) +#define MMIO_UART_TX ((volatile uint32_t *)0x60020000UL) + +// _write: route stdout/stderr through MMIO UART so printf works in simulation. +// nosys.specs provides a weak _write stub; we override it here. +int _write(int fd, const char *buf, int len) { + (void)fd; + for (int i = 0; i < len; i++) { + *MMIO_UART_TX = (uint32_t)(unsigned char)buf[i]; + } + return len; +} + +// _exit: write exit code to MMIO sim-exit register; C++ mmio_tick() detects +// this and calls sim_exit(). +void __attribute__((noreturn)) _exit(int code) { + *MMIO_SIM_EXIT = (uint32_t)code; + while (1) { + } // wait for C++ to process the MMIO write and call sim_exit() +} +#endif diff --git a/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.h b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.h new file mode 100644 index 0000000..f0aa3e6 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/bb-tests/workloads/lib/buckyball.h @@ -0,0 +1,90 @@ +#ifndef BUCKYBALL_H +#define BUCKYBALL_H + +#include + +// String macros (from xcustom.h) +// #define STR1(x) #x +// #ifndef STR +// #define STR(x) STR1(x) +// #endif + +#define CAT_(A, B) A##B +#define CAT(A, B) CAT_(A, B) + +// Data type for matrix elements +typedef int8_t elem_t; +typedef int32_t result_t; + +#if defined(BUCKYBALL_RUSHB) +#define MULTICORE_INIT(hart_id) + +static inline void multicore(int target_hart_id) { (void)target_hart_id; } +#else +#define MULTICORE_INIT(hart_id) \ + __attribute__((constructor)) static void _multicore_init() { \ + multicore(hart_id); \ + } + +static inline void multicore(int target_hart_id) { + int hart_id; + asm volatile("csrr %0, mhartid" : "=r"(hart_id)); + + if (hart_id != target_hart_id) { + while (1) { + asm volatile("wfi"); // Wait for interrupt + } + } + // If hart_id == target_hart_id, continue execution +} +#endif + +// Utility functions + +/* Read CPU cycle counter (64-bit). Implemented in buckyball.c for global use */ +unsigned long long read_rdcycle(void); + +void print_u32_matrix(const char *name, result_t *matrix, int rows, int cols); +void print_u8_matrix(const char *name, elem_t *matrix, int rows, int cols); +void print_i32_matrix(const char *name, result_t *matrix, int rows, int cols); +void print_i8_matrix(const char *name, elem_t *matrix, int rows, int cols); + +void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value); +void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed); +void init_i8_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_i32_random_matrix(result_t *matrix, int rows, int cols, int seed); + +int compare_u8_matrices(elem_t *a, elem_t *b, int rows, int cols); +int compare_u32_matrices(result_t *a, result_t *b, int rows, int cols); +int compare_i8_matrices(elem_t *a, elem_t *b, int rows, int cols); +int compare_i32_matrices(result_t *a, result_t *b, int rows, int cols); +int compare_u32_matrices_with_tolerance(result_t *a, result_t *b, int rows, + int cols, double tolerance); +void clear_u32_matrix(result_t *matrix, int rows, int cols); +void clear_u8_matrix(elem_t *matrix, int rows, int cols); +void clear_i32_matrix(result_t *matrix, int rows, int cols); +void clear_i8_matrix(elem_t *matrix, int rows, int cols); + +void init_ones_matrix(elem_t *matrix, int rows, int cols); +void init_identity_matrix(elem_t *matrix, int size); +void init_row_vector(elem_t *matrix, int cols, elem_t value); +void init_col_vector(elem_t *matrix, int rows, elem_t value); +void init_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_matrix_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_sequence_matrix(elem_t *matrix, int rows, int cols); +void init_col_aligned_random_matrix(elem_t *aligned_matrix, elem_t *matrix, + int align, int rows, int cols, int seed); +/* Matrix operation functions */ +void transpose_u8_matrix(elem_t *src, elem_t *dst, int rows, int cols); +void transpose_u32_matrix(result_t *src, result_t *dst, int rows, int cols); +void cpu_matmul(elem_t *a, elem_t *b, result_t *c, int rows, int cols, + int inner); +result_t gemmini_in_shift(result_t v, int shift); +void cpu_relu(elem_t *a, elem_t *matrix, int rows, int cols); +void cpu_transfer(elem_t *src, elem_t *dst, int rows, int cols); + +unsigned long long read_cycle(void); + +#endif diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt new file mode 100644 index 0000000..a144971 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt @@ -0,0 +1,15 @@ +add_buckyball_ctests( + gemmini_os_cisc_atranspose_test.c + gemmini_os_cisc_basic_test.c + gemmini_os_cisc_btranspose_test.c + gemmini_os_cisc_shift_test.c + gemmini_os_risc_abtranspose_test.c + gemmini_os_risc_atranspose_test.c + gemmini_os_risc_basic_test.c + gemmini_os_risc_btranspose_test.c + gemmini_os_risc_shift_test.c + gemmini_ws_cisc_conv_test.c + gemmini_ws_risc_basic_test.c + gemmini_ws_risc_btranspose_test.c + gemmini_ws_risc_shift_test.c +) diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c new file mode 100644 index 0000000..424b541 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c new file mode 100644 index 0000000..0eee2d3 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c @@ -0,0 +1,45 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC Basic Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c new file mode 100644 index 0000000..9e29309 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c new file mode 100644 index 0000000..098d48f --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c @@ -0,0 +1,48 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c new file mode 100644 index 0000000..73ce600 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC ab_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_at, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC ab_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC ab_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c new file mode 100644 index 0000000..e7d2fa4 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c new file mode 100644 index 0000000..7effed4 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c @@ -0,0 +1,71 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t zeros[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini OS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2, bank_d_zeros = 3; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mem_alloc(bank_d_zeros, 1, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_mvin((uintptr_t)zeros, bank_d_zeros, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, 0); + /* Preload D from zeros bank so C = A*B + D = A*B (not A*B + A) */ + bb_gemmini_preload(bank_d_zeros, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + bb_mem_release(bank_d_zeros); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC Basic Test PASSED\n"); + return 0; + } + + printf("got mat_c: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", mat_c[i]); + } + printf("\n"); + // for (int i = 0; i < DIM; i++) { + // for (int j = 0; j < DIM; j++) { + // printf("%d ", mat_c[i * DIM + j]); + // } + // printf("\n"); + // } + + printf("exp row0: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", expected[i]); + } + printf("\n"); + printf("Gemmini OS RISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c new file mode 100644 index 0000000..ac88ccb --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c new file mode 100644 index 0000000..d6ad4c9 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c @@ -0,0 +1,52 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c new file mode 100644 index 0000000..d990afd --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c @@ -0,0 +1,74 @@ +#include "buckyball.h" +#include +#include +#include +#include + +// Pointwise conv: batch=1, in_dim=1, in_channels=DIM, out_channels=DIM, +// kernel=1 Degenerates to a single DIM x DIM matmul (input[1x1xIC] * +// weight[1x1xICxOC]) +#define DIM 16 +#define BATCH 1 +#define IN_DIM 1 +#define OUT_DIM 1 +#define IN_CH DIM +#define OUT_CH DIM +#define KERNEL_DIM 1 + +// input layout: [batch, in_dim, in_dim, in_ch] = [1, 1, 1, 16] = 16 bytes +// weight layout: [krow, kcol, in_ch, out_ch] = [1, 1, 16, 16] = 256 bytes +// output layout: [batch, out_dim, out_dim, out_ch] = [1, 1, 1, 16] x 4 bytes = +// 64 bytes +static elem_t input[BATCH * IN_DIM * IN_DIM * IN_CH] + __attribute__((aligned(64))); +static elem_t weight[KERNEL_DIM * KERNEL_DIM * IN_CH * OUT_CH] + __attribute__((aligned(64))); +static result_t output[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); +static result_t expected[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS CISC Loop Conv Test ===\n"); + + for (int k = 0; k < IN_CH; ++k) { + input[k] = k % 7 - 3; + for (int out = 0; out < OUT_CH; ++out) + weight[k * OUT_CH + out] = (2 * k + 3 * out) % 5 - 2; + } + + // CPU reference: output[0..OUT_CH] = sum_k(input[k] * weight[k][j]) + // cpu_matmul(A[M×K], B[K×N], C[M×N]) — here A=input(1×IN_CH), + // B=weight(IN_CH×OUT_CH) + cpu_matmul(input, weight, expected, 1, OUT_CH, IN_CH); + + // Strides: + // input_stride = in_ch * elemSize = 16 * 1 = 16 (bytes per spatial step) + // weight_stride = in_ch * out_ch * elemSize = 16 * 16 * 1 = 256 (bytes per + // kernel step) output_stride = out_ch * accBytes = 16 * 4 = 64 + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_1(BATCH, IN_DIM, IN_CH); + bb_gemmini_loop_conv_ws_config_2(OUT_CH, OUT_DIM, 1, 0); + bb_gemmini_loop_conv_ws_config_3(KERNEL_DIM, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_4(0); // no bias + bb_gemmini_loop_conv_ws_config_5((uintptr_t)input); + bb_gemmini_loop_conv_ws_config_6((uintptr_t)weight); + bb_gemmini_loop_conv_ws_config_7((uintptr_t)output); + bb_gemmini_loop_conv_ws_config_8( + IN_CH, IN_CH * OUT_CH); // input_stride, weight_stride + bb_gemmini_loop_conv_ws_config_9(OUT_CH * 4); // output_stride (accBytes=4) + bb_gemmini_loop_conv_ws( + 0, 1, 2, 1); // bank_input=0, bank_weight=1, bank_output=2, no_bias=1 + bb_fence(); + + if (compare_u32_matrices(output, expected, 1, OUT_CH)) { + printf("Gemmini WS CISC Loop Conv Test PASSED\n"); + return 0; + } + printf("Gemmini WS CISC Loop Conv Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c new file mode 100644 index 0000000..6c8f7df --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini WS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC Basic Test PASSED\n"); + return 0; + } + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c new file mode 100644 index 0000000..e4c3149 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c @@ -0,0 +1,56 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 1, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c new file mode 100644 index 0000000..905824e --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c @@ -0,0 +1,57 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h new file mode 100644 index 0000000..2994d8f --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h @@ -0,0 +1,12 @@ +#ifndef _BB_GEMMINI_ISA_H_ +#define _BB_GEMMINI_ISA_H_ + +#include "gemmini_compute_accumulated.h" +#include "gemmini_compute_preloaded.h" +#include "gemmini_config.h" +#include "gemmini_flush.h" +#include "gemmini_loop_conv_ws.h" +#include "gemmini_loop_ws.h" +#include "gemmini_preload.h" + +#endif // _BB_GEMMINI_ISA_H_ diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h new file mode 100644 index 0000000..d3fda03 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ +#define _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ + +#include +#include + +#define BB_GEMMINI_COMPUTE_ACCUMULATED_RS2 3ULL + +// Compute matmul reusing previously accumulated results +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B/D matrix +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_accumulated(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter, op1_base, op2_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_ITER(iter)), \ + BB_GEMMINI_COMPUTE_ACCUMULATED_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(op2_base) << 16) | ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_COMPUTE_ACCUMULATED)) + +#endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h new file mode 100644 index 0000000..c39d3b1 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_COMPUTE_PRELOADED_H_ +#define _BB_GEMMINI_COMPUTE_PRELOADED_H_ + +#include +#include + +#define BB_GEMMINI_COMPUTE_PRELOADED_RS2 2ULL + +// Compute matmul using preloaded data: C = A * B + D(preloaded) +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B matrix (OS) or D matrix (WS) +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter, op1_base, op2_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_ITER(iter)), \ + BB_GEMMINI_COMPUTE_PRELOADED_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(op2_base) << 16) | ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_COMPUTE_PRELOADED)) + +#endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h new file mode 100644 index 0000000..fc50c07 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_CONFIG_H_ +#define _BB_GEMMINI_CONFIG_H_ + +#include +#include + +// Configure Gemmini matrix array +// All config parameters go in rs2 (special), starting from bit 4. +// rs2[3:0] is the sub-command field and remains 0 for this instruction. +// dataflow: 0=OS, 1=WS +// activation: 0=none, 1=relu +// a_transpose, b_transpose: transpose flags +// in_shift: right-shift amount for output +#define bb_gemmini_config(dataflow, activation, a_transpose, b_transpose, \ + in_shift) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(dataflow, 4, 4) | FIELD(activation, 5, 6) | \ + FIELD(a_transpose, 7, 7) | \ + FIELD(b_transpose, 8, 8) | \ + FIELD(in_shift, 9, 40)), \ + BB_FUNC7(GEMMINI_CONFIG)) + +#endif // _BB_GEMMINI_CONFIG_H_ diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h new file mode 100644 index 0000000..2c55b62 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h @@ -0,0 +1,13 @@ +#ifndef _BB_GEMMINI_FLUSH_H_ +#define _BB_GEMMINI_FLUSH_H_ + +#include +#include + +#define BB_GEMMINI_FLUSH_RS2 4ULL + +// Flush the matrix array state +#define bb_gemmini_flush() \ + BUCKYBALL_INSTRUCTION_R_R(0, BB_GEMMINI_FLUSH_RS2, BB_FUNC7(GEMMINI_FLUSH)) + +#endif // _BB_GEMMINI_FLUSH_H_ diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h new file mode 100644 index 0000000..5f04089 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h @@ -0,0 +1,62 @@ +#ifndef _BB_GEMMINI_LOOP_CONV_WS_H +#define _BB_GEMMINI_LOOP_CONV_WS_H + +#include +#include + +#define bb_gemmini_loop_conv_ws_config_1(batch_size, in_dim, in_channels) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(batch_size, 0, 15) | \ + FIELD(in_dim, 16, 31) | \ + FIELD(in_channels, 32, 47)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_1)) + +#define bb_gemmini_loop_conv_ws_config_2(out_channels, out_dim, stride, \ + padding) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(out_channels, 0, 15) | \ + FIELD(out_dim, 16, 31) | FIELD(stride, 32, 39) | \ + FIELD(padding, 40, 47)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_2)) + +#define bb_gemmini_loop_conv_ws_config_3(kernel_dim, pool_size, pool_stride, \ + pool_padding) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(kernel_dim, 0, 7) | FIELD(pool_size, 8, 15) | \ + FIELD(pool_stride, 16, 23) | FIELD(pool_padding, 24, 31)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_3)) + +#define bb_gemmini_loop_conv_ws_config_4(addr_bias) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_bias, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_4)) + +#define bb_gemmini_loop_conv_ws_config_5(addr_input) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_input, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_5)) + +#define bb_gemmini_loop_conv_ws_config_6(addr_weight) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_weight, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_6)) + +#define bb_gemmini_loop_conv_ws_config_7(addr_output) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_output, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_7)) + +#define bb_gemmini_loop_conv_ws_config_8(input_stride, weight_stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(input_stride, 0, 31) | FIELD(weight_stride, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_8)) + +#define bb_gemmini_loop_conv_ws_config_9(output_stride) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(output_stride, 0, 31), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_9)) + +#define bb_gemmini_loop_conv_ws(bank_input, bank_weight, bank_output, no_bias) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(bank_input, 0, 9) | FIELD(bank_weight, 10, 19) | \ + FIELD(bank_output, 20, 29) | FIELD(no_bias, 30, 30)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS)) + +#endif diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h new file mode 100644 index 0000000..769c1f6 --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h @@ -0,0 +1,44 @@ +#ifndef _BB_GEMMINI_LOOP_WS_H +#define _BB_GEMMINI_LOOP_WS_H + +#include +#include + +#define bb_gemmini_loop_ws_config_bounds(max_i, max_j, max_k) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(max_k, 0, 15) | FIELD(max_j, 16, 31) | FIELD(max_i, 32, 47)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_BOUNDS)) + +#define bb_gemmini_loop_ws_config_addr_a(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_A)) + +#define bb_gemmini_loop_ws_config_addr_b(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_B)) + +#define bb_gemmini_loop_ws_config_addr_d(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_D)) + +#define bb_gemmini_loop_ws_config_addr_c(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_C)) + +#define bb_gemmini_loop_ws_config_strides_ab(stride_a, stride_b) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_a, 0, 31) | FIELD(stride_b, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_STRIDES_AB)) + +#define bb_gemmini_loop_ws_config_strides_dc(stride_d, stride_c) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_d, 0, 31) | FIELD(stride_c, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_STRIDES_DC)) + +#define bb_gemmini_loop_ws(bank_a, bank_b, bank_c, low_d) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(bank_a, 0, 9) | FIELD(bank_b, 10, 19) | \ + FIELD(bank_c, 20, 29) | FIELD(low_d, 30, 30)), \ + BB_FUNC7(GEMMINI_LOOP_WS)) + +#endif diff --git a/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h new file mode 100644 index 0000000..f1f578b --- /dev/null +++ b/platforms/arty-a7-toy/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h @@ -0,0 +1,20 @@ +#ifndef _BB_GEMMINI_PRELOAD_H_ +#define _BB_GEMMINI_PRELOAD_H_ + +#include +#include + +#define BB_GEMMINI_PRELOAD_RS2 1ULL + +// Preload D/B matrix into matrix array +// op1_bank_id: source bank for D (OS) or B (WS) +// wr_bank_id: destination bank for C output +// iter: number of rows to preload +#define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter, op1_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + BB_GEMMINI_PRELOAD_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_PRELOAD)) + +#endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/platforms/arty-a7-toy/tests/serial_loop_stress.c b/platforms/arty-a7-toy/tests/serial_loop_stress.c new file mode 100644 index 0000000..380f87b --- /dev/null +++ b/platforms/arty-a7-toy/tests/serial_loop_stress.c @@ -0,0 +1,39 @@ +// Four 8x8 column tiles: 11 loop rows exceed the 8-row SubROB. +// Forty alternating OS/WS loops cross the 255-token mesh-tag wrap point. +// Compare every INT32 result against the pinned CPU matrix reference. +#include "buckyball.h" +#include +#include +#include + +#define M 8 +#define N 32 +#define K 8 +static elem_t a[M * K] __attribute__((aligned(64))); +static elem_t b[K * N] __attribute__((aligned(64))); +static result_t c[M * N] __attribute__((aligned(64))); +static result_t expected[M * N] __attribute__((aligned(64))); + +int main(void) { + for (int r = 0; r < M; ++r) + for (int k = 0; k < K; ++k) a[r * K + k] = (r * 3 + k * 5) % 9 - 4; + for (int k = 0; k < K; ++k) + for (int n = 0; n < N; ++n) b[k * N + n] = (k * 7 + n * 2) % 11 - 5; + cpu_matmul(a, b, expected, M, N, K); + for (int run = 0; run < 40; ++run) { + int mode = run & 1; + clear_u32_matrix(c, M, N); + bb_gemmini_config(mode, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 4, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)c); + bb_gemmini_loop_ws_config_strides_ab(K, N); + bb_gemmini_loop_ws_config_strides_dc(0, N * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + if (!compare_u32_matrices(c, expected, M, N)) return run + 1; + } + return 0; +} diff --git a/platforms/arty-a7-toy/tests/tb_axi_fullwidth.sv b/platforms/arty-a7-toy/tests/tb_axi_fullwidth.sv new file mode 100644 index 0000000..c610b66 --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_axi_fullwidth.sv @@ -0,0 +1,110 @@ +`timescale 1ns/1ps +module tb_axi_fullwidth; + reg clk=0;always #5 clk=~clk; + reg reset=1; + reg [3:0] s_awid=0,s_arid=0; + reg [31:0] s_awaddr=0,s_araddr=0; + reg [7:0] s_awlen=0,s_arlen=0; + reg [2:0] s_awsize=0,s_arsize=0; + reg [1:0] s_awburst=1,s_arburst=1; + reg s_awvalid=0,s_arvalid=0,s_wvalid=0,s_wlast=0,s_bready=0,s_rready=0; + wire s_awready,s_arready,s_wready; + reg [127:0] s_wdata=0;reg [15:0] s_wstrb=0; + wire [3:0] s_bid,s_rid;wire [1:0] s_bresp,s_rresp; + wire s_bvalid,s_rvalid,s_rlast;wire [127:0] s_rdata; + wire [3:0] m_awid,m_arid; + wire [27:0] m_awaddr,m_araddr;wire [7:0] m_awlen,m_arlen; + wire [2:0] m_awsize,m_arsize;wire [1:0] m_awburst,m_arburst; + wire m_awvalid,m_arvalid,m_wvalid,m_wlast,m_bready,m_rready; + wire m_awready,m_arready,m_wready; + wire [127:0] m_wdata;wire [15:0] m_wstrb; + wire [3:0] m_bid,m_rid;wire [1:0] m_bresp,m_rresp; + wire m_bvalid,m_rvalid,m_rlast;wire [127:0] m_rdata; + reg [7:0] expected[0:4095]; + integer beats=0; + axi_fullwidth dut(.*); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset), + .aw_ready(m_awready),.aw_valid(m_awvalid),.aw_bits_id(m_awid),.aw_bits_addr(m_awaddr), + .aw_bits_len(m_awlen),.aw_bits_size(m_awsize),.aw_bits_burst(m_awburst), + .w_ready(m_wready),.w_valid(m_wvalid),.w_bits_data(m_wdata),.w_bits_strb(m_wstrb),.w_bits_last(m_wlast), + .b_ready(m_bready),.b_valid(m_bvalid),.b_bits_id(m_bid),.b_bits_resp(m_bresp), + .ar_ready(m_arready),.ar_valid(m_arvalid),.ar_bits_id(m_arid),.ar_bits_addr(m_araddr), + .ar_bits_len(m_arlen),.ar_bits_size(m_arsize),.ar_bits_burst(m_arburst), + .r_ready(m_rready),.r_valid(m_rvalid),.r_bits_id(m_rid),.r_bits_data(m_rdata),.r_bits_resp(m_rresp),.r_bits_last(m_rlast)); + always @(posedge clk) begin + if(m_awvalid && m_awready && (m_awaddr[3:0]!=0 || m_awsize!=4 || m_awlen!=0)) $fatal(1,"MIG narrow write"); + if(m_arvalid && m_arready && (m_araddr[3:0]!=0 || m_arsize!=4 || m_arlen!=0)) $fatal(1,"MIG narrow read"); + end + task automatic write_burst(input integer address,z,n,id,input bit fixed_addr,input [1:0] response); + integer a; + begin + @(negedge clk);s_awaddr=address;s_awsize=z;s_awlen=n-1;s_awid=id;s_awburst=!fixed_addr;s_awvalid=1; + do @(posedge clk);while(!s_awready); + @(negedge clk);s_awvalid=0; + for(integer b=0;b>(addr[2:0]*8) & 255)!==expected) + $fatal(1,"SCU read addr=%h data=%h resp=%h",addr,rdata,rresp); + @(negedge clk); + end + rready=1;@(negedge clk);rready=0; + end + endtask + initial begin + repeat(4) @(negedge clk);reset=0; + @(negedge clk);rx_data=8'h71;rx_valid=1;@(negedge clk);rx_valid=0; + read_byte(31'h60020005,1,0); + if(!interrupt) $fatal(1,"RX IRQ missing"); + read_byte(31'h60020004,8'h71,0); + if(interrupt) $fatal(1,"RX not popped exactly once"); + read_byte(31'h60020005,0,0); + // A whole pasted command must survive a long interval between SBI polls. + for(integer j=0;j<200;j=j+1) begin + @(negedge clk);rx_data=j;rx_valid=1;@(negedge clk);rx_valid=0; + end + if(dut.overflow) $fatal(1,"FIFO overflow on a 200-byte paste"); + for(integer j=0;j<200;j=j+1) read_byte(31'h60020004,j[7:0],0); + if(interrupt) $fatal(1,"FIFO not drained after paste"); + read_byte(31'h60030000,0,2); + @(negedge clk);awaddr=31'h60020000;awid=3;awvalid=1; + @(negedge clk);awvalid=0;wdata=64'h53;wstrb=1;wvalid=1; + repeat(10) begin @(negedge clk);if(wready || bvalid) $fatal(1,"SCU lost TX backpressure");end + tx_ready=1;@(negedge clk);wvalid=0; + repeat(4) @(negedge clk); + if(!bvalid || bid!==3 || bresp!==0 || tx_count!=1) $fatal(1,"SCU TX response/count"); + bready=1;@(negedge clk);bready=0; + awaddr=31'h60000000;awsize=2;awvalid=1;@(negedge clk);awvalid=0; + wdata=64'h12345678;wstrb=15;wvalid=1;@(negedge clk);wvalid=0; + if(!exited || exit_code!==32'h12345678) $fatal(1,"SCU EXIT decode"); + $display("PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT");$finish; + end + initial begin #100000;$fatal(1,"SCU watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/tests/tb_fpu_rf.sv b/platforms/arty-a7-toy/tests/tb_fpu_rf.sv new file mode 100644 index 0000000..482c44c --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_fpu_rf.sv @@ -0,0 +1,98 @@ +`timescale 1ns/1ps +module tb; + reg clk = 0; + always #5 clk = ~clk; + reg [4:0] ra0 = 0, ra1 = 0, ra2 = 0, wa0 = 0, wa1 = 0; + reg re0 = 0, re1 = 0, re2 = 0, we0 = 0, we1 = 0; + reg [64:0] wd0 = 0, wd1 = 0; + wire [64:0] old0, old1, old2, new0, new1, new2; + reg [64:0] expected [0:31]; + reg [31:0] valid = 0; + integer seed = 99127; + integer comparisons = 0, dual_writes = 0, same_address_writes = 0; + + FpuRfOriginal original( + .R0_addr(ra0), .R0_en(re0), .R0_clk(clk), .R0_data(old0), + .R1_addr(ra1), .R1_en(re1), .R1_clk(clk), .R1_data(old1), + .R2_addr(ra2), .R2_en(re2), .R2_clk(clk), .R2_data(old2), + .W0_addr(wa0), .W0_en(we0), .W0_clk(clk), .W0_data(wd0), + .W1_addr(wa1), .W1_en(we1), .W1_clk(clk), .W1_data(wd1) + ); + FpuRfLvt candidate( + .R0_addr(ra0), .R0_en(re0), .R0_clk(clk), .R0_data(new0), + .R1_addr(ra1), .R1_en(re1), .R1_clk(clk), .R1_data(new1), + .R2_addr(ra2), .R2_en(re2), .R2_clk(clk), .R2_data(new2), + .W0_addr(wa0), .W0_en(we0), .W0_clk(clk), .W0_data(wd0), + .W1_addr(wa1), .W1_en(we1), .W1_clk(clk), .W1_data(wd1) + ); + + function [64:0] random_data; + reg [31:0] lo, hi, extra; + begin + lo = $random(seed); hi = $random(seed); extra = $random(seed); + random_data = {extra[0], hi, lo}; + end + endfunction + + task check; + begin + if (re0 && valid[ra0]) begin + if (old0 !== expected[ra0] || new0 !== expected[ra0]) + $fatal(1, "R0 mismatch at %0d", ra0); + comparisons = comparisons + 1; + end + if (re1 && valid[ra1]) begin + if (old1 !== expected[ra1] || new1 !== expected[ra1]) + $fatal(1, "R1 mismatch at %0d", ra1); + comparisons = comparisons + 1; + end + if (re2 && valid[ra2]) begin + if (old2 !== expected[ra2] || new2 !== expected[ra2]) + $fatal(1, "R2 mismatch at %0d", ra2); + comparisons = comparisons + 1; + end + end + endtask + + task edge_and_check; + begin + #1; check(); + @(posedge clk); + if (we0) begin expected[wa0] = wd0; valid[wa0] = 1; end + if (we1) begin expected[wa1] = wd1; valid[wa1] = 1; end + if (we0 && we1) begin + dual_writes = dual_writes + 1; + if (wa0 == wa1) same_address_writes = same_address_writes + 1; + end + #1; check(); + // Asynchronous reads must follow new addresses without a clock edge. + ra0 = ra0 + 1; ra1 = ra1 + 3; ra2 = ra2 + 7; + #1; check(); + end + endtask + + initial begin + for (integer i = 0; i < 32; i = i + 1) begin + @(negedge clk); + wa0 = i; we0 = 1; we1 = 0; wd0 = random_data(); + re0 = 1; re1 = 1; re2 = 1; + edge_and_check(); + end + for (integer i = 0; i < 20000; i = i + 1) begin + @(negedge clk); + wa0 = $random(seed); wa1 = $random(seed); + if (i % 4 == 0) wa1 = wa0; + we0 = (i % 8 != 0); we1 = (i % 8 != 1); + wd0 = random_data(); wd1 = random_data(); + ra0 = wa0; ra1 = wa1; ra2 = $random(seed); + re0 = (i % 5 != 0); re1 = (i % 5 != 1); re2 = (i % 5 != 2); + edge_and_check(); + end + if (dual_writes < 10000 || same_address_writes < 2000 || comparisons < 100000) + $fatal(1, "Insufficient conflict/asynchronous read coverage"); + $display("PASS FPU_RF_LVT cycles=20032 comparisons=%0d dual_writes=%0d same_address_writes=%0d", + comparisons, dual_writes, same_address_writes); + $finish; + end + initial begin #1000000; $fatal(1, "RF test timeout"); end +endmodule diff --git a/platforms/arty-a7-toy/tests/tb_group_query.sv b/platforms/arty-a7-toy/tests/tb_group_query.sv new file mode 100644 index 0000000..c340835 --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_group_query.sv @@ -0,0 +1,23 @@ +module tb; + reg clock = 0; + reg reset = 1; + wire passed; + GroupQueryCheck dut(.clock(clock), .reset(reset), .passed(passed)); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + wait(passed); + @(negedge clock); + reset = 1; + repeat (5) @(negedge clock); + reset = 0; + wait(passed); + $display("PASS: 256 concurrent group queries, stalls, shared/private selection, reset and repeat"); + $finish; + end + initial begin + #200000; + $fatal(1, "Group query timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/tests/tb_round_shift.sv b/platforms/arty-a7-toy/tests/tb_round_shift.sv new file mode 100644 index 0000000..725a304 --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_round_shift.sv @@ -0,0 +1,59 @@ +module tb; + logic signed [19:0] value20; + logic signed [31:0] value32; + logic [4:0] amount; + wire signed [19:0] actual20, original20; + wire signed [31:0] actual32, original32; + RoundShiftChecks dut(.*); + integer comparisons = 0; + logic [63:0] rng = 64'h17339cab28eaf641; + + // Independent oracle: magnitude division/remainder, not a barrel-shift copy. + function automatic longint signed nearest_even(input longint signed v, + input integer s); + longint signed magnitude, divisor, quotient, remainder; + if (s == 0) return v; + magnitude = v < 0 ? -v : v; + divisor = 64'sd1 << s; + quotient = magnitude / divisor; + remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2 != 0)) quotient++; + return v < 0 ? -quotient : quotient; + endfunction + + task automatic check(input longint signed v, input integer s); + longint signed expected20, expected32; + value20 = v[19:0]; + value32 = v[31:0]; + amount = s[4:0]; + #1; + expected20 = nearest_even(longint'(value20), s); + expected32 = nearest_even(longint'(value32), s); + if (actual20 !== expected20[19:0] || actual32 !== expected32[31:0] || + actual20 !== original20 || actual32 !== original32) + $fatal(1, "RNE v=%0d s=%0d actual20=%0d gold20=%0d actual32=%0d gold32=%0d", + v, s, actual20, expected20, actual32, expected32); + comparisons += 2; + endtask + + initial begin + for (integer s = 0; s < 32; s++) begin + check(0, s); check(1, s); check(-1, s); + check(2147483647, s); check(-2147483648, s); + check(524287, s); check(-524288, s); + if (s > 0) begin + // Halfway and adjacent values on either side, odd/even positive/negative. + for (integer q = -6; q <= 6; q++) + for (integer delta = -1; delta <= 1; delta++) + check(q * (64'sd1 << s) + (64'sd1 << (s - 1)) + delta, s); + end + end + for (integer i = 0; i < 200000; i++) begin + rng ^= rng << 13; rng ^= rng >> 7; rng ^= rng << 17; + check(longint'(int'(rng[31:0])), int'(rng[36:32])); + end + $display("PASS ROUND_SHIFT comparisons=%0d widths=20,32 shifts=0..31", comparisons); + $finish; + end +endmodule diff --git a/platforms/arty-a7-toy/tests/tb_subrob.sv b/platforms/arty-a7-toy/tests/tb_subrob.sv new file mode 100644 index 0000000..90d00a7 --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_subrob.sv @@ -0,0 +1,16 @@ +module tb; + reg clock = 0, reset = 1; + wire passed; + integer cycles = 0; + SubRobCheck dut(.*); + always #5 clock = ~clock; + initial begin repeat(5) @(negedge clock); reset=0; end + always @(posedge clock) if (!reset) begin + cycles <= cycles + 1; + if (passed) begin + $display("PASS SUBROB streaming rows=40 commands=39 cycles=%0d", cycles); + $finish; + end + if (cycles > 10000) $fatal(1, "SubROB timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/tests/ws_round_edges.c b/platforms/arty-a7-toy/tests/ws_round_edges.c new file mode 100644 index 0000000..fa5cced --- /dev/null +++ b/platforms/arty-a7-toy/tests/ws_round_edges.c @@ -0,0 +1,63 @@ +// Independent integer oracle and alternating OS/WS cases on the real CPU. +#include "buckyball.h" +#include +#include +#include + +#define DIM 8 +static elem_t a[DIM * DIM] __attribute__((aligned(64))); +static elem_t b[DIM * DIM] __attribute__((aligned(64))); +static elem_t d[DIM * DIM] __attribute__((aligned(64))); +static result_t c[DIM * DIM] __attribute__((aligned(64))); +static const int shifts[] = {0, 1, 2, 4, 8, 19, 20, 31}; +static const int ties[] = {-41, -40, -39, -25, -24, -23, -9, -8, + -7, -3, -2, -1, 0, 1, 2, 3, + 7, 8, 9, 23, 24, 25, 39, 40, 41}; + +static int32_t nearest_even(int32_t value, int shift) { + if (!shift) return value; + int64_t magnitude = value < 0 ? -(int64_t)value : value; + int64_t divisor = (int64_t)1 << shift; + int64_t quotient = magnitude / divisor; + int64_t remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2)) quotient++; + return value < 0 ? -quotient : quotient; +} + +int main(void) { + int run = 0; + for (unsigned si = 0; si < sizeof(shifts) / sizeof(shifts[0]); si++) + for (int pattern = 0; pattern < 4; pattern++) + for (int mode = 0; mode < 2; mode++, run++) { + for (int r = 0; r < DIM; r++) + for (int k = 0; k < DIM; k++) { + int index = r * DIM + k; + a[index] = pattern == 3 ? -128 : (r == k ? (pattern == 2 ? 4 : 1) : 0); + b[index] = pattern == 3 ? ((k & 1) ? 127 : -128) : ties[(index + 7 * pattern) % 25]; + d[index] = mode && pattern == 1 ? (index % 7 - 3) : 0; + c[index] = 0x12345678; + } + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 1); + bb_mem_alloc(3, 1, 4); + bb_mvin((uintptr_t)b, 0, DIM, 1); + bb_mvin((uintptr_t)a, 1, DIM, 1); + bb_mvin((uintptr_t)d, 2, DIM, 1); + bb_gemmini_config(mode, 0, 0, 0, shifts[si]); + bb_gemmini_preload(mode ? 0 : 1, 3, DIM, 0, 0); + bb_gemmini_compute_preloaded(1, mode ? 2 : 0, 3, DIM, 0, 0, 0); + bb_mvout((uintptr_t)c, 3, DIM, 1); + bb_fence(); + for (int r = 0; r < DIM; r++) + for (int col = 0; col < DIM; col++) { + int32_t sum = d[r * DIM + col]; + for (int k = 0; k < DIM; k++) + sum += (int32_t)a[r * DIM + k] * b[k * DIM + col]; + if (c[r * DIM + col] != nearest_even(sum, shifts[si])) return run + 1; + } + for (int bank = 0; bank < 4; bank++) bb_mem_release(bank); + } + return 0; +} diff --git a/platforms/arty-a7-toy/tests/ws_shift_edges.c b/platforms/arty-a7-toy/tests/ws_shift_edges.c new file mode 100644 index 0000000..bbeccdf --- /dev/null +++ b/platforms/arty-a7-toy/tests/ws_shift_edges.c @@ -0,0 +1,63 @@ +// Focused RNE regression with zero bias; nonzero bias stays in ws_round_edges.c. +#include "buckyball.h" +#include +#include +#include + +#define DIM 8 +static elem_t a[DIM * DIM] __attribute__((aligned(64))); +static elem_t b[DIM * DIM] __attribute__((aligned(64))); +static elem_t d[DIM * DIM] __attribute__((aligned(64))); +static result_t c[DIM * DIM] __attribute__((aligned(64))); +static const int shifts[] = {0, 1, 2, 4, 8, 19, 20, 31}; +static const int ties[] = {-41, -40, -39, -25, -24, -23, -9, -8, + -7, -3, -2, -1, 0, 1, 2, 3, + 7, 8, 9, 23, 24, 25, 39, 40, 41}; + +static int32_t nearest_even(int32_t value, int shift) { + if (!shift) return value; + int64_t magnitude = value < 0 ? -(int64_t)value : value; + int64_t divisor = (int64_t)1 << shift; + int64_t quotient = magnitude / divisor; + int64_t remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2)) quotient++; + return value < 0 ? -quotient : quotient; +} + +int main(void) { + int run = 0; + for (unsigned si = 0; si < sizeof(shifts) / sizeof(shifts[0]); si++) + for (int pattern = 0; pattern < 4; pattern++) + for (int mode = 0; mode < 2; mode++, run++) { + for (int r = 0; r < DIM; r++) + for (int k = 0; k < DIM; k++) { + int index = r * DIM + k; + a[index] = pattern == 3 ? -128 : (r == k ? (pattern == 2 ? 4 : 1) : 0); + b[index] = pattern == 3 ? ((k & 1) ? 127 : -128) : ties[(index + 7 * pattern) % 25]; + d[index] = 0; + c[index] = 0x12345678; + } + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 1); + bb_mem_alloc(3, 1, 4); + bb_mvin((uintptr_t)b, 0, DIM, 1); + bb_mvin((uintptr_t)a, 1, DIM, 1); + bb_mvin((uintptr_t)d, 2, DIM, 1); + bb_gemmini_config(mode, 0, 0, 0, shifts[si]); + bb_gemmini_preload(mode ? 0 : 1, 3, DIM, 0, 0); + bb_gemmini_compute_preloaded(1, mode ? 2 : 0, 3, DIM, 0, 0, 0); + bb_mvout((uintptr_t)c, 3, DIM, 1); + bb_fence(); + for (int r = 0; r < DIM; r++) + for (int col = 0; col < DIM; col++) { + int32_t sum = d[r * DIM + col]; + for (int k = 0; k < DIM; k++) + sum += (int32_t)a[r * DIM + k] * b[k * DIM + col]; + if (c[r * DIM + col] != nearest_even(sum, shifts[si])) return run + 1; + } + for (int bank = 0; bank < 4; bank++) bb_mem_release(bank); + } + return 0; +}